5 4 3 2 1
MODEL NAME : Marble Falls/ Discrete UV17 UV18 UV19 UV20 RV59 ZZZ
PROJECT CODE : ZAL50, ZAL60
PCB NO : LA-B072P VRAM VRAM VRAM VRAM 20K X7653531L01
X76_HYX@ X76_HYX@ X76_HYX@ X76_HYX@ X76_HYX@ X76_HYX_R@
D D
UV17 UV18 UV19 UV20 RV59 ZZZ
ZZZ R1@ UC1
VRAM VRAM VRAM VRAM 24.9K X7653531L51
PCB 14B LA-B072P REV0 M/B CPU X76_MIC@ X76_MIC@ X76_MIC@ X76_MIC@ X76_MIC@ X76_MIC_R@
UV17 UV18 UV19 UV20 RV59 ZZZ
VRAM VRAM VRAM VRAM 30.1K X7653531L02
X76_SAM@ X76_SAM@ X76_SAM@ X76_SAM@ X76_SAM@ X76_SAM_R@
For Post RTS
C C
Dell / Compal Confidential
Schematic Document
Intel Broadwell ULT
B
Marble Falls 14"/15" Value B
DIS
2013-10-03 Rev: 0.1
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU A
Date: Monday, April 07, 2014 Sheet 1 of 54
5 4 3 2 1
5 4 3 2 1
D D
eDP Conn. eDP
Page 21
HDMI Conn. DDI Memory Bus (DDR3L) DDRIIIL-DIMM X2
Page 19 Dual Channel
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
1.35V DDR3L 1600 MHz Page 17, 18
CRT Conn. DP to CRT DDI
Page 20 IT6513FN 8GB Max
Page 20
USB 3.0 Port 1
DDR3L nVIDIA Intel USB 3.0 Conn. 1
Port 0 Page 24
256MX16 N15S-GM PCI-E X4 Broadwell ULT-U
2GBPage 51,52 GB2B-64 Processor USB2.0 Port 2
BGA 595 Port 1 USB 3.0 Conn. 2
BGA 1168 Page 24
C
Page 46~50 C
Port 2
USB 2.0 Conn. 3
PCI-E Port 3 Fingerprint Page 26
Page 27
x1 x1
Port 4 Port 3
Port 4 NGFF
NGFF 2230 Ethernet WiFi/BT4.0 Page 25
WiFi/BT4.0 RTL8111GUS-CG
Port 7 Digital Camera
Page 25 Page 22
(With Digital MIC)Page 21
Port 5
Touch Screen Page 21
Port 6 Card Reader
RTS5176E Page 27
SATA HDD Conn. Port 0 SATA Rediver SATA3.0
Page 26 Page 26
B B
Digital Mic.
HD Audio Audio Codec Headphone Jack /
ALC3234 Mic. Jack comboPage 23
LS-B071P Page 23
USB2.0 Conn
USB2.0 Port 2 Int. Speaker R / L
SPI ROM SPI
Page 23
8MB Page 6~16
Card Reader Page 9
IOR/B USB2.0 Port 6
LPC Bus
33MHz
LS-B072P LED *2 SMSC SIO BC Bus SMSC KBC PS/2
ECE1099 Touch Pad
MEC5085
A
Page 28 Page 29 Page 27 A
Lid Switch KBD
BC Bus KB control Page 30
LED/B ECE1117 KB BKL
Page 30 Page 30
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019RU
Date: Monday, April 07, 2014 Sheet 2 of 45
5 4 3 2 1
5 4 3 2 1
D D
M
/
B
IOR /B
C C
JUSB3
JREAD
16pin
3in1 JIO1
FFC JIO
pin 1 pin 1 pin 1
JLED
8pin
B B
pin 1
Lid Switch JLED1
LED2 LED1
LED /B
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019RU
Date: Monday, April 07, 2014 Sheet 3 of 54
5 4 3 2 1
5 4 3 2 1
Board ID Table USB3.0
Phase ID
RE79 CE54 REV Port1 USB connector 1
240K 4700p X00 Port2 USB connector 2
130K 4700p X01
D
62K 4700p X02 Port3 D
33K 4700p X03
8.2K 4700p A00 Port4
4.3K 4700p
2K 4700p USB2.0
1K 4700p
BOARD_ID rise time is measured from 5%~68%. Port0 USB connector 1
Config ID
Port1 USB connector 2
RE89 RE90 Config
De-Pop Pop Discrete USB connector 3 (IO/B)
Port2
Pop De-Pop UMA
Port3 Finger print
SMBUS Control Table Port4 NGFF (BT + WLAN)
SOURCE BATT Charger DDR3L XDP WLAN Touch VGA
C NGFF pad Port5 Touch Screen Panel C
CHARGER_SMBCLK MEC5085 ULT Port6 Card Reader
CHARGER_SMBDAT V
PBAT_SMBCLK MEC5085
PBAT_SMBDAT V Port7 Camera
GPU_SMBCLK
GPU_SMBDAT
MEC5085 V PCI EXPRESS
SML1_SMBCLK MEC5085
SML1_SMBDATA Lane 1
SMBCLK ULT
SMBDATA V V V V Lane 2
Link
SML0CLK ULT
SML0DATA Lane 3 10/100/1000 LAN
SML1CLK ULT
SML1DATA Lane 4 NGFF (BT + WLAN)
B
Lane 5 PEG (N15S) B
Lane 6
CLOCK SIGNAL
SATA
CLKOUT_PCIE0
SATA0 HDD
CLKOUT_PCIE1
SATA1
CLKOUT_PCIE2 10/100/1000 LAN
Symbol Note : SATA2
CLKOUT_PCIE3 NGFF (BT + WLAN)
: means Digital Ground SATA3
CLKOUT_PCIE4
DDI
CLKOUT_PCIE5 : means Analog Ground
A
DDI1 HDMI A
DDI2 DP to CRT
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019RU
Date: Monday, April 07, 2014 Sheet 4 of 54
5 4 3 2 1
5 4 3 2 1
2.2K 2.2K
SMBUS Address [0x9a]
2.2K
+3.3V_ALW_PCH 2.2K
+3VS
D
MEM_SMBCLK
N-MOS DDR_XDP_WLAN_TP_SMBCLK 202
D
AP2 DIMMA SMBUS Address [A0]
MEM_SMBDATA
N-MOS DDR_XDP_WLAN_TP_SMBDAT 200
AH1
1K
202 DIMMB
+3.3V_ALW_PCH SMBUS Address [A4]
1K 200
AN1 SML0CLK
MCP 0 ohm
AK1 SML0DATA DDR_XDP_SMBCLK_R1 53 JXDP1 SMBUS Address [TBD]
0 ohm DDR_XDP_SMBDAT_R1 51
2.2K
2.2K
+3.3V_ALW_PCH
AN1 SML1_SMBCLK
AK1 SML1_SMBDATA
C C
79 SML1_SMBCLK
80 SML1_SMBDATA
2.2K
2.2K
+3VALW_5085
77 CHARGER_SMBCLK
0 ohm SCL 11 PU700 POWER SMBUS Address [0x12]
0 ohm Charger
B
MEC 5085 78 CHARGER_SMBDAT SDA 10
B
2.2K
2.2K
+3VALW_5085
PBAT_SMBCLK
100 ohm 3 4 Z4304 3
PD1 PBATT1 BATT SMBUS Address [0x16]
100 ohm CONN
PBAT_SMBDAT 1 6 Z4305 5
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 5 of 54
5 4 3 2 1
5 4 3 2 1
+1.05VS
+3VS
+1.05VS +1.05VS
0.1U_0402_10V7K
0.1U_0402_10V7K
CC13
2 1 1 1
XDP@ UC4 XDP@ JXDP
CC14
@
CC15
@
0.1U_0402_10V7K 1 2
14 XDP_PREQ# 3 GND0 GND1 4
VCC 2 2 OBSFN_A0 OBSFN_C0 CFG17 [16]
XDP_PRDY# 5 6
OBSFN_A1 OBSFN_C1 CFG16 [16]
PCH_JTAG_TDO 1 @ 2 TDO_XDP 2 3 XDP_TDO 7 8
[8] PCH_JTAG_TDO 1A 1B GND2 GND3
RC43 0_0402_5% 9 10
[16] CFG0 OBSDATA_A0 OBSDATA_C0 CFG8 [16]
11 12
[16] CFG1 OBSDATA_A1 OBSDATA_C1 CFG9 [16]
D RUNPWROK 1 13 14 D
1OE 15 GND4 GND5 16
[16] CFG2 OBSDATA_A2 OBSDATA_C2 CFG10 [16]
1 @ 2 TDI_XDP 1 @ 2 TDI_XDP_R 5 6 XDP_TDI CFG3 17 18
[8] PCH_JTAG_TDI 2A 2B [16] CFG3 OBSDATA_A3 OBSDATA_C3 CFG11 [16]
RC44 0_0402_5% RC45 0_0402_5% Place near JXDP1 19 20
XDP_OBS0_R 21 GND6 GND7 22
OBSFN_B0 OBSFN_D0 CFG19 [16]
RUNPWROK 4 XDP_OBS1_R 23 24
X02.08 2OE 25 OBSFN_B1 OBSFN_D1 26
CFG18 [16]
1 @ 2 TMS_XDP 9 8 XDP_TMS 27 GND8 GND9 28
[8] PCH_JTAG_TMS 3A 3B [16] CFG4 OBSDATA_B0 OBSDATA_D0 CFG12 [16]
RC46 0_0402_5% 29 30
[16] CFG5 OBSDATA_B1 OBSDATA_D1 CFG13 [16]
RC5 need to close to JCPU1 31 32
RUNPWROK 10 33 GND10 GND11 34
3OE [16] CFG6 OBSDATA_B2 OBSDATA_D2 CFG14 [16]
RC114 1 XDP@ 2 1K_0402_5% 35 36
[13] H_VCCST_PWRGD [16] CFG7 OBSDATA_B3 OBSDATA_D3 CFG15 [16]
TRST#_XDP 12 11 XDP_TRST# 37 38
4A 4B H_CPUPWRGD RC48 1 @ 2 1K_0402_5% H_VCCST_PWRGD_XDP 39 GND12 GND13 40
RC49 1 @ 2 0_0402_1% CFD_PWRBTN#_XDP 41 PWRGOOD/HOOK0 ITPCLK/HOOK4 42
[10,29] SIO_PWRBTN# HOOK1 ITPCLK#/HOOK5
RUNPWROK 13 7 43 44
[29] RUNPWROK 4OE GND VCC_OBS_AB VCC_OBS_CD
RC50 1 @ 2 0_0402_1% CPU_PWR_DEBUG#_R 45 46 XDP_RST#_R 2 1
[13] CPU_PWR_DEBUG# HOOK2 RESET#/HOOK6 PCH_PLTRST#_EC [10,22,25,29]
1 15 SYS_PWROK RC52 1 @ 2 0_0402_1% SYS_PWROK_XDP 47 48 XDP_DBRESET# XDP@ 2 1 +3VS
GND PAD [10,29] SYS_PWROK HOOK3 DBR#/HOOK7
CC29 ESD@ 49 50 RC51
RC53 1 @ 2 0_0402_1% DDR_XDP_SMBDAT_R1 51 GND14 GND15 52 TDO_XDP 1K_0402_5% RC362
[9,17,18] DDR_XDP_WLAN_TP_SMBDAT SDA TD0
0.1U_0402_10V7K 74CBTLV3126BQ_DHVQFN14_2P5X3 RC54 1 @ 2 0_0402_1% DDR_XDP_SMBCLK_R1 53 54 TRST#_XDP 1K_0402_1%
2 [9,17,18] DDR_XDP_WLAN_TP_SMBCLK SCL TRST#
PCH_JTAG_TCK 55 56 TDI_XDP 1 2
XDP_TCLK 57 TCK1 TDI 58 TMS_XDP XDP@
59 TCK0 TMS 60 CFG3_R 1 XDP@ 2 CFG3 CC17
reference Shark Bay ULT Validation Customer Debug Port GND16 GND17 RC56 1K_0402_5% 0.1U_0402_10V7K
Implementation Requirement Rev 1.0 +3VALW_PCH SAMTE_BSH-030-01-L-D-A
Place CC29 CONN@
close to UC4 X02.08
2
PCH_JTAG_RST# 2 @ 1 XDP_TRST# XDP@
[8] PCH_JTAG_RST#
0_0402_5% RC57 RC64
1K_0402_5% XDP_DBRESET#
XDP_DBRESET# [10]
2 @ 1 XDP_TCLK
[8] PCH_JTAG_JTAGX
1
0_0402_5% RC59
SYS_PWROK_XDP
2 1 TDO_XDP
0_0402_5% @ RC62 1
C @ C
PCH_JTAG_TDO 2 1 TDI_XDP_R CC16
0_0402_5% @ RC63 0.1U_0402_10V7K
2
2 1 XDP_TCLK Place near JXDP1.47
[8] PCH_JTAG_TCK
0_0402_5% @ RC65
HASWELL_MCP_E
UC1A
DDI1_LANE_N0 C54 C45
[19] DDI1_LANE_N0 DDI1_TXN0 EDP_TXN0 EDP_TX0# [21]
DDI1_LANE_P0 C55 B46
[19] DDI1_LANE_P0 DDI1_TXP0 EDP_TXP0 EDP_TX0 [21]
DDI1_LANE_N1 B58 A47
[19] DDI1_LANE_N1 DDI1_TXN1 EDP_TXN1 EDP_TX1# [21]
DDI1_LANE_P1 C58 B47
[19] DDI1_LANE_P1 DDI1_TXP1 EDP_TXP1 EDP_TX1 [21]
DDI1_LANE_N2 B55
[19] DDI1_LANE_N2 DDI1_TXN2
DDI1_LANE_P2 A55 C47
[19] DDI1_LANE_P2 DDI1_TXP2 EDP_TXN2
DDI1_LANE_N3 A57 C46
[19] DDI1_LANE_N3
DDI1_LANE_P3 B57 DDI1_TXN3 EDP_TXP2 A49 COMPENSATION PU FOR eDP
[19] DDI1_LANE_P3 DDI1_TXP3 DDI EDP EDP_TXN3 B49
DDI2_LANE_N0 C51 EDP_TXP3
[20] DDI2_LANE_N0 DDI2_TXN0 +VCCIOA_OUT
DDI2_LANE_P0 C50 A45
[20] DDI2_LANE_P0 DDI2_TXP0 EDP_AUXN EDP_AUX# [21]
DDI2_LANE_N1 C53 B45
[20] DDI2_LANE_N1 DDI2_TXN1 EDP_AUXP EDP_AUX [21]
DDI2_LANE_P1 B54
[20] DDI2_LANE_P1 DDI2_TXP1
C49 D20 EDP_COMP 2 1
B50 DDI2_TXN2 EDP_RCOMP A43 EDP_DISP_UTIL 1 2 24.9_0402_1% RC71
DDI2_TXP2 EDP_DISP_UTIL EDP_BIA_PWM [10,21]
A53 RC72 @ 0_0402_5%
B53 DDI2_TXN3
DDI2_TXP3 CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
B B
1 OF 19 Rev1p2
@
+1.05VS
HASWELL_MCP_E
UC1B
1 2 H_CATERR#
@ RC58 49.9_0402_1%
1 2 H_PROCHOT# D61
RC60 62_0402_5% H_CATERR# K61 PROC_DETECT MISC
N62 CATERR J62 XDP_PRDY#
[29] PECI_EC PECI PRDY +1.05VS
K62 XDP_PREQ# PU/PD for JTAG signals
JTAG
PREQ E60 XDP_TCLK
PROC_TCK E61 XDP_TMS
H_PROCHOT# 1 2 H_PROCHOT#_R K63 PROC_TMS E59 XDP_TRST#
[29,38,41] H_PROCHOT# PROCHOT PROC_TRST
RC67 56_0402_5% THERMAL F63 XDP_TDI XDP_TMS 1 8
PROC_TDI F62 XDP_TDO XDP_TDI 2 7
PROC_TDO XDP_PREQ# 3 6
1 H_CPUPWRGD C61 TDO_XDP 4 5
EMI@ PROCPWRGD PWR
1
CA26 1 J60 XDP_OBS0_R
22P_0402_50V8J RC66 CC27 BPM#0 H60 XDP_OBS1_R RP44 @
2 10K_0402_5% 100P_0402_50V8J BPM#1 H61 @ T111 51_8P4R_5%
ESD@ BPM#2 H62 @ T112
2 SM_RCOMP0 AU60 BPM#3 K59 @ T113 XDP_TDO 1 8
2
SM_RCOMP1 AV60 SM_RCOMP0 DDR3 BPM#4 H63 @ T114 XDP_TCLK 2 7
ESD solution SM_RCOMP2 AU61 SM_RCOMP1 BPM#5 K60 @ T115 3 6
AV15 SM_RCOMP2 BPM#6 J61 @ T116 4 5
[17] DDR3_DRAMRST#_CPU SM_DRAMRST BPM#7
AV61
[17] DDR_PG_CTRL SM_PG_CNTL1 RP45
1 51_8P4R_5%
CC35 2 OF 19 Rev1p2
@ @ XDP_TRST# 2 1 @ RC129
0.047U_0402_16V4Z 51_0402_5%
2
A A
DDR3 COMPENSATION SIGNALS
200_0402_1% 2 1 RC68 SM_RCOMP0
Place CC35
on BOT
121_0402_1% 2 1 RC69 SM_RCOMP1
100_0402_1% 2 1 RC70 SM_RCOMP2
Security Classification Compal Secret Data Compal Electronics, Inc.
CAD Note: Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
Trace width=12~15 mil, Spcing=20 mils THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Max trace length= 500 mil Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 6 of 54
5 4 3 2 1
5 4 3 2 1
Interleaved Memory
HASWELL_MCP_E
UC1D
HASWELL_MCP_E [17] DDR_A_D[32..47]
D UC1C D
[17] DDR_A_D[0..15]
DDR_A_D0 AH63 AU37 M_CLK_DDR#0 DDR_A_D32 AY31 AM38 M_CLK_DDR#2
SA_DQ0 SA_CLK#0 M_CLK_DDR#0 [17] SB_DQ0 SB_CK#0 M_CLK_DDR#2 [18]
DDR_A_D1 AH62 AV37 M_CLK_DDR0 DDR_A_D33 AW31 AN38 M_CLK_DDR2
SA_DQ1 SA_CLK0 M_CLK_DDR0 [17] SB_DQ1 SB_CK0 M_CLK_DDR2 [18]
DDR_A_D2 AK63 AW36 M_CLK_DDR#1 DDR_A_D34 AY29 AK38 M_CLK_DDR#3
SA_DQ2 SA_CLK#1 M_CLK_DDR#1 [17] SB_DQ2 SB_CK#1 M_CLK_DDR#3 [18]
DDR_A_D3 AK62 AY36 M_CLK_DDR1 DDR_A_D35 AW29 AL38 M_CLK_DDR3
SA_DQ3 SA_CLK1 M_CLK_DDR1 [17] SB_DQ3 SB_CK1 M_CLK_DDR3 [18]
DDR_A_D4 AH61 DDR_A_D36 AV31
DDR_A_D5 AH60 SA_DQ4 AU43 DDR_CKE0_DIMMA DDR_A_D37 AU31 SB_DQ4 AY49 DDR_CKE2_DIMMB
SA_DQ5 SA_CKE0 DDR_CKE0_DIMMA [17] SB_DQ5 SB_CKE0 DDR_CKE2_DIMMB [18]
DDR_A_D6 AK61 AW43 DDR_CKE1_DIMMA DDR_A_D38 AV29 AU50 DDR_CKE3_DIMMB
SA_DQ6 SA_CKE1 DDR_CKE1_DIMMA [17] SB_DQ6 SB_CKE1 DDR_CKE3_DIMMB [18]
DDR_A_D7 AK60 AY42 DDR_A_D39 AU29 AW49
DDR_A_D8 AM63 SA_DQ7 SA_CKE2 AY43 DDR_A_D40 AY27 SB_DQ7 SB_CKE2 AV50
DDR_A_D9 AM62 SA_DQ8 SA_CKE3 DDR_A_D41 AW27 SB_DQ8 SB_CKE3
DDR_A_D10 AP63 SA_DQ9 AP33 DDR_CS0_DIMMA# DDR_A_D42 AY25 SB_DQ9 AM32 DDR_CS2_DIMMB#
SA_DQ10 SA_CS#0 DDR_CS0_DIMMA# [17] SB_DQ10 SB_CS#0 DDR_CS2_DIMMB# [18]
DDR_A_D11 AP62 AR32 DDR_CS1_DIMMA# DDR_A_D43 AW25 AK32 DDR_CS3_DIMMB#
SA_DQ11 SA_CS#1 DDR_CS1_DIMMA# [17] SB_DQ11 SB_CS#1 DDR_CS3_DIMMB# [18]
DDR_A_D12 AM61 DDR_A_D44 AV27
DDR_A_D13 AM60 SA_DQ12 AP32 DDR_A_D45 AU27 SB_DQ12 AL32
DDR_A_D14 AP61 SA_DQ13 SA_ODT0 DDR_A_D46 AV25 SB_DQ13 SB_ODT0
DDR_A_D15 AP60 SA_DQ14 AY34 DDR_A_RAS# DDR_A_D47 AU25 SB_DQ14 AM35 DDR_B_RAS#
[18] DDR_B_D[0..15] SA_DQ15 SA_RAS DDR_A_RAS# [17] [18] DDR_B_D[32..47] SB_DQ15 SB_RAS DDR_B_RAS# [18]
DDR_B_D0 AP58 AW34 DDR_A_WE# DDR_B_D32 AM29 AK35 DDR_B_WE#
SA_DQ16 SA_WE DDR_A_WE# [17] SB_DQ16 SB_WE DDR_B_WE# [18]
DDR_B_D1 AR58 AU34 DDR_A_CAS# DDR_B_D33 AK29 AM33 DDR_B_CAS#
SA_DQ17 SA_CAS DDR_A_CAS# [17] SB_DQ17 SB_CAS DDR_B_CAS# [18]
DDR_B_D2 AM57 DDR_B_D34 AL28
DDR_B_D3 AK57 SA_DQ18 AU35 DDR_A_BS0 DDR_B_D35 AK28 SB_DQ18 AL35 DDR_B_BS0
SA_DQ19 SA_BA0 DDR_A_BS0 [17] SB_DQ19 SB_BA0 DDR_B_BS0 [18]
DDR_B_D4 AL58 AV35 DDR_A_BS1 DDR_B_D36 AR29 AM36 DDR_B_BS1
SA_DQ20 SA_BA1 DDR_A_BS1 [17] SB_DQ20 SB_BA1 DDR_B_BS1 [18]
DDR_B_D5 AK58 AY41 DDR_A_BS2 DDR_B_D37 AN29 AU49 DDR_B_BS2
SA_DQ21 SA_BA2 DDR_A_BS2 [17] SB_DQ21 SB_BA2 DDR_B_BS2 [18]
DDR_B_D6 AR57 DDR_B_D38 AR28
SA_DQ22 DDR_A_MA[0..15] [17] SB_DQ22 DDR_B_MA[0..15] [18]
DDR_B_D7 AN57 AU36 DDR_A_MA0 DDR_B_D39 AP28 AP40 DDR_B_MA0
DDR_B_D8 AP55 SA_DQ23 SA_MA0 AY37 DDR_A_MA1 DDR_B_D40 AN26 SB_DQ23 SB_MA0 AR40 DDR_B_MA1
DDR_B_D9 AR55 SA_DQ24 SA_MA1 AR38 DDR_A_MA2 DDR_B_D41 AR26 SB_DQ24 SB_MA1 AP42 DDR_B_MA2
DDR_B_D10 AM54 SA_DQ25 SA_MA2 AP36 DDR_A_MA3 DDR_B_D42 AR25 SB_DQ25 SB_MA2 AR42 DDR_B_MA3
DDR_B_D11 AK54 SA_DQ26 SA_MA3 AU39 DDR_A_MA4 DDR_B_D43 AP25 SB_DQ26 SB_MA3 AR45 DDR_B_MA4
DDR_B_D12 AL55 SA_DQ27 SA_MA4 AR36 DDR_A_MA5 DDR_B_D44 AK26 SB_DQ27 SB_MA4 AP45 DDR_B_MA5
DDR_B_D13 AK55 SA_DQ28 SA_MA5 AV40 DDR_A_MA6 DDR_B_D45 AM26 SB_DQ28 SB_MA5 AW46 DDR_B_MA6
DDR_B_D14 AR54 SA_DQ29 SA_MA6 AW39 DDR_A_MA7 DDR_B_D46 AK25 SB_DQ29 SB_MA6 AY46 DDR_B_MA7
DDR_B_D15 AN54 SA_DQ30 SA_MA7 AY39 DDR_A_MA8 DDR_B_D47 AL25 SB_DQ30 SB_MA7 AY47 DDR_B_MA8
[17] DDR_A_D[16..31] SA_DQ31 SA_MA8 [17] DDR_A_D[48..63] SB_DQ31 SB_MA8
DDR_A_D16 AY58 AU40 DDR_A_MA9 DDR_A_D48 AY23 AU46 DDR_B_MA9
DDR_A_D17 AW58 SA_DQ32 SA_MA9 AP35 DDR_A_MA10 DDR_A_D49 AW23 SB_DQ32 SB_MA9 AK36 DDR_B_MA10
DDR_A_D18 AY56 SA_DQ33 SA_MA10 AW41 DDR_A_MA11 DDR_A_D50 AY21 SB_DQ33 DDR CHANNEL B SB_MA10 AV47 DDR_B_MA11
C SA_DQ34 SA_MA11 SB_DQ34 SB_MA11 C
DDR_A_D19 AW56 DDR CHANNEL A AU41 DDR_A_MA12 DDR_A_D51 AW21 AU47 DDR_B_MA12
DDR_A_D20 AV58 SA_DQ35 SA_MA12 AR35 DDR_A_MA13 DDR_A_D52 AV23 SB_DQ35 SB_MA12 AK33 DDR_B_MA13
DDR_A_D21 AU58 SA_DQ36 SA_MA13 AV42 DDR_A_MA14 DDR_A_D53 AU23 SB_DQ36 SB_MA13 AR46 DDR_B_MA14
DDR_A_D22 AV56 SA_DQ37 SA_MA14 AU42 DDR_A_MA15 DDR_A_D54 AV21 SB_DQ37 SB_MA14 AP46 DDR_B_MA15
DDR_A_D23 AU56 SA_DQ38 SA_MA15 DDR_A_D55 AU21 SB_DQ38 SB_MA15
SA_DQ39 DDR_A_DQS#[0..1] [17] SB_DQ39 DDR_A_DQS#[4..5] [17]
DDR_A_D24 AY54 AJ61 DDR_A_DQS#0 DDR_A_D56 AY19 AW30 DDR_A_DQS#4
DDR_A_D25 AW54 SA_DQ40 SA_DQSN0 AN62 DDR_A_DQS#1 DDR_A_D57 AW19 SB_DQ40 SB_DQSN0 AV26 DDR_A_DQS#5
SA_DQ41 SA_DQSN1 DDR_B_DQS#[0..1] [18] SB_DQ41 SB_DQSN1 DDR_B_DQS#[4..5] [18]
DDR_A_D26 AY52 AM58 DDR_B_DQS#0 DDR_A_D58 AY17 AN28 DDR_B_DQS#4
DDR_A_D27 AW52 SA_DQ42 SA_DQSN2 AM55 DDR_B_DQS#1 DDR_A_D59 AW17 SB_DQ42 SB_DQSN2 AN25 DDR_B_DQS#5
SA_DQ43 SA_DQSN3 DDR_A_DQS#[2..3] [17] SB_DQ43 SB_DQSN3 DDR_A_DQS#[6..7] [17]
DDR_A_D28 AV54 AV57 DDR_A_DQS#2 DDR_A_D60 AV19 AW22 DDR_A_DQS#6
DDR_A_D29 AU54 SA_DQ44 SA_DQSN4 AV53 DDR_A_DQS#3 DDR_A_D61 AU19 SB_DQ44 SB_DQSN4 AV18 DDR_A_DQS#7
SA_DQ45 SA_DQSN5 DDR_B_DQS#[2..3] [18] SB_DQ45 SB_DQSN5 DDR_B_DQS#[6..7] [18]
DDR_A_D30 AV52 AL43 DDR_B_DQS#2 DDR_A_D62 AV17 AN21 DDR_B_DQS#6
DDR_A_D31 AU52 SA_DQ46 SA_DQSN6 AL48 DDR_B_DQS#3 DDR_A_D63 AU17 SB_DQ46 SB_DQSN6 AN18 DDR_B_DQS#7
[18] DDR_B_D[16..31] SA_DQ47 SA_DQSN7 [18] DDR_B_D[48..63] SB_DQ47 SB_DQSN7
DDR_B_D16 AK40 DDR_B_D48 AR21
SA_DQ48 DDR_A_DQS[0..1] [17] SB_DQ48 DDR_A_DQS[4..5] [17]
DDR_B_D17 AK42 AJ62 DDR_A_DQS0 DDR_B_D49 AR22 AV30 DDR_A_DQS4
DDR_B_D18 AM43 SA_DQ49 SA_DQSP0 AN61 DDR_A_DQS1 DDR_B_D50 AL21 SB_DQ49 SB_DQSP0 AW26 DDR_A_DQS5
SA_DQ50 SA_DQSP1 DDR_B_DQS[0..1] [18] SB_DQ50 SB_DQSP1 DDR_B_DQS[4..5] [18]
DDR_B_D19 AM45 AN58 DDR_B_DQS0 DDR_B_D51 AM22 AM28 DDR_B_DQS4
DDR_B_D20 AK45 SA_DQ51 SA_DQSP2 AN55 DDR_B_DQS1 DDR_B_D52 AN22 SB_DQ51 SB_DQSP2 AM25 DDR_B_DQS5
SA_DQ52 SA_DQSP3 DDR_A_DQS[2..3] [17] SB_DQ52 SB_DQSP3 DDR_A_DQS[6..7] [17]
DDR_B_D21 AK43 AW57 DDR_A_DQS2 DDR_B_D53 AP21 AV22 DDR_A_DQS6
DDR_B_D22 AM40 SA_DQ53 SA_DQSP4 AW53 DDR_A_DQS3 DDR_B_D54 AK21 SB_DQ53 SB_DQSP4 AW18 DDR_A_DQS7
SA_DQ54 SA_DQSP5 DDR_B_DQS[2..3] [18] SB_DQ54 SB_DQSP5 DDR_B_DQS[6..7] [18]
DDR_B_D23 AM42 AL42 DDR_B_DQS2 DDR_B_D55 AK22 AM21 DDR_B_DQS6
DDR_B_D24 AM46 SA_DQ55 SA_DQSP6 AL49 DDR_B_DQS3 DDR_B_D56 AN20 SB_DQ55 SB_DQSP6 AM18 DDR_B_DQS7
DDR_B_D25 AK46 SA_DQ56 SA_DQSP7 DDR_B_D57 AR20 SB_DQ56 SB_DQSP7
DDR_B_D26 AM49 SA_DQ57 AP49 DDR_B_D58 AK18 SB_DQ57
SA_DQ58 SM_VREF_CA +SM_VREF_CA SB_DQ58
DDR_B_D27 AK49 AR51 +SM_VREF_DQ0 DDR_B_D59 AL18
DDR_B_D28 AM48 SA_DQ59 SM_VREF_DQ0 AP51 DDR_B_D60 AK20 SB_DQ59
SA_DQ60 SM_VREF_DQ1 +SM_VREF_DQ1 SB_DQ60
DDR_B_D29 AK48 DDR_B_D61 AM20
DDR_B_D30 AM51 SA_DQ61 DDR_B_D62 AR18 SB_DQ61
DDR_B_D31 AK51 SA_DQ62 DDR_B_D63 AP18 SB_DQ62
SA_DQ63 SB_DQ63
B B
4 OF 19 Rev1p2
3 OF 19 Rev1p2 @
@
+1.35V +1.35V +1.35V
1
1
RC14 RC15 RC16
1.82K_0402_1% 1.82K_0402_1% 1.82K_0402_1%
+SM_VREF_CA_DIMM +SM_VREF_CA +SM_VREF_DQ1_DIMM2 +SM_VREF_DQ1 +SM_VREF_DQ0_DIMM1 +SM_VREF_DQ0
2
2
1 2 1 2 1 2
1 1
RC17 1 RC18 RC19
2.2_0402_1% 2.2_0402_1% CC9 2.2_0402_1% CC10
1
1
CC8 0.022U_0402_16V7K 0.022U_0402_16V7K
RC20 RC21 2 RC22 2
0.022U_0402_16V7K
1.82K_0402_1% 2 1.82K_0402_1% 1.82K_0402_1%
change 22nF change 22nF
1
1
change 22nF
1
RC24 RC25
2
2
RC23 24.9_0402_1% 24.9_0402_1%
24.9_0402_1%
2
2
2
A confirm by intel request PDG P141 A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 7 of 54
5 4 3 2 1
5 4 3 2 1
Service Mode Switch:
RTC Battery +RTCBATT
JRTC Add a switch to ME_FWP signal to unlock the ME region and
+RTCVCC +RTCBATT 1
2 1 allow the entire region of the SPI flash to be updated using FPT.
2
2
3
RC10 4 GND +3VALW_PCH
1
+CHGRTC GND
1K_0402_5%
D RC1 ACES_50271-0020N-001 D
1
330K_0402_1% CONN@
1
RC9
1K_0402_5%
2
SW3
PCH_INTVRMEN W=20mils PJP12
2
3
2
1
1
W=20mils DC1 2 1 ME_EN 2
+CHGRTC 2 1 +3VLP
@
BAT54CW_SOT323-3 [29] ME_FWP_EC 3
RC2 JUMP_43X39
330K_0402_1% @ 4 G
5
2
1
G
SSAL120100_3P
+RTCVCC
INTVRMEN ‐ INTEGRATED SUS 1.05V VRM 1
CC26
ME_FWP PCH has internal 20K PD.
ENABLE W=20mils 1U_0603_10V6K FLASH DESCRIPTOR SECURITY OVERRIDE
High ‐ Enable Internal VRs 2
Low ‐ Enable External VRs HIGH → DISABLE ME (ME can update) ‐‐> Pin1 & Pin2 short
LOW → ENABLE ME (DEFAULT) ‐‐> Pin2 & Pin3 short
X02.13
CC1
15P_0402_50V8J
1 2 PCH_RTCX1
1
YC1
C ESR MAX=50k ohm 32.768KHZ_12.5PF_9H03220008 RC4 C
HASWELL_MCP_E
10M_0402_5% UC1E
2
X02.03
2
CC2
15P_0402_50V8J AW5
1 2 PCH_RTCX2 AY5 RTCX1
1 2 INTRUDER# AU6 RTCX2 J5
INTRUDER RTC SATA_RN0/PERN6_L3 SATA_PRX_DTX_N0_C [26]
RC7 1M_0402_5% PCH_INTVRMEN AV7 H5
INTVRMEN SATA_RP0/PERP6_L3 SATA_PRX_DTX_P0_C [26]
+RTCVCC 1 2 SRTCRST# AV6 B15 SATA HDD
SRTCRST SATA_TN0/PETN6_L3 SATA_PTX_DRX_N0_C [26]
RC5 1 2 20K_0402_5% PCH_RTCRST# AU7 A15
RTCRST SATA_TP0/PETP6_L3 SATA_PTX_DRX_P0_C [26]
RC6 20K_0402_5%
J8
[10] PCH_RTCRST# SATA_RN1/PERN6_L2 H8
1 2 SATA_RP1/PERP6_L2 A17
1 2 SATA_TN1/PETN6_L2 B17
CMOS1 CMOS setting SATA_TP1/PETP6_L2
Shunt Clear CMOS PCH_AZ_BITCLK AW8 J6
@ PCH_AZ_SYNC AV11 HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1 H6
CMOS1 SHORT PADS~D PCH_AZ_RST# AU8 HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 B14
Open Keep CMOS 1 2 AY10 HDA_RST/I2S_MCLK SATA_TN2/PETN6_L1 C15
1U_0402_6.3V6K [23] PCH_AZ_CODEC_SDIN0 HDA_SDI0/I2S0_RXD AUDIO SATA SATA_TP2/PETP6_L1
CC4 AU12
ME_EN 1 2 PCH_AZ_SDOUT AU11 HDA_SDI1/I2S1_RXD F5 +3VS
1 2 RC8 1K_0402_5% AW10 HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0 E5
CC3 1U_0402_6.3V6K AV10 HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0 C17
AY8 HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 D17 X02.04
CMOS place near DIMM I2S1_SCLK SATA_TP3/PETP6_L0
HDD_DET# 1 8
V1 PCH_GPIO34 SATA_ACT# 2 7
SATA0GP/GPIO34 U1 HDD_DET# PCH_GPIO37 3 6
SATA1GP/GPIO35 HDD_DET# [26] +1.05VS_ASATA3PLL
V6 PCH_GPIO36 PCH_GPIO34 4 5
+1.05VS SATA2GP/GPIO36 PCH_GPIO36 [10]
AC1 PCH_GPIO37
+1.05VS AU62 SATA3GP/GPIO37 X02.08 RP37
[6] PCH_JTAG_RST# PCH_TRST
PCH_JTAG_TCK AE62 A12 SATA_IREF RC126 1 @ 2 0_0603_5% 10K_8P4R_5%
[6] PCH_JTAG_TCK PCH_TCK SATA_IREF
PCH_JTAG_TDI AD61 L11
[6] PCH_JTAG_TDI PCH_TDI RSVD
1 8 PCH_JTAG_TDI 2 @ 1 PCH_JTAG_JTAGX PCH_JTAG_TDO AE61 K10
[6] PCH_JTAG_TDO PCH_TDO JTAG RSVD
2 7 PCH_JTAG_TDO RC130 1K_0402_1% PCH_JTAG_TMS AD62 C12 SATA_RCOMP RC131 1 2 3.01K_0402_1%
3 6 PCH_JTAG_TMS
[6] PCH_JTAG_TMS
AL11 PCH_TMS SATA_RCOMP U3 SATA_ACT# SATA Impedance Compensation
4 5 2 @ 1 PCH_JTAG_TCK AC4 RSVD SATALED
B RSVD within 500 mils B
RC135 51_0402_1% PCH_JTAG_JTAGX AE63 CAD note:
[6] PCH_JTAG_JTAGX JTAGX
RP48 AV2
51_8P4R_5% RSVD Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.
reference FFRD sch 0.5
5 OF 19 Rev1p2
@
HDA for Codec
EMI@ R2356 1 2 33_0402_5% PCH_AZ_SDOUT
[23] PCH_AZ_CODEC_SDOUT
EMI@ R2357 1 2 33_0402_5% PCH_AZ_SYNC
[23] PCH_AZ_CODEC_SYNC
EMI@ R2358 1 2 33_0402_5% PCH_AZ_RST#
[23] PCH_AZ_CODEC_RST#
EMI@ R2359 1 2 33_0402_5% PCH_AZ_BITCLK
[23] PCH_AZ_CODEC_BITCLK
1 EMI@
CC5
27P_0402_50V8J
2
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 8 of 54
5 4 3 2 1
5 4 3 2 1
+3VALW_PCH
1
D R2329 R2330 D
10K_0402_5% 10K_0402_5%
HASWELL_MCP_E
UC1G
2
+3VALW_PCH
AU14 AN2 PCH_SMB_ALERT#
[29] LPC_LAD0 LAD0 SMBALERT/GPIO11
AW12 AP2 MEM_SMBCLK
[29] LPC_LAD1 LAD1 LPC SMBCLK
AY12 AH1 MEM_SMBDATA RP40
[29] LPC_LAD2 LAD2 SMBDATA
AW11 AL2 MEM_SMBCLK 1 8
[29] LPC_LAD3 LAD3 SMBUS SML0ALERT/GPIO60
AV12 AN1 SML0CLK MEM_SMBDATA 2 7
[29] LPC_LFRAME# LFRAME SML0CLK AK1 SML0DATA SML1_SMBCLK 3 6
SML0DATA AU4 PCH_GPIO73 SML1_SMBDATA 4 5
SML1ALERT/PCHHOT/GPIO73 AU3 SML1_SMBCLK
SML1CLK/GPIO75 SML1_SMBCLK [29]
AH3 SML1_SMBDATA 2.2K_0804_8P4R_5%
SML1DATA/GPIO74 SML1_SMBDATA [29]
PCH_SPI_CLK_R R2333 1 2 15_0402_1% PCH_SPI_CLK AA3
PCH_SPI_CS0# Y7 SPI_CLK AF2 @ T97
1 SPI_CS0 CL_CLK
Y4 AD2 @ T98
EMI@ RP39 AC2 SPI_CS1 SPI C-LINK CL_DATA AF4 @ T99 SML0CLK R2527 1 2 1K_0402_1%
C2326 PCH_SPI_MOSI_1 1 8 PCH_SPI_MOSI AA2 SPI_CS2 CL_RST SML0DATA R2528 1 2 1K_0402_1%
68P_0402_50V8J 2 PCH_SPI_MISO_1 2 7 PCH_SPI_MISO AA4 SPI_MOSI
PCH_SPI_WP1# 3 6 PCH_SPI_WP# Y6 SPI_MISO
PCH_SPI_HOLD1# 4 5 PCH_SPI_HOLD# AF1 SPI_IO2
SPI_IO3
15_0804_8P4R_5%
+3VS
R2334 1 2 1K_0402_1% 7 OF 19 Rev1p2
R2335 1 2 1K_0402_1% @
MEM Bus : DDR/XDP/WLAN/TP
C +3VS C
+3VS +3VS
1
C2327
0.1U_0402_10V7K R2331 R2332
SPI ROM ( 8MByte ) 1 2 2.2K_0402_5% 2.2K_0402_5%
2
U2302
2
PCH_SPI_CS0# 1 8
G
PCH_SPI_MISO_1 2 /CS VCC 7 PCH_SPI_HOLD1# MEM_SMBCLK 6 1
DO(IO1) /HOLD(IO3) DDR_XDP_WLAN_TP_SMBCLK [6,17,18]
S
PCH_SPI_WP1# 3 6 PCH_SPI_CLK_R
4 /WP(IO2) CLK 5 PCH_SPI_MOSI_1 QC1B
GND DI(IO0)
5
DMN66D0LDW-7_SOT363-6
W25Q64FVSSIQ_SO8
G
MEM_SMBDATA 3 4
DDR_XDP_WLAN_TP_SMBDAT [6,17,18]
S
QC1A
DMN66D0LDW-7_SOT363-6
PN : SA000039A30 ,W25Q64FVSSIQ
CC6
15P_0402_50V8J
2 1
1M_0402_5%
2
B B
3
4
HASWELL_MCP_E
RC12
UC1F
YC2
24MHZ_12PF_X3G024000DC1H
1
2
CC7
C43 A25 XTAL24_IN 15P_0402_50V8J
C42 CLKOUT_PCIE_N0 XTAL24_IN B25 XTAL24_OUT 2 1
R2341 1 2 10K_0402_5% U2 CLKOUT_PCIE_P0 XTAL24_OUT
+3VS PCIECLKRQ0/GPIO18 K21 RC13
B41 RSVD M21 3.01K_0402_1%
A41 CLKOUT_PCIE_N1 RSVD C26 CLK_BIASREF 1 2
CLKOUT_PCIE_P1 DIFFCLK_BIASREF +PCH_VCCACLKPLL
+3VS R2343 1 2 10K_0402_5% Y5
PCIECLKRQ1/GPIO19 C35 R2523 1 2 10K_0402_5%
C41 CLOCK TESTLOW_C35 C34 R2524 1 2 10K_0402_5%
[22] CLK_PCIE_LAN# CLKOUT_PCIE_N2 TESTLOW_C34
LAN -------> B42 AK8 R2525 1 2 10K_0402_5%
[22] CLK_PCIE_LAN CLKOUT_PCIE_P2 SIGNALS TESTLOW_AK8
AD1 AL8 R2526 1 2 10K_0402_5%
[22] LAN_CLKREQ# PCIECLKRQ2/GPIO20 TESTLOW_AL8
+3VS R2340 1 2 10K_0402_5%
B38 AN15 CLKOUT_LPC0 R2336 2 EMI@ 1 22_0402_5%
[25] CLK_PCIE_WLAN# CLKOUT_PCIE_N3 CLKOUT_LPC_0 CLK_PCI_MEC [29]
WLAN(Mini Card)---> C37 AP15 CLKOUT_LPC1 R2339 2 1 22_0402_5%
[25] CLK_PCIE_WLAN CLKOUT_PCIE_P3 CLKOUT_LPC_1 CLK_PCI_LPDEBUG [29]
N1 EMI@
[25] WLAN_CLKREQ# PCIECLKRQ3/GPIO21
+3VS R2342 1 2 10K_0402_5% B35
CLK_PCIE_GFX# A39 CLKOUT_ITPXDP_N A35
[45] CLK_PCIE_GFX# CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P
CLK_PCIE_GFX B39
[45] CLK_PCIE_GFX CLKOUT_PCIE_P4
GFXCLK_REQ# U5
[45] GFXCLK_REQ# PCIECLKRQ4/GPIO22
+3VS R2345 1 2 10K_0402_5%
B37
A37 CLKOUT_PCIE_N5
R2344 1 2 10K_0402_5% T2 CLKOUT_PCIE_P5
+3VS PCIECLKRQ5/GPIO23
6 OF 19 Rev1p2
@
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 9 of 54
5 4 3 2 1
5 4 3 2 1
JAPS
+3VALW_PCH 1
SIO_SLP_S3# 2 1
+3VS 3 2
D +3V_DSW 3 D
SIO_SLP_S5# 4
@ CC11 SIO_SLP_S4# 5 4
X02.08 1 2 SIO_SLP_A# 6 5
RC78 1 @ 2 0_0402_5% 7 6
+3V_DSW 7
0.1U_0402_10V7K 8
9 8
[8] PCH_RTCRST# 9
10
10
5
+3VS +3VS 11
[27,29] POWER_SW#_MB 11
12
VCC
PCH_PLTRST# 1 SYS_RESET# 13 12
IN1 13
5
1 2 CLKRUN# 4 14
OUT PCH_PLTRST#_EC [6,22,25,29] 14
RC36 10K_0402_5% 1 2 SIO_SLP_S0# 15
GND
[6] XDP_DBRESET# B IN2 15
1 2 ME_RESET# 4 SYS_RESET# 1 16
O 16
1
@ RC95 8.2K_0402_5% 2 1 ME_RESET# 2 CC33 ESD@ UC3 17
A 17
G
@ RC80 8.2K_0402_5% @ UC5 MC74VHC1G08DFT2G_SC70-5 R159 1 @ 2 18
PLTRST_GPU# [45]
3
74AHC1G09GW_TSSOP5 0.047U_0402_16V4Z 100K_0402_5% RC367 0_0402_1% 19 18
3
2 20 GND
+3VALW_PCH GND
2
Place CC33 CONN@
1 2 ME_SUS_PWR_ACK ACES_50506-01841-P01
RC27 10K_0402_5% close to UC3.1 & UC3.2
1 2 SUSACK#
RC28 10K_0402_5%
1 2 SUS_STAT#/LPCPD#
@ RC29 10K_0402_5%
+3V_DSW
1 2 PCH_BATLOW#
RC39 10K_0402_5%
1 2 AC_PRESENT
RC32 10K_0402_5% DSWODVREN ‐ ON DIE DSW VR ENABLE
1 2 PCH_PCIE_WAKE#_R +RTCVCC
C RC34 10K_0402_5% HIGH = ENABLED (DEFAULT) C
HASWELL_MCP_E
UC1H
R2337 1 2 330K_0402_5%
1 @ 2 PCH_RSMRST#_R R2338 1 @ 2 330K_0402_5%
RC92 10K_0402_5% X02.08 SYSTEM POWER MANAGEMENT LOW = DISABLED
SUSACK# RC37 1 @ 2 0_0402_5% SUSACK#_R AK2 AW7 DSWODVREN
[29] SUSACK#
SYS_RESET# AC3 SUSACK DSWVRMEN AV5 X02.08
SYS_RESET DPWROK PCH_DPWROK [29]
RC40 1 @ 2 0_0402_5% SYS_PWROK_R AG2 AJ5 PCH_PCIE_WAKE#_R 1 @ 2
[6,29] SYS_PWROK SYS_PWROK WAKE PCH_PCIE_WAKE# [28,29]
RC47 1 @ 2 0_0402_5% RESET_OUT#_R AY7 RC97 0_0402_5%
[13,29] RESET_OUT# PCH_PWROK
RC55 1 @ 2 0_0402_5% PM_APWROK_R AB5
PCH_PLTRST# AG7 APWROK V5 CLKRUN#
PLTRST CLKRUN/GPIO32 CLKRUN# [29]
AG4 SUS_STAT#/LPCPD#
SUS_STAT/GPIO61 AE6 SUSCLK_R RC107 1 @ 2 0_0402_5%
SUSCLK/GPIO62 SUSCLK [25]
AP5 SIO_SLP_S5#
SLP_S5/GPIO63 SIO_SLP_S5# [29]
RESET_OUT# SYS_PWROK RC41 1 @ 2 0_0402_5% PCH_RSMRST#_R AW6
[29] PCH_RSMRST# RSMRST
1 1 RC42 1 @ 2 0_0402_5% ME_SUS_PWR_ACK_R AV4
[29] ME_SUS_PWR_ACK SUSWARN/SUSPWRDNACK/GPIO30
CC34 @ CC31 @ AL7 AJ6 SIO_SLP_S4#
[6,29] SIO_PWRBTN# PWRBTN SLP_S4 SIO_SLP_S4# [29]
AC_PRESENT AJ8 AT4 SIO_SLP_S3#
[29] AC_PRESENT ACPRESENT/GPIO31 SLP_S3 SIO_SLP_S3# [29]
0.047U_0402_16V4Z 0.047U_0402_16V4Z PCH_BATLOW# AN4 AL5 SIO_SLP_A#
2 2 SIO_SLP_S0# AF3 BATLOW/GPIO72 SLP_A AP4 SIO_SLP_SUS#
SLP_S0 SLP_SUS SIO_SLP_SUS# [29]
AM5 AJ7
[28] SIO_SLP_WLAN# SLP_WLAN/GPIO29 SLP_LAN
Place CC34 Place CC31
close to RP50.2&RP50.3 on BOT PCH_BATLOW# Need pull high to VCCDSW3_3
(If no deep Sx , connect to VCCSUS3_3) 8 OF 19 Rev1p2
@
B +3VS B
HASWELL_MCP_E
UC1I
RP52
+3VS CPU_DPB_CTRLDAT 1 8
CPU_DPB_CTRLCLK 2 7
X02.08 CPU_DPC_CTRLCLK 3 6
EDP_BIA_PWM 1 @ 2 EDP_BKLCTL B8 B9 CPU_DPB_CTRLCLK CPU_DPC_CTRLDAT 4 5
[6,21] EDP_BIA_PWM EDP_BKLCTL DDPB_CTRLCLK CPU_DPB_CTRLCLK [19]
RP43 RC81 0_0402_5% A9 C9 CPU_DPB_CTRLDAT
[21] PANEL_BKLEN EDP_BKLEN eDP SIDEBAND DDPB_CTRLDATA CPU_DPB_CTRLDAT [19]
1 8 SIO_RCIN# ENVDD_PCH C6 D9 CPU_DPC_CTRLCLK
SIO_RCIN# [11,29] [21,29] ENVDD_PCH EDP_VDDEN DDPC_CTRLCLK 2.2K_0804_8P4R_5%
2 7 PCH_GPIO36 D11 CPU_DPC_CTRLDAT
PCH_GPIO36 [8] DDPC_CTRLDATA
3 6 DGPU_PWROK
RP51
4 5 PCH_GPIO80
PCH_GPIO77 U6 CPU_DPB_AUX# 1 8
[11] PCH_GPIO77 PIRQA/GPIO77
10K_8P4R_5% DGPU_PWROK P4 C5 CPU_DPB_AUX# CPU_DPB_AUX 2 7
[28,44,45] DGPU_PWROK PIRQB/GPIO78 DISPLAY DDPB_AUXN
N4 B6 CPU_DPC_AUX# CPU_DPC_AUX 3 6
[11] PCH_GPIO79 PIRQC/GPIO79 DDPC_AUXN CPU_DPC_AUX# [20]
1 @ 2 EDP_BIA_PWM PCH_GPIO80 N2 B5 CPU_DPB_AUX CPU_DPC_AUX# 4 5
RC75 10K_0402_5% T117 @ AD4 PIRQD/GPIO80 DDPB_AUXP A6 CPU_DPC_AUX
PME GPIO DDPC_AUXP CPU_DPC_AUX [20]
U7 100K_0804_8P4R_5%
1 2 DGPU_PWR_EN L1 GPIO55
RC370 10K_0402_5% DGPU_PWR_EN L3 GPIO52 C8 DPC_HPD 2 1
[49] DGPU_PWR_EN GPIO54 DDPB_HPD DPB_HPD [19]
DGPU_CORE_EN R5 A8 DPC_HPD RC84 @ 100K_0402_5%
GPIO51 DDPC_HPD DPC_HPD [20]
L4 D6 CPU_EDP_HPD
GPIO53 EDP_HPD CPU_EDP_HPD [21]
CPU_EDP_HPD 1 2
RC89 100K_0402_5%
9 OF 19 Rev1p2
1 @ 2 DGPU_PWR_EN @
RC368 10K_0402_5%
1 @ 2 DGPU_CORE_EN
RC369 10K_0402_5%
A
1 2 ENVDD_PCH A
@ RC87 100K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 10 of 54
5 4 3 2 1
5 4 3 2 1
D D
+1.05VS
Close to R2353
1
CC28 +1.05VS
100P_0402_50V8J
@
1
UC1J HASWELL_MCP_E 2
ESD solution R2353
1K_0402_5%
+3V_DSW X02.08
2
PCH_GPIO76 P1 D60 H_THERMTRIP#_R R2355 1 @ 2 0_0402_5% H_THERMTRIP#
BMBUSY/GPIO76 THERMTRIP H_THERMTRIP# [29]
SIO_EXT_WAKE# AU2 V4 H_THERMTRIP#
[29] SIO_EXT_WAKE# GPIO8 RCIN/GPIO82 SIO_RCIN# [10,29]
RC153 1 2 10K_0402_5% LAN_WAKE# PCH_GPIO12 AM7 T4 IRQ_SERIRQ
@ T182 PAD~D LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ IRQ_SERIRQ [29]
HOST_ALERT1_R_N AD6 AW15 PCH_OPI_COMP 1 2
Y1 GPIO15 MISC PCH_OPI_RCOMP AF20
T3 GPIO16 RSVD AB21 RC101 +3VS
AD5 GPIO17 RSVD 49.9_0402_1%
+3VS LAN_WAKE# AN5 GPIO24
[22,29] LAN_WAKE# GPIO27
AD7
AN3 GPIO28
RC98 1 2 100K_0402_5% SIO_EXT_SCI# GPIO26 R6 GC6_EVENT#
GSPI0_CS/GPIO83 PAD~D T177 @
AG6 L6 GPU_GC6_FB_EN IRQ_SERIRQ 2 1
GPIO56 GSPI0_CLK/GPIO84 PAD~D T176 @
RC116 2 1 10K_0402_5% PCH_GPIO76 AP1 N6 PCH_GPIO85 10K_0402_5% RC102
GPIO57 GSPI0_MISO/GPIO85 PAD~D T175 @
AL4 L8 BBS_BIT LCD_CBL_DET# 2 1
AT5 GPIO58 GSPI0_MOSI/GPIO86 R7 PCH_GPIO87 10K_0402_5% RC106
GPIO59 GSPI1_CS/GPIO87 PAD~D T4931@
AK4 L5 CPPE# 2 @ 1
PCH_GPIO47 AB6 GPIO44 GPIO GSPI1_CLK/GPIO88 N7 TS_EN 100K_0402_5% RC108
C @ T174 PAD~D GPIO47 GSPI1_MISO/GPIO89 TS_EN [21] C
+3VALW_PCH PCH_GPIO48 U4 K2 PCH_GPIO90 CPUSB# 2 @ 1
@ T124 PAD~D GPIO48 GSPI_MOSI/GPIO90 PAD~D T179 @
DGPU_HOLD_RST# Y3 J1 CPPE# 10K_0402_5% RC111
[45] DGPU_HOLD_RST# GPIO49 UART0_RXD/GPIO91
P3 K3 CPUSB#
Y2 GPIO50 UART0_TXD/GPIO92 J2 PCH_GPIO93
HSIOPC/GPIO71 LPIO UART0_RTS/GPIO93 PAD~D T180 @
RC109 2 1 10K_0402_5% SIO_EXT_WAKE# KB_DET# AT3 G1 PCH_GPIO94 RP53
[30] KB_DET# GPIO13 UART0_CTS/GPIO94 PAD~D T181 @
PCH_GPIO14 AH4 K4 I2C1_SDA_TCH_PAD 1 8
@ T126 PAD~D GPIO14 UART1_RXD/GPIO0
RC105 2 1 10K_0402_5% SIO_EXT_SMI# PCH_GPIO25 AM4 G2 I2C1_SCL_TCH_PAD 2 7
@ T127 PAD~D GPIO25 UART1_TXD/GPIO1
SIO_EXT_SMI# AG5 J3 LCD_CBL_DET# I2C0_SDA 3 6
[29] SIO_EXT_SMI# GPIO45 UART1_RST/GPIO2 LCD_CBL_DET# [21]
RC103 2 1 10K_0402_5% KB_DET# AG3 J4 I2C0_SCL 4 5
GPIO46 UART1_CTS/GPIO3 F2 I2C0_SDA
RC117 2 1 10K_0402_5% PCH_GPIO12 AM3 I2C0_SDA/GPIO4 F3 I2C0_SCL 2.2K_0804_8P4R_5%
PCH_GPIO10 AM2 GPIO9 I2C0_SCL/GPIO5 G4 I2C1_SDA_TCH_PAD
@ T27 PAD~D GPIO10 I2C1_SDA/GPIO6
P2 F1 I2C1_SCL_TCH_PAD RP60
C4 DEVSLP0/GPIO33 I2C1_SCL/GPIO7 E3 PCH_GPIO77 8 1
SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 [10] PCH_GPIO77
L2 F4 CAM_MIC_CBL_DET# TS_EN 7 2
[26] HDD_DEVSLP DEVSLP1/GPIO38 SDIO_CMD/GPIO65 CAM_MIC_CBL_DET# [21]
SIO_EXT_SCI# N5 D3 PCH_GPIO66 PCH_GPIO79 6 3
[29] SIO_EXT_SCI# DEVSLP2/GPIO39 SDIO_D0/GPIO66 [10] PCH_GPIO79
HDA_SPKR V2 E4 CAM_MIC_CBL_DET# 5 4
[23] HDA_SPKR SPKR/GPIO81 SDIO_D1/GPIO67 C3
SDIO_D2/GPIO68 E2 10K_8P4R_5%
SDIO_D3/GPIO69
10 OF 19 Rev1p2
@
+3VS +3VS
+3VALW_PCH +3VS
B B
1
1
@ RC119
RC118 10K_0402_5% @
1K_0402_5% RC120 RC121
1K_0402_5% 1K_0402_5%
2
2
PCH_GPIO66 BBS_BIT
PCH_GPIO66 has internal pull down 20k PCH_GPIO86 has internal pull down 20k HOST_ALERT1_R_N HDA_SPKR
GPIO66 GPIO86 GPIO15 GPIO81
TOP‐BLOCK SWAP OVERRIDE BOOT BIOS STRAP BIT BBS TLS CONFIDENTIALITY NO REBOOT STRAP
HIGH depop RC118 (DEFAULT) HIGH LPC HIGH HIGH disable
LOW pop RC122 LOW(DEFAULT) SPI LOW(DEFAULT) LOW(DEFAULT) enable
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 11 of 54
5 4 3 2 1
5 4 3 2 1
PEG_CTX_GRX_P[0..3]
[45] PEG_CTX_GRX_P[0..3]
PEG_CTX_GRX_N[0..3]
[45] PEG_CTX_GRX_N[0..3]
PEG_CRX_GTX_P[0..3]
D [45] PEG_CRX_GTX_P[0..3] D
PEG_CRX_GTX_N[0..3]
[45] PEG_CRX_GTX_N[0..3]
HASWELL_MCP_E
UC1K
PEG_CRX_GTX_N0 F10 AN8
PERN5_L0 USB2N0 USB20_JUSB1_N0 [24]
PEG_CRX_GTX_P0 E10 AM8 USB Conn JUSB1
PERP5_L0 USB2P0 USB20_JUSB1_P0 [24]
PEG_CTX_GRX_N0 CC18 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N0_C C23 AR7
PETN5_L0 USB2N1 USB20_JUSB2_N1 [24]
PEG_CTX_GRX_P0 CC19 2 1 0.22U_0402_16V7K PEG_CTX_GRX_P0_C C22 AT7 USB Conn JUSB2
PETP5_L0 USB2P1 USB20_JUSB2_P1 [24]
PEG_CRX_GTX_N1 F8 AR8
PERN5_L1 USB2N2 USB20_JUSB3_N2 [27]
PEG_CRX_GTX_P1 E8 AP8 USB Conn JUSB3
PERP5_L1 USB2P2 USB20_JUSB3_P2 [27]
PEG_CTX_GRX_N1 CC20 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N1_C B23 AR10
PETN5_L1 USB2N3 USB20_BIO_N3 [26]
PEG_CTX_GRX_P1 CC21 2 1 0.22U_0402_16V7K PEG_CTX_GRX_P1_C A23 AT10 Finger print
PETP5_L1 USB2P3 USB20_BIO_P3 [26]
PEG_CRX_GTX_N2 H10 AM15
PERN5_L2 USB2N4 USB20_MINI1_N4 [25]
PEG_CRX_GTX_P2 G10 AL15 Mini Card (WLAN)
PERP5_L2 USB2P4 USB20_MINI1_P4 [25]
PEG_CTX_GRX_N2 CC22 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N2_C B21 AM13
PETN5_L2 USB2N5 USB20_TOUCH_N5 [21]
PEG_CTX_GRX_P2 CC23 2 1 0.22U_0402_16V7K PEG_CTX_GRX_P2_C C21 AN13 Touch screen panel
PETP5_L2 USB2P5 USB20_TOUCH_P5 [21]
PEG_CRX_GTX_N3 E6 AP11
PERN5_L3 USB2N6 USB20_CR_N6 [27]
PEG_CRX_GTX_P3 F6 AN11 Card Reader
PERP5_L3 USB2P6 USB20_CR_P6 [27]
PEG_CTX_GRX_N3 CC24 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N3_C B22 AR13
PETN5_L3 USB2N7 USB20_CAM_N7 [21]
PEG_CTX_GRX_P3 CC25 2 1 0.22U_0402_16V7K PEG_CTX_GRX_P3_C A21 AP13 Camera
PETP5_L3 USB2P7 USB20_CAM_P7 [21]
C C
G11
[22] PCIE_PRX_LANTX_N3 PERN3
F11 G20
[22] PCIE_PRX_LANTX_P3 PERP3 USB3RN1 USB3RN1_JUSB1 [24]
LAN H20
USB3RP1 USB3RP1_JUSB1 [24]
CC32 1 2 0.1U_0402_10V7K PCIE_PTX_LANRX_N3_C C29 USB Conn JUSB1
[22] PCIE_PTX_LANRX_N3 PETN3 USB
CC40 1 2 0.1U_0402_10V7K PCIE_PTX_LANRX_P3_C B30 PCIe C33 +3VALW_PCH
[22] PCIE_PTX_LANRX_P3 PETP3 USB3TN1 USB3TN1_JUSB1 [24]
B34
USB3TP1 USB3TP1_JUSB1 [24]
F13 USB_OC0# 1 8
[25] PCIE_PRX_WLANTX_N4 PERN4
G13 E18 USB_OC1# 2 7
[25] PCIE_PRX_WLANTX_P4 PERP4 USB3RN2 USB3RN2_JUSB2 [24]
NGFF WLAN F18 USB_OC2# 3 6
USB3RP2 USB3RP2_JUSB2 [24]
B29 USB Conn JUSB2 USB_OC3# 4 5
[25] PCIE_PTX_WLANRX_N4 PETN4
A29 B33
[25] PCIE_PTX_WLANRX_P4 PETP4 USB3TN2 USB3TN2_JUSB2 [24]
A33 RP55
USB3TP2 USB3TP2_JUSB2 [24]
G17 10K_8P4R_5%
F17 PERN1/USB3RN3
PERP1/USB3RP3
C30
C31 PETN1/USB3TN3 AJ10 USBRBIAS
PETP1/USB3TP3 USBRBIAS AJ11
F15 USBRBIAS AN10 PAD~D T118 @
PERN2/USB3RN4 RSVD CAD NOTE:
1
G15 AM10 PAD~D T119 @
PERP2/USB3RP4 RSVD RC90
Route single-end 50-ohms and max 500-mils length.
B31 22.6_0402_1% Avoid routing next to clock pins or under stitching capacitors.
PETN2/USB3TN4
A31
PETP2/USB3TP4
Recommended minimum spacing to other signal traces is 15 mils.
AL3 USB_OC0#
USB_OC0# [24]
2
OC0/GPIO40 AT1 USB_OC1#
OC1/GPIO41 USB_OC1# [24]
AH2 USB_OC2#
OC2/GPIO42 USB_OC2# [27]
RC91 @ T120PAD~D E15 AV3 USB_OC3#
3.01K_0402_1% @ T121PAD~D E13 RSVD OC3/GPIO43
1 2 PCH_PCIE_RCOMP A27 RSVD
+1.05VS_AUSB3PLL PCIE_RCOMP
B27
PCIE_IREF
11 OF 19 Rev1p2
@
B B
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 12 of 54
5 4 3 2 1
5 4 3 2 1
+CPU_CORE +1.35V
+1.05VS +VCCIO_OUT C40
1 2
+1.05VS
1 @ 2 22U_0603_6.3V6M
R245 0_0603_5% ESD@
1
RC363 RESISTOR STUFFING OPTIONS ARE
@ 10K_0402_5% ESD solution
PROVIDED FOR TESTING PURPOSES
2
D D
VR_ON 2 1 H_VR_READY
1 1.5K_0402_5% RC364
UC1L HASWELL_MCP_E
C80 @ +CPU_CORE
0.1U_0402_10V7K L59 C36
2 +1.35V J58 RSVD VCC C40
RSVD VCC C44
AH26 VCC C48
Place C80 AJ31 VDDQ VCC C52
close to R250.1 AJ33 VDDQ VCC C56
AJ37 VDDQ VCC E23
AN33 VDDQ VCC E25
AP43 VDDQ VCC E27
AR48 VDDQ VCC E29
+1.05VS AY35 VDDQ VCC E31
AY40 VDDQ VCC E33
+3VALW AY44 VDDQ VCC E35
VDDQ VCC
2
+CPU_CORE AY50 E37
UC6 VDDQ VCC E39
1 5 1 2 RC365 F59 VCC E41
NC VCC @ CC41 0.1U_0402_25V6 1K_0402_5% N58 VCC VCC E43
2 AC58 RSVD VCC E45
[10,29] RESET_OUT#
1
A 4 H_VCCST_PWRGD +VCCIO_OUT RSVD VCC E47
3 Y VCCSENSE E63 VCC E49
GND T38 @ AB23 VCC_SENSE VCC E51
1 RSVD VCC
74AUP1G07GW_TSSOP5 EMI@ A59 E53
CC42 E20 VCCIO_OUT VCC E55
+VCCIOA_OUT VCCIOA_OUT VCC
100P_0402_50V8J AD23 E57
X02.23 2 AA23 RSVD 12 OF 19 VCC F24
AE59 RSVD VCC F28
RSVD VCC F32
X02.08 H_CPU_SVIDALRT# L62 VCC F36
1 @ 2 H_CPU_SVIDCLK N63 VIDALERT VCC F40
[38] VR_SVID_CLK VIDSCLK VCC
R248 0_0402_5% H_CPU_SVIDDATA L63 F44
H_VCCST_PWRGD B59 VIDSOUT HSW ULT POWER VCC F48
+1.05VS [6] H_VCCST_PWRGD VCCST_PWRGD VCC
1 @ 2 VR12.5_VR_ON_R F60 F52
C
SVID ALERT [38]
[38] VR_ON
H_VR_READY
R250 1 @ 2 0_0402_5% VR_READY_R C59 VR_EN
VR_READY
VCC
VCC
F56 C
R251 0_0402_5% G23
VCC
1
Place the PU D63 G25
R252 CPU_PWR_DEBUG# H59 VSS VCC G27
75_0402_5%
resistors close to CPU [6] CPU_PWR_DEBUG#
P62 PWR_DEBUG VCC G29
T39 @ P60 VSS VCC G31
R254 T40 @ P61 RSVD_TP VCC G33
2
43_0402_1% T41 @ N59 RSVD_TP VCC G35
2 1 H_CPU_SVIDALRT# T42 @ N61 RSVD_TP VCC G37
[38] VR_SVID_ALRT# RSVD_TP VCC
H_CPU_SVIDCLK T43 @ T59 G39
T44 @ AD60 RSVD VCC G41
T45 @ AD59 RSVD VCC G43
1 RSVD VCC
T46 @ AA59 G45
C5212 @ T47 @ AE60 RSVD VCC G47
+1.05VS 68P_0402_50V8J T48 @ AC59 RSVD VCC G49
SVID DATA 2 T49 @ AG58 RSVD
RSVD
VCC
VCC
G51
Place the PU +1.05VS T50 @ U59 G53
T51 @ V59 RSVD VCC G55
SVID_DAT need to pull-up double side resistors close to CPU RSVD VCC
1
G57
( PWR_VR & CPU ) R256 AC22 VCC H23
X02.08 130_0402_1% +CPU_CORE AE22 VCCST VCC J23
AE23 VCCST VCC K23
R257 VCCST VCC K57
2
0_0402_5% AB57 VCC L22
2 @ 1 H_CPU_SVIDDATA AD57 VCC VCC M23
[38] VR_SVID_DAT VCC VCC
AG57 M57
C24 VCC VCC P57
C28 VCC VCC U57
C32 VCC VCC W57
VCC VCC
+CPU_CORE Rev1p2
@
1
R1
B 100_0402_1% B
+1.35V
2
VDDQ DECOUPLING
VCCSENSE
CAD Note: PU resistor on HW side
[38] VCCSENSE close to process
+1.35V : 470UF/2V/7343 *2 (PWR)
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
C35
C36
C37
C38
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
+1.05VS 1 1 1 1 1 1 1 1 1 1 10UF/6.3V/0603 * 6
2.2UF/6.3V/0402 * 4
C39
C41
C72
C42
C45
C74
2 2 2 2 2 2 2 2 2 2
2
R253
150_0402_1%
1
CPU_PWR_DEBUG# R253
INTEL Check list , XDP use only
2
@
R255
10K_0402_5%
1
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 13 of 54
5 4 3 2 1
5 4 3 2 1
D D
+1.05VS_AUSB3PLL
+1.05VS
C58 1 2 1U_0402_6.3V6K
L1 1 2 C59 1 2 100U_1206_6.3V6M
2.2UH_LQM2MPN2R2NG0L_30%
UC1M HASWELL_MCP_E
+RTCVCC
+1.05VS_ASATA3PLL K9
+1.05VS VCCHSIO
L10 0_0603_5% 2 1 R264 +3VALW_PCH
M9 VCCHSIO
VCCHSIO
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
L2 1 2 C63 1 2 1U_0402_6.3V6K N8 mPHY AH11 C51 1 2 1U_0402_6.3V6K
+1.05VS VCC1_05 RTC VCCSUS3_3
C65 1 2 100U_1206_6.3V6M P9 AG10 +RTCVCC 1 1 1
2.2UH_LQM2MPN2R2NG0L_30% B18 VCC1_05 VCCRTC AE7
+1.05VS_AUSB3PLL VCCUSB3PLL DCPRTC
C54
C55
C56
+1.05VS_ASATA3PLL B11 +VCCRTCEXT C52 1 2 0.1U_0402_10V7K
R267 +1.05VS_APLLOPI VCCSATA3PLL
+3VS 2 2 2
0_0805_5%
1 2 Y20 SPI Y8 @ C68 1 2 0.1U_0402_10V7K
C69 1 2 1U_0402_6.3V6K AA21 RSVD OPI VCCSPI
+1.05VS_APLLOPI VCCAPLL
L3 1 @ 2 C70 @
@1 2 100U_1206_6.3V6M W21
2.2UH_LQM2MPN2R2NG0L_30% VCCAPLL AG14
VCCASW +1.05VS
AG13
+PCH_VCC1P05 VCCASW
USB3
+1.05VS
T53 @ J13
DCPSUS3 J11 C60 1 2 10U_0603_6.3V6M
C83 1 2 1U_0402_6.3V6K VCC1_05 H11 C61 1 2 1U_0402_6.3V6K
L4 1 2 C84 1 2 100U_1206_6.3V6M AH14 AXALIA/HDA VCC1_05 H15 C62 1 2 1U_0402_6.3V6K
+VCCHDA VCCHDA VCC1_05 +1.05VS
2.2UH_LQM2MPN2R2NG0L_30% AE8 C64 +3VS
C VCC1_05 AF22 X02.08 1U_0402_6.3V6K C44
C
T55 @ AH13 VRM/USB2/AZALIA VCC1_05 AG19 +PCH_VCCDSW 1 @ 2+PCH_VCCDSW_R 1 2 1 2
+PCH_VCCACLKPLL DCPSUS2 CORE DCPSUSBYP AG20 R265 0_0402_5%
DCPSUSBYP +PCH_VCCDSW
AE9 +1.05VS 22U_0603_6.3V6M
C85 1 2 1U_0402_6.3V6K VCCASW AF9 @ C66 1 2 22U_0603_6.3V6M ESD@
L5 1 2 C86 1 2 100U_1206_6.3V6M AC9 VCCASW AG8 C67 1 2 1U_0402_6.3V6K
+3VALW_PCH VCCSUS3_3 VCCASW
2.2UH_LQM2MPN2R2NG0L_30% AA9 AD10
+3V_DSW AH10 VCCSUS3_3 DCPSUS1 AD8 T58 @ ESD solution
V8 VCCDSW3_3 GPIO/LCC DCPSUS1 T59 @
+3VS VCC3_3
W9
VCC3_3 J15
THERMAL SENSOR VCCTS1_5 +1.5VS
+3V_DSW C1313 1 2 0.47U_0402_10V4 +PCH_VCCDSW K14 +3VS
VCC3_3 K16 C71 1 2 0.1U_0402_10V7K
VCC3_3 +1.05VS +1.35V
@
C43
+PCH_VCC1P05 J18 1 2
K19 VCCCLK SDIO/PLSS U8
VCCCLK VCCSDIO +3VS
+PCH_VCCACLKPLL A20 T9 C73 1 2 1U_0402_6.3V6K 22U_0603_6.3V6M
+3VALW_PCH +VCCHDA J17 VCCACLKPLL VCCSDIO ESD@
+1.05VS VCCCLK
+1.05VS R21
RC127 1 2 0_0402_5% T21 VCCCLK LPT LP POWER
K18 VCCCLK SUS OSCILLATOR AB8 T56 @ ESD solution
M20 RSVD DCPSUS4
C77 1 2 0.1U_0402_10V7K V21 RSVD
+VCCHDA RSVD
+3VALW_PCH AE20 AC20
AE21 VCCSUS3_3 RSVD AG16
Reserve for HDA issue, C77 close to AH14 VCCSUS3_3 USB2 VCC1_05 AG17
+1.05VS
VCC1_05 C76 1 2 1U_0402_6.3V6K
13 OF 19 Rev1p2
@
C50 1 2 1U_0402_6.3V6K
+1.05VS C53 1 2 1U_0402_6.3V6K Close to K9,M9
B B
+3VALW_PCH C81 1 2 0.1U_0402_10V7K Close to AH10
@
+3VALW_PCH C78 1 2 22U_0603_6.3V6M Close to AC9/AA9/AE20/AE21
+3VS C82 1 2 22U_0603_6.3V6M Close to V8
+1.05VS C87 1 2 1U_0402_6.3V6K Close to J17
+1.05VS C88 1 2 1U_0402_6.3V6K Close to R21
+1.05VS C57 1 2 1U_0402_6.3V6K Close to N8
@
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 14 of 54
5 4 3 2 1
5 4 3 2 1
D D
HASWELL_MCP_E HASWELL_MCP_E
UC1N UC1O UC1P HASWELL_MCP_E
H17
A11 AJ35 AP22 AV59 D33 VSS H57
A14 VSS VSS AJ39 AP23 VSS VSS AV8 D34 VSS VSS J10
A18 VSS VSS AJ41 AP26 VSS VSS AW16 D35 VSS VSS J22
A24 VSS VSS AJ43 AP29 VSS VSS AW24 D37 VSS VSS J59
A28 VSS VSS AJ45 AP3 VSS VSS AW33 D38 VSS VSS J63
A32 VSS VSS AJ47 AP31 VSS VSS AW35 D39 VSS VSS K1
A36 VSS VSS AJ50 AP38 VSS VSS AW37 D41 VSS VSS K12
A40 VSS VSS AJ52 AP39 VSS VSS AW4 D42 VSS VSS L13
A44 VSS VSS AJ54 AP48 VSS VSS AW40 D43 VSS VSS L15
A48 VSS VSS AJ56 AP52 VSS VSS AW42 D45 VSS VSS L17
A52 VSS VSS AJ58 AP54 VSS VSS AW44 D46 VSS VSS L18
A56 VSS VSS AJ60 AP57 VSS VSS AW47 D47 VSS VSS L20
AA1 VSS VSS AJ63 AR11 VSS VSS AW50 D49 VSS VSS L58
AA58 VSS VSS AK23 AR15 VSS VSS AW51 D5 VSS VSS L61
AB10 VSS VSS AK3 AR17 VSS VSS AW59 D50 VSS VSS L7
AB20 VSS VSS AK52 AR23 VSS VSS AW60 D51 VSS VSS M22
AB22 VSS VSS AL10 AR31 VSS VSS AY11 D53 VSS VSS N10
C VSS VSS VSS VSS VSS VSS C
AB7 AL13 AR33 AY16 D54 N3
AC61 VSS VSS AL17 AR39 VSS VSS AY18 D55 VSS VSS P59
AD21 VSS VSS AL20 AR43 VSS VSS AY22 D57 VSS VSS P63
AD3 VSS VSS AL22 AR49 VSS VSS AY24 D59 VSS VSS R10
AD63 VSS VSS AL23 AR5 VSS VSS AY26 D62 VSS VSS R22
AE10 VSS VSS AL26 AR52 VSS VSS AY30 D8 VSS VSS R8
AE5 VSS VSS AL29 AT13 VSS VSS AY33 E11 VSS VSS T1
AE58 VSS VSS AL31 AT35 VSS VSS AY4 E17 VSS VSS T58
AF11 VSS VSS AL33 AT37 VSS VSS AY51 F20 VSS VSS U20
AF12 VSS VSS AL36 AT40 VSS VSS AY53 F26 VSS VSS U22
AF14 VSS VSS AL39 AT42 VSS VSS AY57 F30 VSS VSS U61
AF15 VSS VSS AL40 AT43 VSS VSS AY59 F34 VSS VSS U9
AF17 VSS VSS AL45 AT46 VSS VSS AY6 F38 VSS VSS V10
AF18 VSS VSS AL46 AT49 VSS VSS B20 F42 VSS VSS V3
AG1 VSS VSS AL51 AT61 VSS VSS B24 F46 VSS VSS V7
AG11 VSS VSS AL52 AT62 VSS VSS B26 F50 VSS VSS W20
AG21 VSS VSS AL54 AT63 VSS VSS B28 F54 VSS VSS W22
AG23 VSS VSS AL57 AU1 VSS VSS B32 F58 VSS VSS Y10
AG60 VSS VSS AL60 AU16 VSS VSS B36 F61 VSS VSS Y59
AG61 VSS VSS AL61 AU18 VSS VSS B4 G18 VSS VSS Y63
AG62 VSS VSS AM1 AU20 VSS VSS B40 G22 VSS VSS
AG63 VSS VSS AM17 AU22 VSS VSS B44 G3 VSS
AH17 VSS VSS AM23 AU24 VSS VSS B48 G5 VSS V58
AH19 VSS VSS AM31 AU26 VSS VSS B52 G6 VSS VSS AH46
AH20 VSS VSS AM52 AU28 VSS VSS B56 G8 VSS VSS V23
AH22 VSS VSS AN17 AU30 VSS VSS B60 H13 VSS VSS E62
VSS VSS VSS VSS VSS VSS_SENSE VSSSENSE [38]
AH24 AN23 AU33 C11 AH16
AH28 VSS VSS AN31 AU51 VSS VSS C14 16 OF 19 Rev1p2 VSS
AH30 VSS VSS AN32 AU53 VSS VSS C18
VSS VSS VSS VSS @
1
AH32 AN35 AU55 C20
AH34 VSS VSS AN36 AU57 VSS VSS C25
AH36 VSS VSS AN39 AU59 VSS VSS C27 R2
AH38 VSS VSS AN40 AV14 VSS VSS C38 100_0402_1%
AH40 VSS VSS AN42 AV16 VSS VSS C39
2
AH42 VSS VSS AN43 AV20 VSS VSS C57
AH44 VSS VSS AN45 AV24 VSS VSS D12
AH49 VSS VSS AN46 AV28 VSS VSS D14
B VSS VSS VSS VSS B
AH51 AN48 AV33 D18
AH53 VSS VSS AN49 AV34 VSS VSS D2
AH55 VSS VSS AN51 AV36 VSS VSS D21
close to process
AH57 VSS VSS AN52 AV39 VSS VSS D23
AJ13 VSS VSS AN60 AV41 VSS VSS D25
AJ14 VSS VSS AN63 AV43 VSS VSS D26
AJ23 VSS VSS AN7 AV46 VSS VSS D27
AJ25 VSS VSS AP10 AV49 VSS VSS D29
AJ27 VSS VSS AP17 AV51 VSS VSS D30
AJ29 VSS VSS AP20 AV55 VSS VSS D31
VSS VSS VSS 15 OF 19 Rev1p2 VSS
@
14 OF 19 Rev1p2
@
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 15 of 54
5 4 3 2 1
5 4 3 2 1
D D
HASWELL_MCP_E
UC1R
HASWELL_MCP_E
UC1Q
@
N23 RSVD_N23 PAD~D T129
RSVD @
DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3 R23 RSVD_R23 PAD~D T130
DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 RSVD @
DC_TEST_AY3_AW3 AY3 A4 DC_TEST_A4 PAD~D T168 @ @ T23 RSVD_T23 PAD~D T131
DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4 T128 PAD~D RSVD_AT2 AT2 RSVD @
@ T166PAD~D DC_TEST_AY60 AY60 @ RSVD U10 RSVD_U10 PAD~D T133
DAISY_CHAIN_NCTF_AY60 T132 PAD~D RSVD_AU44 AU44 RSVD
DC_TEST_AY61_AW61 AY61 A60 DC_TEST_A60 PAD~D T169 @ @ RSVD
DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 T134 PAD~D RSVD_AV44 AV44
DC_TEST_AY62_AW62 AY62 A61 DC_TEST_A61_B61 @ RSVD
DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 T135 PAD~D RSVD_D15 D15 @
@ T167PAD~D TP_DC_TEST_B2 B2 A62 DC_TEST_A62 PAD~D T170 @ RSVD AL1 RSVD_AL1 PAD~D T136
DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 RSVD @
DC_TEST_A3_B3 B3 AV1 DC_TEST_AV1 PAD~D T171 @ AM11 RSVD_AM11 PAD~D T137
DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 RSVD @
DC_TEST_A61_B61 B61 AW1 DC_TEST_AW1 PAD~D T172 @ @ AP7 RSVD_AP7 PAD~D T139
DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 T138 PAD~D RSVD_F22 F22 RSVD @
B62 AW2 DC_TEST_AY2_AW2 @ RSVD AU10 RSVD_AU10 PAD~D T141
DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 T140 PAD~D RSVD_H22 H22 RSVD @
DC_TEST_B62_B63 B63 AW3 DC_TEST_AY3_AW3 @ RSVD AU15 RSVD_AU15 PAD~D T142
DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 T143 PAD~D RSVD_J21 J21 RSVD @
C1 AW61 DC_TEST_AY61_AW61 RSVD AW14 RSVD_AW14 PAD~D T144
DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 RSVD @
DC_TEST_C1_C2 C2 AW62 DC_TEST_AY62_AW62 AY14 RSVD_AY14 PAD~D T145
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW63 DC_TEST_AW63 PAD~D T173 @ RSVD
17 OF 19 Rev1p2DAISY_CHAIN_NCTF_AW63
@ 18 OF 19 Rev1p2
@
C C
UC1S HASWELL_MCP_E
CFG0 AC60 AV63 PAD~D T146 @
CFG STRAPS for CPU
[6] CFG0 CFG0 RSVD_TP
AC62 AU63 PAD~D T147 @
[6] CFG1 CFG1 RSVD_TP
AC63
[6] CFG2 CFG2
AA63
[6] CFG3 CFG3
CFG4 AA60 C63 PAD~D T148 @
[6] CFG4 CFG4 RSVD_TP
Y62 C62 PAD~D T149 @ CFG4
[6] CFG5 CFG5 RSVD_TP
Y61 B43 PAD~D T150 @
[6] CFG6 CFG6 RSVD
Y60
[6] CFG7 CFG7
1
1K_0402_5%
V62 A51 PAD~D T151 @
[6] CFG8 CFG8 RSVD_TP
RC191
V61 B51 PAD~D T152 @
[6] CFG9 CFG9 RSVD_TP
V60
[6] CFG10 CFG10
U60 L60 PAD~D T153 @
[6] CFG11 CFG11 RESERVED RSVD_TP
T63
[6] CFG12
2
T62 CFG12 N60 PAD~D T154 @
[6] CFG13 CFG13 RSVD
T61
[6] CFG14 CFG14
T60 W23 PAD~D T155 @
[6] CFG15 CFG15 RSVD Y22 PAD~D T156 @
AA62 RSVD AY15 PROC_OPI_RCOMP 1 2
[6] CFG16 CFG16 PROC_OPI_RCOMP
U63 49.9_0402_1% RC134
[6]
[6]
CFG18
CFG17
AA61 CFG18 AV62 PAD~D T157 @ Display Port Presence Strap
U62 CFG17 RSVD D58 PAD~D T158 @
[6] CFG19 CFG19 RSVD
2 1 CFG_RCOMP V63 P22 1 : Disabled; No Physical Display Port
RC132 49.9_0402_1% CFG_RCOMP VSS N21
@ T159PAD~D A5 VSS CFG4 attached to Embedded Display Port
RSVD P20
@ T161PAD~D E1 RSVD R20 0 : Enabled; An external Display Port device is
@ T163PAD~D D1 RSVD RSVD
@ T164PAD~D J20 RSVD connected to the Embedded Display Port
@ T165PAD~D H18 RSVD
1 2 TDI_IREF B12 RSVD
B TD_IREF B
RC133 8.2K_0402_1%
19 OF 19 Rev1p2
@ CFG0
1
1K_0402_1%
@ RC183
2
EAR‐STALL/NOT STALL RESET SEQUENCE AFTER PCU PLL IS LOCKED
1:(Default) Normal Operation; No stall
CFG0
0:Lane Reversed
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 16 of 54
5 4 3 2 1
5 4 3 2 1
+DIMM1_VREF_DQ
H=4mm
+1.35V +1.35V
1 2 1
JDIMM1
2
2-3A to 1 DIMMs/channel
+SM_VREF_DQ0_DIMM1 VREF_DQ VSS1
3 4 DDR_A_D4
VSS2 DQ4
2.2U_0402_6.3V6M
0.1U_0402_10V7K
D RD1 DDR_A_D0 5 6 DDR_A_D5 D
0_0402_5% DDR_A_D1 7 DQ0 DQ5 8 +1.35V
9 DQ1 VSS3 10 DDR_A_DQS#0
Populate RD1, De-Populate RD7 for Intel DDR3 1 1 VSS4 DQS#0
CD1
CD2
11 12 DDR_A_DQS0
VREFDQ multiple methods M1 13 DM0 DQS0 14
VSS5 VSS6
1
Populate RD7, De-Populate RD1 for Intel DDR3 DDR_A_D2 15 16 DDR_A_D6
2 2 DDR_A_D3 17 DQ2 DQ6 18 DDR_A_D7 RD3
VREFDQ multiple methods M3 19 DQ3 DQ7 20 470_0402_5%
DDR_A_D8 21 VSS7 VSS8 22 DDR_A_D12
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
2
25 DQ9 DQ13 26
DDR_A_DQS#1 27 VSS9 VSS10 28 1 2
DQS#1 DM1 [18] DDR3_DRAMRST# DDR3_DRAMRST#_CPU [6]
DDR_A_DQS1 29 30 DDR3_DRAMRST#
31 DQS1 RESET# 32 RD5
DDR_A_D10 33 VSS11 VSS12 34 DDR_A_D14 @ 0_0402_5%
[7] DDR_A_DQS#[0..7] DQ10 DQ14 1
DDR_A_D11 35 36 DDR_A_D15 CD3
37 DQ11 DQ15 38 0.1U_0402_10V7K
[7] DDR_A_D[0..63] All VREF traces should VSS13 VSS14
have 10 mil trace width DDR_A_D16 39 40 DDR_A_D20
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21 2
[7] DDR_A_DQS[0..7] DQ17 DQ21
43 44
DDR_A_DQS#2 45 VSS15 VSS16 46
[7] DDR_A_MA[0..15] DQS#2 DM2
DDR_A_DQS2 47 48
49 DQS2 VSS17 50 DDR_A_D22
DDR_A_D18 51 VSS18 DQ22 52 DDR_A_D23
Layout Note: Note: DDR_A_D19 53 DQ18 DQ23 54 CAD NOTE
55 DQ19 VSS19 56 DDR_A_D28
Place near JDIMM1 Check voltage tolerance of DDR_A_D24 57 VSS20 DQ28 58 DDR_A_D29
PLACE THE CAP NEAR TO
DQ24 DQ29
DDR_A_D25 59
DQ25 VSS21
60 DIMM RESET PIN
VREF_DQ at the DIMM socket 61
63 VSS22 DQS#3
62
64
DDR_A_DQS#3
DDR_A_DQS3
65 DM3 DQS3 66
DDR_A_D26 67 VSS23 VSS24 68 DDR_A_D30
+1.35V DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31
71 DQ27 DQ31 72
VSS25 VSS26
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
C 1 1 1 1 1 1 1 1 DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA C
[7] DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA [7]
75 76
VDD1 VDD2
CD4
CD5
CD6
CD7
CD8
CD9
CD10
CD11
77 78 DDR_A_MA15
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
2 2 2 2 2 2 2 2 [7] DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7 M_ODT
87 A9 A7 88
VDD5 VDD6 1
DDR_A_MA8 89 90 DDR_A_MA6 CD64 ESD@
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94 0.1U_0402_10V7K
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2 2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
+1.35V 99 A1 A0 100 Place CC31
[7] M_CLK_DDR0
M_CLK_DDR0
M_CLK_DDR#0
101
103
VDD9
CK0
VDD10
CK1
102
104
M_CLK_DDR1
M_CLK_DDR#1
M_CLK_DDR1 [7] DDR3L SODIMM ODT GENERATION between QD2 and R2349
[7] M_CLK_DDR#0 CK0# CK1# M_CLK_DDR#1 [7]
105 106
VDD11 VDD12 +5VALW +1.35V
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
330U_D3_2.5VY_R6M
DDR_A_MA10 107 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 [7] QD2
DDR_A_BS0 109 110 DDR_A_RAS#
[7] DDR_A_BS0 BA0 RAS# DDR_A_RAS# [7]
1 111 112 L2N7002WT1G_SC-70-3
113 VDD13 VDD14 114
1 1@ 1 1 1@ 1 1 1 [7] DDR_A_WE#
DDR_A_WE#
WE# S0#
DDR_CS0_DIMMA#
DDR_CS0_DIMMA# [7]
1
CD16
CD17
CD12
CD18
CD19
CD20
CD13
CD14
CD15
+ DDR_A_CAS# 115 116 M_ODT0 1 3 M_ODT 1 2 M_ODT0
S
[7] DDR_A_CAS# CAS# ODT0
117 118 R2347 R2348 66.5_0402_1%
DDR_A_MA13 119 VDD15 VDD16 120 M_ODT1 220K_0402_5% 1 2 M_ODT1
2 2 2 2 2 2 2 2 2 DDR_CS1_DIMMA# 121 A13 ODT1 122 +SM_VREF_CA_DIMM R2349 66.5_0402_1%
G
[7] DDR_CS1_DIMMA#
2
123 S1# NC2 124 1 2
M_ODT2 [18]
2
125 VDD17 VDD18 126 1 2 R2350 66.5_0402_1%
NCTEST VREF_CA
2.2U_0402_6.3V6M
0.1U_0402_10V7K
127 128 1 2
VSS27 VSS28 M_ODT3 [18]
DDR_A_D32 129 130 DDR_A_D36 RD4 R2352 66.5_0402_1%
DQ32 DQ36
2
DDR_A_D33 131 132 DDR_A_D37 1 1 0_0402_5% @
DQ33 DQ37
CD21
CD22
133 134 R2351
DDR_A_DQS#4 135 VSS29 VSS30 136 2M_0402_5% 0.675V_DDR_VTT_ON
DQS#4 DM4 0.675V_DDR_VTT_ON [37]
DDR_A_DQS4 137 138
139 DQS4 VSS31 140 DDR_A_D38 2 2
1
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39
Layout Note: DQ34 DQ39
DDR_A_D35 143 144
Place near JDIMM1.203,204 145 DQ35 VSS33 146 DDR_A_D44
DDR_A_D40 147 VSS34 DQ44 148 DDR_A_D45
B DQ40 DQ45 B
DDR_A_D41 149 150
151 DQ41 VSS35 152 DDR_A_DQS#5
153 VSS36 DQS#5 154 DDR_A_DQS5
155 DM5 DQS5 156 +1.35V
DDR_A_D42 157 VSS37 VSS38 158 DDR_A_D46 @
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47 CD23
+0.675VS 161 DQ43 DQ47 162 U2303 0.1U_0402_10V7K
DDR_A_D48 163 VSS39 VSS40 164 DDR_A_D52 1 5 1 2
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53 NC VCC
167 DQ49 DQ53 168 2
VSS41 VSS42 [6] DDR_PG_CTRL A
DDR_A_DQS#6 169 170 4 0.675V_DDR_VTT_ON
DQS#6 DM6 Y
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_A_DQS6 171 172 3
173 DQS6 VSS43 174 DDR_A_D54 GND
1 1 1 1 1 1 VSS44 DQ54
CD24
CD25
CD26
CD27
CD28
CD29
DDR_A_D50 175 176 DDR_A_D55 74AUP1G07GW_TSSOP5
DDR_A_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_A_D60
2 2 2 2 2 2 DDR_A_D56 181 VSS46 DQ60 182 DDR_A_D61 X02.23
DDR_A_D57 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDR_A_DQS#7
187 VSS48 DQS#7 188 DDR_A_DQS7
189 DM7 DQS7 190
DDR_A_D58 191 VSS49 VSS50 192 DDR_A_D62
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63
195 DQ59 DQ63 196
RD61 2 10K_0402_5% 197 VSS51 VSS52 198
199 SA0 EVENT# 200
+3VS VDDSPD SDA DDR_XDP_WLAN_TP_SMBDAT [6,9,18]
1 2 201 202
SA1 SCL DDR_XDP_WLAN_TP_SMBCLK [6,9,18]
2.2U_0402_6.3V6M
RD7 10K_0402_5% 1 1 203 204 +0.675VS
VTT1 VTT2
0.1U_0402_10V7K
@ +0.675VS
CD30
CD31
205 206
G1 G2
2 2 FOX_AS0A621-U4R6-7H
CONN@
A A
+3VS +1.35V
CD62
1 2
22U_0603_6.3V6M
ESD@
ESD solution
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 17 of 54
5 4 3 2 1
5 4 3 2 1
+DIMM2_VREF_DQ +1.35V
H=4mm +1.35V
JDIMM2
2-3A to 1 DIMMs/channel
+SM_VREF_DQ1_DIMM2 1 2 1 2
3 VREF_DQ VSS 4 DDR_B_D22
VSS DQ4
2.2U_0402_6.3V6M
0.1U_0402_10V7K
RD8 DDR_B_D23 5 6 DDR_B_D16
0_0402_5% DDR_B_D17 7 DQ0 DQ5 8
9 DQ1 VSS 10 DDR_B_DQS#2
1 1 VSS DQS0#
CD32
CD33
D
11 12 DDR_B_DQS2 D
13 DM0 DQS0 14
Populate RD4, De-Populate RD8 for Intel DDR3 DDR_B_D21 15 VSS VSS 16 DDR_B_D19
VREFDQ multiple methods M1 2 2 DDR_B_D18 17 DQ2 DQ6 18 DDR_B_D20
19 DQ3 DQ7 20
Populate RD8, De-Populate RD4 for Intel DDR3 DDR_B_D3 21 VSS VSS 22 DDR_B_D4
VREFDQ multiple methods M3 DDR_B_D2 23 DQ8 DQ12 24 DDR_B_D5
25 DQ9 DQ13 26
DDR_B_DQS#0 27 VSS VSS 28
DDR_B_DQS0 29 DQS1# DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# [17]
31 32
[7] DDR_B_DQS#[0..7] VSS VSS
DDR_B_D0 33 34 DDR_B_D6 1
DDR_B_D1 35 DQ10 DQ14 36 DDR_B_D7
[7] DDR_B_D[0..63] All VREF traces should
37 DQ11 DQ15 38 @
have 10 mil trace width VSS VSS
DDR_B_D12 39 40 DDR_B_D13 CD34
[7] DDR_B_DQS[0..7] DQ16 DQ20 2
DDR_B_D8 41 42 DDR_B_D9 0.1U_0402_10V7K
43 DQ17 DQ21 44
[7] DDR_B_MA[0..15] VSS VSS
DDR_B_DQS#1 45 46
DDR_B_DQS1 47 DQS2# DM2 48
49 DQS2 VSS 50 DDR_B_D11
Layout Note: Note: DDR_B_D14 51 VSS
DQ18
DQ22
DQ23
52 DDR_B_D10
CAD NOTE
DDR_B_D15 53 54
Place near JDIMM2 Check voltage tolerance of DDR_B_D31
55
57
DQ19
VSS
VSS
DQ28
56
58
DDR_B_D30
DDR_B_D26
PLACE THE CAP NEAR TO
DQ24 DQ29
VREF_DQ at the DIMM socket DDR_B_D25 59
61 DQ25 VSS
60
62 DDR_B_DQS#3
DIMM RESET PIN
63 VSS DQS3# 64 DDR_B_DQS3
65 DM3 DQS3 66
DDR_B_D27 67 VSS VSS 68 DDR_B_D29
DDR_B_D24 69 DQ26 DQ30 70 DDR_B_D28
+1.35V 71 DQ27 DQ31 72
VSS VSS
DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
[7] DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB [7]
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
75 76
77 VDD VDD 78 DDR_B_MA15
1 1 1 1 1 1 1 1 NC A15
DDR_B_BS2 79 80 DDR_B_MA14
[7] DDR_B_BS2 BA2 A14
CD35
CD36
CD37
CD38
CD39
CD40
CD41
CD42
C
81 82 C
DDR_B_MA12 83 VDD VDD 84 DDR_B_MA11
2 2 2 2 2 2 2 2 DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA8 89 VDD VDD 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA3 95 VDD VDD 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
+1.35V M_CLK_DDR2 101 VDD VDD 102 M_CLK_DDR3
[7] M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 [7]
M_CLK_DDR#2 103 104 M_CLK_DDR#3
[7] M_CLK_DDR#2 CK0# CK1# M_CLK_DDR#3 [7]
105 106
DDR_B_MA10 107 VDD VDD 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 [7]
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
330U_D3_2.5VY_R6M
DDR_B_BS0 109 110 DDR_B_RAS#
[7] DDR_B_BS0 BA0 RAS# DDR_B_RAS# [7]
111 112
DDR_B_WE# 113 VDD VDD 114 DDR_CS2_DIMMB#
1 [7] DDR_B_WE# WE# S0# DDR_CS2_DIMMB# [7]
1 1 @ 1 1 @ 1 1 1 1 DDR_B_CAS# 115 116 M_ODT2
[7] DDR_B_CAS# CAS# ODT0 M_ODT2 [17]
CD43
CD44
CD45
CD46
CD47
CD48
CD49
CD50
CD51
+ 117 118
DDR_B_MA13 119 VDD VDD 120 M_ODT3
A13 ODT1 M_ODT3 [17] +SM_VREF_CA_DIMM
DDR_CS3_DIMMB# 121 122
2 2 2 2 2 2 2 2 2 [7] DDR_CS3_DIMMB# S1# NC
123 124
125 VDD VDD 126 1 2
127 TEST VREF_CA 128
VSS VSS
2.2U_0402_6.3V6M
0.1U_0402_10V7K
DDR_B_D32 129 130 DDR_B_D33 RD10
DDR_B_D35 131 DQ32 DQ36 132 DDR_B_D34 0_0402_5%
133 DQ33 DQ37 134
VSS VSS 1 1
CD53
DDR_B_DQS#4 135 136
DQS4# DM4
CD52
DDR_B_DQS4 137 138
139 DQS4 VSS 140 DDR_B_D39
DDR_B_D36 141 VSS DQ38 142 DDR_B_D37 2 2
DDR_B_D38 143 DQ34 DQ39 144
145 DQ35 VSS 146 DDR_B_D44
DDR_B_D40 147 VSS DQ44 148 DDR_B_D41
Layout Note: DQ40 DQ45
DDR_B_D45 149 150
Place near JDIMM2.203,204 151 DQ41 VSS 152 DDR_B_DQS#5
153 VSS DQS5# 154 DDR_B_DQS5
155 DM5 DQS5 156
B VSS VSS B
DDR_B_D43 157 158 DDR_B_D47
DDR_B_D42 159 DQ42 DQ46 160 DDR_B_D46
161 DQ43 DQ47 162
DDR_B_D52 163 VSS VSS 164 DDR_B_D51
DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D55
+0.675VS 167 DQ49 DQ53 168
DDR_B_DQS#6 169 VSS VSS 170
DDR_B_DQS6 171 DQS6# DM6 172
173 DQS6 VSS 174 DDR_B_D48
DDR_B_D50 175 VSS DQ54 176 DDR_B_D54
DQ50 DQ55
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_B_D53 177 178
179 DQ51 VSS 180 DDR_B_D56
1 1 1 1 1 1 VSS DQ60
CD54
CD55
CD56
CD57
CD58
CD59
DDR_B_D63 181 182 DDR_B_D57
DDR_B_D62 183 DQ56 DQ61 184
185 DQ57 VSS 186 DDR_B_DQS#7
2 2 2 2 2 2 187 VSS DQS7# 188 DDR_B_DQS7
189 DM7 DQS7 190
DDR_B_D58 191 VSS VSS 192 DDR_B_D60
DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D61
195 DQ59 DQ63 196
+3VS 197 VSS VSS 198
199 SA0 EVENT# 200
+3VS VDDSPD SDA DDR_XDP_WLAN_TP_SMBDAT [6,9,17]
2 1 201 202
SA1 SCL DDR_XDP_WLAN_TP_SMBCLK [6,9,17]
RD12 10K_0402_5% +0.675VS 203 204 +0.675VS
VTT VTT
1
10K_0402_5%
RD13
0.1U_0402_10V7K
205 206
GND1 GND1
2.2U_0402_6.3V6M
1 1
CD61
@
CD60
2
FOX_AS0A621-U4S6-7H
2 2
CONN@
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 18 of 54
5 4 3 2 1
5 4 3 2 1
D Place close to JHDMI +VDISPLAY_VCC
D
CX12 2 1 0.1U_0402_10V7K TMDS_TXCN
[6] DDI1_LANE_N3
CX13 2 1 0.1U_0402_10V7K TMDS_TXCP FX1 W=40mils
[6] DDI1_LANE_P3
+5VS 2 1
10U_0603_6.3V6M
0.1U_0402_10V7K
CX14 2 1 0.1U_0402_10V7K TMDS_TX0N DLW21HN900HQ2L_4P 1 1
[6] DDI1_LANE_N2
CX21
CX22
CX15 2 1 0.1U_0402_10V7K TMDS_TX0P TMDS_TXCN 4 3 TMDS_L_TXCN 1.5A_8V_1206L150THWR
[6] DDI1_LANE_P2 4 3
CX16 2 1 0.1U_0402_10V7K TMDS_TX1N
[6] DDI1_LANE_N1 2 2
CX17 2 1 0.1U_0402_10V7K TMDS_TX1P TMDS_TXCP 1 2 TMDS_L_TXCP +3VS
[6] DDI1_LANE_P1 1 2
CX18 2 1 0.1U_0402_10V7K TMDS_TX2N LX2 EMI@
[6] DDI1_LANE_N0
CX19 2 1 0.1U_0402_10V7K TMDS_TX2P
[6] DDI1_LANE_P0
1
RX12
10K_0402_5%
1
2
3
4
4
3
2
1
RP59 RP58 DLW21HN900HQ2L_4P
2
470_0804_8P4R_5% 470_0804_8P4R_5% TMDS_TX0N 4 3 TMDS_L_TX0N JHDMI
4 3 HDMI_HPLUG 19
18 HP_DET
8
7
6
5
5
6
7
8
TMDS_TX0P 1 2 TMDS_L_TX0P 17 +5V
1 2 CPU_DPB_CTRLDAT_R 16 DDC/CEC_GND
LX3 EMI@ CPU_DPB_CTRLCLK_R 15 SDA
14 SCL
13 Reserved
HSW: SD309680080 (S ROW RES 1/16W 680 +-5% 8P4R 0804) CEC
TMDS_L_TXCN 12 20
11 CK- GND 21
BDW: SD309470080 (S ROW RES 1/16W 470 +-5% 8P4R 0804) +3VS CK_shield GND
TMDS_L_TXCP 10 22
TMDS_L_TX0N 9 CK+ GND 23
DLW21HN900HQ2L_4P 8 D0- GND
TMDS_TX1N 4 3 TMDS_L_TX1N TMDS_L_TX0P 7 D0_shield
4 3 D0+
1
TMDS_L_TX1N 6
RX13 5 D1-
10K_0402_5% TMDS_TX1P 1 2 TMDS_L_TX1P TMDS_L_TX1P 4 D1_shield
1 2 TMDS_L_TX2N 3 D1+
LX4 EMI@ 2 D2-
C C
2
D2_shield
1
D TMDS_L_TX2P 1
2 QX3 D2+
G L2N7002LT1G_SOT23-3 CONCR_099ATAC19NBLCNF
S CONN@
3
DLW21HN900HQ2L_4P
TMDS_TX2N 4 3 TMDS_L_TX2N
4 3
TMDS_TX2P 1 2 TMDS_L_TX2P
1 2
LX5 EMI@
+VDISPLAY_VCC +3VS
TMDS_L_TXCN EMI@ CX23 1 2 3.3P_0402_50V8C
+3VS TMDS_L_TXCP EMI@ CX24 1 2 3.3P_0402_50V8C
2
TMDS_L_TX0N EMI@ CX25 1 2 3.3P_0402_50V8C RV18
2
1M_0402_5%
RX16 RX17 TMDS_L_TX0P EMI@ CX26 1 2 3.3P_0402_50V8C
2
G
2.2K_0402_5% 2.2K_0402_5%
1
TMDS_L_TX1N EMI@ CX27 1 2 3.3P_0402_50V8C
QX4B 3 1 HDMI_HPLUG 1 2
[10] DPB_HPD
1
1
2
DMN66D0LDW-7_SOT363-6 TMDS_L_TX1P EMI@ CX28 1 2 3.3P_0402_50V8C RV20 20K_0402_5%
D
G
1 6 CPU_DPB_CTRLCLK_R TMDS_L_TX2N EMI@ CX29 1 2 3.3P_0402_50V8C QV5
[10] CPU_DPB_CTRLCLK
S
L2N7002WT1G_SC-70-3
TMDS_L_TX2P EMI@ CX30 1 2 3.3P_0402_50V8C
5
B B
G
4 3 CPU_DPB_CTRLDAT_R
[10] CPU_DPB_CTRLDAT
S
QX4A
DMN66D0LDW-7_SOT363-6 EMI
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 19 of 54
5 4 3 2 1
5 4 3 2 1
+3VS +3VS_VGA +3VS_VGA +3VS_VGA +1.8V_VGA +1.8V_VGA
+1.8V_VGA_IVDD
1 2
Close UV6 pin 38, 39
1U_0402_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
10U_0603_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
RV214 0_0603_5% 1 1 1 1 1 1 1 1
CV358
CV357
CV356
CV340
CV337
CV336
CV343
CV361
ISPSDA
ISPSCL
22U_0603_6.3V6M
2 2 2 2 2 2 2 2
+5VS
13
48
35
36
38
39
12
14
44
46
UV6
1
2
G
+3VS_VGA +CRT_VCC
DDCSDA
DDCSCL
OVDD
OVDD
IVDD33
IVDD33
IVDDO
IVDDO
IVDD
IVDD
IVDD
IVDD
D D
3 1 DP_HPD DP_HPD 40
[10] DPC_HPD S HPD X02.08
D
1
45 RV215 1 @ 2 0_0402_5% 1 2
Q2416 R2495 0.1U_0402_10V7K 1 2 CV342 IT6511_P0_C 26 MCUVDDH RV169 1K_0402_5%
[6] DDI2_LANE_P0 RX0P
L2N7002LT1G_SOT23-3 4.7K_0402_5% 0.1U_0402_10V7K 1 2 CV346 IT6511_N0_C 27
[6] DDI2_LANE_N0 RX0N
1
UV5
0.1U_0402_10V7K 1 2 CV347 IT6511_P1_C 29 47
OE#
[6] DDI2_LANE_P1
2 0.1U_0402_10V7K 1 2 CV348 IT6511_N1_C 30 RX1P MCURSTN HSYNC 1 2 HSYNC_R 2 4 HSYNC_CRT
[6] DDI2_LANE_N1 RX1N A Y
@ T4930 RV170 39_0402_5%
G
28 PAD~D
URDBG POP for flash IC FW 74AHCT1G125GW_SOT353-5~D
3
15 ISPSCL RV163 1 @ 2 0_0402_5% CLK_DDC2_CRT_R
ISPSCL 16 ISPSDA RV164 1 @ 2 0_0402_5% DAT_DDC2_CRT_R
0.1U_0402_10V7K 1 2 CV349 IT6511_AUX_C 20 ISPSDA
[10] CPU_DPC_AUX
0.1U_0402_10V7K 1 2 CV350 IT6511_AUX#_C 19 RXAUXP 23 CLK_DDC2_CRT_R X02.08
+1.8V_VGA [10] CPU_DPC_AUX# RXAUXN VGADDCCLK 21 DAT_DDC2_CRT_R
VGADDCSDA
1
UV3
18 3 VSYNC
OE#
17 DCAUXP VSYNC 4 HSYNC VSYNC 1 2 VSYNC_R 2 4 VSYNC_CRT
1 2 +1.8V_VGA_PVCC DCAUXN HSYNC RV171 39_0402_5% A Y
G
1U_0402_6.3V6K
LV14 BLM15PD600SN1D_2P
1 74AHCT1G125GW_SOT353-5~D
3
CV351
+1.8V_VGA_PVCC 25 10 +1.8V_VGA_VDD
2 AVCC VDDC
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
31 1 1
AVCC
1 1 1
IT6513FN
CV352
CV353
CV354
CV338
CV339
+1.8V_VGA
22 2 2
2 2 2 PVCC 11 RED_CRT
IORP
1 2 +1.8V_VGA_IVDD
LV15 BLM15PD600SN1D_2P 9 GREEN_CRT
IOGP
4.7U_0402_6.3V6M
1
+1.8V_VGA_IVDD 24
DVDD18
CV359
0.1U_0402_25V6
C
8 BLUE_CRT C
IOBP
2 1
CV355
41 6513_27M_IN
NC/VGADETECT
1
5 1 2
2 32 RSET RV160 100_0402_1% RV210
+1.8V_VGA ASPVCC @ 1M_0402_5%
7 +1.8V_VGA_VDD @ YV3
VDDA 27MHZ_12PF_X1E000021042600
2
+3VS_VGA 6513_27M_OUT 1 @ 2 3 1
1 2 +1.8V_VGA_VDD 6 1 2 RV159 0_0402_5% OUT IN
COMP
1U_0402_6.3V6K
20P_0402_50V8J
20P_0402_50V8J
LV21 BLM15PD600SN1D_2P 1 2 43 CV341 0.1U_0402_25V6 2 4 2 1
RV161 1 2 2.2K_0402_5% 42 PCSDA @ GND GND @
1 PCSCL
CV345
CV344
RV162 2.2K_0402_5% 34 6513_27M_IN
XTALIN
CV360
33 6513_27M_OUT
XTALOUT
1
1 2
PWDNB
2 RV518
PAD
10K_0402_5%
IT6513FN_QFN48_6X6
2
37
49
X02.19 +5VS
3
DV5 DV6
1
PJDLC05C_SOT23-3 PJDLC05C_SOT23-3
ESD@ ESD@ UV4
IN
AP2330W-7_SC59-3
1
X02.17
GND
OUT
B B
RED_CRT 1 2
EMI@ LV16 BLM15BB470SN1D_2P
3
GREEN_CRT 1 2 +CRT_VCC
EMI@ LV17 BLM15BB470SN1D_2P
BLUE_CRT 1 2
EMI@ LV18 BLM15BB470SN1D_2P
40mils
EMI@
EMI@
EMI@
12P_0402_50V8J
12P_0402_50V8J
12P_0402_50V8J
12P_0402_50V8J
12P_0402_50V8J
12P_0402_50V8J
3.3P_0402_50V8C
3.3P_0402_50V8C
3.3P_0402_50V8C
1
1
1
75_0402_1%
75_0402_1%
75_0402_1%
1 1 1 1 1 1
1 1 1 CV50
1U_0402_6.3V6K
RV32
RV33
RV34
CV54
CV55
CV56
2 JCRT
2 2 2 2 2 2
CV62
CV61
CV60
CV51
CV52
CV53 @ @ @ 6
2
2 2 2 @ T87 PAD~D JCRT-11 11
RED 1
7
12
+CRT_VCC GREEN 2
8
[0823] EMI request to add one LC HSYNC_CONN 13
BLUE 3
1K_0402_5%
1K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
9
1
VSYNC_CONN 14
+3VS_VGA +3VS_VGA
RV35
RV36
RV37
RV38
M_ID2# 4
10 G 16
15 G 17
@
5
2
DAT_DDC2_CRT
1
0.1U_0402_25V6
1 C-K_80443A-5K1-152
RV517 RV516 CLK_DDC2_CRT CONN@
CV57
4.7K_0402_5% 4.7K_0402_5%
HSYNC_CRT 1 2
EMI@ LV19 BLM15AG121SN1D_L0402_2P 2
X02.21
2
VSYNC_CRT 1 2
EMI@ LV20 BLM15AG121SN1D_L0402_2P
2
22P_0402_50V8J
22P_0402_50V8J
A CV58 1 1 A
CV59
DAT_DDC2_CRT_R 1 6 DAT_DDC2_CRT
@
@
QV89A DMN66D0LDW-7_SOT363-6
5
2 2
CLK_DDC2_CRT_R 4 3 CLK_DDC2_CRT
QV89B DMN66D0LDW-7_SOT363-6
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 20 of 54
5 4 3 2 1
5 4 3 2 1
X02.08
1 @ 2
RX32 0_0402_5%
LX8 @
0.1U_0402_10V7K 2 1 C4312 EDP_TX0_R 1 2 EDP_TX0_C
LCD PWR CTRL [6] EDP_TX0
[6] EDP_TX0#
0.1U_0402_10V7K 2 1 C4311 EDP_TX0#_R 4 3 EDP_TX0#_C eDP Connector
CONN@
CMMI21T-670Y-N_4P
1 @ 2 ACES_50398-04041-001
RX33 0_0402_5% EDP_TX0_C 40 45
EDP_TX0#_C 39 40 G5 44
D
+3VALW +LCDVDD +LCDVDD_CONN 1 @ 2 38 39 G4 43
D
W=60mils RX34 0_0402_5% EDP_TX1_C 37 38 G3 42
W=60mils UX1 LX9 @ EDP_TX1#_C 36 37 G2 41
5 1 1 2 0.1U_0402_10V7K 2 1 C4314 EDP_TX1_R 1 2 EDP_TX1_C 35 36 G1
IN OUT [6] EDP_TX1
FBMA-L11-201209-221LMA30_2P EDP_AUX_C 34 35
33 34
0.1U_0402_10V7K
CX11
4.7U_0805_10V4Z
CX8
1 2 LX1 EDP_AUX#_C
GND 0.1U_0402_10V7K 2 1 C4313 EDP_TX1#_R 4 3 EDP_TX1#_C 32 33
1 1 [6] EDP_TX1#
CX7 ENVDD_R 4 3 RX30 1 2 +3VALW CPU_EDP_HPD 31 32
EN OC [10] CPU_EDP_HPD
4.7U_0805_10V4Z CMMI21T-670Y-N_4P 30 31
2 100K_0402_5% 1 @ 2 29 30
SY6288C20AAC_SOT23-5 2 2 RX35 0_0402_5% USB20_TOUCH_N5_R 28 29
1 @ 2 USB20_TOUCH_P5_R 27 28
RX36 0_0402_5% 26 27
LX10 @ 25 26
0.1U_0402_10V7K 2 1 C4321 EDP_AUX_R 1 2 EDP_AUX_C 24 25
[6] EDP_AUX
23 24
BAT54CW_SOT323-3 22 23
[11] LCD_CBL_DET#
0.1U_0402_10V7K 2 1 C4322 EDP_AUX#_R 4 3 EDP_AUX#_C 21 22
[6] EDP_AUX#
3 Css Tss CAM_MIC_CBL_DET# 20 21
[10,29] ENVDD_PCH [11] CAM_MIC_CBL_DET#
CMMI21T-670Y-N_4P +5VS_TOUCH 19 20
1 ENVDD_R 0.1uF 100mS 1 @ 2 18 19
RX37 0_0402_5% 17 18
[29] LCD_VCC_TEST_EN
2 10nF 10mS SS table W=60mils +LCDVDD_CONN 16 17
15 16
DV7 1nF 1mS USB20_CAM_P7_R 14 15
USB20_CAM_N7_R 13 14
Open or 1mS +3VS_CAM 12 13
tied to MIC_CLK 11 12
[23] MIC_CLK
VIN 10 11
BAT54CW_SOT323-3 MIC_DATA 9 10
[23] MIC_DATA
LCD_TST 8 9
[29] LCD_TST
3 7 8
[6,10] EDP_BIA_PWM
CBL_LOOP_BACK 6 7
1 5 6
DISPOFF# 4 5
LCD backlight PWR CTRL [29] BIA_PWM_EC
2 3 4
2 3
+INV_PWR_SRC
1 2
1
C DV1 1 C
RX26 W=60mils
QX2 100K_0402_5% RX29 JEDP
60mil SI3457CDV-T1-GE3_TSOP6 60mil 1K_0402_1%
+INV_PWR_SRC
2
B+ 6
5
2 DLW21HN900HQ2L_4P
4 1 4 3 USB20_TOUCH_N5_R
S
[12] USB20_TOUCH_N5 4 3
1
1000P_0402_50V7K
CX4
CX5 1 2 USB20_TOUCH_P5_R
G
1 [12] USB20_TOUCH_P5 1 2
RX2 0.1U_0603_25V7K
3
270K_0402_5% 2 LX7 EMI@
2
2
1 2
PWR_SRC_ON RX24 @ 0_0402_5%
1
1 2
RX3 RX23 @ 0_0402_5% BAT54CW_SOT323-3
X02.14 47K_0402_5%
3
[10] PANEL_BKLEN
1 2
1 DISPOFF#
D DLW21HN900HQ2L_4P
1
2 QX1 4 3 USB20_CAM_N7_R 2
[29] EN_INVPWR [12] USB20_CAM_N7 4 3 [28] PANEL_BKEN_EC
G L2N7002WT1G_SC-70-3
10K_0402_5%
S DV2
3
1 2 USB20_CAM_P7_R RX9
[12] USB20_CAM_P7 1 2
2
LX6 EMI@
1 2
RX21 @ 0_0402_5%
B * Touch Screen Panel RX22
1
@
2
0_0402_5%
B
+5VS +5VS_TOUCH
RX28
2 1 Css Tss
@ 0_0603_5% 0.1uF 100mS
+5VS_TOUCH 10nF 10mS
+5VS +5VS
1nF 1mS
UX3
5 1 Open or 1mS
IN OUT
0.1U_0402_10V7K
CX50
4.7U_0805_10V4Z
CX49
tied to
2 1 1 VIN
GND
CX51
1
[11] TS_EN
4
EN OC
3 1
RX31
2
100K_0402_5%
close to JEDP
4.7U_0805_10V4Z
2
2 2 SS table
SY6288C20AAC_SOT23-5
USB20_CAM_P7_R USB20_TOUCH_N5_R MIC_CLK
+LCDVDD_CONN +5VS_TOUCH +3VS +3VS_CAM +INV_PWR_SRC
USB20_CAM_N7_R USB20_TOUCH_P5_R MIC_DATA
0.1U_0402_10V7K
10U_0805_10V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_25V6
X02.06 1 1 1 1 1 1
CX2
CX3
CX6
CX10
CX20
3
CX31
AZ5125-02S.R7G_SOT23-3
DX3 ESD@
DX2 ESD@
AZ5125-02S.R7G_SOT23-3
AZ5125-02S.R7G_SOT23-3
DX4 @
2 2 2 2 2 2
X02.21
Webcam PWR CTRL
close to JEDP close to JEDP close to JEDP close to JEDP close to JEDP
A A
1
+3VALW +3VS_CAM
QX5
AO3419L_SOT23-3
S
3 1
G
2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
[29,31] SUSP#
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 21 of 54
5 4 3 2 1
1 2 3 4 5
W=40mils
W=40mils
+3VALW
+LAN_IO rising time : >1ms and <100ms
X02.16 +LAN_IO
CL39 W=40mils
1U_0402_6.3V6K UL2 1.5A
2 1 5 1
IN OUT
0.1U_0402_10V7K
0.1U_0402_10V7K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
A 2 +3VALW 1 1 1 1 A
GND
4 3 RL41 1 2 100K_0402_5% CL15 CL19 CL43 CL44
[29] LAN_EN EN OC @
2 2 2 2
2
SY6288C20AAC_SOT23-5
RL27
100K_0402_5%
These caps close to Pin 11,32
1
W=20mils +LAN_VDD
+LAN_IO +LAN_VDD
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
UL1 1 1 1
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
CL30 1 2 0.1U_0402_10V7K PCIE_PRX_LANTX_P3_C 17 1 MDI0+ 1 1 1 1 CL20 CL22 CL26
[12] PCIE_PRX_LANTX_P3 HSOP MDIP0
CL31 1 2 0.1U_0402_10V7K PCIE_PRX_LANTX_N3_C 18 4 MDI1+
[12] PCIE_PRX_LANTX_N3 HSON MDIP1 2 2 2
2 MDI0- CL21 CL45 CL34 CL35
MDIN0 5 MDI1-
PCIE_PTX_LANRX_P3 13 MDIN1 2 2 2 2
[12] PCIE_PTX_LANRX_P3 HSIP
PCIE_PTX_LANRX_N3 14
[12] PCIE_PTX_LANRX_N3 HSIN 8 +LAN_VDD
AVDD10 30
19 AVDD10 32
[6,10,25,29] PCH_PLTRST#_EC PERSTB AVDD33 +LAN_IO
23
B
R2360 1 @ 2 0_0402_5% ISOLATEB 20 DVDD33 B
[28] LAN_DISABLE#_R ISOLATEB 15
[11,29] LAN_WAKE#
R2363 1 @ 2 0_0402_5% LAN_WAKE#_R 21
LANWAKEB
REFCLK_P
REFCLK_N
16
CLK_PCIE_LAN
CLK_PCIE_LAN#
[9]
[9] These caps close to Pin 23 These caps close to Pin 22 These caps close to Pin 3,8,30
R2532 1 @ 2 0_0402_5% WLAN_LAN_DISBL 26 12
[25,28] PCIE_WAKE# GPO CLKREQB LAN_CLKREQ# [9]
28 XTLO
CKXTAL1 29 XTLI
X02.08 +LAN_VDD 3 CKXTAL2
MDI2+ 6 AVDD10 27 @ T94 PAD~D
MDI2- 7 MDIP2 LED0 25 @ T95 PAD~D
MDI3+ 9 MDIN2 LED1 CL36
MDI3- 10 MDIP3 31 RL31 2 1 2.49K_0402_1% XTLI 2 1
11 MDIN3 RSET
+LAN_IO AVDD33
+LAN_VDD 22 33 YL2 10P_0402_50V8J
1 2 24 DVDD10 GND 2 1
+LAN_VDD REGOUT GND0 XTAL0
L18 2.2UH_NLC252018T-2R2J-N_5%
1 1 RTL8111GUS-CG_QFN32_4X4 4 3
CL25 GND1 XTAL1
1
4.7U_0402_6.3V6M CL24 25MHZ_10PF_7V25000014 CL37
0.1U_0402_10V7K CL42 @ XTLO 2 1
2 2 0.1U_0402_10V7K
2 10P_0402_50V8J
C C
TL2 JLAN
+LAN_IO MDI3- 1 24 MDO3-
TD1+ TX1+ MDO3- 8
MDI3+ 2 23 MDO3+ PR4-
TD1- TX1- MDO3+ 7
+V_DAC 3 22 MCT0 PR4+
TDCT1 TXCT1
1
+3VS MDO1- 6
+V_DAC 4 21 MCT1 PR2-
R11 TDCT2 TXCT2 MDO2- 5
Place close to TCT pin PR3-
1
100K_0402_5% MDI2- 5 20 MDO2-
RL33 TD2+ TX2+ MDO2+ 4
2
1K_0402_5% MDI2+ 6 19 MDO2+ PR3+
[28] WLAN_LAN_DISBL# TD2- TX2- RL19 1 2 75_0603_5% MDO1+ 3
MDI1- 7 18 MDO1- RL20 1 2 75_0603_5% PR2+
2
TD3+ TX3+
1
D RL39 1 2 75_0603_5% MDO0- 2
ISOLATEB WLAN_LAN_DISBL 2 Q9 MDI1+ 8 17 MDO1+ RL40 1 2 75_0603_5% PR1-
G TD3- TX3- MDO0+ 1
L2N7002LT1G_SOT23-3 PR1+
1
S +V_DAC 9 16 MCT2
3
TDCT3 TXCT3 9
@ RL30 +V_DAC 10 15 MCT3 GND
15K_0402_1% TDCT4 TXCT4 10
1 GND
2 MDI0- 11 14 MDO0- EMI@
2
TD4+ TX4+ CL33
CL41 MDI0+ 12 13 MDO0+ 10P_1206_2KV8J CONN@
TD4- TX4- 2
0.01U_0402_16V7K
1
TAIMA_IH-115-F
D D
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 22 of 54
1 2 3 4 5
5 4 3 2 1
CA53, CA55 change Value
CA71, CA51 place close to Pin 26 from 10U_0603_6.3V6M~D to
4.7U_0603_6.3V6K
CA57,CA58 close +5VA +5V_PVDD +5V_PVDD
to UA1 pin1 +1.5VS +CODEC_AVDD2
+3VA
10U_0603_6.3V6M
CA71
10U_0603_6.3V6M
CA53
10U_0603_6.3V6M
CA55
1
1
1 1 1 RA8 1 2 0_0402_5%
0.1U_0402_10V7K
CA51
0.1U_0402_10V7K
CA54
0.1U_0402_10V7K
CA56
1 1
2
+5VS +5V_PVDD
CA58
0.1U_0402_10V7K
4.7U_0603_6.3V6K
CA57
2 2 2
2 2 RA1110 1 2 0_0603_5%
D D
+5VS +5VA JACK_SENSE#
L2N7002WT1G_SC-70-3
RA1111 1 2 0_0603_5%
+3VA 1 +CODEC_AVDD2
1
UA1 CA61 +3VS +3VA D
CA59 CA60 close 1 1
QA7
CA59 CA60 1 26 4.7U_0603_6.3V6K 2
DVDD AVDD1 AUD_HP_NB_SENSE [28]
4.7U_0603_6.3V6K 0.1U_0402_10V7K 40
to UA1 pin9 9 AVDD2 2 RA1125 1 2 0_0603_5% S
G
3
DVDD-IO
1
2 2
1
0.1U_0402_10V7K
CA75
36 +3VA @
CPVDD 41 RA1128
6 PVDD1 46 +MIC2-VREFO 100K_0402_5%
[8] PCH_AZ_CODEC_BITCLK BCLK PVDD2 2
2
5 2 1 SLEEVE
[8] PCH_AZ_CODEC_SDOUT SDATA-OUT 13 JACK_SENSE# RA53 2.2K_0402_5%
10 HP/LINE1 JD(JD1) 14
[8] PCH_AZ_CODEC_SYNC SYNC MIC2/LINE2 JD(JD2) 15 2 1 RING2 X02.08
1 2 8 SPDIFO/FRONT JD(JD3)/GPIO3 RA1109 2.2K_0402_5%
[8] PCH_AZ_CODEC_SDIN0 SDATA-IN
RA130 33_0402_5% RA1114 1 @ 2 0_0603_5%
11
[8] PCH_AZ_CODEC_RST# RESETB 32 HPOUT-L RA1115 1 @ 2 0_0603_5%
HPOUT-L(PORT-I-L) 33 HPOUT-R Place on the moat between GND & GNDA.
@ LINE1-R 21 HPOUT-R(PORT-I-R) RA1116 1 @ 2 0_0603_5%
RA1112 LINE1-L 22 LINE1-R(PORT-C-R)
0_0402_5% Line1-VREFO-R 30 LINE1-L(PORT-C-L) +3VA RA1117 1 @ 2 0_0603_5%
PCH_AZ_CODEC_BITCLK 1 2 Line1-VREFO-L 31 LINE1-VREFO-R 42 INT-SPK-L+
23 LINE1-VREFO-L SPK-OUT-L+ 43 INT-SPK-L-
1 LINE2-R(PORT-E-R) SPK-OUT-L- 1
@ 24 45 INT-SPK-R+ CA77
CA21 LINE2-L(PORT-E-L) SPK-OUT-R+ 44 INT-SPK-R- 4.7U_0603_6.3V6K
22P_0402_50V8J SPK-OUT-R-
2 16 2 GNDA GND
+3VA MONO-OUT
2 LA1 EMI@
GPIO0/DMIC-DATA MIC_DATA [21]
29 3 MIC_CLK_C 1 2 MIC_CLK Line1-VREFO-L
+MIC2-VREFO
RING2 17 MIC2-VREFO GPIO1/DMIC-CLK 48 BLM15BB221SN1D_2P
MIC_CLK [21] close PIN36 Line1-VREFO-R
MIC2-L(PORT-F-L)/RING SPDIF-OUT/GPIO2
2
C SLEEVE 18 C
RA10 2 1 MIC1-L 19 MIC2-R(PORT-F-R)/SLEEVE
MIC_CAP 1
1
10K_0402_5% 10U_0603_6.3V6M CA74 37 @
CBP 35 1U_0402_6.3V6K 2 1 CA24 CA22 RA165 RA166
RA1130 1 @ 2 0_0402_5% 20 CBN 22P_0402_50V8J 4.7K_0402_5%
+3VA 4.7K_0402_5%
1
NC 2
RC38 1 2 0_0402_5% 47 X02.10
[28] EC_MUTE# close PIN3
2
PDB 28 2.2U_0402_6.3V6M 2 1 CA23
RA1129 1 2 100K_0402_5% VREF 12
CA62 1 2 10U_0603_6.3V6M 27 PCBEEP 34 1U_0402_6.3V6K 2 1 CA25 LINE1-L CA67 1 2 1 2 Line-IN-L
1 LDO1-CAP CPVEE
CA63 1 2 10U_0603_6.3V6M 39 4.7U_0603_6.3V6K RA80 1K_0402_1%
CA76 CA64 1 2 10U_0603_6.3V6M 7 LDO2-CAP LINE1-R CA68 1 2 1 2 Line-IN-R
LDO3-CAP CA65 1 2 1 2 PC_BEEP 4.7U_0603_6.3V6K RA82 1K_0402_1%
1U_0402_6.3V6K
2 0_0402_5% 0.1U_0402_10V7K RA79 20K_0402_5%
1 2 4 25
DVSS AVSS1 DA8
@ RA1113 38 @CA69
@ CA69 1 2 100P_0402_50V8J
49 AVSS2 2
GND EC Beep [29] BEEP
ALC3234-CG_MQFN48_6X6 RA81 2 1 10K_0402_5% 1 PC_BEEP
3
MCU Beep [11] HDA_SPKR
1
@
BAT54CW_SOT323-3 RA19
10K_0402_5%
2
PC Beep
+RTCVCC Close to UA1
Pin11,13,14,16
close to Codec
1
B SLEEVE JSPK B
INT-SPK-R- EMI@ RA1121 1 2 BLM15PX181SN1D_2P SPK_R1-_CONN 1
RA5 INT-SPK-R+ EMI@ RA1122 1 2 BLM15PX181SN1D_2P SPK_R2+_CONN 2 1
470K_0402_5% INT-SPK-L- EMI@ RA1123 1 2 BLM15PX181SN1D_2P SPK_L1-_CONN 3 2
INT-SPK-L+ EMI@ RA1124 1 2 BLM15PX181SN1D_2P SPK_L2+_CONN 4 3
2
5 4
G1
3
6
Trace width for SPK-L+/SPK-L-/SPK-R+/SPK-R- G2
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
D
5 G QA6A
QA6B DMN66D0LDW-7_SOT363-6 ACES_50278-00401-001
S
Speaker 4 ohm : 40mil
1
EMI@ CA29
EMI@ CA30
EMI@ CA31
EMI@ CA32
DMN66D0LDW-7_SOT363-6 CONN@
4
6
EC_MUTE# 1 2 2 G
D Speaker 8 ohm : 20mil
2
RA6 10K_0402_5% S
1
+3VA
2
RA1120
10K_0402_5%
JHP normal open
1
RING2_L 3
AUD_HP_OUT_L_CN 1
iPhone and Nokia type Combo Jack AUD_HP_NB_SENSE 6
EMI@ AUD_HP_OUT_R_CN 2
SLEEVE 40mil LA10 2 1 BLM15PX330SN1D_2P 40mil SLEEVE_L
EMI@ SLEEVE_L 4
RA55 RING2 40mil LA11 2 1 BLM15PX330SN1D_2P 40mil RING2_L 7
2
15_0402_1% EMI@
AZ5125-02S.R7G_SOT23-3
DA13 ESD@
HPOUT-L 1 2 Line-IN-L LA8 2 1 MURATA BLM15AX700SN1D_2P AUD_HP_OUT_L_CN SINGA_2SJ3080-001111F
EMI@ CONN@
A HPOUT-R 1 2 Line-IN-R LA9 2 1 MURATA BLM15AX700SN1D_2P AUD_HP_OUT_R_CN A
3
15_0402_1%
1
RA56
AZ5125-02S.R7G_SOT23-3
DA10 ESD@
AZ5123-01F.R7G DFN1006P2X
DA12 ESD@
AZ5123-01F.R7G DFN1006P2X
DA14 ESD@
RA84 RA83 1 1
1
1
100P_0402_50V8J
CA39 EMI@
100P_0402_50V8J
CA33 EMI@
690P_0402_50V8J
CA38
690P_0402_50V8J
CA40
10K_0402_5% 10K_0402_5%
1
@ @
2
2 2
2
2
EMI@
EMI@
Security Classification Compal Secret Data Compal Electronics, Inc.
1
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 23 of 54
5 4 3 2 1
5 4 3 2 1
USB connector1
+5VALW
USB20 port0
USB30 port1
1
CI12
LI1 EMI@ 1U_0603_10V6K +5V_USB_PWR1
[12] USB3RN1_JUSB1
USB3RN1_JUSB1 1 2 USB3RN1_JUSB1_R
2
2.0A
D D
USB3RP1_JUSB1 4 3 USB3RP1_JUSB1_R UI3 +5V_USB_PWR1
[12] USB3RP1_JUSB1
1
CMMI21T-670Y-N_4P 5 OUT 80mil JUSB1
IN 2 1
GND VBUS
10U_0603_6.3V6M
0.1U_0402_10V7K
4 USB20_JUSB1_N0_R 2
[28] USB_PWR_EN1# EN D-
100U_1206_6.3V6M
3 USB20_JUSB1_P0_R 3
OCB USB_OC0# [12] D+
1 1 1 4
GND
1
@ CI13 1 USB3RN1_JUSB1_R 5
StdA-SSRX-
CI1
CI40
CI2
SY6288D20AAC_SOT23-5 @ CI15 USB3RP1_JUSB1_R 6 10
0.1U_0402_10V7K 7 StdA-SSRX+ GND 11
2
2 0.1U_0402_10V7K 2 2 USB3TN1_JUSB1_R 8 GND-DRAIN GND 12
StdA-SSTX- GND
3
2 USB3TP1_JUSB1_R 9 13
@ DI2 StdA-SSTX+ GND
PJDLC05C_SOT23-3 TAITW_PUBAU6-09FLBS1NN4H0
LI3 EMI@ ESD@ CONN@
USB3TN1_JUSB1 2 1 USB3TN1_JUSB1_C 1 2 USB3TN1_JUSB1_R
[12] USB3TN1_JUSB1
CI3 0.1U_0402_10V7K
USB3TP1_JUSB1 2 1 USB3TP1_JUSB1_C 4 3 USB3TP1_JUSB1_R
[12] USB3TP1_JUSB1
CI4 0.1U_0402_10V7K ESD@
1
CMMI21T-670Y-N_4P DI1
USB3RN1_JUSB1_R 1 10 USB3RN1_JUSB1_R
X02.20
USB3RP1_JUSB1_R 2 9 USB3RP1_JUSB1_R
USB3TN1_JUSB1_R 4 7 USB3TN1_JUSB1_R
USB3TP1_JUSB1_R 5 6 USB3TP1_JUSB1_R
8
DLW21HN900HQ2L_4P
USB20_JUSB1_N0 4 3 USB20_JUSB1_N0_R IP4292CZ10-TBR_XSON10_2.5X1
[12] USB20_JUSB1_N0 4 3
C C
USB20_JUSB1_P0 1 2 USB20_JUSB1_P0_R
[12] USB20_JUSB1_P0 1 2
LI2 EMI@
+5VALW 2.0A USB connector2
USB20 port1
1
CI6
USB30 port2
1U_0603_10V6K
+5V_USB_PWR2
2
LI4 EMI@
USB3RN2_JUSB2 1 2 USB3RN2_JUSB2_R
[12] USB3RN2_JUSB2
UI2 80mil
1
USB3RP2_JUSB2 4 3 USB3RP2_JUSB2_R 5 OUT
[12] USB3RP2_JUSB2 IN +5V_USB_PWR2
B
2 B
CMMI21T-670Y-N_4P 4 GND
[28] USB_PWR_EN3# EN 3 JUSB2
OCB USB_OC1# [12]
1 1
VBUS
10U_0603_6.3V6M
0.1U_0402_10V7K
@ CI26 1 USB20_JUSB2_N1_R 2
D-
100U_1206_6.3V6M
SY6288D20AAC_SOT23-5 @ CI17 USB20_JUSB2_P1_R 3
0.1U_0402_10V7K 4 D+
1 1 GND
1
2 0.1U_0402_10V7K USB3RN2_JUSB2_R 5
2 StdA-SSRX-
CI8
CI43
CI9
USB3RP2_JUSB2_R 6 10
7 StdA-SSRX+ GND 11
2
2 2 USB3TN2_JUSB2_R 8 GND-DRAIN GND 12
LI6 EMI@ USB3TP2_JUSB2_R 9 StdA-SSTX- GND 13
StdA-SSTX+ GND
3
USB3TN2_JUSB2 2 1 USB3TN2_JUSB2_C 1 2 USB3TN2_JUSB2_R @
[12] USB3TN2_JUSB2
CI10 0.1U_0402_10V7K DI5 TAITW_PUBAU6-09FLBS1NN4H0
PJDLC05C_SOT23-3 CONN@
USB3TP2_JUSB2 2 1 USB3TP2_JUSB2_C 4 3 USB3TP2_JUSB2_R ESD@
[12] USB3TP2_JUSB2
CI11 0.1U_0402_10V7K
CMMI21T-670Y-N_4P
1
X02.20
ESD@
DI4
USB3RN2_JUSB2_R 1 10 USB3RN2_JUSB2_R
DLW21HN900HQ2L_4P
USB20_JUSB2_N1 4 3 USB20_JUSB2_N1_R USB3RP2_JUSB2_R 2 9 USB3RP2_JUSB2_R
[12] USB20_JUSB2_N1 4 3
USB3TN2_JUSB2_R 4 7 USB3TN2_JUSB2_R
USB20_JUSB2_P1 1 2 USB20_JUSB2_P1_R
[12] USB20_JUSB2_P1 1 2 USB3TP2_JUSB2_R 5 6 USB3TP2_JUSB2_R
LI5 EMI@
3
A A
8
IP4292CZ10-TBR_XSON10_2.5X1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 24 of 54
5 4 3 2 1
5 4 3 2 1
closed to pin 2, 4 closed to pin 64, 66
+3VS_WLAN_NGFF +3VS_WLAN_NGFF
D D
0.1U_0402_10V7K
0.1U_0402_10V7K
22U_0603_6.3V6M
22U_0603_6.3V6M
1 1 1 1
+3VS_WLAN_NGFF
+3VALW TO +3VS_WLAN_NGFF
CM4
CM6
CM5
CM7
JNGFF
1 2 2 2 2 2
3 GND 3.3VAUX 4
[12] USB20_MINI1_P4 USB_D+ 3.3VAUX +3VS +3VS_WLAN_NGFF
5 6 @ T3861 PAD~D
[12] USB20_MINI1_N4 USB_D- LED1#
7 8
9 GND PCM_CLK 10
11 SIDO_CLK PCM_SYNC 12
13 SDIO_CMD PCM_IN 14 RM7
SDO_DAT0 PCM_OUT
0.1U_0402_10V7K
15 16 1 2
SDO_DAT1 LED2# @ T3862 PAD~D
17 18
19 SDO_DAT2 GND 20 0_0805_5%
SDO_DAT3 UART_WAKE# 2
21 22 @
SDIO_WAKE# UART_RX +3VALW
CM3
23
SDIO_RESET# UM1
1
1 7
24 2 VIN VOUT 8
25 UART_TX 26 VIN VOUT
CM2 1 2 0.1U_0402_10V7K PCIE_PTX_WLANRX_P4_C 27 GND UART_CTS 28 3 6
[12] PCIE_PTX_WLANRX_P4 PETP0 UART_RTS [28] AUX_EN_WOWL ON CT
CM1 1 2 0.1U_0402_10V7K PCIE_PTX_WLANRX_N4_C 29 30
[12] PCIE_PTX_WLANRX_N4 PETN0 RESERVED
31 32
GND RESERVED
1
33 34 4
[12] PCIE_PRX_WLANTX_P4 PERP0 RESERVED VBIAS
1
35 36 RM8 5 @
[12] PCIE_PRX_WLANTX_N4 PERN0 COEX3 @ T4927 PAD~D GND
37 38 9 CM8
39 GND COEX2 40
@ T4928 PAD~D X02.08 100K_0402_5% GND
2200P_0402_25V7K
[9] CLK_PCIE_WLAN @ T4929 PAD~D
2
41 REFCLKP0 COEX1 42 SUSCLK_NGFF RM5 1 @ 2 0_0402_5%
[9] CLK_PCIE_WLAN# SUSCLK [10]
2
43 REFCLKN0 SUSCLK 44 PLT_RST#_R RM6 1 @ 2 0_0402_5% TPS22967DSGR_SON8_2X2
GND PERST0# PCH_PLTRST#_EC [6,10,22,29]
45 46
[9] WLAN_CLKREQ# CLKEQ0# W_DISABLE2# BT_RADIO_DIS# [28]
47 48
[22,28] PCIE_WAKE#
49 PEWAKE0# W_DISABLE1# 50
WLAN_WIGIG60GHZ_DIS# [28] X02.05
51 GND I2C_DATA 52
53 RSRVD/PETP1 I2C_CLK 54
C RSRVD/PETN1 ALERT C
55 56
57 GND RESERVED 58
59 RSRVD/PERP1 RESERVED 60
61 RSRVD/PERN1 RESERVED 62
63 GND RESERVED 64
65 RESERVED 3.3VAUX 66
67 RESERVED 3.3VAUX
GND
69 68
MTG77 MTG76
LOTES_APCI0019-P009A
CONN@
B B
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 25 of 54
5 4 3 2 1
A B C D E F G H
PERICOM PI3EQX6741ST: +3VS
Pin6/16, NC
Pin8/9, Pre-emphasis
SATA HDD Connector
0.01U_0402_16V7K
0.1U_0402_25V6K
TI SN75LVCP601RTJR CONN@
Pin6/16, de-emphasis width setup 1 1 ACES_50208-01001-001
Pin8/9, de-emphasis 12
+3VS GND
CS27
CS29
US2 11
DEW2_REXT 6 10 2 2 GND
Parade PS8527CT-A1 X02.07 NC VDD
DEW1 16 20
Pin6/16, output swing, de-emphasis width setup NC VDD +3VS
Pin8/9, de-emphasis 3 13
A_EQ 17 TDet_B# TDet_A# 19 B_EQ
1 A_EQ B_EQ 1
A_EM 9 8 B_EM
A_EM B_EM
2
RS22 1 @ 2 0_0402_5% 7 18 TDeT_EN SATA_PRX_DTX_P0 10
EN TDeT_EN RN5 SATA_PRX_DTX_N0 9 10
CS37 1 2 0.01U_0402_16V7K SATA_PTX_DRX_P0_R 1 15 SATA_PTX_DRX_P0_RC CS30 1 2 0.01U_0402_16V7K SATA_PTX_DRX_P0 8 9
[8] SATA_PTX_DRX_P0_C AI+ AO+ 10K_0402_5% 8
CS36 1 2 0.01U_0402_16V7K SATA_PTX_DRX_N0_R 2 14 SATA_PTX_DRX_N0_RC CS32 1 2 0.01U_0402_16V7K SATA_PTX_DRX_N0 @ SATA_PTX_DRX_N0 7
[8] SATA_PTX_DRX_N0_C AI- AO- 7
SATA_PTX_DRX_P0 6
1
CS33 1 2 0.01U_0402_16V7K SATA_PRX_DTX_N0_RC 4 12 SATA_PRX_DTX_N0_R CS31 1 2 0.01U_0402_16V7K SATA_PRX_DTX_N0 5 6
[8] SATA_PRX_DTX_N0_C BO- BI- 5
CS35 1 2 0.01U_0402_16V7K SATA_PRX_DTX_P0_RC 5 11 SATA_PRX_DTX_P0_R CS34 1 2 0.01U_0402_16V7K SATA_PRX_DTX_P0 RS8 1 @ 2 0_0402_5% JHDD_P10 4
[8] SATA_PRX_DTX_P0_C BO+ BI+ [11] HDD_DEVSLP
HDD_DET# 3 4 X02.02
[8] HDD_DET# 3
21 2
GND 1 2
+5V_HDD 1
PI3EQX6741STZDEX_TQFN20_4X4 JHDD
+3VS
@
RS41 1 2 100K_0402_5% DEW2_REXT RS40 1 @ 2 0_0402_5%
+5V_HDD
X02.07
@
RS43 1 2 100K_0402_5% DEW1 RS42 1 @ 2 0_0402_5%
+5V_HDD Source
@
RS21 1 2 100K_0402_5% A_EQ RS25 1 @ 2 0_0402_5%
0.1U_0402_25V6K
@
1000P_0402_50V7K
10U_0805_10V6K
RS30 1 2 100K_0402_5% A_EM RS32 1 @ 2 0_0402_5%
1 1
1
@
RS19 1 2 100K_0402_5% B_EQ RS38 1 @ 2 0_0402_5% +5V_HDD @ +5VS
PJP13 CS5 CS6 CS7
@
RS36 1 2 100K_0402_5% B_EM RS35 1 @ 2 0_0402_5% 1 2
2
1 2 2 2
@
RS24 1 2 100K_0402_5% TDeT_EN RS33 1 @ 2 0_0402_5% JUMP_43X79
2 SHORT DEFAULT 2
DEW2 B_EM A_EM TDeT_A DEW1 A_EQ TDeT_EN B_EQ
PIN6 PIN8 PIN9 PIN13 PIN16 PIN17 PIN18 PIN19
Pericom PI3EQX6741ST NC PD
(RS35)
NC
(IPU)
PD NC NC PH
(RS24) (RS38)
PD
TI SN75LVCP601 NC
(IPU)
PD
(RS35)
PD
(RS32)
PD NC
(IPU)
PD
(RS25)
PD
(RS33)
NC
Parade PS8527C PD
(RS40)
PD
(RS35)
PH
(RS30)
PD NC PD
(RS25)
PD
(RS33)
NC
A_EQ B_EQ A_EM B_EM
0 3dB 3dB 0 0dB 0dB
Main Pericom NC 6dB 6dB NC
1 9dB 9dB 1 1.5dB 1.5dB
0 7dB 7dB 0 0dB 0dB
3 2nd TI NC 0dB 0dB NC -6dB -6dB
Finger print 3
1 14dB 14dB 1 -3dB -3dB
EQ2 EQ1 A_EQ B_EQ A_EM B_EM
X02.08 +3.3V_BIO
(M = VDD/2)
RS39 1 @ 2 0_0402_5%
0 M 2.4dB 2.4dB +3VS
0 0 7.4dB 7.4dB CS28
1
3rd Parade 14.4dB 14.4dB RS26 1 @ 2 0_0402_5%
0 1 0 0dB 0dB 0.1U_0402_25V6K
2 E-T_6916K-Q06N-00L
M M 12.2dB 12.2dB M -3.5dB -3.5dB RS27 1 @ 2 0_0402_5%
6 8
L12 5 6 G2 7
M 0 9.4dB 9.4dB 1 -1.5dB -1.5dB 1 EMI@
2 USB20_BIO_N3_R 4 5 G1
[12] USB20_BIO_N3 1 2
13.3dB 13.3dB 3 4
M 1 2 3
4 3 USB20_BIO_P3_R 1 2
1 M 6.2dB 6.2dB [12] USB20_BIO_P3 4 3 1
11.2dB 11.2dB DLW21HN900HQ2L_4P JFP
1 0 CONN@
3
1 1 5dB 5dB DS1
*
r
e
d
c
o
l
o
r
i
s
c
u
r
r
e
n
t
s
e
t
t
i
n
g
PJDLC05C_SOT23-3
ESD@
1
4 X02.20 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 26 of 54
A B C D E F G H
5 4 3 2 1
+5V_USB_PWR3 +3VS
IO to MB CONN
+5VALW 1 1
1
CI48 JIO
0.1U_0402_10V7K
CI49
10U_0603_6.3V6M
CI50
1U_0402_6.3V6K
+5V_USB_PWR3 1
2 1
ON/OFF switch
2
2 2 3 2
4 3
1 4
CI44 +5V_USB_PWR3 5
1U_0603_10V6K 6 5
2
2.0A +3VS
7
8
6
7 TOP Side
UI4 80mil close to JIO power pin 9 8
1 10 9 SW1
D OUT 10 D
5 USB20_CR_P6 11 EVQPLHA15_4P
IN [12] USB20_CR_P6 11
2 USB20_CR_N6 12 3 1
GND [12] USB20_CR_N6 12
4 13
[28] USB_PWR_EN2# EN 13
3 USB20_JUSB3_P2 14 4 2
OCB USB_OC2# [12] [12] USB20_JUSB3_P2 14 POWER_SW#_MB [10,29]
1 USB20_JUSB3_N2 15
[12] USB20_JUSB3_N2 15
@ CI46 1 16
5
6
16
1
SY6288D20AAC_SOT23-5 @ CI47
0.1U_0402_10V7K 17
2 0.1U_0402_10V7K 18 GND X02.22
2 GND DW1
ACES_51524-0160N-001 AZ5125-01H.R7G_SOD523-2
CONN@ @
2
X02.06
C
LED/B TO M/B C
+5VS +5VALW +3VALW
1 1 1
+3VALW +5VALW CZ50 CZ51 CZ49
X02.04 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
JLED 2 2 2
1
X02.04 2 1
3 2
4 3
[29] LID_CL#
5 4 close to JLED power pin
[29] BAT1_LED# 5
6 9
[29] BAT2_LED# 6 G1
7 10
8 7 G2
X02.04 [29] BREATH_LED# 8
ACES_51524-0080N-001
CONN@
B B
+3VS +3VS_TP
R246 2 1 0_0603_5%
+3VS
FAN Touch pad
1
+5VS
RE50 +3VS_TP
10K_0402_5%
+3VS_TP
1
40mil JFAN
2
1 +3VS_TP CE68
2 1 1U_0402_6.3V6K
[29] FAN1_TACH 2 CONN@ 2
1 @ 2 3
[29] FAN1_PWM 3
1
RE58 0_0402_5% 4 JTP
4
10U_0603_6.3V6M
1 R2521 R2522 1
1
2
@ 5 4.7K_0402_5% 4.7K_0402_5% 2
X02.08 GND 2
1
CE24 DE3 D1 6 3
GND 3
C7
0.01U_0402_16V7K PJDLC05C_SOT23-3 4
2
2 ESD@ 5 4
ACES_50279-0040N-001
2
RB751S40T1G_SOD523-2 6 5 9
[29] CLK_TP_SIO
2
7 6 G1 10
[29] DAT_TP_SIO 7 G2
8
8
3
1
DE1
X02.20 PJDLC05C_SOT23-3
ESD@
X02.15
A A
1
X02.20
Security Classification Compal Secret Data
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 27 of 54
5 4 3 2 1
5 4 3 2 1
D D
+3VALW +3VALW_1099
PJP14
1 2
10U_0603_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
PAD-OPEN1x1m
1
@
1
CE4
CE3
CE10
2
2
28
8
+3VALW_1099 UE4
VCC
VCC
RPE9
PCIE_WAKE# [22,25]
8 1 USB_PWR_EN2# 32
[29] BC_DAT_ECE1099 BC_DAT/SMB_DATA
7 2 USB_PWR_EN1# 33
[29] BC_CLK_ECE1099 BC_CLK/SMB_CLK
6 3 USB_PWR_EN3#
5 4 9 SMART_DET# PAD~D T32@
GPIO21/KSO01 10 PCIE_WAKE#_R 2 @ 1 1 2
GPIO22/KSO02 PCH_PCIE_WAKE# [10,29]
100K_0804_8P4R_5% 39 11 CPU_ID 0_0402_5% RE275 0_0402_5% @ RE274
[10] SIO_SLP_WLAN#
EXPRESS_DET# 40 GPIO10/KSI0 GPIO23/KSO03 12 BT_RADIO_DIS# X02.12
C
1 2 WLAN_WIGIG60GHZ_DIS#
@ T100 PAD~D
1 GPIO11/KSI1 GPIO24/KSO04 13
BT_RADIO_DIS# [25] X02.08 C
[22] LAN_DISABLE#_R GPIO12/KSI2 GPIO25/KSO05 WLAN_LAN_DISBL# [22]
RE14 100K_0402_5% 2 14 Stuff RE275 and no stuff RE274 keep E5 design
1 2 BT_RADIO_DIS#
[23] AUD_HP_NB_SENSE
3 GPIO13/KSI3 GPIO26/KSO06 15 X02.04 Stuff RE274 and no stuff RE275 to save two GPIOs on EC(PCH_PCIE_WAKE# should be output with OD)
RE13 100K_0402_5% [23] EC_MUTE# 4 GPIO14/KSI4 GPIO27/KSO07 16
1 2 PCIE_WAKE#_R 5 GPIO15/KSI5 GPIO30/KSO08 17 WLAN_WIGIG60GHZ_DIS#
RE35 10K_0402_5% [21] PANEL_BKEN_EC 6 GPIO16/KSI6 GPIO31/KSO09 18 PCIE_WAKE#_R WLAN_WIGIG60GHZ_DIS# [25]
[25] AUX_EN_WOWL USB_DB_DET# 7 GPIO17/KSI7 GPIO32/KSO10 19 VGA_ID
@ T102 PAD~D GPIO20/KSO00 GPIO33/KSO11 20
GPIO34/KSO12 DGPU_PWROK [10,44,45]
21
GPIO35/KSO13 22 GPU_PWR_LEVEL +3VALW_1099 +3VALW_1099
GPIO36/KSO14 23 GPU_PWR_LEVEL [45]
GPIO37/KSO15 24
GPIO00/KSO16
2
1 2 SMB_ADDR 25 USB_PWR_EN3#
GPIO01/KSO17 USB_PWR_EN3# [24]
RE87 10K_0402_5% 26 RE279 HSW@ RE89 @
GPIO02/KSO18 27
GPIO03/KSO19 100K_0402_5% 100K_0402_5%
29
X02.04 34 GPIO04/KSO20 30 USB_PWR_EN1#
[29] BC_INT#_ECE1099 USB_PWR_EN1# [24]
1
BC_INT#/SMB_INT# GPIO05/KSO21 31 USB_PWR_EN2#
SMB_ADDR 35 GPIO06/KSO22 36 TOUCH_SCREEN_PD# USB_PWR_EN2# [27] CPU_ID VGA_ID
SMB_ADDR GPIO07 PAD~D T101@
37
RESERVED
1
2 1 38 RE280 BDW@ RE90
10K_0402_5% RE24 TEST_PIN 41
Thermal Slug(VSS) 100K_0402_5% 100K_0402_5%
ECE1099-FZG_QFN40_6X6~D
2
CPU_ID VGA_ID
HSW 1 UMA 1
B B
BDW 0 Discrete 0
X02.12
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 28 of 54
5 4 3 2 1
5 4 3 2 1
+RTCVCC
1 @ 2 +RTC_CELL_VBAT
0.1U_0402_25V6
RE32 0_0402_5%
CE65
2
+3VALW_5085
0.1U_0402_25V6
1U_0402_6.3V6K
+3VALW_5085
1
CE63
CE14
1 2 BC_DAT_ECE1099
RE39 100K_0402_5% +3VALW_5085
2
1 2 PBAT_SMBDAT
RE38 2.2K_0402_5%
1 2 PBAT_SMBCLK
RE45 2.2K_0402_5%
1U_0402_6.3V6K
0.1U_0402_25V6
D +3VS D
1
CE64
CE17
1 2 FAN1_PWM UE5
RE48 10K_0402_5%
2
B64 A10 AC_DIS [41]
VBAT GPIO021/RC_ID1 B10 BOARD_ID
GPIO020/RC_ID2 B8
RPE10 +3VALW +3VALW_5085 A22 GPIO014/GPTP-IN7/RC_ID3 B27
H_VTR GPIO025/UART_CLK LAN_WAKE# [11,22]
8 1 RUN_ON B44 HOST_DEBUG_TX
7 2 SUS_ON PJP15 GPIO120/UART_TX/V2P_COUT_HI1 B46 +3VALW_5085
GPIO124/GPTP-OUT5/UART_RX/V2P_COUT_LO1 ME_FWP_EC [8]
6 3 LCD_TST 1 2 A58 B26 RUNPWROK
5 4 PCH_ALW_ON VTR_ADC VCC_PWRGD A25 EN_INVPWR RUNPWROK [6]
GPIO060/KBRST/BCM_B_INT# EN_INVPWR [21]
10U_0603_6.3V6M
0.1U_0402_25V6
PAD-OPEN1x1m B36
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
GPIO101/ECGP_SCLK SIO_SLP_S4# [10]
100K_0804_8P4R_5% @ B3 B37 +3VS
VTR GPIO103/ECGP_MISO LAN_EN [22]
1
@CE46
A11 B38 RPE3
VTR GPIO105/ECGP_MOSI
CE42
CE43
CE38
CE41
CE44
CE40
1 2 EN_INVPWR A26 A34 PCH_ALW_ON CHARGER_SMBDAT 1 8
RE55 100K_0402_5% B35 VTR GPIO102/BCM_C_INT# A35 PCH_ALW_ON [31] CHARGER_SMBCLK 2 7
2
A41 VTR GPIO104/SLP_S0# A36 SIO_SLP_S3# [10] GPU_SMBDAT 3 6
1 2 RESET_OUT# A52 VTR GPIO106 A40 MSDATA PCH_DPWROK [10] GPU_SMBCLK 4 5
@ RE56 8.2K_0402_5% VTR GPIO116/MSDATA/V2P_COUT_LO/TAP_SEL_STRAP B43 MSCLK
GPIO117/MSCLK/V2P_COUT_HI A45 2.2K_0804_8P4R_5%
GPIO127/A20M B65 FWP# PCH_RSMRST# [10]
A5 nFWP
[9] SML1_SMBDATA GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA
B6 +RTCVCC
[9] SML1_SMBCLK GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK/GANG_DATA0
A37 B57 RPE5
[27] CLK_TP_SIO
B40 GPIO110/PS2_CLK2/GPTP-IN6 GPIO156/LED1/GANG_DATA1 B1
BREATH_LED# [27] X02.04 BC_DAT_ECE1117 1 8
[27] DAT_TP_SIO GPIO111/PS2_DAT2/GPTP-OUT6 GPIO157/LED0 BAT1_LED# [27]
LCD_TST A38 A55 VCI_IN3# 2 7
[21] LCD_TST GPIO112/PS2_CLK1A GPIO153/LED2/GANG_DATA4 BAT2_LED# [27]
for no‐dock : A38 use LCD_TST B41 A1 VCI_IN1# 3 6
GPIO113/PS2_DAT1A GPIO027/GPTP-OUT1 ALW_PWRGD_3V_5V [34]
for no‐dock : B41 use Free A39 B28 VCI_IN2# 4 5
[21] LCD_VCC_TEST_EN GPIO114/PS2_CLK0A GPIO026/GPTP-IN1
for no‐dock : A39 use SLP_ME_CSW_DEV# B42 B2
+RTCVCC for no‐dock :B42 use Free PBAT_SMBDAT B59 GPIO115/PS2_DAT0A GPIO001/ECSPI_CS1/32KHZ_OUT A8 100K_0804_8P4R_5%
[33] PBAT_SMBDAT GPIO154/I2C1C_DATA/PS2_CLK1B/GANG_DATA5 GPIO015/GPTP-OUT7 ME_SUS_PWR_ACK [10]
PBAT_SMBCLK A56 B9 RUN_ON
[33] PBAT_SMBCLK GPIO155/I2C1C_CLK/PS2_DAT1B/GANG_DATA6 GPIO016/GPTP-IN8 RUN_ON [31,36,39]
A9
GPIO017/GPTP-OUT8
1
100K_0402_5%
JTAG_TDI A51 B39 RESET_OUT#
GPIO145/I2C1K_DATA/JTAG_TDI GPIO107/NRESET_OUT RESET_OUT# [10,13]
RE31
JTAG_TDO B55 A44
JTAG_CLK B56 GPIO146/I2C1K_CLK/JTAG_TDO GPIO125/GPTP-IN5/PECI_REQUEST#/GANG_BUSY PCH_PCIE_WAKE# [10,28] +3VALW_5085
JTAG_TMS A53 GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK A54
GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS GPIO151/GPTP-IN4/GANG_DATA2 B58 AC_PRESENT [10]
JTAG_RST# B47 RPE6
SIO_PWRBTN# [6,10]
2
JTAG_RST# GPIO152/GPTP-OUT4 THERMATRIP3# 1 8
2 1 POWER_SW_IN# [27] FAN1_TACH FAN1_TACH B22 A3 2 7
[10,27] POWER_SW#_MB GPIO050/FAN_TACH1/GTACH0/GANG_START GPIO003/I2C1A_DATA
10K_0402_5% RE33 for no‐dock : A21 use LID_CL_SIO# LID_CL_SIO# A21 B4 MSDATA 3 6
GPIO051/FAN_TACH2/GANG _MODE GPIO004/I2C1A_CLK
1U_0402_6.3V6K
SUS_ON B23 A4 PCH_RSMRST# 4 5
[37] SUS_ON GPIO052/FAN_TACH3/GTACH1/GANG_ERROR GPIO005/I2C1B_DATA/BCM_B_DAT
1
trace width 20 mils B24 B5
[33] PS_ID GPIO053/PWM0 GPIO006/I2C1B_CLK/BCM_B_CLK SIO_EXT_WAKE# [11]
1
CE49
trace width 20 mils SUSACK# A23 B7 10K_8P4R_5%
[10] SUSACK# GPIO054/PWM1/GPWM1 GPIO012/I2C1H_DATA/I2C2D_DATA SYS_PWROK [6,10]
CE21 [21] BIA_PWM_EC B25 A7
ENVDD_PCH [10,21]
2
FAN1_PWM A24 GPIO055/PWM2 GPIO013/I2C1H_CLK/I2C2D_CLK/GANG_DATA3 B48 GPU_SMBDAT
1U_0402_6.3V6K [27] FAN1_PWM GPU_SMBDAT [45]
2
GPIO056/PWM3/GPWM0 GPIO130/I2C2A_DATA/BCM_C_DAT B49 GPU_SMBCLK
@ GPIO131/I2C2A_CLK/BCM_C_CLK GPU_SMBCLK [45]
A47 CHARGER_SMBDAT
GPIO132/I2C1G_DATA CHARGER_SMBDAT [41]
B50 CHARGER_SMBCLK
GPIO140/I2C1G_CLK CHARGER_SMBCLK [41]
for no‐dock : A43 use BC_CLK_ECE1099 A43 B52
[28] BC_CLK_ECE1099 GPIO123/BCM_A_CLK GPIO141/I2C1F_DATA/I2C2B_DATA SIO_SLP_SUS# [10]
for no‐dock : B45 use BC_DAT_ECE1099 BC_DAT_ECE1099 B45 A49
[28] BC_DAT_ECE1099 GPIO122/BCM_A_DAT GPIO142/I2C1F_CLK/I2C2B_CLK PBAT_PRES# [33,41]
for no‐dock : A42 use BC_INT#_ECE1099 A42 B53
C [28] BC_INT#_ECE1099 GPIO121/BCM_A_INT# GPIO143/I2C1E_DATA C
ACAV_IN 2 @ 1 ACAV_IN_NB B20 A50
RE278 0_0402_5% A18 GPIO032/BCM_E_CLK GPIO144/I2C1E_CLK
[10] SIO_SLP_S5# BEEP B19 GPIO031/GPTP-OUT2/BCM_E_DAT A59 1 2
[23] BEEP GPIO030/GPTP-IN2/BCM_E_INT#/GANG_DATA7 SYSPWR_PRES +3VLP
BC_CLK_ECE1117 A20 RE57 1K_0402_5%
[30] BC_CLK_ECE1117 GPIO047/LSBCM_D_CLK
1
100K_0402_5%
+3VALW_5085 [30] BC_DAT_ECE1117 BC_DAT_ECE1117 B21 B62
BC_INT#_ECE1117 A19 GPIO046/LSBCM_D_DAT/GANG_STROBE BGP0 A64 +3VS
[30] BC_INT#_ECE1117 GPIO045/LSBCM_D_INT# VCI_OVRD_IN ACAV_IN [41]
RE63
A60
VCI_OUT ALWON [31,34]
A6 B67 POWER_SW_IN#
[11] SIO_EXT_SMI# GPIO011/nSMI VCI_IN0#
1
1
100K_0402_5%
A27 A63 VCI_IN1#
2
[10,11] SIO_RCIN# A28 GPIO061/LPCPD# VCI_IN1# B63 VCI_IN2# RE67
[11] IRQ_SERIRQ SER_IRQ VCI_IN2#
RE25
PCH_PLTRST#_EC B30 B68 VCI_IN3# 10K_0402_5%
[6,10,22,25] PCH_PLTRST#_EC LRESET# VCI_IN3#
CLK_PCI_MEC A29
[9] CLK_PCI_MEC PCI_CLK
LPC_LFRAME# B31 B51 +1.05VS
[9] LPC_LFRAME#
2
2
LPC_LAD0 A30 LFRAME# VREF_PECI A48 PECI_EC_R 1 2
[9] LPC_LAD0 LAD0 PECI_DAT PECI_EC [6]
1
0.1U_0402_25V6
LPC_LAD1 B32 RE61 43_0402_5% RUNPWROK
[9] LPC_LAD1 LAD1
1 2 LID_CL_SIO# LPC_LAD2 A31 B13 REM_DIODE1_N CE58 1 2 2200P_0402_50V7K
[27] LID_CL# [9] LPC_LAD2 LAD2 DN1_DP1A/THERM
CE50
10_0402_5% RE26 LPC_LAD3 B33 A13 REM_DIODE1_P
[9] LPC_LAD3 LAD3 DP1_DN1A/VREF_T
A32 B14 REM_DIODE2_N CE70 1 2 2200P_0402_50V7K DE2
[10] CLKRUN# CLKRUN# DN2_DP2A
0.047U_0402_16V4Z
A33 A14 REM_DIODE2_P AZ5125-01H.R7G_SOD523-2
[11] SIO_EXT_SCI#
2
GPIO100/NEC_SCI DP2_DN2A
1
A15 REM_DIODE3_N CE39 1 2 2200P_0402_50V7K @ D
DN3_DP3A
1
MEC_XTAL1 A61 B16 REM_DIODE3_P [21,31] SUSP# 2 Q10
XTAL1 DP3_DN3A
CE13
MEC_XTAL2 2 @ 1 MEC_XTAL2_R A62 A16 REM_DIODE4_N CE60 1 2 2200P_0402_50V7K G L2N7002LT1G_SOT23-3
2
RE62 0_0402_5% XTAL2 DN4_DP4A B17 REM_DIODE4_P S
2
3
DP4_DN4A B15
VIN A17 VSET_5085
VSET CE58, CE39, CE60, Place near UE5
A12 I_ADP [41]
VCP B34 THERMATRIP2#
THERMTRIP2# A2 THERMATRIP3#
GPIO002/THERMTRIP3# B29 THSEL_STRAP THERMATRIP3# [45]
VSS_ADC
VSS_RO
GPIO024/THSEL_STRAP
VR_CAP
A46
[0910] connect to GPU
H_VSS
PROCHOT_IN#/PROCHOT_IO# H_PROCHOT# [6,38,41]
AGND
B61 1 2 I_BATT [41]
VSS
V_ISYS0 A57 RE64 4.7K_0402_5%
EP
V_ISYS1 I_SYS [41]
MEC5085-LZY_DQFN132_11X11
B66
B11
B60
+VR_CAP B12
B54
B18
C1
15mil
4.7U_0603_6.3V6K
S
e
t
t
i
n
g
f
o
r
T
h
e
r
m
a
l
D
e
s
i
g
n
1
CE45
2
ESR <2ohms
Thermal diode mapping
REM_DIODE2_P
5085 Channel Location
B B
32 KHz Clock DP1/DN1 CPU(OTP) QE12
1
100P_0402_50V8J
C
1
@ CE69
MEC_XTAL1 1 2 MEC_XTAL2 2
+3.3V_ALW_DEG +3VALW_5085 JDEG +3VALW_5085
YE1 DP1a/DN1a DIMM E
B
3
RE76 32.768KHZ_9PF_Q13FC135000040 1 MMST3904-7-F_SOT323-3
1
1
100K_0402_5%
2 1 CE53 REM_DIODE2_N
CE62 X02.18 27P_0402_50V8J DP2/DN2 GVR
RE65
49.9_0402_1% 22P_0402_50V8J Place QE12 close to GVR
2
8
7
6
5
+3VALW_5085 2
10K_8P4R_5%
DP3/DN3 NGFF CE69 should close to QE12 +3VALW_5085
2
RPE7
DP4/DN4 VR
1
1
10K_0402_5%
10K_0402_5%
100K_0402_5%
8.2K_0402_5%
JTAG_RST#
1
2
3
4
1
@ RE75
JDEG
RE72
RE74
RE69
1
1
1
2 JTAG_TDI CLK_PCI_MEC
2 2
1U_0402_6.3V6K
EMI@
3 JTAG_TMS REM_DIODE1_P
1
2
3
1
1
@SHORT PADS~D
JTAG1 @
100_0402_1%
10_0402_5%
4 JTAG_CLK
2
4 4
1
MMST3904-7-F_SOT323-3
@ RE66
100P_0402_50V8J
5 JTAG_TDO QE3
5
1
CE59
100P_0402_50V8J
E
6 MSCLK QE7 C
6 6
1
RE80
@ CE48
@ CE47
B
7 MSDATA 2 2 THERMATRIP2#
2
7 8 HOST_DEBUG_TX B
2
1
8 8 +1.05VS
4.7P_0402_50V8C
EMI@
MMST3904-7-F_SOT323-3
C
9 E
3
9
2
0.1U_0402_25V6
10 MMST3904-7-F_SOT323-3
10 10
1
Pin8 5085_TXD for EC Debug REM_DIODE1_N C
2
1
11 pin9 5048_TXD for SBIOS 1 2 2
G1
1
CE52
QE9
CE61
12 debug RE70 2.2K_0402_5% B
13 G2 Place QE7 close to SODIMM Place QE3 close to CPU E
3
14 G3 CE48 should close to QE7 CE47 should close to QE3
2
G4 EMI depop location
ACES_87153-10411
CONN@ Place close pin A29 REM_DIODE3_P
[11] H_THERMTRIP#
QE10
1
100P_0402_50V8J
C
1
@ CE66
@
2
RE79 CE54 REV B
X02.24
JLPDE +3VALW_5085 +3VALW_5085 E
3
+3VS MMST3904-7-F_SOT323-3
JLPDE 240K 4700p X00 REM_DIODE3_N
1 VSET_5085 THSEL_STRAP 1 2
1 130K 4700p X01
1
2 Place QE10 close to JNGFF1 RE78 1K_0402_5%
2 2
0.1U_0402_25V6
3 LPC_LAD0 RE79 RE81
3 62K 4700p X02
1
4 4
4 LPC_LAD1 62K_0402_5% 10K_0402_5% CE66 should close to QE10
1
5 LPC_LAD2 RE77
5 33K 4700p X03 X02.09
CE55
6 LPC_LAD3 1.96K_0402_1%
2
6 6 7 LPC_LFRAME# REM_DIODE4_P
8.2K 4700p A00 1: Channel 1 will provide Thermistor Readings
2
7 8 PCH_PLTRST#_EC BOARD_ID FWP#
2
8 8
100P_0402_50V8J
9
A 9 10 CLK_PCI_LPDEBUG [9] 4.3K 4700p QE8 0: Channel 1 will provide Diode Readings A
10 10
2
1
@CE51
C
2K 4700p
1
11 CE54 2
12 G1 4700P_0402_25V7K RE82 B
1K 4700p
1
13 G2 10K_0402_5% E
2
3
14 G3 MMST3904-7-F_SOT323-3 Rest=1.96K , Tp=99 degree
1
G4
ACES_87153-10411 REM_DIODE4_N
CONN@
BOARD_ID rise time is measured from 5%~68%. Place QE8 close to VR Choke (MB Top side)
CE51 should close to QE8
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019RU
Date: Monday, April 07, 2014 Sheet 29 of 54
5 4 3 2 1
5 4 3 2 1
+3VALW
KBD Conn.
U2412
4 11 KSO00
24 VCC KSO00 13 KSO01
37 VCC KSO01 12 KSO02 ACES_51510-0304N-P01
VCC KSO02 14 KSO03 30 32
KSO03 16 KSO04 [11] KB_DET# KSI7 29 30 GND 31
KSO04 17 KSO05 KSI6 28 29 GND
1 1 1 KSO05 15 KSO06 KSI4 27 28
D C5256 C5254 C5255 38 KSO06 5 KSO11 KSI2 26 27 D
0.1U_0402_25V6K 0.1U_0402_25V6K 0.1U_0402_25V6K BKLGT_DET 39 GPIO10 KSO11 10 KSO12 KSI5 25 26
2 2 2 BKLT_PWM 40 GPIO11 KSO12 7 KSO13 KSI1 24 25
CAP_LED# 41 GPIO12/PWM1 KSO13 6 KSO14 KSI3 23 24
42 GPIO13/PWM2 KSO14 8 KSO15 KSI0 22 23
43 GPIO14/PWM3 KSO15 9 KSO16 KSO05 21 22
44 GPIO15/PWM4/BC_INT_DN3#/SMB_INT_DN3# KSO16 3 KSO17 KSO04 20 21
GPIO20/PWM7 KSO17 2 KSO18 KSO11 19 20
GPIO01/KSO18 1 KSO19 KSO06 18 19
GPIO00/KSO19 47 KSO20 KSO12 17 18
GPIO23/KSO20/PWM8 46 KSO03 16 17
GPIO22/KSO21/PWM9 45 KSO01 15 16
GPIO21/KSO22 KSO02 14 15
KSO00 13 14
KSO16 12 13
31 KSO20 11 12
30 GPIO04/BC_DAT_DN1/SMB_DAT_DN1/TP_DAT KSO19 10 11
GPIO03/BC_CLK_DN1/SMB_CLK_DN1/TP_CLK KSO17 9 10
36 +3VS +5VS KSO18 8 9
35 GPIO07/BC_DAT_DN2/SMB_DAT_DN2/PS2_DAT +5VS Q330 KSO13 7 8
GPIO06/BC_CLK_DN2/SMB_CLK_DN2/PS2_CLK AO3419L_SOT23-3 KSO15 6 7
5 6
2
R944 KSO14
4 5
D
R990 3 1 1 2 CAPS_LED
34 3 4
[29] BC_DAT_ECE1117 BC_DATA_UP/SMB_DAT_UP 2 3
2
G
33 18 KSI0 100K_0402_5% 240_0402_1%
[29] BC_CLK_ECE1117 BC_CLK_UP/SMB_CLK_UP KSI0
32 20 KSI1 1 2
G
[29] BC_INT#_ECE1117
2
BC_INT_UP#/SMB_INT_UP# KSI1 23 KSI2 CAP_LED# 3 1 1
KSI2 19 KSI3
D
KSI3 JKB
R2484 2 1 10K_0402_1% 28 25 KSI4
48 SMB_ADDR KSI4 22 KSI5 CONN@
29 OCS_TRM KSI5 26 KSI6 Q327
TEST_PIN KSI6 1
27 KSI7 L2N7002WT1G_SC-70-3
KSI7 C1160 @
21 0.1U_0402_10V7K
VR_CAP 2
1 49
GND_PAD
C C5259 C
4.7U_0603_6.3V6K
2 ECE1117-HZH_QFN48_7X7~D
+5VS_KBL
+5VS_KBL 1
JKBBL C5263
1U_0603_10V6K
+5VS 20mil +5VS_KBL 1
BKLGT_DET R2518 1 2 47K_0402_5% 2 1 2
F1 3 2 5
1 2 KB_BL_PWM# 4 3 G1 6
4 G2
2
0.5A_15V_SMD1206P050TF ACES_50524-00401-P01
R2517 20mil
100K_0402_5% CONN@
B B
1
1
1
C5261
1U_0603_10V6K C5262
1
10U_0603_6.3V6M D
2
2 BKLT_PWM 2 QE11
G L2N7002WT1G_SC-70-3
S
3
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019RU
Date: Monday, April 07, 2014 Sheet 30 of 54
5 4 3 2 1
A B C D E
+5VS and +3VS switch
1 1
+5VALW
SHORT DEFAULT +3VS
U2301 PJP511 @
+3VALW 1 14 3VS 2 1
2 VIN1 VOUT1 13 2 1
VIN1 VOUT1
C2324
10U_0603_6.3V6M
C2323
10U_0603_6.3V6M
@ JUMP_43X79
RUN_ON 1 2 470K_0402_5% 3VS_GATE 3 12 C5292 1 2 2200P_0402_25V7K 1 1
[29,36,39] RUN_ON ON1 CT1
R2318
4 11
VBIAS GND @ @
1 2 82K_0402_5% 5VS_GATE 5 10 C5293 1 2 2200P_0402_25V7K 2 2
R2313 ON2 CT2
6 9 5VS
7 VIN2 VOUT2 8
VIN2 VOUT2
15 +5VS
GPAD
1
1
C2322
0.01U_0603_25V7K C2309 TPS22966DPUR_SON14_2X3
0.01U_0603_25V7K
PJP510 @
2 1
2
2 2 1
+3VALW +5VALW
C2307
10U_0805_10V4Z
C2308
10U_0603_6.3V6M
JUMP_43X79
1 1
SHORT DEFAULT @
C2316 2 2
10U_0603_6.3V6M
C2318
10U_0603_6.3V6M
C2306
10U_0603_6.3V6M
C2305
10U_0603_6.3V6M
1 1 1 1
2 2 2 2
2 2
+3VALW_PCH switch
3 3
+3VALW +3VALW_PCH
SHORT DEFAULT
U2304 PJP513 @
1 14 3VALW_PCH 2 1
X02.08 2 VIN1 VOUT1 13 2 1 +5VALW
VIN1 VOUT1
C2310
10U_0805_10V4Z
C2312
10U_0603_6.3V6M
JUMP_43X79
R416 1 @ 2 0_0402_5% +3VALW_PCH_GATE 3 12 1 1
[29] PCH_ALW_ON ON1 CT1 +0.675VS
4 11
VBIAS GND
1
@
1
R2451 1 @ 2 0_0402_5% +3V_DSW_GATE 5 10 C5291 1 2 2200P_0402_25V7K 2 2
[29,34] ALWON ON2 CT2 R2314 R10
6 9 3V_DSW 22_0603_5% 100K_0402_5%
VIN2 VOUT2
1
C2325 C2314 7 8
2
VIN2 VOUT2
0.01U_0603_25V7K
0.01U_0603_25V7K
SUSP#
[21,29] SUSP#
2
15 +3V_DSW
2
GPAD
1
TPS22966DPUR_SON14_2X3 PJP512 @ D D
2 1 Q2307 2 SUSP# RUN_ON 2 Q8
2 1 G G
L2N7002LT1G_SOT23-3 L2N7002LT1G_SOT23-3
C2329
10U_0603_6.3V6M
C2328
10U_0603_6.3V6M
JUMP_43X79 S S
3
1
+3VALW +3VALW
1 1
R16
SHORT DEFAULT @
100K_0402_5% @
2 2
2
C2315
10U_0603_6.3V6M
C2317
10U_0603_6.3V6M
C2311
10U_0603_6.3V6M
C2313
10U_0603_6.3V6M
1 1 1 1
@ @
2 2 2 2 For Intel S3 Power Reduction
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 31 of 54
A B C D E
5 4 3 2 1
D D
Screw Hole
H1 H3 H4 H8 H11 H12 H14
H_2P3 H_2P8 H_2P8 H_2P8 H_2P8 H_2P3N H_6P0
@ @ @ @ @ @ @
1
1
H17 H19
H_2P8 H_2P8 H20 H21
@ @ H_1P1N H_1P1N
@ @
1
1
C C
H5 H2
H_6P6 H_2P8X3P1N
@ @
1
H6 H7 H9 H10
H_3P5 H_3P2X3P5 H_3P2X3P5 H_3P2
@ @ @ @
CPU bracket
1
H24 H15
H_3P3 H_3P2
@ @
eDP Nut NGFF Nut
1
H22 H23
H_3P3 H_3P3
@ @
B B
GPU bracket
1
FD1 FD2 FD3 FD4
@ FIDUCAL @ FIDUCIAL @ FIDUCAL @ FIDUCIAL
1
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/08/01 Deciphered Date 2014/07/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019RU
Date: Monday, April 07, 2014 Sheet 32 of 54
5 4 3 2 1
A B C D
EMI@ PL8
HCB2012KF-121T50_0805
1 2
EMI@ PL1
HCB2012KF-121T50_0805
1 2
EMI@ PL2
HCB2012KF-121T50_0805
+PBATT 1 2 PBATT+_C
1
EMI@ PC3 1000P_0402_50V7K
1 0.01U_0402_25V7K EMI@ PC1 1
1
EMI@ PD1 EMI@ PD2
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
+3VALW
3
GND
Primary Battery Connector
SMART
1
Battery: LLTOP_ALLTOP C144LS-109A9-L 9P BATT P2
01.GND1 1 2
1 PR2
02.GND2 2 3
2200P_0402_50V7K
BAT_ALERT 100K_0402_5%
2
3 4
03.BAT_ALERT GND PRP1
4 5 BATT_PRS 8 1
PBAT_PRES# [29,41]
04.SYS_PRES
5 6
1
EMI@ PC2
DAT_SMB 7 2
6 7 PBAT_SMBDAT [29]
CLK_SMB 6 3
05.BATT_PRS 7 8 5 4
PBAT_SMBCLK [29]
2
8 9
06.DAT_SMB 9 10 100_0804_8P4R_5%
07.CLK_SMB GND 11
GND
08.BATT1+
09.BATT2+
JBATT
CONN@ GND
2 2
+3VALW
@ PR3
2
1 2
0_0402_5%
PR4
2.2K_0402_5%
EMI@ PL3 PR5
1
BLM15AG102SN1D_2P 33_0402_5%
NB_PSID 2 1 1 3 1 2
S
PS_ID [29]
PQ1
2
FDV301N_G_NL_SOT23-3
G
2
1
PR6
100K_0402_1% 1 2
+5VALW
EMI@ PD3 PR7 10K_0402_1%
1
1
C
AZ5125-01H.R7G_SOD523-2 2 PQ2
B MMST3904-7-F_SOT323
3
E 3
2
3
2
PR8
15K_0402_1%
0217 add Erp lot6 circuit
1
EMI@ PL5
HCB2012KF-121T50_0805
1 2 Erp lot6 Circuit
EMI@ PL4 +DC_IN
HCB2012KF-121T50_0805
1 2
+DC_IN
3.3K_1206_5%~D
1
1000P_0402_50V7K
100P_0402_50V8J
1000P_0603_50V7K
1000P_0402_50V7K
PR12
4.7K_0805_5%
+DC_IN
1
1
10U_0805_25V6K
EMI@ PC9
EMI@ PC10
100P_0402_50V8J
@ PR10
1
@ PC18
@ PR16
CONN@ 1M_0402_1%
EMI@ PC5
EMI@ PC17
EMI@ PC16
@
JDCIN
2
3 2
2
1
2
2
1 2 -DCIN_JACK
2
PQ3B
3
2N7002KDWH_SOT363-6
3
1
4 5
4 5 +DCIN_JACK
5 EMI@ PL6 @ PR9
4
6
1
6 HCB2012KF-121T50_0805 200K_0402_1% @
2N7002KDWH_SOT363-6
GND
PQ3A
7 1 2 @ PR11
2
GND
1M_0402_1%
EMI@ PL7 2
ACES_50299-00501-003 HCB2012KF-121T50_0805 @
2
1
0.1U_0402_25V6
1 2
1
PC11
4 @ PR13 4
2
40.2K_0402_1%
0317 add PR13 NC
2
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/04/10 Deciphered Date 2014/05/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 33 of 54
A B C D
A B C D E
1 1
+3VLP
PC109
4.7U_0603_10V6K
1 2
@ PC102 @ PC108
100P_0402_50V8J 100P_0402_50V8J
1 2 1 2
PR109 PR104
130K_0402_1% 150K_0402_1%
1 2 1 2
VFB=2V VFB=2V
PR107 PR106
200K_0402_1% 100K_0402_1%
1 2 1 2
EMI@ PL103
HCB2012KF-121T50_0805
3/5V_B+
1 2
[29] ALW_PWRGD_3V_5V PR105
2 2
EMI@ PL102 22K_0402_1%
+3VALWP
8.66K_0402_1%
HCB2012KF-121T50_0805 1 2
PR108
B+ 0324 PR110 NC
10U_0805_25V6K
FB_3V
FB_5V
1 2 3/5V_B+
CS2
CS1
PC112
2
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0402_25V7K
2
PR115
2
1
1
@ PC113
EMI@ PC114
PC115
@ PR110
MDV1528URH_PDFN33-8-5
MDV1528URH_PDFN33-8-5
5
1
100K_0402_1% PU100
5
5
0_0402_5% 21
CS2
VFB2
VREG3
VFB1
CS1
2
TP
1
3V_EN 6 20 5V_EN
EN2 EN1
PQ101
PQ103
PR114
4 200_0402_5% 4
7 19 1 2
PGOOD VCLK
LX_3V 8 18 LX_5V
1
2
3
3
2
1
PL100 PC104 PR103 SW2 SW1 PR111 PC110 PL101
4.7UH_5.5A_20%_7X7X3_M 0.1U_0402_25V6 2.2_0603_5% TPS51285BRUKR_QFN20_3X3 2.2_0603_5% 0.1U_0402_25V6 2.2UH_7.8A_20%_7X7X3_M
1 2 1 2 1 2 BST_3V 9 17 BST_5V 1 2 1 2 2 1 +5VALWP
+3VALWP VBST2 VBST1
UG_3V 10 16 UG_5V
DRVH2 DRVH1
1
4.7_1206_5%
680P_0603_50V8J 4.7_1206_5%
VREG5
DRVL2
DRVL1
1
@ PR113
@ PR112
VO1
5
5
VIN
FDMC7692S_MLP8-5
FDMC7692S_MLP8-5
ESR=18m ohm
ESR=18m ohm
1 1 1 1
2
11
12
13
14
15
2
PQ102
PQ104
@ PC116 + PC101 + PC107 + + @ PC117
680P_0603_50V8J
150U_D2_6.3VM_R17M 220U_6.3V_M 4 4 220U_6.3V_M 150U_D2_6.3VM_R17M
1
1
2 2 2 2
@ PC103
@ PC111
3 +5VALWP 3
2
1
2
3
3
2
1
2
3/5V_B+
VL
1U_0603_25V6K
Co-Lay
1
1
PC105
0317 add PC116 NC Co-Lay Co-Lay PC106
0317 add PC117 NC Co-Lay
4.7U_0603_10V6K
2
PR100
0_0402_5%
3V_EN 1 2
3VALWP
PR101
TDC 2.76A 0_0402_5%
Peak Current 3.95A 5V_EN 1 2
OCP current 4.6A
TYP MAX 5VALWP
H/S Rds(on): 23.2mohm , 27.8mohm TDC 6.86A
L/S Rds(on):10.8mohm ,13.6mohm Peak Current 9.8A
PR102
2.2K_0402_5% OCP current 11.43A
1 2
3V_EN
[29,31] ALWON TYP MAX
@ PJP100 @ PJP101
4.7U_0603_6.3V6K
5V_EN 1 2 +3VALW 1 2 +5VALW
H/S Rds(on): 23.2mohm , 27.8mohm
+3VALWP +5VALWP
1
PC100
4 L/S Rds(on):10.8mohm , 13.6mohm 4
PAD-OPEN 4x4m PAD-OPEN 4x4m
2
3
@ @ PJP103
EMI@ PD101 1 2
TVNST52302AB0_SOT523-3
PAD-OPEN 4x4m
1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/07/25 Deciphered Date 2014/07/24 Title
Place PD101 close to PU100 SCHEAMTICS,MB AB072
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 34 of 54
A B C D E
A B C D
1 1
2 2
[0823] change DP to VGA solution, delet this design
3 3
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/04/10 Deciphered Date 2014/05/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 35 of 54
A B C D
5 4 3 2 1
Module model information
APL5930_V1.mdd
D D
+3VALW +5VALW
Ultra Low Dropout 0.23V(typical) at 3A Output Current
1
@ PJP400 PC400
1
1U_0402_6.3V6K
JUMP_43X79
2
2
2
PC401 PU400
1
4.7U_0805_6.3V6K APL5930KAI-TRG_SO8
C 6 C
5 VCNTL 3
PJP401
2
PR402 9 VIN VOUT 4 @
100K_0402_5% VIN VOUT
+1.5VSP +1.5VSP 1
1 2
2 +1.5VS
1.54K_0402_1%
1 2 8
[29,31,39] RUN_ON EN
1
7 2 JUMP_43X79
GND
POK FB
PR400
PC403
1
59K_0402_1% 0.01U_0402_25V7K
0.1U_0402_16V7K
Rup
1
PR403
PC402
PC404
2
22U_0805_6.3V6M
2
@
2
1
PR401
1.74K_0402_1%
Rdown
2
Vout=0.8V* (1+Rup/Rdown)
B B
1.5VS
TDC 0.014A
Peak Current 0.2A
OCP current 5.7A
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/04/10 Deciphered Date 2014/05/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019RU
Date: Monday, April 07, 2014 Sheet 36 of 54
5 4 3 2 1
5 4 3 2 1
Module model information
RT8207M_V1.mdd For Single layer
RT8207M_V2.mdd For Dual layer
D D
Pin19 need pull separate from +1.35VP.
If you have +1.35V and +0.675V sequence question, 0.675Volt +/- 5%
EMI@ PL201
HCB2012KF-121T50_0805
you can change from +1.35VP to +1.35V. TDC 0.7A
B+ 1 2 1.35V_B+ PR200 Peak Current 1A
2.2_0603_5%
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
BST_1.35V 1 2 BOOT_1.35V
+1.35VP
1
1
@ PC208
EMI@ PC201
PC206
PC212
DH_1.35V +0.675VSP
2
10U_0805_6.3V6K
10U_0805_6.3V6K
PC200 SW_1.35V
1
0.1U_0603_25V7K
MDV1528URH_PDFN33-8-5
1
PC205
PC211
5
16
17
18
19
20
2
C C
2
LX
BST
VTT
DH
VLDOIN
21
PAD
PQ200
4 DL_1.35V 15 1
DL VTTGND
14 2
PL200 PR205 PGND VTTSNS
1
2
3
1UH_11A_20%_7X7X3_M 14.7K_0402_1%
1 2 1 2 CS_1.35V 13 3
+1.35VP PC204 CS GND
1
1U_0603_10V6K PU200
5
FDMC7692S_MLP8-5
1 2 12 G5616ARZ1U_TQFN20_3X3 4 VTTREF_1.35V
@ PR203 PR206 VPP VTTREF
ESR=9m ohm
330U_2.5V_M
4.7_1206_5% 5.1_0603_5%
330U_D2_2V_Y
1 1
1 2 VDD_1.35V 11 5
1 2
+5VALW VCC VDDQSNS
+1.35VP
1
PQ201
+ +
PC214
PC299
VDDQSET
ESR=15m ohm 4 PC210
1
0.033U_0402_16V7K
PGOOD
@ PC207
2
2 2@ 680P_0402_50V7K PC209
+5VALW
TON
2
1U_0603_10V6K
S5
S3
2
1
2
3
10
6
PR207
EN_0.675VSP
8.06K_0402_1%
Co-Lay
EN_1.35V
PR208 FB_1.35V 1 2 +1.35VP
887K_0402_1%
B 0314 PC214 change from SF000003000 to SF000003100 1.35V_B+ 1 2 TON_1.35V B
1
PR201 PR204
0_0402_5% 10K_0402_1%
MOSFET: 3x3 DFN 1 2
[29] SUS_ON
2
Mode Level +0.675VSP VTTREF_1.35V H/S Rds(on): 23.2mohm(Typ), 27.8mohm(Max)
S5 L off off
1
Idsm: 10.1A@Ta=25C, 5.5A@Ta=70C @ PC202
S3 L off on 0.1U_0402_10V7K
S0 H on on
2
L/S Rds(on): 10.8mohm(Typ), 13.6mohm(Max)
Note: S3 - sleep ; S5 - power off Idsm: 12.5A@Ta=25C, 11A@Ta=70C PR202
0_0402_5%
1 2 @ PJP200
Choke: 7x7x3 [17] 0.675V_DDR_VTT_ON
+1.35VP 1 2 +1.35V
1 2
Rdc=8.3mohm(Typ), 10mohm(Max)
1
JUMP_43X118
@ PC203 @ PJP201
1.35Volt +/- 5% 0.1U_0402_10V7K 1 2
2
1 2
TDC 8.1A JUMP_43X118
Peak Current 8.4A
PJP203@
OCP 13.5A +0.675VSP
1
1 2
2
+0.675VS
JUMP_43X39
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/04/10 Deciphered Date 2014/05/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019RU
Date: Monday, April 07, 2014 Sheet 37 of 54
5 4 3 2 1
5 4 3 2 1
EMI@ PL504
+1.05VS PR500 130_0402_1% HCB2012KF-121T50_0805
1 2 1 2
EMI@ PL501 B+
HCB2012KF-121T50_0805
+VCC_PWR_SRC 1 2
PC548
1U_0402_6.3V6K PR504 54.9_0402_1%
100U_D2_16VM_R50M
100U_D2_16VM_R50M
1 2 1 2
100U_25V_M
100U_25V_M
2200P_0402_25V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V7K
PR505 0_0402_5% 1 1 1 1
1 2
[13] VR_SVID_DAT + + + +
@ PC532
@ PC519
EMI@ PC521
PC516
PC534
PC515
PC533
PR507
1
PC524
PC517
PC518
PR506 0_0402_5% 169K_0402_1%
D
1 2 SDA_CPU 1 2 D
[13] VR_SVID_ALRT# 2@ 2@ 2@ 2@
2
PR508 0_0402_5%
1 2 ALERT#
[13] VR_SVID_CLK
SCLK_CPU
PR511 0_0402_5%
1 2
0311 Change PC515 PC533 from +
[13] VR_ON
PR513 VCC_PWR_SRC to B+
21
20
19
18
17
@ PR519 PU501 0_0603_5%
1.91K_0402_1% 1 2
SCLK
SDA
PAD
ALERT#
PRGM1
1
1 2
+3VS PC500 2 DCR=0.48m-Ohm +/-5%
1 2 VR_ON_1 1 16 LGATE
VR_ON LGATE PL502
1000P_0402_50V7K 7 0.15UH_PCMB104T-R15MS0R485_40A_20%
[13] H_VR_READY 2 15 PHASE 3 6 SW_CPU2 SW_CPU2 1 4
PR521 PGOOD PHASE 5
90.9K_0402_1% 4 2 3
CPU_CORE
+CPU_CORE TDC 10A@15W CPU
1
EMI@ PR534
4.7_1206_5%
1 2 IMON 3 14 UGATE
IMON UGATE
PR510 0_0402_5% ISL95813HRZ-T_QFN20_3X4 Peak Current 32A@15W CPU
1
1 2 VR_HOT#_1 4 13 1 PR538 2 1 2 PQ501
8
[6,29,41] H_PROCHOT# PR525 VR_HOT# BOOT PR536 OCP current 38.4A
2
47P_0402_50V8J
470K_0402_5%_B25/50 4700K 3.83K_0402_1% 2.2_0603_5% PC525 CSD87351Q5D_SON8-7 3.65K_0603_1%
1 2 1 2 NTC 5 12 0.22U_0603_16V7K Choke DCR 1.1m-Ohm(Max)
NTC VCC
1
680P_0603_50V7K
PC510
Load line -2mV/A
ISUMP 2
1
EMI@ PC520
PH500
ISUMN
COMP 6 11
2
COMP PRGM2
ISUMN
ISUMP
2
+5VS
RTN
1
1 2
FB
1
PR528 PR512
124K_0402_1% PC528
C C
10
27.4K_0402_1%
6800P_0402_25V7K 3.16K_0402_1%
0.1U_0603_25V7K
2
1
2
PR539
@ PC531
2
33P_0402_50V8J
2
1
4700P_0402_50V7K
PC526
2
PC523
2
1
200_0402_1%
@
PR535
@ PR533 @ PC522
0217 change for 210 to 200
10_0402_1% 390PF_0402_50V7K Base on BDW PDDG
1 2 1 2
2
1
1.5K_0402_1%
15W 28W
PR545
PR537
1 2
TDC 10A TDC 16A
2
330P_0402_50V7K 2K_0402_1%
1.27K_0402_1% @
1
PR543
Location MAX 32A MAX 40A Note
@ OCP 38.4A OCP 48A
2
4.99M_0402_1%
PC530
0.1U_0402_10V6K
1
PC527
PR558
1 2 Loadline=-2.0mv/A Loadline=-2.0mv/A
2
2
B @ @ PR535 200 Ohm 255 Ohm OCP B
PC529 PR537 1.27kOhm 1.58kOhm Droop
1 2
0.068U_0402_16V7K PC527 @ @ Droop
[13] VCCSENSE
PR543 @ @ Droop
PR549
11K_0402_1%
Check are there a pair 100Ω @ PC541 1 2 PC529 0.068uF 0.068uF RC Match
1 2
at HW side and close to CPU.
0.082U_0402_16V7K
330P_0402_50V7K PR551 PR551 4.42kOhm 4.42kOhm RC Match
1
PC545
4.42K_0402_1%
1 2 1 2
PR539 3.16kOhm 3.16kOhm Comp
2
PC546 @ PH501
1 2 10K_0402_5%_B25/50 4250K
ISUMP PC531 @ @ Comp
0.01U_0402_50V7K
PR507 169kOhm 205kOhm PRGM1
ISUMN
[15] VSSSENSE
PR521 90.9kOhm 100kOhm IMON
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/07/25 Deciphered Date 2014/07/24 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 38 of 54
5 4 3 2 1
5 4 3 2 1
D D
EN pin don't floating
If have pull down resistor at HW side, pls delete PR301
PR300
0_0402_5%
1 2
C RUN_ON [29,31,36] C
1
@ PC300
1M_0402_1%
0.22U_0402_10V6K
2
PR301
2
@ PR302 @ PC301
4.7_1206_5% 680P_0603_50V7K
EMI@ PL302 1 2SNB_1.05V 1 2 +1.05VSP @ PJP300
HCB2012KF-121T50_0805 PU300 1 2 +1.05VS
1 2
B+ 1 2 B+_1.05V 8
IN EN
1 PR303 PC302
10U_0805_25V6K
10U_0805_25V6K
0_0603_5% 0.1U_0603_25V7K JUMP_43X118
2200P_0402_50V7K
6 BST_1.05V 1 2 1 2 PL301
0.1U_0402_25V6
BS
1
1
EMI@ PC303
@ PC304
PC305
PC306
0.68UH_7.9A_20%_5X5X3_M
+1.05V_LDO_3V 9
GND LX
10 LX_1.05V 1 2
+1.05VSP
2
100K_0402_1%
47U_0805_6.3V6M
47U_0805_6.3V6M
22U_0805_6.3VAM
22U_0805_6.3VAM
1
330P_0402_50V7K
1
1
PR305
4
FB
PC307
PC308
PC309
PC310
@ PC311
@ PR304
0_0402_5% ILMT_1.05V 3 7 1 2
Rup
+3VALW
2
ILMT BYP @ PR310
2
2
ILMT_1.05V
+3VS 1 2 +1.05V_PGOOD 2 5+1.05V_LDO_3V 0_0402_5%
4.7U_0603_6.3V6K
PG LDO
1
1
PC313
@ PR308
4.7U_0603_6.3V6K
1
1K_0402_1%
PC312
10K_0402_5% SY8206DQNC_QFN10_3X3
PR309
FB = 0.6V
2
@ PR306
2
0_0402_5%
2
2
1
Pin 7 BYP is for CS. PR307
The current limit is set to 6A, 8A or 12A when this pin 133K_0402_1%
B Common NB can delete +3VALW and PC313 Rdown B
is pull low, floating or pull high
2
VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)
Vout=1.05V
+1.05VSP
TDC 5A
Peak Current 6.6A
OCP current 8A
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/04/10 Deciphered Date 2014/05/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019RU
Date: Monday, April 07, 2014 Sheet 39 of 54
5 4 3 2 1
A
B
C
D
5
5
+CPU_CORE
2 1 2 1 2 1
@
PC917 PC909 PC901
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 1 2 1 2 1
PC918 PC910 PC902
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 1 2 1 2 1
@
PC919 PC911 PC903
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 1 2 1 2 1
4
4
PC920 PC912 PC904
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 1 2 1 2 1
PC921 PC913 PC905
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 1 2 1 2 1
PC922 PC914 PC906
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 1 2 1 2 1
@
@
PC923 PC915 PC907
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 1 2 1
PC916 PC908
22U_0805_6.3V6M 22U_0805_6.3V6M
2 1 2 1
+GPU_CORE
@ PC949 PC932 2 1 2 1
+GPU_CORE
4.7U_0805_6.3V6K 47U_0805_6.3V6M
2 1 2 1 PC926
3
3
PC939
1U_0402_6.3V 4.7U_0603_6.3V6K
@ PC950 PC933 2 1 2 1
4.7U_0805_6.3V6K 22U_0805_6.3V6M
2 1 2 1 PC938
PC931
1U_0402_6.3V 4.7U_0603_6.3V6K
@ PC951 PC934 2 1 2 1
4.7U_0805_6.3V6K 4.7U_0805_6.3V6K
2 1 PC929 PC930
1U_0402_6.3V 4.7U_0603_6.3V6K
PC935 2 1 2 1
4.7U_0805_6.3V6K
2 1 PC927 PC928
1U_0402_6.3V 4.7U_0603_6.3V6K
PC936 2 1
4.7U_0805_6.3V6K
2 1 PC940
Issued Date
4.7U_0603_6.3V6K
PC937 2 1
Security Classification
4.7U_0805_6.3V6K
2 1 PC941
4.7U_0603_6.3V6K
PC942 2 1
4.7U_0805_6.3V6K
PC924
4.7U_0603_6.3V6K
2 1
PC925
4.7U_0603_6.3V6K
2 1
2013/04/10
PC952
4.7U_0603_6.3V6K
2 1
PC953
4.7U_0603_6.3V6K
2
2
Compal Secret Data
Near GPU
Deciphered Date
Under GPU
1uF 0402 * 4
22uF 0805 *1
47uF 0805 *1
4.7uF 0805 *5
4.7uF 0603 * 10
2014/05/01
nVidia GB2B-64 package
nVidia GB2B-64 package
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Title
Date:
Document Number
4019RU
Monday, April 07, 2014
1
1
Sheet
40
SCHEAMTICS,MB AB072
Compal Electronics, Inc.
of
54
Rev
A
A
B
C
D
A B C D
+DC_IN +DC_IN_SS +SDC_IN +PWR_SRC_AC CHAGER_SRC
PQ702 PR702
PQ701 MDS1525URH_SO8 0.01_1206_1% EMI@ PL700
MDU1516URH_POWERDFN56-8-5 1UH_6.6A_20%_5X5X3_M
1 1 8 1 4 1 2
2 2 7
5 3 3 6 2 3
2200P_0402_50V7K
5
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
@ PC702
@ PC734
@ PC703
0.1U_0402_25V6
0.022U_0603_50V7K
0.1U_0402_25V4Z
4
1
PC704
PC705
PC706
PC707
PC708
PC709
PC710
PC711
4.7_0402_1%
1
2
1
PC700
PR737
PC701
@ @
CSSN_1
CSSP_1
1 1
2
2
0217 change PD701(SCS00003800)
to PD702,PD703(SCS0340L010)
1
3
4.02K_0402_1%
@ PQ708B PD702 PR738 PR705
1
DCX124EK-7-F_SC74R-6 SDMK0340L-7-F_SOD323-2
0321 change PR739 0_0402_5% 0_0402_5%
PR731
2 1
+PBATT
2 from 316k to 294k
2
PD703
0311 PQ708A,PQ708B NC SDMK0340L-7-F_SOD323-2 B+
2
1
2 1
+DC_IN PC745 PC746
SIR472DP-T1-GE3_POWERPAK8-5
1
+DC_IN 1U_0603_25V6K 0.1U_0402_25V6
0305 add PC730,PC731,PC732 to de-pop
1
1 2 1 2 1 2
@ PQ708A 5 AC_DIS [29] PR708
DCX124EK-7-F_SC74R-6 PR730 10_1206_5% GNDA_CHG PC747 GNDA_CHG
4.02K_0402_1% 0.1U_0402_25V6
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
294K_0402_1%
2
1
0.1U_0603_25V7K
0.1U_0603_25V7K
0.1U_0603_25V7K
2
5
PR739
PC751
6
1
D
PC716
PC717
EMI@ PC723
EMI@ PC724
EMI@ PC725
PC730
PC731
PC732
PC748 PU700 BQ24777_REGN 1 2
PQ704
2 PQ709 1U_0805_25V6K
ACDRV
ACP
ACN
G DMN65D8LW-7_SOT323-3 1 2 +DCIN 28 1U_0603_10V6K
2
VCC
100K_0402_1%
3 S @ @ @
1
1BQ24777_REGN
PR740 3 24 4
0.047U_0603_25V7K~D
CMSRC REGN
PR741
49.9K_0402_1% PR712
0221 Add PR741 100k ohm 1 2 ACDET 6 2.2_0603_5%
PR719 0_0402_5% ACDET 25CHG_BTS
1 2 CHG_BTS_C
PC750 BTST
CHARGER_SMBCLK 1 2 11
2
3
2
1
SDA
1
BAT_B+
PC712
CHARGER_SMBDAT 1 2 PR721 0_0402_5%
1 2 12 26 CHG_UGATE PR710
pull up 10K in HW side (R827 R828) 0.1U_0402_25V4Z SCL HIDRV PL701 0.01_1206_1%
2
PR713 GNDA_CHG 5 2.2UH_12A_20%_10X10X4_M
100K_0402_1% ACOK 27 CHG_SW 1 2 1 4
[29] CHARGER_SMBDAT PHASE
2 7 2
IADP 2 3
[29] CHARGER_SMBCLK
2
@ PR711
4.7_1206_5%
PR714 0_0402_5% 8 23 CHG_LGATE
10U_0805_25V6K
10U_0805_25V6K
0.1U_0603_25V7K
SIRA06DP-T1-GE_POWERPAKSO-8-5
1 2 IDCHG LODRV
[29] ACAV_IN
2
PQ705
PR716 0_0402_5% 9
PMON
1
1 2 PR717 0_0402_5%
[29] I_ADP
1
CHG_SNUB
@ PC752
PC720
PC721
PR718 0_0402_5% 1 2 10 22
PR715 1 2 /PROCHOT GND 4
2
154K_0402_1% [29] I_BATT PR720 0_0402_5%
1
1 2 PR706 10K_0402_1%
[29] I_SYS 0217 add PR706
1000P_0603_50V7K
13 21 1 2 BQ24777_REGN
100P_0402_50V8J
100P_0402_50V8J
2
CMPIN NC
20K_0402_1%
@ PC722
10Kohm pull high
1
2
3
1
1
GNDA_CHG 14 PC726 PC727 @ PC728
CMPOUT
1
1
PC718
PC719
PR732
20 0.1U_0402_25V6 0.1U_0402_25V6 0.1U_0402_25V6
SRP
1BQ24777_REGN
1 2 1 2 1 2
2
15 19
2
/BATPRES SRN PR704
2
GNDA_CHG 4.02K_0402_1%
16 18 1 2
CELL /BATDRV
[6,29,38] H_PROCHOT#
29 17 1 2 GNDA_CHG GNDA_CHG
PWPD BAT
PR725
0217 change PC753(100P) to PR732 (20K) PR723
1K_0402_1% BQ24777RUYR_WQFN28_4x4 10_0603_1%
0317 change PR725
1
PR728 0_0402_5% PC729
from100K to 1K [29,33] PBAT_PRES#
1 2 GNDA_CHG 1U_0603_25V6K
2
2
PJP701 +PBATT
1 2 BATDRV#
GNDA_CHG
1
@ PR729 PAD-OPEN1x1m
121K_0402_1% GNDA_CHG
0217 PR729 NC
2
GNDA_CHG
3 3
PQ703
AO4407AL_SO8
BAT_B+ 1
2
8
7 +PBATT
3 6
5
4
BATDRV#
4 4
DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/04/10 Deciphered Date 2014/05/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 41 of 54
A B C D
5 4 3 2 1
Power block D
B+
Input +3VALWP: TDC:2.76A
DC IN Switch Page 41 ALWON
+5VALWP: TDC:6.86A
TPS51285BRUKR Page 34
C C
+3VALW +1.5VSP: TDC:3A RUN_ON
CHARGER APL5930KAI
BQ24777(NVDC) Page 36
Page 41
+1.35VP/+0.675VSP: TDC:8.4A/0.7A SUS_ON
G5616ARZ1U
Page 37
0.675V_DDR_VTT_ON
Battery
CC:2A(3cell) or 3.9A(4cell)
CV:13.2V(3cell) / 8.7V(4cell) +VCCIO: TDC:5A RUN_ON
SY8206DQNC
Page 39
B B
CPU_CORE: TDC 10A@15W CPU VR_ON
ISL95813HRZ-T
Page 38
VGA_COREP: TDC 26A 3V3_MAIN_EN
RT8813AGQW
Page 44
+1.35VGPU_DDR: TDC 2.24A FBVDD_EN
TPS51212DSCR
A Page 45 A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/04/10 Deciphered Date 2014/05/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 42 of 54
5 4 3 2 1
A B C D
Vboot=Vvref*Rref2/(Rref1+Rref2+Rboot) Different VGA Chip (different EDP-Peak Current) need select different solution
Rt=Rrefadj // (Rboot+Rref2)
Vmin= Vvref*[Rref2/(Rref2+Rboot)]*[Rt/(Rref1+Rt)] VGA Chip N15S-GM
Vmax=Vvref*Rref2/[(Rref1//Rrefadj)+Rboot+Rref2]
OpenVReg Configurations Config B
Vout=Vmin+N*Vstep
Vstep=(Vmax-Vmin)/Nmax Rated TDP Power at Tj=102C 18W
PWM-VID Spec and component Values Boosted GPU Total at Tj=102C 20W
PWM-VID Spec Config A Config B Config C EDP-Continuous at Tj=102C 22A
1 1
Vmin 0.6V 0.6V 0.65V
EDP-Peak at Tj=102C 48.11 A
Vmax 1.2V 1.2V 1.15V
Vboot 0.875V 0.9V 0.9V Istep max (Evaluation) 29.22 A
Voltage step 6.25mV 6.25mV 25mV
OCP Setting Current 66A
N of Voltage level 96 96 20 H-side MOS:MDU1516URH L-side MOS:MDU1511RH
Rrefadj PR604 39K 20K 39K Rds(on): Rds(on): Rocset 13K
11.7mohm@Vgs=4.5V 2.7mohm@Vgs=4.5V
Rref1 PR602 39K 20K 30K Id :18.6A@Ta=25 degC Id :36.1A@Ta=25 degC Recommendation 2phase 1H1L
Rboot PR603 1.5K 2K 3K
PR607 30K 18K 24K
Rref2=PR607+PR610 Polymer Cap (330uF) 9mohm * 3
PR610 1.5K 0 3K
C PC607 1.5nf 2.7nf 1.8nf
@ PR600
Or OSCON (390uF) NULL
1K_0402_5%
1 2 +3.3V_RUN_GFX
PWM VID and Output voltage control
1.Boot mode PR601 0_0402_5%
0217 PC604 change from pop to de-pop
2.Standby mode (don't support) 1 2 PC627 change from de-pop to pop
GPU_PWM_VID [45] GPU_B+
3.Normal mode EMI@ PL603
Operation phase Number PSI Voltage setting HCB2012KF-121T50_0805
1 2
1 phase with DEM 0V to 0.8V
1
1 EMI@ PL600
B+
PC600 Rref1 1 phase with CCM 1.2V to 1.8V HCB2012KF-121T50_0805
1U_0402_6.3V6K PR602 1 2
2
2 20K_0402_1% Active phase with CCM 2.4V to 5.5V 2
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
Rboot Rrefadj
2
PSI Pull high on HW side PR606
PR603 PR604 PR605 0_0402_5% 2.2_0603_5%
1
PC627
@ PC601
EMI@ PC602
PC603
PC604
2K_0402_5% 20K_0402_1% 1 2 1
U2_BOOT1 2
NVVDD_PSI [45]
1 2 1 2
MDU1516URH_POWERDFN56-8-5
1 +VGA_CORE
2
5
18K_0402_1%
PR608 Pull high on HW side PQ600 @
1
EDP-Continuous 22A
2700P_0402_50V7K
1K_0402_5% PC605
0.01U_0402_16V7K
PR607
1 2 0.22U_0603_25V7K
3V3_MAIN_EN [45,49] 2 EDP-Peak 48.11A
@ PC606
GPU_VID
1
1
PR609 0_0603_5% OCP min 66A
PC607
Rref2 U2_UGATE1 1 2 4
0.1U_0402_25V6
2
@ PC608
C
2
1
2
GPU_REFADJ
U2_BOOT1
U2_UGATE1
1
0_0402_5%
Reserve Location
GPU_PSI
PR610
GPU_EN
3
2
1
PL601 +GPU_CORE
0.22UH_PCME064T-R22MS0R985_28A_20%
2
GPU_FBRTN U2_PHASE1 1 2
PQ601
6
5
PU600
330U_D2_2.5VY_R9M
330U_D2_2.5VY_R9M
1 1
MDU1511RH_POWERDFN56-8-5
1
PR611
REFADJ
PSI
VID
EN
UGATE1
BOOT1
+ +
PC613
PC610
Rton 499K_0402_1% EMI@ PR613
GPU_B+ 1 2 4.7_1206_5%
1 GPU_REFIN 7 24 U2_PHASE1
REFIN PHASE1 U2_LGATE1 4 2 2
2
PR612 0_0402_5% @PC612
@PC612 GPU_VREF 8 23 U2_LGATE1
1 2 0.01UF_0402_25V7K VREF LGATE1
[46] GPU_VSS_SENSE
1
2 GPU_TON 9 22 EMI@ PC614
TON GND/PWM3
13K_0402_1%
680P_0603_50V7K
3
2
1
PR615
1 2 GPU_FBRTN 10 21
2
RGND PVCC
Rocset
1
11 20 U2_LGATE2
TALERT/ISEN2
PR614
100_0402_1% @ PC615 VSNS LAGTE2
TSNS/ISEN3
2
VCC/ISNE1
3 47P_0402_50V8J GPU_COMP 12 19 U2_PHASE2 3
2
SS PHASE2
UGATE2
PGOOD
PR616 0_0402_5%
BOOT2
1 2 GPU_FB
GND
[46] GPU_VDD_SENSE
@ PC616 RT8813AGQW_WQFN24_4X4
25
13
14
15
16
17
18
+GPU_CORE 1 2 Css 0.01U_0402_16V7K
1 2
PR617 GPU_B+
GPU_DSBL/ISEN1
GPU_TSNS/ISEN3
100_0402_1%
GFX_CORE_PG
U2_UGATE2
PR618
U2_BOOT2
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
2.2_0603_5%
MDU1516URH_POWERDFN56-8-5
0.1U_0402_25V6
U2_BOOT2 1 2
@ PC618
1 PQ602
1
EMI@ PC619
PC620
PC621
PC617
0.22U_0603_25V7K
2
GPU_VREF 2 PR619 0_0603_5%
1. VSNS Soft-Start time (Internal) is 0.7ms (PC616 un-pop) U2_UGATE2 1 2 4
Tss=(Css*Vrefin)/Iss+2.3ms
18.7K_0402_1%
=0.01U*0.9V/5uA+2.3ms=4.1ms (PC616 pop)
1
+3.3V_RUN_GFX
PR620
3
2
1
2. Switching frequency setting: PL602 +GPU_CORE
10K_0402_1%
0.22UH_PCME064T-R22MS0R985_28A_20%
470K_0402_5%_TSM0B474J4702RE
Fsw=(Vin-0.5)/(2*Vin*Rton*3.2p)=304.89Khz
1
U2_PHASE2 1 2
2
PR621
330U_D2_2.5VY_R9M
PQ603 1
1
5
1
1U_0402_6.3V6K
MDU1511RH_POWERDFN56-8-5
2
1
+5VS +
PC623
@ PR624 EMI@ PR622
1
PC622
10K_0402_1% 4.7_1206_5%
PH600
GFX_CORE_PG [44] 2
2
2
2
@ @ U2_LGATE2 4
1 2
PR623
4
2.2_0603_5% EMI@ PC625 4
1 2 680P_0603_50V7K
3
2
1
2
+3VS
1
PC626
1U_0402_6.3V6K
2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/07/25 Deciphered Date 2014/07/24 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 43 of 54
A B C D
5 4 3 2 1
D D
EMI@ PL1000
HCB2012KF-121T50_0805
+1.35DGPU_B+ 1 2
B+
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
@ PC1000
1
EMI@ PC1001
PC1002
PC1003
+3VS
2
@
5
1
PQ1000
@ PR1000 MDV1528URH-1N-PDFN33-8
100K_0402_5%
4
2
[10,28,45] DGPU_PWROK PR1001 PC1004
TDC=2.5A
PR1002 1
PU1000
10 1
BST_+1.35DGPU
2.2_0603_5%
2
0.1U_0603_25V7K
1 2
Peak Current=3.5A
3
2
1
PGOOD VBST
45.3K_0402_1% OCP=4.55A
PR1003 1 2TRIP_+1.35DGPU 2 9 UG_+1.35DGPU PL1001
0_0402_5% TRIP DRVH 2.2UH_7.8A_20%_7X7X3_M
1 2 EN_+1.35DGPU 3 8 SW_+1.35DGPU 1 2
[43] GFX_CORE_PG EN SW
+1.35VGPUP
FB_+1.35DGPU 4 7
MDV1526URH_PDFN33-8-5
VFB V5IN
+5VALW
1
0.1U_0402_16V7K
C RF_+1.35DGPU 5 6 LG_+1.35DGPU C
0304 net name change TST DRVL
1
@ PC1005
@ PR1004 1
PQ1001
from FBVDD_EN to GFX_CORE_PG TP
11 4.7_1206_5%
1
+ PC1008
2
2
PR1005 TPS51212DSCR_SON10_3X3 PC1006 4 220U_D2_2VY_R17M
470K_0402_1% 1U_0603_6.3V6M
1
@ PC1009 2
2
680P_0402_50V7K
3
2
1
2
PR1006
9.31K_0402_1%
MOSFET: 3x3 DFN 1 2
H/S Rds(on): 23.2mohm(Typ), 27.8mohm(Max)
Id: 10.1A@Ta=25C, 7A@Ta=70C
1
PR1007
L/S Rds(on): 13.5mohm(Typ), 16.5mohm(Max) 10K_0402_1%
2
Idsm: 13.2A@Ta=25C, 9.5A@Ta=70C
B Choke: 7x7x3 B
Rdc=15.5mohm +/-15% @ PJP1000
+1.35VGPUP 1 2 +1.35VS_VGA
1 2
JUMP_43X118
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/07/25 Deciphered Date 2014/07/24 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019RU
Date: Monday, April 07, 2014 Sheet 44 of 54
5 4 3 2 1
5 4 3 2 1
UV1A
X02.11 Part 1 of 6
PEG_CTX_GRX_P0 AG6 C6
PEG_CTX_GRX_N0 AG7 PEX_RX0 GPIO0 B2
PEG_CTX_GRX_P[0..3] PEG_CTX_GRX_P1 AF7 PEX_RX0_N GPIO1 D6 X02.11
[12] PEG_CTX_GRX_P[0..3] PEX_RX1 GPIO2
PEG_CTX_GRX_N1 AE7 C7
PEG_CTX_GRX_N[0..3] PEG_CTX_GRX_P2 AE9 PEX_RX1_N GPIO3 F9
[12] PEG_CTX_GRX_N[0..3] PEX_RX2 GPIO4
PEG_CTX_GRX_N2 AF9 A3 3V3_MAIN_EN [43,49]
PEG_CRX_GTX_P[0..3] PEG_CTX_GRX_P3 AG9 PEX_RX2_N GPIO5 A4 GC6_EVENT#_D
[12] PEG_CRX_GTX_P[0..3] PEX_RX3 GPIO6
PEG_CTX_GRX_N3 AG10 B6
PEG_CRX_GTX_N[0..3] AF10 PEX_RX3_N GPIO7 A6 THERMATRIP_GPU#
[12] PEG_CRX_GTX_N[0..3] NC OVERT
AE10 F8
AE12 NC GPIO9 C5 FBVREF_ALTV
AF12 NC GPIO10 E7 GPU_PWM_VID
NC GPIO11 GPU_PWM_VID [43]
D AG12 D7 GPU_HOT# D
AG13 NC GPIO12 B4 NVVDD_PSI [43]
GPIO
AF13 NC GPIO13 B3
PEG_CRX_GTX_P0 CV188 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P0 AE13 NC GPIO14 C3
PEG_CRX_GTX_N0 CV189 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N0 AE15 NC GPIO15 D5 1 2
AF15 NC GPIO16 D4 @ RV140 0_0402_5%
PEG_CRX_GTX_P1 CV190 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P1 AG15 NC GPIO17 C2
PEG_CRX_GTX_N1 CV191 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N1 AG16 NC GPIO18 F7
NC GPIO19
D
AF16 E6 THERMATRIP_GPU# 3 1
NC GPIO20 THERMATRIP3# [29]
PEG_CRX_GTX_P2 CV192 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P2 AE16 C4 GPU_PEX_RST_HOLD#
PEG_CRX_GTX_N2 CV193 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N2 AE18 NC GPIO21 QV78
AF18 NC AB6 L2N7002WT1G_SC-70-3
G
1 2
PEG_CRX_GTX_P3 CV194 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P3 AG18 NC PEX_WAKE_NC
PEG_CRX_GTX_N3 CV195 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N3 AG19 NC
AF19 NC DV10
AE19 NC
NC RB751V-40_SOD323-2
AE21 AG3
+3.3V_RUN_GFX AF21 NC NC AF4 +3.3V_RUN_GFX
For fix power on glitch issue
2
AG21 NC NC AF3
AG22 NC NC DGPU_PEX_RST#
NC
10K_0402_5%
[10,28,44] DGPU_PWROK PEG_CRX_GTX_C_P0 AC9 AE3 GPU_SMBCLK_R 1 2
PEX_TX0 NC
DACs
1
RV195
PEG_CRX_GTX_C_N0 AB9 AE4 RV191 1.8K_0402_5%
PEG_CRX_GTX_C_P1 AB10 PEX_TX0_N NC GPU_SMBDAT_R 1 2
PEG_CRX_GTX_C_N1 AC10 PEX_TX1 RV192 1.8K_0402_5%
PEX_TX1_N
PCI EXPRESS
PEG_CRX_GTX_C_P2 AD11 NVVDD_PSI 1 2
PEX_TX2
2
QV88 PEG_CRX_GTX_C_N2 AC11 W5 RV125 10K_0402_5%
G
PEG_CRX_GTX_C_P3 AC12 PEX_TX2_N NC AE2 GPU_HOT# 1 2
1 3 GFXCLK_REQ_Q# PEG_CRX_GTX_C_N3 AB12 PEX_TX3 TSEN_VREF AF2 RV104 100K_0402_5%
[9] GFXCLK_REQ# PEX_TX3_N NC
AB13 THERMATRIP_GPU# 2 1
D
AC13 NC RV103 10K_0402_5%
C L2N7002WT1G_SC-70-3 AD14 NC 3V3_MAIN_EN 2 1 C
2 1 AC14 NC RV188 10K_0402_5%
0_0402_5% RV196 @ AC15 NC GPU_PEX_RST_HOLD# 2 1
AB15 NC RV189 10K_0402_5%
AB16 NC B7 1 2 GC6_EVENT#_D 2 1
+3.3V_RUN_GFX AC16 NC I2CA_SCL A7 RV510 1 2 1.8K_0402_5% RV190 10K_0402_5%
AD17 NC I2CA_SDA RV511 1.8K_0402_5%
AC17 NC C9 1 2
NC I2CB_SCL
0.1U_0402_10V7K
1 AC18 C8 RV512 1 2 1.8K_0402_5%
NC I2CB_SDA
I2C
CV129
AB18 RV513 1.8K_0402_5% FBVREF_ALTV 1 2
AB19 NC A9 1 2 RV92 100K_0402_5%
AC19 NC I2CC_SCL B9 RV514 1 2 1.8K_0402_5%
2 @ AD20 NC I2CC_SDA RV515 1.8K_0402_5%
AC20 NC D9 GPU_SMBCLK_R
NC I2CS_SCL Place close to ball
AC21 D8 GPU_SMBDAT_R
NC I2CS_SDA
5
AB21
AD23 NC LV10
VCC
1 AE23 NC 2 1
[11] DGPU_HOLD_RST# IN1 NC +1.05V_PEX_VDD
0.1U_0402_10V7K
22U_0603_6.3V6M
4SYS_PEX_RST_MON#_R 1 2 SYS_PEX_RST_MON# [46] AF24 BLM18PG300SN1D_2P
2 OUT @ RV520 AE24 NC L6 +CORE_PLLVDD 1 1
GND
[10] PLTRST_GPU# IN2 NC PLLVDD
1
CV134
0_0402_5% AG24 M6
NC SP_PLLVDD
CV46
UV14 RV187 AG25
NC
10K_0402_5%
MC74VHC1G08DFT2G_SC70-5 10K_0402_5% N6
3
NC
2
2 2
1
0_0402_5%
RV45
2
RV208
AE8
[9] CLK_PCIE_GFX PEX_REFCLK LV8
AD8
[9] CLK_PCIE_GFX# GFXCLK_REQ_Q# AC6 PEX_REFCLK_N +PLLVDD 2 1 +1.05V_PEX_VDD
1
PEX_CLKREQ_N
0.1U_0402_10V7K
4.7U_0603_6.3V6K
22U_0603_6.3V6M
HCB1608KF-181T20_0603
2
1 2 PEX_TSTCLK_OUT AF22
CLK
PEX_TSTCLK_OUT 1 1 1
@ RV24 200_0402_1% PEX_TSTCLK_OUT# AE22 C11 GPU_CLK_27M_IN
PEX_TSTCLK_OUT_N XTAL_IN
CV49
CV112
CV33
B10 GPU_CLK_27M_OUT
B XTAL_OUT B
DGPU_PEX_RST# 1 2 DGPU_PEX_RST_R# AC7 A10 XTALSSIN 1 2 2 2 2
RV40 2 1 0_0402_5% AF25 PEX_RST_N XTAL_SSIN C10 XTALOUTBUFF RV23 1 2 10K_0402_5%
RV25 2.49K_0402_1% PEX_TERMP XTAL_OUTBUFF RV39 10K_0402_5%
GM108-ES-S-A1_FCBGA595
YV1
27MHZ_12PF_X1E000021042600
GPU_CLK_27M_IN 1 3 GPU_CLK_27M_OUT_R 1 2 GPU_CLK_27M_OUT
IN OUT RV519 430_0402_1%
2 4
GND GND X02.19
SP_PLLVDD and VID_PLLVDD Power
1
1
PLLVDD Filtering
CV34
18P_0402_50V8J
CV35
18P_0402_50V8J
rail Filtering Combined
2
Capacitor Type Population Capacitor Type Population
0.1uF 0402 1 per ball 0.1uF 0402 1
1 2 4.7uF 0603 1 22uF 0805 1
@ RV30 0_0402_5%
QV14B 22uF 0805 1 Bead 30 ohm
GPU_SMBCLK_R 4 3 GPU_SMBCLK
GPU_SMBCLK [29] Bead 180 ohm (ESR=0.05 ohm) 1
DMN66D0LDW-7_SOT363-6
1
[28] GPU_PWR_LEVEL 1 2 GPU_HOT# 1 2 DGPU_PEX_RST# (ESR=0.2 ohm) 0402
5
DV3 RB751V-40_SOD323-2 RV252
1
0_0402_5%
2 +3.3V_RUN_GFX
0603
@ RV253 0_0402_5%
2
A A
DMN66D0LDW-7_SOT363-6
GPU_SMBDAT_R 1 6 GPU_SMBDAT
GPU_SMBDAT [29]
QV14A
1
@ RV26
2
0_0402_5%
DELL CONFIDENTIAL/PROPRIETARY
GPU_PWR_LEVEL Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/07/25 Deciphered Date 2014/07/24 Title
LOW Low Performace
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
HIGH High Performace AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019RU
Date: Monday, April 07, 2014 Sheet 45 of 54
5 4 3 2 1
5 4 3 2 1
X02.11 UV1C UV1E
Part 3 of 6 F11 A2 Part 5 of 6 K11
AC3 NC AD10 A26 GND_001 GND_057 K13
AC4 NC NC AD7 AB11 GND_002 GND_058 K15
Y4 NC NC B19 AB14 GND_003 GND_059 K17
Y3 NC FBA_CMD32 V5 AB17 GND_004 GND_060 L10
AA3 NC NC V6 AB20 GND_005 GND_061 L12
AA2 NC NC G1 AB24 GND_006 GND_062 L14
AB1 NC NC G2 AC2 GND_007 GND_063 L16
NC NC GND_008 GND_064
NC
AA1 G3 AC22 L18
AA4 NC NC G4 AC26 GND_009 GND_065 L2
AA5 NC NC G5 AC5 GND_010 GND_066 L23
D NC NC G6 AC8 GND_011 GND_067 L25 D
NC G7 AD12 GND_012 GND_068 L5
AB5 NC V1 AD13 GND_013 GND_069 M11
AB4 NC NC V2 AD15 GND_014 GND_070 M13
AB3 NC NC W1 AD16 GND_015 GND_071 M15
AB2 NC NC W2 AD18 GND_016 GND_072 M17
AD3 NC NC W3 +3.3V_RUN_GFX AD19 GND_017 GND_073 N10
AD2 NC NC W4 AD21 GND_018 GND_074 N12
NC NC GND_019 GND_075
I2CS Slave Address AE1
NC
AD22
GND_020 GND_076
N14
1
AD1 AE11 N16
AD4 NC RV51 AE14 GND_021 GND_077 N18
NC GND_022 GND_078
SMBUS_ALT_ADDR Description AD5
NC BUFRST_N
D11 10K_0402_5% AE17
AE20 GND_023 GND_079
P11
P13
D10 1 2 AF1 GND_024 GND_080 P15
2
NC GND_025 GND_081
0 0x9E(Default) T2 AF11 P17
GND
@ RV31 10K_0402_5%
T3 NC E9 SYS_PEX_RST_MON# AF14 GND_026 GND_082 P2
NC GPIO8 SYS_PEX_RST_MON# [45] GND_027 GND_083
T1 AF17 P23
NC GND_028 GND_084
1 0x9C(Multi-GPU usage) R1
R2 NC NC
E10 AF20
AF23 GND_029 GND_085
P26
P5
GENERAL
NC GND_030 GND_086
LVDS/TMDS
R3 F10 AF5 R10
N2 NC NC AF8 GND_031 GND_087 R12
NC GND_032 GND_088
VGA_DEVICE Setting N3
NC D1 STRAP0
AG2
AG26 GND_033 GND_089
R14
R16
STRAP0 D2 STRAP1 B1 GND_034 GND_090 R18
STRAP1 GND_035 GND_091
VGA_DEVICE Description V3
V4 NC STRAP2
E4
E3
STRAP2
STRAP3
B11
B14 GND_036 GND_092
T11
T13
U3 NC STRAP3 D3 STRAP4 B17 GND_037 GND_093 T15
NC STRAP4 GND_038 GND_094
0 Non-Primary 3D Acceleration Device(Class Code 302h) U4
T4 NC NC
C1 B20
B23 GND_039 GND_095
T17
U10
T5 NC B27 GND_040 GND_096 U12
NC GND_041 GND_097
1 Primary Display or VGA Device(Class Code 300h) R4
R5 NC MULTI_STRAP_REF0_GND
F6
F4
MULTI_STRAP_REF0_GND
MULTI_STRAP_REF1_GND
1
RV93 1
2
2 40.2K_0402_1%
B5
B8 GND_042 GND_098
U14
U16
C NC NC F5 MULTI_STRAP_REF2_GND @ RV95 1
@RV95 2 40.2K_0402_1% E11 GND_043 GND_099 U18 C
NC @RV96
@ RV96 40.2K_0402_1% E14 GND_044 GND_100 U2
GND_045 GND_101
Resistance Mapping to Hex Values N1
M1 NC
E17
E2 GND_046 GND_102
U23
U26
M2 NC F12 E20 GND_047 GND_103 U5
NC THERMDP GND_048 GND_104
Resistor Value Pull-up to VDD33 Pull-down to GND M3
K2 NC E12
E22
E25 GND_049 GND_105
V11
V13
K3 NC THERMDN E5 GND_050 GND_106 V15
NC GND_051 GND_107
4.99K 1000 0000 K1
J1 NC
E8
H2 GND_052 GND_108
V17
Y2
NC H23 GND_053 GND_109 Y23
GND_054 GND_110
10K 1001 0001 M4 F2
H25
H5 GND_055 GND_111
Y26
Y5
M5 NC VDD_SENSE GPU_VDD_SENSE [43] GND_056 GND_112
NC
15K 1010 0010 L3
L4 NC
K4 NC
NC Use 16mils trace for sense pin
20K 1011 0011 K5 GND
AA7
AB7
J4 NC F1 GND
NC GND_SENSE GPU_VSS_SENSE [43]
24.9K 1100 0100
GM108-ES-S-A1_FCBGA595
30.1K 1101 0101 J5
N4 NC
N5 NC
NC
TEST
34.8K 1110 0110 P3 AD9 GPU_TESTMODE RV107 1 2 10K_0402_5%
P4 NC TESTMODE AE5 GPU_JTAG_TCK
NC JTAG_TCK
45.3K 1111 0111 JTAG_TDI
AE6
AF6
GPU_JTAG_TDI
GPU_JTAG_TDO +3.3V_RUN_GFX
J2 JTAG_TDO AD6 GPU_JTAG_TMS
B J3 NC JTAG_TMS AG4 GPU_JTAG_TRST# RV108 1 2 10K_0402_5% B
NC JTAG_TRST_N @ RPV3
GPU_JTAG_TDO 5 4
H3 GPU_JTAG_TDI 6 3
H4 NC GPU_JTAG_TCK 7 2
NC SERIAL GPU_JTAG_TMS 8 1
D12
ROM_CS_N B12 ROM_SI_GPU 10K_8P4R_5%
ROM_SI A12 ROM_SO_GPU
ROM_SO C12 ROM_SCLK_GPU
Decive ID change to 0x1056 ROM_SCLK
GM108-ES-S-A1_FCBGA595
+3.3V_RUN_GFX +3.3V_RUN_GFX
49.9K_0402_1%
8.45K_0402_1%
8.45K_0402_1%
8.45K_0402_1%
8.45K_0402_1%
8.45K_0402_1%
8.45K_0402_1%
Strap Pin Name Logical Strapping Bit 3 Logical Strapping Bit 2 Logical Strapping Bit 1 Logical Strapping Bit 0 Note VENDER STRAP Part Number Note(ROM_SI)
2
2
8.45K_0402_1%
2
@ RV124
RV49
@ RV47
RV94
RV97
@ RV122
RV123
RV98
ROM_SCLK SOR3_EXPOSED->0 SOR2_EXPOSED->0 SOR1_EXPOSED->0 SOR0_EXPOSED->0 ROM_SCLK pull-down 4.99k to GND Hynix 0x3 H5TC4G63AFR-11C 20k PD
@ @ @
1
@ ROM_SI RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0] ROM_SI pull-down 20k to GND Micron 0x4 MT41J256M16HA-093G:E 24.9k PD
1
STRAP0
STRAP1 ROM_SO DEVID_SEL->0(default) PCIE_CFG->0(defual) SMB_ALT_ADDR->0(default) VGA_DEVICE->0 ROM_SO pull-down 4.99k to GND Samsung 0x5 K4W4G1646D-BC1A 30.1k PD
STRAP2
STRAP3 Base on RVL RVL-06891-001_v03_secured.pdf
STRAP4 STRAP0 Keep pull up to 3V3_AON and pull-down to GND footprint and stuff 50k ohm pull up STRAP0 pull up 50k to +3.3V_GFX_AON
ROM_SCLK_GPU
A ROM_SI_GPU A
2K_0402_1%
ROM_SO_GPU STRAP1
2
20K_0402_1%
2K_0402_1%
2K_0402_1%
2K_0402_1%
2K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
STRAP2
2
2
RV99
STRAP3 Reserve
RV157
RV129
RV41
RV59
RV126
RV127
RV128
STRAP4
@ @ DEVID_SEL/PCIE_CFG defaul set 0, need refer Platform Update Notification for the latest configuration
DELL CONFIDENTIAL/PROPRIETARY
1
@ @ @ @
Security Classification Compal Secret Data Compal Electronics, Inc.
1
Issued Date 2013/07/25 Deciphered Date 2014/07/24 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019RU
Date: Monday, April 07, 2014 Sheet 46 of 54
5 4 3 2 1
5 4 3 2 1
UV1D PLACE BETWEEN GPU
X02.11 +1.05V_PEX_VDD
Part 4 of 6 PLACE NEAR BALLS PLACE NEAR GPU AND POWER SUPPLY
+1.35VS_VGA I=2000mA B26 AA10
FBVDDQ_01 PEX_IOVDDQ_1
1U_0402_6.3V6K
4.7U_0603_6.3V6K
10U_0603_6.3V6M
22U_0603_6.3V6M
C25 AA12
E23 FBVDDQ_02 PEX_IOVDDQ_2 AA13
PLACE NEAR GPU PLACE UNDER GPU E26 FBVDDQ_03 PEX_IOVDDQ_3 AA16
1 1 1 1
FBVDDQ_04 PEX_IOVDDQ_4
CV211
CV65
CV16
CV36
F14 AA18
FBVDDQ_05 PEX_IOVDDQ_5
PEX_IOVDD/Q Power Rail Combined
22U_0603_6.3V6M
10U_0603_6.3V6M
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
F21 AA19
G13 FBVDDQ_06 PEX_IOVDDQ_6 AA20 2 2 2 2
1 1 1 1 1 1 1 1 FBVDDQ_07 PEX_IOVDDQ_7
G14 AA21
FBVDDQ_08 PEX_IOVDDQ_8
Capacitor Type Population
CV43
CV39
CV47
CV24
CV165
CV168
CV163
CV161
G15 AB22
G16 FBVDDQ_09 PEX_IOVDDQ_9 AC23
2 2 2 2 2 2 2 2 FBVDDQ_10 PEX_IOVDDQ_10
D
G18
G19 FBVDDQ_11 PEX_IOVDDQ_11
AD24
AE25 1uF 0402 1 D
FBVDDQ_12 PEX_IOVDDQ_12
G20
G21 FBVDDQ_13 PEX_IOVDDQ_13
AF26
AF27 4.7uF 0603 1
FBVDDQ_14 PEX_IOVDDQ_14
H24
H26 FBVDDQ_AON 10uF 0805 1
FBVDDQ_AON
22uF 0805 1
J21 AA22
K21 FBVDDQ_AON PEX_IOVDD_1 AB23
L22 FBVDDQ_AON PEX_IOVDD_2 AC24
L24 FBVDDQ_19 PEX_IOVDD_3 AD25
POWER
L26 FBVDDQ_20 PEX_IOVDD_4 AE26
M21 FBVDDQ_21 PEX_IOVDD_5 AE27
N21 FBVDDQ_22 PEX_IOVDD_6
R21 FBVDDQ_23
T21 FBVDDQ_24 +3.3V_RUN_GFX
V21 FBVDDQ_25
W21 FBVDDQ_26 PLACE UNDER GPU PLACE NEAR GPU
G
63
C
2
0_
.
G
1
0
/
G
1
2
p
i
n
c
o
n
n
e
c
t
t
o
FBVDDQ_27 G10
3V3_AON G12
+
.
3
V
G
F
X
_
A
O
N
3V3_AON
DDR3 CPU side FBVDD/FBVDDQ
0.1U_0402_10V7K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
G8
VDD33_3 G9
VDD33_4 1 1 1
Combined Decoupling
CV40
CV199
CV164
Capacitor Type Population
V7
W7 NC 2 2 2
NC
0.1uF 0402 2 AA6
W6 NC D22 1 2 +1.35VS_VGA
NC FB_CAL_PD_VDDQ
1.0uF 0603 2 Y6
NC
RV42 40.2_0402_1% +3.3V_RUN_GFX
4.7uF 0603 2 FB_CAL_PU_GND
C24 1
RV44
2
42.2_0402_1%
10uF 0805 1
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
M7 B25 1 2 1 1 1 1
NC FB_CAL_TERM_GND
22uF 0805 1
C N7 RV43 51.1_0402_1% C
NC
CV68
CV30
CV198
CV130
T6
P6 NC
NC 2 2 2 2
PLACE NEAR BGA
T7 +3.3V_RUN_GFX
R7 IFPD_PLLVDD_2
U6 NC
IFPD_RSET
0.1U_0402_10V7K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
R6 AA8
NC PEX_PLL_HVDD_1
Power Supply Rail N15S-GM N15S-GT PEX_PLL_HVDD_2
AA9 1 1 1
CV64
CV160
CV159
AB8
PEX_SVDD_3V3
2 2 2
(V) (A) (A) J7
K7 NC
NC
GPU_Core - 26 31 K6
H6 NC PEX_PLLVDD_1
AA14
AA15
J6 NC PEX_PLLVDD_2
NC
GPU_FBIO 1.5/1.35 TBD TBD
PLACE UNDER GPU PLACE NEAR GPU
PEX_IOVDD/Q 1.05 0.765 0.765 +1.05V_PEX_VDD
0.1U_0402_10V7K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
GM108-ES-S-A1_FCBGA595 1 1 1
PEX_PLLVDD 1.05 0.130 0.130
CV63
CV205
CV135
2 2 2
FBA_PLL_AVDD 1.05 0.062 0.062
FBA_DLL_AVDD 1.05 0.032 0.032
B B
PLL_VDD 1.05 0.058 0.058
SP_PLLVDD 1.05 0.030 0.030
1.05V Total 1.05 1.060 1.060
VDD33+3V3AON 3.3 0.036 0.036
PEX_PLLVDD Decoupling PEX_SVDD/PEX_PLL_HVDD Decoupling 3V3_MAIN Decoupling
PEX_SVDD_3V3 3.3 0.167 0.167
Capacitor Type Population Capacitor Type Population Capacitor Type Population
0.1uF 0402 1 0.1uF 0402 1 0.1uF 0402 2
PEX_PLL_HVDD 3.3 0.022 0.022 1uF 0603 1 4.7uF 0603 2 1uF 0603 1
3.3V Total 3.3 0.225 0.025
4.7uF 0805 1 4.7uF 0603 1
3V3_AON Decoupling
Capacitor Type Population
0.1uF 0402 1
1uF 0603 1
A A
4.7uF 0603 1
DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/07/25 Deciphered Date 2014/07/24 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019RU
Date: Monday, April 07, 2014 Sheet 47 of 54
5 4 3 2 1
5 4 3 2 1
X02.11
Caps on Power Side
1UX4 4.7UX10 under GPU
4.7UX5 22UX1 47UX2 330UX2 near GPU
D D
UV1F
+GPU_CORE
Part 6 of 6 +GPU_CORE
K10 V18
K12 VDD_001 VDD_041 V16
K14 VDD_002 VDD_040 V14
K16 VDD_003 VDD_039 V12
K18 VDD_004 VDD_038 V10
L11 VDD_005 VDD_037 U17
VDD_006 VDD_036
POWER
L13 U15
L15 VDD_007 VDD_035 U13
L17 VDD_008 VDD_034 U11
M10 VDD_009 VDD_033 T18
M12 VDD_010 VDD_032 T16
M14 VDD_011 VDD_031 T14
M16 VDD_012 VDD_030 T12
M18 VDD_013 VDD_029 T10
N11 VDD_014 VDD_028 R17
N13 VDD_015 VDD_027 R15
N15 VDD_016 VDD_026 R13
N17 VDD_017 VDD_025 R11
P10 VDD_018 VDD_024 P18
P12 VDD_019 VDD_023 P16
VDD_020 VDD_022 P14
VDD_021
C C
GM108-ES-S-A1_FCBGA595
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/07/25 Deciphered Date 2014/07/24 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019RU
Date: Monday, April 07, 2014 Sheet 48 of 54
5 4 3 2 1
5 4 3 2 1
GDDR3L CMD Mapping Table FBA_D[0..63]
FBA_D[0..63] [50,51] FBA_ODT_L
FBA_CMD2 RV132 1 2
UV1B FBA_ODT_H 10K_0402_5%
FBA_RN[0..7] FBA_CMD18 RV117 1 2
FBA_RN[0..7] [50,51]
DATA Bits[31..0] DATA Bits[63..32] FBA_CKE_L 10K_0402_5%
FBA_CMD3 RV118 1 2
CMD0 CS0# Part 2 of 6 FBA_DQM[0..7] FBA_CKE_H 10K_0402_5%
FBA_DQM[0..7] [50,51]
CMD1 FBA_CMD19 RV119 1 2
CMD2 ODT FBA_D0 E18 C27 FBA_RST 10K_0402_5%
FBA_D00 FBA_CMD0 FBA_CMD0 [50] FBA_WP[0..7]
CMD3 CKE FBA_D1 F18 C26 FBA_CMD1 FBA_CMD5 RV114 1 2
FBA_D01 FBA_CMD1 T110 PAD~D@ FBA_WP[0..7] [50,51]
CMD4 A14 A14 FBA_D2 E16 E24 FBA_CMD2 10K_0402_5%
FBA_D02 FBA_CMD2 FBA_CMD2 [50]
CMD5 RST RST FBA_D3 F17 F24 FBA_CMD3
FBA_D03 FBA_CMD3 FBA_CMD3 [50]
CMD6 A9 A9 FBA_D4 D20 D27
FBA_D04 FBA_CMD4 FBA_CMD4 [50,51]
CMD7 A7 A7 FBA_D5 D21 D26 FBA_CMD5
D FBA_D05 FBA_CMD5 FBA_CMD5 [50,51] D
CMD8 A2 A2 FBA_D6 F20 F25
FBA_D06 FBA_CMD6 FBA_CMD6 [50,51]
CMD9 A0 A0 FBA_D7 E21 F26
FBA_D07 FBA_CMD7 FBA_CMD7 [50,51]
CMD10 A4 A4 FBA_D8 E15 F23
FBA_D08 FBA_CMD8 FBA_CMD8 [50,51]
CMD11 A1 A1 FBA_D9 D15 G22
FBA_D09 FBA_CMD9 FBA_CMD9 [50,51]
CMD12 BA0 BA0 FBA_D10 F15 G23
FBA_D10 FBA_CMD10 FBA_CMD10 [50,51]
CMD13 WE# WE# FBA_D11 F13 G24
FBA_D11 FBA_CMD11 FBA_CMD11 [50,51]
CMD14 A15 A15 FBA_D12 C13 F27
FBA_D12 FBA_CMD12 FBA_CMD12 [50,51]
CMD15 CAS# CAS# FBA_D13 B13 G25
FBA_D13 FBA_CMD13 FBA_CMD13 [50,51]
CMD16 CS0# FBA_D14 E13 G27
FBA_D14 FBA_CMD14 FBA_CMD14 [50,51]
CMD17 FBA_D15 D13 G26
FBA_D15 FBA_CMD15 FBA_CMD15 [50,51]
CMD18 ODT FBA_D16 B15 M24
FBA_D16 FBA_CMD16 FBA_CMD16 [51]
CMD19 CKE FBA_D17 C16 M23 FBA_CMD17
FBA_D18 A13 FBA_D17 FBA_CMD17 K24 FBA_CMD18 T183 PAD~D@
CMD20 A13 A13 FBA_D18 FBA_CMD18 FBA_CMD18 [51]
CMD21 A8 A8 FBA_D19 A15 K23 FBA_CMD19
FBA_D19 FBA_CMD19 FBA_CMD19 [51]
CMD22 A6 A6 FBA_D20 B18 M27
FBA_D20 FBA_CMD20 FBA_CMD20 [50,51]
CMD23 A11 A11 FBA_D21 A18 M26
FBA_D21 FBA_CMD21 FBA_CMD21 [50,51]
CMD24 A5 A5 FBA_D22 A19 M25
FBA_D22 FBA_CMD22 FBA_CMD22 [50,51]
CMD25 A3 A3 FBA_D23 C19 K26
FBA_D23 FBA_CMD23 FBA_CMD23 [50,51]
CMD26 BA2 BA2 FBA_D24 B24 K22
FBA_D24 FBA_CMD24 FBA_CMD24 [50,51]
CMD27 BA1 BA1 FBA_D25 C23 J23
FBA_D25 FBA_CMD25 FBA_CMD25 [50,51]
CMD28 A12 A12 FBA_D26 A25 J25
FBA_D26 FBA_CMD26 FBA_CMD26 [50,51]
CMD29 A10 A10 FBA_D27 A24 J24
FBA_D27 FBA_CMD27 FBA_CMD27 [50,51]
CMD30 RAS# RAS# FBA_D28 A21 K27
FBA_D28 FBA_CMD28 FBA_CMD28 [50,51]
CMD31 FBA_D29 B21 K25
FBA_D29 FBA_CMD29 FBA_CMD29 [50,51]
FBA_D30 C20 J27
FBA_D30 FBA_CMD30 FBA_CMD30 [50,51]
FBA_D31 C21 J26 FBA_CMD31
FBA_D32 R22 FBA_D31 FBA_CMD31 T184 PAD~D@
FBA_D33 R24 FBA_D32 D19 FBA_DQM0
INTERFACE A
FBA_D34 T22 FBA_D33 FBA_DQM0 D14 FBA_DQM1
X02.11 FBA_D35 R23 FBA_D34 FBA_DQM1 C17 FBA_DQM2
FBA_D36 N25 FBA_D35 FBA_DQM2 C22 FBA_DQM3
FBA_D37 N26 FBA_D36 FBA_DQM3 P24 FBA_DQM4
MEMORY
C FBA_D38 N23 FBA_D37 FBA_DQM4 W24 FBA_DQM5 C
FBA_D39 N24 FBA_D38 FBA_DQM5 AA25 FBA_DQM6
FBA_D40 V23 FBA_D39 FBA_DQM6 U25 FBA_DQM7 +1.05V_PEX_VDD
FBA_D41 V22 FBA_D40 FBA_DQM7
FBA_D42 T23 FBA_D41 F19 FBA_RN0
FBA_D42 FBA_DQS_RN0
1
FBA_D43 U22 C14 FBA_RN1
FBA_D44 Y24 FBA_D43 FBA_DQS_RN1 A16 FBA_RN2 PJP31
FBA_D45 AA24 FBA_D44 FBA_DQS_RN2 A22 FBA_RN3 +1.05VS
FBA_D45 FBA_DQS_RN3 PAD-OPEN1x1m
FBA_D46 Y22 P25 FBA_RN4 @
FBA_D47 AA23 FBA_D46 FBA_DQS_RN4 W22 FBA_RN5 UV15
FBA_D48 AD27 FBA_D47 FBA_DQS_RN5 AB27 FBA_RN6 1 14 +1.05V_PEX_VDD_UV15 1 2
2
FBA_D49 AB25 FBA_D48 FBA_DQS_RN6 T27 FBA_RN7 2 VIN1 VOUT1 13 CV139 0.1U_0402_10V7K
+1.05V_PEX_VDD FBA_D50 AD26 FBA_D49 FBA_DQS_RN7 VIN1 VOUT1 @
FBA_D51 AC25 FBA_D50 E19 FBA_WP0 1 2 3V3_MAIN_EN_R 3 12 1 2
LV26 PLACE UNDER GPU FBA_D52 AA27 FBA_D51 FBA_DQS_WP0 C15 FBA_WP1
[43,45] 3V3_MAIN_EN
RV185 0_0402_5% ON1 CT1 CV140 1000P_0402_50V7K
1 2 +FB_PLLAVDD FBA_D53 AA26 FBA_D52 FBA_DQS_WP1 B16 FBA_WP2 4 11
FBA_D53 FBA_DQS_WP2 +5VALW VBIAS GND
0.1U_0402_10V7K
0.1U_0402_10V7K
BLM18PG300SN1D_2P FBA_D54 W26 B22 FBA_WP3 @
FBA_D54 FBA_DQS_WP3
22U_0603_6.3V6M
1 1 FBA_D55 Y25 R25 FBA_WP4 1 2 5 10 1 2
FBA_D55 FBA_DQS_WP4 [10] DGPU_PWR_EN ON2 CT2
@
1 FBA_D56 R26 W23 FBA_WP5 RV193 0_0402_5% CV141 470P_0402_50V7K
FBA_D56 FBA_DQS_WP5
CV32
CV133
CV45
FBA_D57 T25 AB26 FBA_WP6 6 9 @ PJP30
FBA_D58 N27 FBA_D57 FBA_DQS_WP6 T26 FBA_WP7 7 VIN2 VOUT2 8 +3.3V_RUN_GFX_UV15 1 2
2 2 FBA_D58 FBA_DQS_WP7 VIN2 VOUT2 +3.3V_RUN_GFX
FBA_D59 R27
2 FBA_D60 V26 FBA_D59 15
FBA_D61 V27 FBA_D60 GPAD PAD-OPEN1x1m
FBA_D61 +3VALW
0.1U_0402_10V7K
FBA_D62 W27 TPS22966DPUR_SON14_2X3
FBA_D62
2
FBA_D63 W25
FBA_D63
0.1U_0402_10V7K
CV142
D24
FBA_CLK0 CLKA0 [50]
F16 D25
PLACE CLOSE to GPU 1 CLKA0# [50]
1
P22 FB_PLLAVDD_1 FBA_CLK0_N
FB_PLLAVDD_2
CV48
N22
FBA_CLK1 CLKA1 [51]
D23 M22
2 @T96 PAD~D FB_VREF_PROBE FBA_CLK1_N CLKA1# [51]
B D18 B
I=35mA FBA_WCK01
H22 C18
FB_DLLAVDD FBA_WCK01_N D17
2 1 FB_CLAMP_GPU F3 FBA_WCK23 D16
RV48 10K_0402_5% FB_CLAMP FBA_WCK23_N T24
FBA_WCK45 U24
2 1 F22 FBA_WCK45_N V24
+1.35VS_VGA FBA_CMD34 FBA_WCK67
@ RV46 2 1 60.4_0402_1% J22 V25
@ RV130 60.4_0402_1% FBA_CMD35 FBA_WCK67_N
FBx_PLL_AVDD and FB_DLL_AVDD GM108-ES-S-A1_FCBGA595
Combined
Capacitor Type Population
0.1uF 0402 2
22uF 0805 1
Bead 30 ohm
1
(ESR=0.01 ohm)
0603
A A
DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/07/25 Deciphered Date 2014/07/24 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019RU
Date: Monday, April 07, 2014 Sheet 49 of 54
5 4 3 2 1
5 4 3 2 1
Memory Partition A - Upper 16 bits 256x16 DDR3L
FBA_D[0..31]
FBA_D[0..31] [49]
FBA_WP[0..3]
FBA_WP[0..3] [49]
FBA_DQM[0..3]
FBA_DQM[0..3] [49]
FBA_RN[0..3]
FBA_RN[0..3] [49]
D D
X02.11
DATA Bits[31..0]
UV17 CMD0 CS0# UV18
CMD1
+FBA_VREF_CA0 +FBA_VREF_CA0 M8 E3 FBA_D11 CMD2 ODT +FBA_VREF_CA0 M8 E3 FBA_D1
+FBA_VREF_DQ0 H1 VREFCA DQL0 F7 FBA_D13 +FBA_VREF_DQ0 H1 VREFCA DQL0 F7 FBA_D4
+FBA_VREF_DQ0 VREFDQ DQL1 CMD3 CKE VREFDQ DQL1
F2 FBA_D10 CMD4 A14 F2 FBA_D3
FBA_CMD9 N3 DQL2 F8 FBA_D15 FBA_CMD9 N3 DQL2 F8 FBA_D6
[49,51] FBA_CMD9 A0 DQL3 CMD5 RST A0 DQL3
FBA_CMD11 P7 H3 FBA_D9 CMD6 A9 FBA_CMD11 P7 H3 FBA_D0
[49,51] FBA_CMD11 FBA_CMD8 P3 A1 DQL4 H8 FBA_D14 FBA_CMD8 P3 A1 DQL4 H8 FBA_D7
[49,51] FBA_CMD8 A2 DQL5 CMD7 A7 A2 DQL5
FBA_CMD25 N2 G2 FBA_D8 CMD8 A2 FBA_CMD25 N2 G2 FBA_D2
[49,51] FBA_CMD25 FBA_CMD10 P8 A3 DQL6 H7 FBA_D12 FBA_CMD10 P8 A3 DQL6 H7 FBA_D5
CMD9 A0
ADDRESS
ADDRESS
[49,51] FBA_CMD10 FBA_CMD24 P2 A4 DQL7 FBA_CMD24 P2 A4 DQL7
DATA
DATA
[49,51] FBA_CMD24 A5 CMD10 A4 A5
FBA_CMD22 R8 CMD11 A1 FBA_CMD22 R8
[49,51] FBA_CMD22 FBA_CMD7 R2 A6 D7 FBA_D17 FBA_CMD7 R2 A6 D7 FBA_D25
[49,51] FBA_CMD7 A7 DQU0 CMD12 BA0 A7 DQU0
FBA_CMD21 T8 C3 FBA_D21 CMD13 WE# FBA_CMD21 T8 C3 FBA_D29
[49,51] FBA_CMD21 FBA_CMD6 R3 A8 DQU1 C8 FBA_D18 FBA_CMD6 R3 A8 DQU1 C8 FBA_D26
[49,51] FBA_CMD6 A9 DQU2 CMD14 A15 A9 DQU2
FBA_CMD29 L7 C2 FBA_D20 CMD15 CAS# FBA_CMD29 L7 C2 FBA_D28
[49,51] FBA_CMD29 FBA_CMD23 R7 A10/AP DQU3 A7 FBA_D19 FBA_CMD23 R7 A10/AP DQU3 A7 FBA_D27
[49,51] FBA_CMD23 A11 DQU4 CMD16 A11 DQU4
FBA_CMD28 N7 A2 FBA_D22 CMD17 FBA_CMD28 N7 A2 FBA_D30
[49,51] FBA_CMD28 FBA_CMD20 T3 A12/BC DQU5 B8 FBA_D16 FBA_CMD20 T3 A12/BC DQU5 B8 FBA_D24
[49,51] FBA_CMD20 A13 DQU6 CMD18 A13 DQU6
FBA_CMD4 T7 A3 FBA_D23 CMD19 FBA_CMD4 T7 A3 FBA_D31
[49,51] FBA_CMD4 FBA_CMD14 M7 A14 DQU7 FBA_CMD14 M7 A14 DQU7
[49,51] FBA_CMD14 NC CMD20 A13 NC
CMD21 A8
C CMD22 A6 C
FBA_CMD12 M2 B2 CMD23 A11 FBA_CMD12 M2 B2
[49,51] FBA_CMD12 FBA_CMD27 N8 BA0 VDD D9 FBA_CMD27 N8 BA0 VDD D9
[49,51] FBA_CMD27 BA1 VDD CMD24 A5 BA1 VDD
FBA_CMD26 M3 G7 CMD25 A3 FBA_CMD26 M3 G7
[49,51] FBA_CMD26 BA2 VDD K2 BA2 VDD K2
VDD CMD26 BA2 VDD
K8 CMD27 BA1 K8
VDD N1 VDD N1
VDD CMD28 A12 VDD
CLKA0 J7 N9 CMD29 A10 CLKA0 J7 N9
[49] CLKA0 CLKA0# K7 CK VDD R1 CLKA0# K7 CK VDD R1
[49] CLKA0# CK VDD CMD30 RAS# CK VDD
FBA_CMD3 K9 R9 CMD31 FBA_CMD3 K9 R9
POWER
POWER
RV145 [49] FBA_CMD3 CKE VDD CKE VDD
1 2 +1.35VS_VGA +1.35VS_VGA
162_0402_1% FBA_CMD2 K1 A1 FBA_CMD2 K1 A1
[49] FBA_CMD2 FBA_CMD0 L2 ODT VDDQ A8 FBA_CMD0 L2 ODT VDDQ A8
[49] FBA_CMD0 CS VDDQ CS VDDQ
80.6_0402_1%
80.6_0402_1%
@ @ FBA_CMD30 J3 C1 FBA_CMD30 J3 C1
[49,51] FBA_CMD30 RAS VDDQ RAS VDDQ
1
FBA_CMD15 K3 C9 FBA_CMD15 K3 C9
[49,51] FBA_CMD15 CAS VDDQ CAS VDDQ
RV146
RV147
FBA_CMD13 L3 D2 FBA_CMD13 L3 D2
[49,51] FBA_CMD13 WE VDDQ WE VDDQ
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
E9 E9
VDDQ VDDQ
@ CV42
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
F1 1 1 1 1 1 1 1 F1
VDDQ VDDQ
Control & DQM
Control & DQM
CV143
CV151
CV178
CV183
CV184
@ CV136
FBA_WP1 F3 H2 FBA_WP0 F3 H2 1 1 1 1 1 1 1
2
DQSL VDDQ DQSL VDDQ
CV131
CV174
CV172
CV179
CV186
CV187
FBA_WP2 C7 H9 FBA_WP3 C7 H9
DQSU VDDQ DQSU VDDQ
CV132
CLKA0_C
2 2 2 2 2 2 2
2 2 2 2 2 2 2
0.01U_0402_25V7K
@ FBA_DQM1 E7 A9 FBA_DQM0 E7 A9
FBA_DQM2 D3 DML VSS B3 FBA_DQM3 D3 DML VSS B3
1 DMU VSS DMU VSS
CV335
E1 E1
VSS G8 VSS G8
FBA_RN1 G3 VSS J2 FBA_RN0 G3 VSS J2
2 FBA_RN2 B7 DQSL VSS J8 PLACE UNDER DRAM FBA_RN3 B7 DQSL VSS J8
DQSU VSS M1 PLACE CLOSE DRAM DQSU VSS M1 PLACE UNDER DRAM
VSS M9 VSS M9
VSS P1 VSS P1
FBA_CMD5 T2 VSS P9 FBA_CMD5 T2 VSS P9
[49,51] FBA_CMD5 RESET VSS T1 RESET VSS T1
FBA_ZQ0 L8 VSS T9 FBA_ZQ1 L8 VSS T9 PLACE CLOSE DRAM
ZQ VSS ZQ VSS
GND
GND
243_0402_1%
243_0402_1%
1
1
B
J1 B1 J1 B1 B
NC VSSQ NC VSSQ
RV148
RV152
L1 B9 L1 B9
J9 NC VSSQ D1 J9 NC VSSQ D1
L9 NC VSSQ D8 L9 NC VSSQ D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
2
2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
H5TC4G63AFR-11C_FBGA96 H5TC4G63AFR-11C_FBGA96
@ @
SA00006E800 Link done
SA00006E800 Link done
DDR3 per Memory FBVDD/Q Decoupling
FBVDD/Q Combined
Capacitor Type Population
0.1uF 0402 2
+1.35VS_VGA +1.35VS_VGA 1.0uF 0603 4
10uF 0805 0
1.33K_0402_1%
1.33K_0402_1%
1
1
RV139
RV144
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT A
2
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
+FBA_VREF_CA0 +FBA_VREF_DQ0 NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1.33K_0402_1%
0.01U_0402_25V7K
1.33K_0402_1%
0.01U_0402_25V7K
1
1 1
RV110
CV326
RV112
CV334
DELL CONFIDENTIAL/PROPRIETARY
2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
2
Issued Date 2013/07/25 Deciphered Date 2014/07/24 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 50 of 54
5 4 3 2 1
5 4 3 2 1
Memory Partition A - Lower 16 bits 256x16 DDR3L
FBA_D[32..63]
FBA_D[32..63] [49]
FBA_WP[4..7]
FBA_WP[4..7] [49]
FBA_DQM[4..7]
FBA_DQM[4..7] [49]
FBA_RN[4..7]
FBA_RN[4..7] [49]
D D
X02.11
UV19 DATA Bits[63..32] UV20
+FBA_VREF_CA1 M8 E3 FBA_D52 CMD0 +FBA_VREF_CA1 M8 E3 FBA_D35
+FBA_VREF_DQ1 H1 VREFCA DQL0 F7 FBA_D49 +FBA_VREF_DQ1 H1 VREFCA DQL0 F7 FBA_D37
VREFDQ DQL1 CMD1 VREFDQ DQL1
F2 FBA_D53 CMD2 F2 FBA_D34
FBA_CMD9 N3 DQL2 F8 FBA_D50 FBA_CMD9 N3 DQL2 F8 FBA_D39
[49,50] FBA_CMD9 A0 DQL3 CMD3 A0 DQL3
FBA_CMD11 P7 H3 FBA_D54 CMD4 A14 FBA_CMD11 P7 H3 FBA_D33
[49,50] FBA_CMD11 FBA_CMD8 P3 A1 DQL4 H8 FBA_D48 FBA_CMD8 P3 A1 DQL4 H8 FBA_D38
[49,50] FBA_CMD8 A2 DQL5 CMD5 RST A2 DQL5
FBA_CMD25 N2 G2 FBA_D55 CMD6 A9 FBA_CMD25 N2 G2 FBA_D32
[49,50] FBA_CMD25 FBA_CMD10 P8 A3 DQL6 H7 FBA_D51 FBA_CMD10 P8 A3 DQL6 H7 FBA_D36
CMD7 A7
ADDRESS
ADDRESS
[49,50] FBA_CMD10 FBA_CMD24 P2 A4 DQL7 FBA_CMD24 P2 A4 DQL7
DATA
DATA
[49,50] FBA_CMD24 A5 CMD8 A2 A5
FBA_CMD22 R8 CMD9 A0 FBA_CMD22 R8
[49,50] FBA_CMD22 FBA_CMD7 R2 A6 D7 FBA_D44 FBA_CMD7 R2 A6 D7 FBA_D56
[49,50] FBA_CMD7 A7 DQU0 CMD10 A4 A7 DQU0
FBA_CMD21 T8 C3 FBA_D40 CMD11 A1 FBA_CMD21 T8 C3 FBA_D60
[49,50] FBA_CMD21 FBA_CMD6 R3 A8 DQU1 C8 FBA_D46 FBA_CMD6 R3 A8 DQU1 C8 FBA_D58
[49,50] FBA_CMD6 A9 DQU2 CMD12 BA0 A9 DQU2
FBA_CMD29 L7 C2 FBA_D41 CMD13 WE# FBA_CMD29 L7 C2 FBA_D61
[49,50] FBA_CMD29 FBA_CMD23 R7 A10/AP DQU3 A7 FBA_D45 FBA_CMD23 R7 A10/AP DQU3 A7 FBA_D57
[49,50] FBA_CMD23 A11 DQU4 CMD14 A15 A11 DQU4
FBA_CMD28 N7 A2 FBA_D43 CMD15 CAS# FBA_CMD28 N7 A2 FBA_D63
[49,50] FBA_CMD28 FBA_CMD20 T3 A12/BC DQU5 B8 FBA_D47 FBA_CMD20 T3 A12/BC DQU5 B8 FBA_D59
[49,50] FBA_CMD20 A13 DQU6 CMD16 CS0# A13 DQU6
FBA_CMD4 T7 A3 FBA_D42 CMD17 FBA_CMD4 T7 A3 FBA_D62
[49,50] FBA_CMD4 FBA_CMD14 M7 A14 DQU7 FBA_CMD14 M7 A14 DQU7
[49,50] FBA_CMD14 NC CMD18 ODT NC
CMD19 CKE
C CMD20 A13 C
FBA_CMD12 M2 B2 CMD21 A8 FBA_CMD12 M2 B2
[49,50] FBA_CMD12 FBA_CMD27 N8 BA0 VDD D9 FBA_CMD27 N8 BA0 VDD D9
[49,50] FBA_CMD27 BA1 VDD CMD22 A6 BA1 VDD
FBA_CMD26 M3 G7 CMD23 A11 FBA_CMD26 M3 G7
[49,50] FBA_CMD26 BA2 VDD K2 BA2 VDD K2
VDD CMD24 A5 VDD
K8 CMD25 A3 K8
VDD N1 VDD N1
VDD CMD26 BA2 VDD
CLKA1 J7 N9 CMD27 BA1 CLKA1 J7 N9
[49] CLKA1 CLKA1# K7 CK VDD R1 CLKA1# K7 CK VDD R1
[49] CLKA1# CK VDD CMD28 A12 CK VDD
FBA_CMD19 K9 R9 CMD29 A10 FBA_CMD19 K9 R9
POWER
POWER
RV151 [49] FBA_CMD19 CKE VDD CKE VDD
CMD30 RAS#
1 2 CMD31 +1.35VS_VGA
162_0402_1% FBA_CMD18 K1 A1 +1.35VS_VGA FBA_CMD18 K1 A1
[49] FBA_CMD18 FBA_CMD16 L2 ODT VDDQ A8 FBA_CMD16 L2 ODT VDDQ A8
[49] FBA_CMD16 CS VDDQ CS VDDQ
80.6_0402_1%
80.6_0402_1%
@ @ FBA_CMD30 J3 C1 FBA_CMD30 J3 C1
[49,50] FBA_CMD30 RAS VDDQ RAS VDDQ
1
FBA_CMD15 K3 C9 FBA_CMD15 K3 C9
[49,50] FBA_CMD15 CAS VDDQ CAS VDDQ
RV153
RV154
FBA_CMD13 L3 D2 FBA_CMD13 L3 D2
[49,50] FBA_CMD13 WE VDDQ E9 WE VDDQ E9
VDDQ 0.1U_0402_10V6K VDDQ
0.1U_0402_10V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
F1 F1
VDDQ VDDQ
Control & DQM
Control & DQM
@ CV15
@ CV158
FBA_WP6 F3 H2 1 1 1 1 1 1 1 FBA_WP4 F3 H2 1 1 1 1 1 1 1
2
DQSL VDDQ DQSL VDDQ
CV180
CV181
CV208
CV210
CV196
CV203
CV204
CV209
CV197
CV215
FBA_WP5 C7 H9 FBA_WP7 C7 H9
DQSU VDDQ DQSU VDDQ
CV170
CV173
CLKA1_C
2 2 2 2 2 2 2 2 2 2 2 2 2 2
0.01U_0402_25V7K
@ FBA_DQM6 E7 A9 FBA_DQM4 E7 A9
FBA_DQM5 D3 DML VSS B3 FBA_DQM7 D3 DML VSS B3
1 DMU VSS DMU VSS
CV218
E1 E1
VSS G8 VSS G8
FBA_RN6 G3 VSS J2 FBA_RN4 G3 VSS J2
2 FBA_RN5 B7 DQSL VSS J8 FBA_RN7 B7 DQSL VSS J8
DQSU VSS M1 PLACE UNDER DRAM DQSU VSS M1 PLACE UNDER DRAM
VSS M9 VSS M9
VSS P1 PLACE CLOSE DRAM VSS P1
FBA_CMD5 T2 VSS P9 FBA_CMD5 T2 VSS P9
[49,50] FBA_CMD5 RESET VSS T1 RESET VSS T1 PLACE CLOSE DRAM
FBA_ZQ2 L8 VSS T9 FBA_ZQ3 L8 VSS T9
ZQ VSS ZQ VSS
GND
GND
243_0402_1%
243_0402_1%
1
1
B
J1 B1 J1 B1 B
NC VSSQ NC VSSQ
RV155
RV156
L1 B9 L1 B9
J9 NC VSSQ D1 J9 NC VSSQ D1
L9 NC VSSQ D8 L9 NC VSSQ D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
2
2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
H5TC4G63AFR-11C_FBGA96 H5TC4G63AFR-11C_FBGA96
@ @
SA00006E800 Link done
SA00006E800 Link done
20130606
+1.35VS_VGA +1.35VS_VGA
reduce 1 ???
1.33K_0402_1%
1.33K_0402_1%
1
1
RV149
RV150
2
PROPRIETARY NOTE:
+FBA_VREF_CA1 +FBA_VREF_DQ1
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
1.33K_0402_1%
0.01U_0402_25V7K
1.33K_0402_1%
0.01U_0402_25V7K
A A
1
1 1 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
RV142
CV216
RV143
CV217
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2 2
2
DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/07/25 Deciphered Date 2014/07/24 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 51 of 54
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List ) Page 1
Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
1 31 KB control 2013/10/21 EE Change Fuse package for sales suggestion Change F1 From SP040003E00 to SP040003A00 X01
2 23 Audio Codec ALC3234 2013/10/21 EE fix POP noise issue Add RA1129 from 100K to UA1 pin 27, and NC RC366 X01
D JCRT1 --> JCRT, JAPS1 --> JAPS, JDEG1 --> JDEG, JLPDE1 --> JLPDE, JKB1 --> JKB, JNGFF1 --> JNGFF D
3 ALL ALL 2013/10/21 EE Re-name part of connector JXDP1 --> JXDP, JRTC1 --> JRTC, PJPDC1 --> JDCIN, PBATT1 --> JBATT X01
PJ200 --> PJP200, PJ201 --> PJP201, PJ203 --> PJP203, PJ400 --> PJP400, PJ401 --> PJP401, JP12 --> PJP12
4 ALL ALL 2013/10/21 EE Re-name part of jump JP13 --> PJP13, J510 --> PJP510, J511 --> PJP511, J512 --> PJP512, J513 --> PJP513, PJ1000 --> PJP1000
5 23 Audio Codec ALC3234 2013/10/23 EE Update P/N for X1 code issue Change LA8, LA9 form SM010018110 to SM01000EI00
6 1 Cover page 2013/10/28 EE Add Micron sku for X76 level Add UV17, UV18, UV19, UV20 for SA000077K0L, RV59 for 24.9K X01
7 27 LED/DB 2013/10/29 EE delete circuit for EC control LED blink issue Delete Q2417
8 29 KBC & GPIO MEC5085 2013/10/31 EE Depop item by EC request Depop RE278
9 22 LAN RTL8111GUS-CG 2013/10/31 EE Change Power switch for cost down plan Change UL2 from SA00003AR00 to SA000079400, Delete CL38, Add RL41 X01
10 21 eDP/webcam/touch 2013/10/31 EE Change Power switch for cost down plan Change UX1, UX3 from SA00003AR00 to SA000079400, Delete CX9, CX52, Add RX30, RX31 to 100K X01
11 31 DC/DC interface 2013/10/31 EE Change Load switch for cost down plan Change U2301, U2304 from SA00004MM00 to SA00006FD00 X01
12 50 N15S-MEM Interface A 2013/10/31 EE Change Load switch for cost down plan Change UV15 from SA00004MM00 to SA00006FD00 X01
13 25 NGFF_WLAN 2013/10/31 EE Change Power switch for cost down plan Change UM1 from SA00005XM00 to SA000070L00, Add CM8 to 2200P X01
14 22 LAN RTL8111GUS-CG 2013/10/31 EE Change Transformer for cost down plan Change TL2 from SP050007Q00 to SP050006P00 X01
C 15 20 DP to CRT 2013/11/05 EE Add cap for reduce power ripple by vendor confirm Add CV361 to 22uF and close UV6 pin 38 X01 C
16 23 Audio Codec ALC3234 2013/11/05 EE Add capacitor for codec stable Add CA77 to 4.7uF_0603 and close UA1 pin36
19,24, Change L12,LX2,LI2,LX3,LX4,LX5,LI5,LX6,LX7,LI9,LI10 from SM070001S00 to SM070003Y00
17 26,27 Common mode Choke 2013/11/12 EE Change Common mode choke for X1 code Change LI1, LI3, LI4, LI6 from SM070001R00 to SM070003Q00 X01
18 27 LED/DB 2013/11/12 EE Delete MB common mode choke by EA measure Delete LI9, LI10 X01
19 46 N15S-PCIE 2013/11/13 EE change bead for X1 code Change LV8 from SM010028480 to SM010004700 X01
20 24, 27 USB 2013/11/13 EE Change USB I/O power switch for Cost down Change UI2, UI3, UI4 from SA00003XM00 to SA00007AO00, Delete CI7, CI14, CI18, CI45, Change CI6, CI12, CI44 from 4.7U_0805 to 1U_0603
21 13, 17 Buffer output 2013/11/13 EE change buffer output for cost down Change UC6, U2303 from SA00005U600 to SA00007KJ00 X01
22 46 N15S-PCIE 2013/11/14 EE change AND gate for cost down Change UV14 from SA007080120 to SA00000OH00 X01
23 17, 27, 30 DDR & LED & KB 2013/11/14 EE change MOSFET for cost down Change Q12, QE11, Q327 from SB00000UO00 to SB00000ST00, Change QD2 from SB501380050 to SB00000ST00 X01
24 23 Audio Codec ALC3234 2013/11/15 EE modify by EMC request Change RA1126, RA1127 to SM01000FG00, Change CA38, CA40 from 100p to 680p X01
25 46, 50 N15S-PCIE 2013/11/15 EE modify for GPU power sequence Change RV45 from pull high to 45.3K pull down, Depop CV141, Change CV140 from 470P to 1000P
26 23 Audio Codec ALC3234 2013/11/18 EE Change EMI solution Change RA1121, RA1122, RA1123, RA1124 from 0 ohm to SM01000NO00 X01
27 29 KBC & GPIO MEC5085 2013/11/18 EE Add ESD diode by EMC request Add DE2 for PECI_EC net
B B
28 26 HDD/Finger print 2013/11/19 EE Rename Location Re-name U2413 to DS1
29 08, 29 Crystal 2013/11/20 EE Crystal fine tune Change CE53 from 22P to 27P
30 20 DP to CRT 2013/11/21 EE Add Power pin connect to power by vendor Add RV518 10K to +3VS_VGA
31 21 eDP/ HDD / PAD 2013/11/21 EE change connector & PAD by ME Change JEDP to SP010013I00, JHDD to SP02000TR00, H1, H2, H15, H24 update footprint
32 23, 26 Audio & Finger 2013/11/21 EE modify by EMC request Change LA8, LA9 from SM010018110 to SM01000MJ00, Change RS39 from 0603 to 0402
33 27 ESD 2013/11/21 EE ESD BOM slim plan Change DE1, DV5, DV6 to SCA00001L00,
34 21 Camera 2013/11/21 EE Camera voltage drop Delete RX27, Add QX5 and Change +3VS to +3VALW
35 23 Audio 2013/11/25 EE Change ESD diode by EMC request Change DA12 to SC400007Q00, Add DA14 to SC400007Q00
36 46 N15S-PCIE 2013/11/26 EE Add diode for prevent leakage Add DV9 for GC6_EVENT#
37 32 Screw Hole 2013/11/26 EE Modify Screw hole by ME update DXF Delete H13, H18, Add H24
38 29 KBC & GPIO MEC5085 2013/11/27 EE Change Connector for ME issue Change JDEG from SP01001FP00 to SP01001L100, Change JLPDE from SP01001FP00 to SP01000HE00
39 21 eDP 2013/11/27 EE Add EMI solution for eDP Add LX8, LX9, LX10, for SM070003Q00, Add RX32, RX33, RX34, RX35, RX36, RX37 for 0 ohm
A A
40 29 KBC & GPIO MEC5085 2013/11/27 EE Change Resistor for Thermal request Change RE77 from 1.58K to 1.96K
41 46 N15S-PCIE 2013/11/28 EE GPU circuit modify by vendor feedback Add RV519 for GPU_CLK_27M_OUT, pop DV8, RV29, reserve RV208, Change power for ROM_SO_GPU/ROM_SI_GPU/ROM_SCLK_GPU
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/04/10 Deciphered Date 2014/05/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 52 of 54
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List ) Page 2
Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
42 24 USB3.0 2013/11/28 EE Rename by EC request Delete RI1, connect UI2 to UE4 by USB_PWR_EN3# X01
43 32 Screw Hole 2013/11/29 EE Modify Screw hole by ME update DXF Delete H16, Update H12 & H15 X01
D D
44 23 Audio 2013/12/02 EE Change EMC bead by EMC request Change RA1126, RA1127 to LA10, LA11, P/N from SM01000FG00 to SM01000NA00, RC366 rename to RA1130 X01
45 19 HDMI 2013/12/02 EE Update HDMI connector Change JHDMI from DC232001500 to DC232001K00 X01
46 46 N15S-PCIE 2013/12/03 EE fine tune crystal capacitor Change CV34, CV35 from 10P to 18P X01
47 22 LAN RTL8111GUS-CG 2013/12/03 EE Change Wake on LAN fnction GPIO by EC request Add R2532 for PCIE_WAKE# to LAN_WAKE# X01
48 27 LED/DB 2013/12/04 EE Change Tough PAD pin define for vendor request Delete R2529, R2530, R2531 pull high, and change net CLK_TP_SIO/DAT_TP_SIO from pin1, pin2 to pin6, pin7 X01
49 26 HDD/Finger print 2013/12/04 EE Update footprint by DFB request Update JFP connector footprint X01
50 27 LED/DB 2013/12/06 EE Change Power button design for SMT issue delete net from SW1 pin1 & pin4 X01
01 22 LAN 2014/02/10 EE Update Jump name Change JP3 to PJP3 X02
02 26 HDD 2014/02/10 EE Update connector footprint for ME Update JHDD connector X02
03 08 RTC 2014/02/10 EE Change crystal by Intel SPEC Change YC1 from SJ100001K00 to SJ10000LT00
04 27 LED 2014/02/10 EE Change design by Dell request Delete RZ24,Q12,RE21, change LED signal from SATA_ACT# to BREATH_LED#, SATA_ACT# connect to RP37
05 25 NGFF 2014/02/11 EE Update CIS symbol for pin define correct. Change UM1 from SA000070L00 to SA000070S00
C 06 21,27 MIC/Power Switch 2014/02/11 EE Add ESD solution by EMC Add DX4, DW1 for MIC_CLK/MIC_DATA, POWER_SW#_MB C
07 26 HDD 2014/02/25 EE update circuit for 2nd source plan Add RS40, RS41, RS42, RS43 for US2
08 ALL 0 ohm to short pad 2014/02/25 EE change footprint for 0 ohm cost down Change RC43,RC44,RC45,RC46,RC57,RC59,RC126,RC37,RC40,RC41,RC42,RC47,RC55,RC78,RC81,RC97,RC107,R2355,R248,R250,R251,R257,R265,RV163,RV164,RV215,
R2360,R2632,RM5,RM6,RS39,RE58,RE275,R416,R2451,RX32,RX33,RX34,RX35,RX36,RX37,RA1114,RA1115,RA1116,RA1117
09 29 EC 2014/02/26 EE Update EC Reversion resistor Change RE79 from 130K to 62K
10 23 AUDIO 2014/03/12 EE Change footprint for cost down Change CA23 from 0603 to 0402
GC6 Function Changes:
Delete DV8,RV29,DV9,DV8,RV29,DV9,QV86,CV363,RV181,QV87, Reserve RV520, Add RV51 pull high for SYS_PEX_RST_MON#.
1. Update GPU circuit for GC6 feature change to Use DGPU_PWR_EN to replace 3V3_MAIN_EN for +3V_RUN_GFX turn on time tuning.
2014/03/04 pure Optimus function. Delete DV4 and use GFX_CORE_PG to replace FBVDD_EN turn on +1.35VS_VGA.
11 45-51 GPU EE Change net name +3.3V_GFX_AON to +3.3V_RUN_GFX.
2. fine tune GPU power sequence
Other Changes:
Chang RV45 from 45K to 10K, De-pop RV31 as FAE recommend no use.
Add DV10 solve DGPU_PEX_RST# turn on glitch issue.
reserve CV140 for fine tune GPU turn on timing
12 28 EC 2014/03/05 EE Add CPU_ID for HSW & BDW sku by EC request Add RE279,RE280 for CPU_ID pin
13 08 ME 2014/03/05 EE Change ME switch for layout placemant Change SW3 from SN200003E00 to SN200002Y00
B B
14 21 eDP 2014/03/07 EE Fine tune B+ range Change RX2 from 100K to 270K, Change RX3 from 100K to 47K
15 27 FAN 2014/03/10 EE Add ESD by EMC request Add DE3 on FAN1_TACH/FAN1_PWM
16 22 LAN 2014/03/12 EE Remove jump for layout placement Delete PJP3
17 20 CRT 2014/03/12 EE Remove 0 ohm for EMC request Delete RV211,RV212,RV213
18 29 EC 2014/03/12 EE Update crystal for measure result Change YE1 from CL=12.5pF(SJ100001K00) to 9pF(SJ10000IA00)
19 45 GPU 2014/03/12 EE Update Resistor for measure result Change RV519 form 0 ohm to 430 ohm
20,24,
20 26,27 ESD 2014/03/13 EE Update ESD diode footprint for ME height limit Change DI2,DI5,DS1,DE1,DV5,DV6,DE3 from SCA00001L00 to SCA00001100
21 21 eDP 2014/03/14 EE Change Capacitor for measure result Change CX31 from 10V(SE102104K00) to 25V(SE00000G880), Change CV57 from Y5V(SE070104Z80) to X5R(SE00000G880)
22 27 PWR Button 2014/03/17 EE Change Footprint for layout require Change SW1 footprint (the same P/N)
23 13,17 MCP & DDR buffer 2014/03/18 EE Change main source for IC issue Change UC6, U2303 from SA00007KJ00 to SA00005U600
24 29 Thermal 2014/03/18 EE Reserve NGFF thermal sensor by Thermal team request Reserve QE10
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/04/10 Deciphered Date 2014/05/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 53 of 54
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List ) Page 1
Item Page# Title Date Request Issue Description Solution Description Rev.
Owner
PC901,PC907,PC923,PC912,PC903 change from pop to
1 P40 PROCESSOR DECOUPLING 2013/11/12 PWR SSI verify , Vcore keep 18 keep de-pop
2 P41 Charger_BQ24777 2013/11/12 PWR EMI requirement Pc723,PC724,PC725 change from de-pop to pop
D D
3 P33 DCIN/BATT CONN/OTP 2013/11/12 PWR EMI requirement Add PL5/PL7(SM01000C000)
Add PL8(SM01000C000), PL1/PL2/PL5/PL6 change from SM010009C80 to SM01000C000
4 P33 DCIN/BATT CONN/OTP 2013/11/12 PWR EMI requirement for finding 2nd source easily
5 P33 VCORE 2013/11/12 PWR EMI requirement PL502 change from 0.22uH to 0.15uH
6 P38 VCORE 2013/11/12 PWR Vcore test result abjustmet value PR521 change from 97.6k to 95.3k
7 P38 VCORE 2013/11/12 PWR change to Vendor ( CYNTEC) PL502 change to SH00000PQ00
8 P38 VCORE 2013/11/12 PWR EMI requirement add PL504(SM01000C000)
9 P38 VCORE 2013/11/12 PWR for common part PL501 change from SM010009C80 to SM01000C000
10 P34 3.3VALWP/5VALWP 2013/11/13 PWR for common part PL100 change from SH00000MS00 to SH00000YC00
11 P37 +1.35VP/0.675VSP 2013/11/13 PWR for common part PL200 change from SH00000KS00 to SH00000YE00
12 P45 +1.35VGPU_DDR 2013/11/13 PWR for common part PL1001 change from SH00000MR00 to SH00000YV00
13 P38 VCORE 2013/11/14 PWR Vcore test result abjustmet value PR521 change from 95.3k to 90.9k
14 P39 +VCCIO 2013/11/15 PWR for common part PL302 change form SM010009C80 to SM01000C000
C C
15 P33 DCIN/BATT CONN/OTP 2013/11/21 PWR ESD requirement add PD3 (AZ5125-01H.R7G_SOD523-2)
16 P34 3.3VALWP/5VALWP 2013/11/21 PWR change to same material PD101 change from SCA00002A00 to SCA00001W00
17 P41 Charger_BQ24777 2013/11/21 PWR peak shift issue Add PQ709
18 P44 VGA_COREP 2013/11/21 PWR ocp modify to 66A PR615 change from 10.7k to 13k
19 P38 VCORE 2013/11/25 PWR current rating issue PC520 change from 0402 to 0603
20 P41 Charger_BQ24777 2013/11/26 PWR check circuit modify error PQ708A swap pin1 and pin6
21 P39 +VCCIO 2013/11/28 PWR for buyer suggest change material PR303 chang from SD00001FX00 to SD013000080
22 P43 Charger_BQ24777 2013/11/28 PWR Vendor spec BQ24777_REGN modify to 5.4V R715 change from 121k to 154k
23 P38 VCORE 2013/12/04 PWR DFB issue remove PL503
24 P41 Charger_BQ24777 2014/2/17 PWR peak shift issue PR729 NC
25 P41 Charger_BQ24777 2014/2/17 PWR PIN21 change from NC to input current limit mode add PR706 10Kohm and pull high
26 P41 Charger_BQ24777 2014/2/17 PWR leakage current issue change PD701(SCS00003800) to PD702,PD703(SCS0340L010)
B 27 P41 Charger_BQ24777 2014/2/17 PWR PIN9 change from Voltage monitor to current monitor change PC753(100P) to PR732 (20K) B
28 P38 VCORE 2014/2/17 PWR Vcore test result abjustmet value PR535 change from 210 to 200
29 P43 VGA_COREP 2014/2/17 PWR ME Z-High issue PC604 change from pop to de-pop,PC627 change from de-pop to pop
DCIN/BATT CONN/OTP
30 P33 2014/2/17 PWR hiccup mode issue add Erp lot 6 circuit
31 P41 Charger_BQ24777 2014/2/21 PWR plug Adapter system no work issue add PR741 connect PQ709 Gate to GND
32 P44 +1.35VGPU_DDR 2014/3/4 PWR for EE suggest net name change from FBVDD_EN to GFX_CORE_PG
33 P41 Charger_BQ24777 2014/3/5 PWR acoustic noise add PC730,PC731,PC732 to de-pop
34 P41 Charger_BQ24777 2014/3/11 PWR Follow Houston test summary solution NC PQ708A,PQ708B NC
34 P38 VCORE 2014/3/11 PWR acoustic noise Change PC515 PC533 from VCC_PWR_SRC to B+
35 P37 +1.35VP/0.675VSP 2014/3/14 PWR select the correct voltage to 2.5V PC214 change from SF000003000 to SF000003100
36 P33 DCIN/BATT CONN/OTP 2014/3/17 PWR hiccup mode issue add PR13 NC
37 P34 3.3VALWP/5VALWP 2014/3/17 PWR Co-Lay add PC116 PC117 NC
38 P41 Charger_BQ24777 2014/3/17 PWR follow TI solution change PR725 from 100K to 1K
A A
39 P41 Charger_BQ24777 2014/3/21 PWR hiccup mode issue change PR739 from 316K to 294K
40 P34 3.3VALWP/5VALWP 2014/3/24 PWR follow EC solution PR110 NC
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/07/25 Deciphered Date 2014/07/24 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEAMTICS,MB AB072
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019RU
Date: Monday, April 07, 2014 Sheet 54 of 54
5 4 3 2 1
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