IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 68, NO.
4, APRIL 2021
A Study of the Gate-Stack Small-Signal Model
and Determination of Interface Traps in
GaN-Based MIS-HEMTs
Zhangwei Huang, Shuhao Xiong , Ninggang Dong, Lining Zhang , and Xinnan Lin, Member, IEEE
Abstract — The existing gate-stack small-signal models
of metal–insulator–semiconductor high-electron-mobility
transistors (MIS-HEMTs) were analyzed, and a new model
that could fit the measured admittance characteristics in
the whole bias regime after learning about their shortcom-
ings was presented. The capacitance and conductance fre-
quency characteristics were fitted simultaneously, and the
extracted fitting parameters showed reasonable values and
trends. These parameters were then used in the determina-
tion of interface traps as well as the quantitative analysis of
two C-V slopes for MIS-HEMTs. It was proven that the intrin-
sic barrier resistance was also a critical factor for the second
slope. Thus, this resistance could not be neglected by
the capacitance method that determined the interface trap
densities directly by the frequency dispersion of the second
slope. This article extracted the energy distribution of the
interface trap density, which could be fitted by a Gaussian
distribution with a maximum value of ∼3 × 1012 cm−2
eV−1 . Although this method was a suitable alternative
because the capacitance and conductance were correlated
by the admittance characteristics, the detected shallow-
level traps may not account for the threshold voltage
drift or other reliability problems of MIS-HEMTs.
Index Terms — AlGaN/GaN metal–insulator–semiconduc-
tor high-electron-mobility transistors (MIS-HEMTs),
capacitance method, conductance method, gate-stack
small-signal model, interface trap.
I. I NTRODUCTION
G aN-BASED metal–insulator–semiconductor
electron-mobility transistors (MIS-HEMTs) are
considered potential candidates for the next generation
high-
of power switching transistors [1]–[4]. Despite the advantages
of less gate leakage and greater gate voltage swing of
MIS-HEMTs, the dielectric/III-V interface quality is always
Manuscript received December 7, 2020; revised January 12, 2021
and January 23, 2021; accepted January 31, 2021. Date of publi-
cation March 3, 2021; date of current version March 24, 2021. This
work was supported by the Natural Science Foundation of China
under Grant 62074006, Shenzhen Project JCYJ20170810163407761,
Shenzhen Project KQJSCX20170728102129176, and Shenzhen Project
JSGG20180504170016884. The review of this article was arranged by
Editor T. Grasser. (Corresponding author: Shuhao Xiong.)
The authors are with the Shenzhen Key Laboratory of Advanced
Electron Device and Integration, School of Electronic and Computer
Engineering, Peking University, Shenzhen 518055, China (e-mail:
xnlin@pkusz.edu.cn).
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TED.2021.3057019.
Digital Object Identifier 10.1109/TED.2021.3057019
0018-9383 © 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
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1507
a problem [5]–[7]. The high density of insulator/III-V
interface traps can enable the threshold voltage (VTH )
instability effect, the positive-bias temperature instability
(PBTI) effect, the current collapse effect, dynamic resistance
degradation, and so on [6]–[9]. Hence, various materials,
processes, and treatments have been introduced to eliminate
interface traps and enhance the interface quality in such
transistors [10]–[12]. Accurately extracting and characterizing
the density of interface traps (Dit ) is, therefore, central to
judging the effectiveness of those techniques at eliminating
interface traps.
The technologies commonly used to determine the inter-
face trap density of MIS-HEMTs include the pulse-mode
IV method [13], [14], the stress-recovery method [15]–[18],
the conductance method [10], [19]–[25], and the capacitance
method [9]–[10], [25]–[28]. However, none of these tech-
nologies have been proven accurate. Transient measurements
can detect larger energy ranges but cannot avoid system
measurement errors [15]. The conductance method and the
capacitance method adopt ac admittance measurements. The
conventional conductance method is considered of little use
owing to the improper gate-stack model originating from
Si-based MOSFETs, which are significantly different from
MIS-HEMTs [19]–[21]. Although several modified models
have been proposed [27]–[29], they may not be appropriate
alternatives because they still cannot explain the admittance
characteristics of MIS-HEMTs. The capacitance method has
been proposed to extract interface traps from the frequency
dispersion of the second C-V slope. However, Capriotti et al.
simulated the second slope without interface traps considered
in the gate-stack model [29], which indicated that the traps
may not be the only reason for the capacitance–frequency
dispersion. In fact, the conductance and capacitance are
strongly related and are extracted from the real and imaginary
components, respectively. In principle, it is not suitable to use
only one of these methods for defect analysis.
This article analyzed the existing MIS-HEMT gate-stack
models and found that they were unable to fit the measured
admittance characteristics in the spillover regime. Therefore,
this work presented a new model that can effectively fit
both G p - f and C p -f of MIS-HEMTs in the whole bias
regime. The value as well as the trend of the extracted
fitting parameters were reasonable. By quantitatively analyzing
the fitting parameters, the physical mechanisms of two C-V
1508 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 68, NO. 4, APRIL 2021

Fig. 2. Typical lumped-element models of the GaN-based MIS-HEMT

Fig. 1. (a) Top view and (b) cross-sectional view of AlGaN/GaN MIS gate-stack proposed in recent years. (a) Model A, (b) Model B, and
diodes on Si. R is the radius of the circular gate metal layer; L is the (c) Model C.
distance from the gate to the ohmic contact. The two-electrode plane
direction is a 2DEG conductive channel. In addition, the thickness of the
SiN dielectric layer is 35 nm.

slopes were explained, and the energy distribution of the

interface traps was extracted in the spillover region. It was
confirmed that the intrinsic barrier resistance was also critical
to the second slope, and thus, the capacitance method would
result in the misestimation of the interface trap density. In the
end, the disadvantage of utilizing the admittance measurement
to determine the interface traps for MIS-HEMTs was analyzed.
Only “fast” traps can be detected by this technology, and these
traps may not be responsible for the serious reliability effects
the devices encounter.

II. D EVICE AND FABRICATION

AlGaN/GaN MIS diodes were fabricated and studied in this
work so that the potential at the interface was not affected by
the drain voltage. Fig. 1 shows the top view as well as the
cross-sectional view of the MIS diodes. The epitaxy consists of
a 22-μm bow, a 140-nm GaN layer, a 4.2-μm buffer, a 420-nm
i-GaN layer, a 25-nm Al0.25 Ga0.75 N barrier, and a 3-nm GaN
cap. The 35-nm SiN insulator was deposited on the epitaxy
by low-power chemical vapor deposition (LPCVD).
In Fig. 1(a), R and L are the radius of the circular gate
layer and the distance from the gate to the ohmic contact,
respectively. L is a fixed value of 60 μm. Three devices
with different R sizes (Device A: 50 μm, Device B: 40 μm,
and Device C: 30 μm) were studied in this article, and
theoretically, their results after area normalization should be
consistent.
III. M ODEL V ERIFICATION AND A NALYSIS
The recently proposed modified gate-stack models of
GaN-based MIS-HEMTs are shown in Fig. 2: Model A in
Fig. 2(a) [27], Model B in Fig. 2(b) [29], and Model C in
Fig. 2(c) [28].
Models A and B introduce the barrier-layer conductance
effect. When the gate bias becomes positive, the barrier height
of the MIS-HEMT barrier layer decreases gradually with
increasing gate bias, and the barrier-layer resistance decreases
due to the intrinsic excitation of the barrier layer. The barrier-
layer resistance is expressed as Rb in the model. Therefore,
the channel layer plays an important role in the resistance
behavior that cannot be ignored.
Fig. 3. Equivalent parallel capacitance and conductance as functions of
frequency in the spillover region simulated by existing MIS-HEMT gate-
stack models: Models A, B, and C. The scattered points are measured
data, while the lines are fitted curves.
Model C introduces the channel layer, but the barrier-layer
conductance effect is not considered. When the MIS-HEMT
is in on state, the barrier-layer conductance decreases, which
cannot be ignored. However, the channel layer is parallel at
both ends of the barrier layer, which is not consistent with the
MIS-HEMT device structure.
Although they aimed to better describe the ac characteristics
of MIS-HEMTs, these models still cannot explain the admit-
tance characteristics, including G p -f and C p -f. Fig. 3 shows
that Models A and B failed to simulate the measured G p -f
characteristics, while Model C seemed to have a better effect
but was still unable to fit the measured C p -f curves. Therefore,
a developed gate-stack model of GaN-based MIS-HEMTs is
urgently needed for a more accurate determination of interface
traps.

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HUANG et al.: STUDY OF THE GATE-STACK SMALL-SIGNAL MODEL 1509

Fig. 4. The gate-stack small-signal model of the MIS-HEMT proposed

in this article (a) for a negative gate bias when the conductance of the
AlGaN barrier layer and the effect of interface traps can be neglected
and (b) for a positive gate bias when the effect of interface traps has to
be taken into consideration.

Fig. 4 shows the new gate-stack model proposed by this

article. Consistent with the actual physical structure, the model
has three layers including a dielectric layer, an AlGaN barrier
layer, and a channel layer on the surface of i-GaN. The
contribution of interface traps as well as the barrier conduc-
tance need to be taken into account when the barrier height
decreases, as Fig. 4(b) shows. Cd is the capacitance of the gate
dielectrics. Cb and Rb are the equivalent parallel barrier capac-
itance and resistance, respectively. Cc and Rc are the equiva-
lent series channel capacitance and resistance, respectively. Cit Fig. 5. Capacitance and conductance frequency characteristics of the
and Rit are the series representations of frequency-independent three devices in the first slope. The scattered points are measured data
trap capacitance and resistance, respectively. For the energy and the lines are fitting curves using a simplified model, as shown in
Fig. 4(a). Gate bias voltages from −11.3 to −10.0 V were chosen from the
band of the barrier layer, when there is a V change in the subthreshold region to the conductance region. R2 is the worst goodness
AlGaN barrier layer, V will trap/detrap the AlGaN surface of fit measurement for the curves in each graph.
defects; for the equivalent capacitance of AlGaN, a V change
will result in a change in Q 2 produced by the equivalent
capacitance of AlGaN. Therefore, the model considers Cit and
Rit in parallel to the capacitance and resistance of the barrier.
Among these parameters, Cd and Cb are measurement
parameters obtained from two C-V steps at a low frequency,
and they remain constant when the gate voltage changes. The
equivalent parallel capacitance C p and conductance G p at a
set frequency can be calculated from the total admittance of
this model. It should be noted that a slight difference between
gate-stack models might result in a very large difference in
admittance characteristics.
Quite a few studies have tried to analyze interface traps from
admittance–voltage characteristics at different MIS-HEMT Fig. 6. Cc and Rc of the three devices as a function of Vgs extracted
frequencies. However, the charge states of those interface from the first slope by the model shown in Fig. 2(a). Cc data are plotted
traps might change due to the gate stress during repetitive by red scattered points and Rc data are the blue points. Rc and Cc reach
nonnegligible values.
voltage-sweeping measurements, especially when the gate
voltage reaches the spillover region. If the threshold voltage
drifted, the admittance–frequency characteristics could not be in the first slope, and the different admittance characteristics
extracted as the fitting standard of the model. Although a of different devices at the same bias resulted from slightly
slower voltage-sweeping rate can reduce this impact, C p /G p - different threshold voltages less than 0.3 V. These differences
f sweeping is recommended to maintain a constant τit -Vgs might be caused by process fluctuation.
relationship. The plots of Cc and Rc with the gate bias in the first slope
Fig. 5 shows the plot of the parallel capacitance (C p ) are shown in Fig. 6. As electrons accumulated in the 2DEG
and conductance (G p ) as functions of frequency ( f ) in the conductive channel, Cc increased and Rc decreased rapidly
first slope for three different MIS diodes. The capacitance– until reaching a nonnegligible value. However, Rb and τit were
frequency characteristics and the conductance–frequency char- still so large that they could be ignored in the first slope
acteristics were fitted at the same time by the simplified model because of the high potential barrier of the AlGaN barrier
in Fig. 4(a). The bias gate voltages were arbitrarily chosen layer. Therefore, the model in Fig. 4(b) can be simplified to

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1510 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 68, NO. 4, APRIL 2021

The total admittance of the barrier layer in the spillover

region can be expressed as follows:
 
1 ω2 τit C it Cit
Ybr = + + j ω Cb + (3)
Rb 1 + ω2 τit2 1 + ω2 τit2
where Ybr is the total admittance of the barrier layer.
Assuming the equivalent parallel barrier capacitance is
Cbp and the equivalent parallel barrier resistance is Rbp , the
equivalent series impedance of the dielectric layer and the
barrier layer is
 
Rbp 1 ω2 Cbp Rbp
2
1
Z db = + + (4)
1 + ω2 Cbp
2 2
Rbp j ω 1 + ω2 Cbp2 2
Rbp Cd
where Z db is the total impedance of the dielectric layer and
the barrier layer.
Defining two characteristic frequencies: ω1 = 1/τit and ω1 =
1/(Cbp Rbp ), if ω  ω1 and ω  ω2 , (4) can be simplified as
 
1 1 1
Z db = + . (5)
j ω Cd Cb
The equivalent circuit becomes consistent with the circuit
shown in Fig. 4(a), and the total capacitance of the dielectric
layer and the barrier layer remains unchanged.
The total capacitance of these layers does not change with
Fig. 7. Capacitance and conductance frequency characteristics of the the gate bias, which means there will be no second slope.
three devices in the second slope. The scattered points are measured
data and the lines are fitting curves using the model shown in Fig. 4(b). If ω  ω1 and ω  ω2 , (4) can be simplified as
Gate bias voltages from 2 to 6 V were chosen in the spillover region. R2
1
is the worst goodness of fit measurement for the curves in each graph. Z db = Rb + . (6)
j ωCd

a series of three capacitors with one resistor, as shown in
Fig. 4(a). The total admittance can be expressed as
ω2 Rc Cs2 j ωCs
Y = + (1)
1 + ω Cs Rc 1 + ω2 Cs2 Rc2
2 2 2
The parallel capacitance is therefore
Cs
Cp = (2)
1 + ω2 Cs2 Rc2
where Cs is the equivalent series capacitance of Cd , Cb ,
and Cc .
Equation (2) is a function of frequency and explains why
a C-V frequency dispersion also exists in the first slope. This
dispersion is an intrinsic characteristic of the channel layer
and partly explains why the Vth in MIS-HEMTs rises as the
measurement frequency increases.
Model verification in the second slope is more critical
because the mechanisms of model frequency dispersion are
not fully understood, and the interface trap-related parameters
can be extracted only in this region. Fig. 7 shows the plots
of C p and G p as functions of frequency in the spillover
region for the three devices. Good fits for both C p -f and G p -f
were also observed when the complete model in Fig. 4(b)
was used. In the second slope, Rc and Cc change very little.
Therefore, only the barrier layer and the dielectric layer are
analyzed.
The total capacitance of the dielectric layer and the barrier
layer becomes the capacitance of the gate dielectric Cd , which
means that the second step has been reached.
Equations (5) and (6) imply that the equivalent parallel
capacitance of the dielectric layer and the barrier layer,
C p , will decrease from Cd to 1/(1/Cd + 1/Cb ) as the fre-
quency increases, which represents the frequency dispersion
of the second slope.
Fig. 8 shows the behavior of related fitting parameters in
the spillover region. Rb was reduced by almost three orders
of magnitude during the second rise, but Rc was almost
unchanged. In this region, the value of Rc was much smaller
than that of Rb because the conductivity of the channel
layer was greatly improved with the gradual accumulation of
electrons in 2DEG but was still nonnegligible. Meanwhile,
trap-related parameters also showed dramatic changes that
were then used to calculate the energy distribution of the
density of interface traps. All of these effects in the spillover
region indicated that the AlGaN barrier height dropped as the
positive gate voltage bias increased, while both the barrier
resistance and the electron emission time constant of interface
traps rapidly decreased; hence, the appearance of the second
slope according to (3).
IV. A NALYSIS OF THE C APACITANCE M ETHOD
The capacitance method tries to extract Dit from the fre-
quency dispersion at the onset of the second slope, assuming
that the effect of barrier conductance is too small compared

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HUANG et al.: STUDY OF THE GATE-STACK SMALL-SIGNAL MODEL
Fig. 8. The fitting parameters (a) Rb , Rc and (b) Rit , Cit as functions of
the gate voltages of the three devices in the spillover region. Rc could not
be normalized by the area because current flowed laterally in the 2DEG
conductive channel.
with the effect of interface traps to be taken into account.
However, such an assumption is not supported from the data
perspective. Therefore, the simulated admittance characteris-
tics neglecting the effect of MIS-HEMT barrier conductance
are shown in Fig. 9. Rb remained so large that it could be
regarded as an open circuit in the spillover region under this
assumption. The results showed that both the capacitance and
the conductance were far lower than the actual measured
data, especially at low frequencies below 100 kHz. This
behavior indicated that regarding the interface traps as either
the only or the main reason for the second C-V slope and its
frequency dispersion was not a rigorous approach.
In addition, the C-V sweeping measurement used by the
capacitance method may cause threshold voltage drift, as men-
tioned in Section III. This disadvantage could not even be
overcome by compensating for Vth because the frequency
dispersion of the first slope of the C-V characteristics was an
intrinsic characteristic of MIS-HEMTs. This first slope was
analyzed in (2). Based on the above results, the capacitance
method is most likely to overestimate the interface traps of
MIS-HEMTs.
V. D ETERMINATION OF I NTERFACE T RAPS
The energy level could be deduced from τit , a product of Cit
and Rit , by using Shockley–Read–Hall statistics and assuming
τe was much larger than τc
 
1 Ec − E T
τit = exp (7)
νth ξn Nc kT
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1511
Fig. 9. Comparison of the admittance characteristics simulated without
intrinsic barrier resistance and the measured data of the three devices
in the spill-over region.
TABLE I
F ITTING PARAMETERS OF G AUSSIAN D ISTRIBUTION
where νth = 2 × 107 cm/s, ξn = 1 × 10−14 cm2 , and
Nc = 4.3 × 1014 × T3/2 cm−2 . νth , ξn , and Nc are the
electron thermal velocity, electron capture cross-sectional area,
and effective density of states in the GaN conduction band,
respectively. Dit could be deduced from Cit
Cit
Dit = . (8)
q
The values of the Gaussian distribution fitting parameters
are shown in Table I, in which slight differences among the
three devices arise from process fluctuations. Nit is the total
number of interface traps in the range of energy levels that
could be detected by the admittance measurement. Therefore,
the maximum value of the threshold voltage drift could be
calculated based on Nit
q N it
Vth,max = (9)
Cox
where Cox is the area normalized insulator capacitance. How-
ever, Vth,max was calculated to be approximately 0.06 V and
1512
was far less than the actual result of ∼1.6 V measured by
the 1000 s forward-bias stress test, which is not shown in
this article. This result indicated that deep-level traps were
the main factors accounting for the threshold-voltage drift of
these samples, which was difficult to detect by the admittance
measurement.
VI. C ONCLUSION
In this article, a new gate-stack small-signal model for
GaN-based MIS-HEMTs was proposed. This model was able
to fit the measured C p -f and G p -f at the same time in the whole
bias regime. Thus, the model fitting parameters could be used
to calculate the energy distribution of interface traps and ana-
lyze the shape of two C-V steps for MIS-HEMTs. In contrast,
other existing models used in the conductance method could
not simulate the admittance characteristics of MIS-HEMTs.
Then, the cause of the second C-V slope was quantitatively
analyzed by the gate-stack model proposed in this article. The
intrinsic barrier conductance was proven to be an important
factor for the second slope, as well as its frequency dispersion,
which was neglected by the capacitance method. In addition to
the effect of the repetitive C-V sweeping test, the capacitance
method was most likely to overestimate the density of interface
traps for MIS-HEMTs. We believe that this work can provide
a proper alternative method for interface trap characterization
based on admittance measurements. However, the limitation
of the ac admittance measurement is that it can detect only
shallow-level traps, which is probably not the main cause of
the MIS-HEMT reliability problems caused by interface traps.
Therefore, this method is recommended for use with transient
measurements, such as the stress-recovery method.
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