ISSCC 2022 / SESSION 28 / DRAM AND INTERFACE / 28.
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28.8 A Supply-Noise-Induced Jitter-Cancelling Clock Distribution
Network for LPDDR5 Mobile DRAM featuring a 2nd-order
Adaptive Filter
Yeonwook Jung*1, Seongseop Lee*2, Hyojun Kim3, SeongHwan Cho4
1
Samsung Electronics, Hwaseong-si, Korea
2
SK hynix, Icheon, Korea
3
Korea Aerospace Research Institute, Daejeon, Korea
4
KAIST, Daejeon, Korea
*Equally Credited Authors (ECAs)
With the increasing demand for low-power, high-speed DRAMs, LPDDR5 featuring a
speed of 6.4Gb/s has recently been announced [1]. One of the most critical issues of
high-performance DRAM is the supply-noise induced jitter (SIJ) generated by the clock
distribution network (CDN) and the transmit and receive paths. Conventional CDN SIJ
coping methods use supply voltage regulators and decoupling capacitors. Unfortunately,
a supply regulator is not suitable for low-voltage mobile DRAM due to the required drop-
out voltage headroom, while the decoupling capacitor cannot sufficiently filter
2022 IEEE International Solid- State Circuits Conference (ISSCC) | 978-1-6654-2800-2/22/$31.00 ©2022 IEEE | DOI: 10.1109/ISSCC42614.2022.9731682
low-frequency noise without requiring excessive area. In this paper, we propose an SIJ
cancelation technique based on an adaptive filter (AF) using a least mean square (LMS)
algorithm; it cancels jitter along the CDN and the transmit and receive paths, which
include serializers and pre-drivers. The proposed technique includes a 2nd-order AF to
maximize jitter cancellation in the clock path, which has a non-linear supply-to-jitter
characteristic [2]. Implemented in 28nm CMOS, the proposed SIJ cancellation scheme
reduces the RMS jitter of the RDQS_c clock from 27.33 to 4.20ps and improves the data
eye opening from 22.34 to 99.12ps when operating at 6.4Gb/s with a 60mVp-p 1MHz
supply noise.
The block diagram of the proposed jitter canceling CDN is shown in Fig. 28.8.1, which
includes the essential LPDDR5 I/O structures; transmit clock (RDQS_c), differential
receive clock (WCK_t,c) and data channels (DQ0,1,2). The received clock is divided-by-
2 to generate quadrature-phase clocks, which are distributed by a tree of repeaters, based
on an inverter chain, whose power naturally scales well with various low-speed DRAM
modes [4]. The transmitter consists of typical serializers, pre-drivers and output drivers
[4]. A pseudorandom binary sequence (PRBS) generator is also added to mimic data
from memory. In the presence of supply noise, CDN, serializer and pre-driver create SIJ.
VCDL cancels jitter by using the scaled-down supply noise as its control voltage to create
a delay that is opposite to that generated by the CDN and the transmitter. VCDL is placed
at the beginning of the CDN to save power and area overhead, since placing the VCDL
for every transmit path will require as many VCDLs as there are channels. Although
mismatch among channels may degrade the overall performance, measurement results
show that it is very small. The cancellation of SIJ will be maximized if the supply-to-jitter
transfer function of the CDN and the transmitter is matched to that of the VCDL.
Unfortunately, the clock-path transfer function has 1st- and 2nd-order components of
supply noise; hence, a 2nd-order AF is needed.
The proposed 2nd-order AF is shown in Fig. 28.8.1, where a 2nd-order noise cancelling
path is added in addition to a typical 1st-order noise cancellation. To obtain the optimum
gains for the 1st and 2nd-order AF, an LMS algorithm is used. For ease of implementation
a sign-sign LMS is used, where we further simplify the implementation by exploiting the
fact that sign of noise squared always positive: sign(n2) · sign(e) = sign(e).
A schematic for the proposed noise cancelling AF is shown in Fig. 28.8.2. The supply
noise is scaled and fed to the noise amplifier whose 1st and 2nd-order gains are set by the
sign-sign LMS algorithm. The sign of the supply noise is determined by using a
comparator and a voltage reference. Obtaining the sign of the jitter is not as
straightforward due to the inevitable delay created by the CDN, which creates an offset
time between the jittery output clock and the clean reference clock. Hence a simple arbiter
(D flip flop) cannot be used to detect the sign. In this work, we use a time-to-digital
converter (TDC) to digitally extract the offset time. The TDC is implemented using a
gated-ring oscillator (GRO) [5] for low-power consumption and high resolution. The
GRO-TDC measures the sign of the output clock (RDQS_c), which is physically located
right next to the input reference clock (fref). The offset delay is obtained by low-pass
filtering the output of the GRO-TDC and is stored in a register when the DRAM is in idle
mode. The sign of the jitter is achieved by comparing the register value with the output
of the GRO-TDC. Since power supply noise should not affect the GRO-TDC and the
reference clock, a step-up LDO (SU-LDO) [6] is used, which internally boosts the supply
voltage for regulation. The SU-LDO also powers the VCDL to reduce its dynamic range
required to cancel jitter. The sign of the jitter and the sign of the noise are multiplied and
accumulated to optimally set the 1st-order gain. For 2nd-order cancellation, only the sign
of the jitter is accumulated since sign of noise square is always positive.
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Schematics of key circuits are shown in Fig. 28.8.3. The 1st-order noise amplifier is a
differential amplifier, whose gain is controlled by a programmable resistor array. The
2nd-order amplifier uses a voltage squarer [7] after the differential amplifier. Note that
the 1st- and 2nd-order AFs share most of the blocks, such as the GRO-TDC, and hence
the 2nd-order noise cancellation overhead is due to the additional noise amplifier, bias
generator and digital accumulator. VCDL consists of current starved delay elements and
a bias circuit [8]. AF can be turned-off, by gating the clock, to save power consumption
during read and write operations; in which case, the gains (W1st, W2nd) are no longer
updated, but VCDL is still able to cancel jitter.
The proposed CDN was fabricated in a 28nm CMOS process; it occupies 0.11mm2 of
active area as shown in Fig. 28.8.7. The I/O pins are placed to best mimic the LPDDR5
standard. The measured 6.4Gb/s data eye diagram at DQ0 is shown in Fig. 28.8.4: the
horizontal eye width is increased from 22.34 to 91.55ps with a 1st-order AF and to
99.12ps with a 2nd-order AF. Measurements at DQ2 show a difference in the eye opening,
relative to DQ0, of less than 3ps. The measured jitter during reads (3.2GHz, RDQS_c)
are shown in Fig. 28.8.5 when a 60mVp-p 1MHz sinusoidal noise is injected. To verify the
operation of AF in a multi-frequency noise environment, a 1MHz bandwidth limited white
noise is injected on the supply. The phase noise plot, shown in Fig. 28.8.5, shows that
the RMS jitter is reduced from 9 to 1.54ps with a 1st-order AF and to 1.28ps with a 2nd-
order AF. The total power consumption, at 6.4Gb/s and with AF enabled, is 10.49mW
for one DQ channel. Overhead of the jitter cancellation circuits (SU-LDO, VCDL and AF)
is 2.7mW, where components for 2nd-order AF consume 0.21mW. AF power can be
reduced by 0.70mW by turning off LMS gain updates and its supporting circuits. The
performance of this work is summarized and compared to other related work in Fig.
28.8.6.
Acknowledgement:
This work was supported by Samsung Electronics and IITP grant funded by the Korea
government (MSIT) (2020-0-00850). Chip fabrication was supported by IC Design
Education Center (IDEC) of Korea
References:
[1] H-J. Chi et al., “An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank
Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd
generation 10nm DRAM Process,” ISSCC, pp. 382-384, 2020.
[2] M. Saint-Laurent, “Impact of power-supply noise on timing in high-frequency
microprocessors,” IEEE Trans. on Adv. Packaging, vol. 27, no. 1, pp. 135-144, Feb. 2004.
[3] JEDEC LPDDR5(JESD209-5A).
[4] K. Song et al., “A 1.1 V 2y-nm 4.35 Gb/s/pin 8 Gb LPDDR4 Mobile Device With
Bandwidth Improvement Techniques,” IEEE JSSC, vol. 50, no. 8, pp. 1945-1959, Aug.
2015.
[5] M. Z. Straayer and M. H. Perrott, “A Multi-Path Gated Ring Oscillator TDC With First-
Order Noise Shaping,” IEEE JSSC, vol. 44, no. 4, pp. 1089-1098, Apr. 2009.
[6] M. Q. Hasan and G. Slaughter, “Step-up LDO voltage regulator for a self-powered
biosensor,” IEEE SENSORS, 2017, pp. 1-3.
[7] G. Giustolisi et al., “A Novel CMOS Voltage Squarer,” IEEE ISCAS, pp. 253-256, 1997.
[8] G. Jovanovic et al., “Delay locked loop with linear delay element,” TELSIKS, pp. 397-
400, 2005.
[9] T. S. Sandhu and K. El-Sankary, “Supply-Insensitive Digitally Controlled Delay Lines
for 3-D IC Clock Synchronization Architectures,” IEEE VLSI Systems, vol. 27, no. 6, pp.
1480-1484, June 2019.
[10] D. Kim and S. Cho, “A supply noise insensitive PLL with a rail-to-rail swing ring
oscillator and a wideband noise suppression loop,” IEEE Symp. on VLSI Circuits, pp.
180-181, 2017.
[11] F. O’Mahony et al., “A Low-Jitter PLL and Repeaterless Clock Distribution Network
for a 20Gb/s Link,” IEEE Symp. on VLSI Circuits, pp. 29, 2006.
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 ISSCC 2022 / February 24, 2022 / 8:10 AM

Figure 28.8.1: Overall architecture of the proposed-supply-noise-insensitive clock Figure 28.8.2: Block diagram of the proposed AF for clock and data jitter
distribution and block diagram of 2nd-order adaptive filter. compensation. SU-LDO provides the supply for circuits shaded in blue.

Figure 28.8.3: Schematic of VCDL, noise amplifier, voltage squarer and bias
generator. Figure 28.8.4: Measured data eye with 60mVP-P 1MHz sinusoidal supply noise.

28

Figure 28.8.5: Measured clock jitter with 60mVP-P 1MHz sinusoidal supply noise of
RDQS_c (3.2GHz) and measured phase noise of 3.2GHz clock (RDQS_c) with 1MHz
bandwidth-limited 6.8mVRMS white noise on supply. Figure 28.8.6: Power breakdown and performance summary and comparison.
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Figure 28.8.7: Die micrograph.

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• 2022 IEEE International Solid-State Circuits Conference 978-1-6654-2800-2/22/$31.00 ©2022 IEEE