V381 50 (00205363) Decrypt

00
2
RD 05 SI M
(C 36 C
)2 3 ON TABLE OF CONTENTS
F
SHEET NO. SHEET NAME SHEET NO. SHEET NAME
02
1 TOC 26 SMALL RAIL REGULATORS
w I
2 NAVI10 PCIe Interface 27 NAVI10 DECAPS
3 NAVI10 GPIOs 28 NAVI10 POWER
劉 00 ei DE
4 NAVI10 XTAL 29 NAVI10 GND
5 NAVI10 MEM CHAB 30 POWER MANAGEMENT
6 NAVI10 MEM CHCD 31 SVI2 & BAMACO
7 NAVI10 MEM CHEF 32 MECHANICAL & THERMAL
巍 52 st NT
8 NAVI10 MEM CHGH 33 DE B UG
9 GDDR6 MEM CHAB 34 BLOCK DIAGRAM
10 GDDR6 MEM CHCD 35 REVISION HISTORY
11 GDDR6 MEM CHEF
00 an IA
12 GDDR6 MEM CHGH
13 NAVI10 TMDPA - DP
14 NAVI10 TMDPC - HDMI
15 NAVI10 TMDPEF - DP DP
g( L
16 GFX & SOC CONTROLLER
(3 2
17 VDDCR_GFX PHASES 2 and 5
20 VDDCR_GFX PHASES 6 and VDDCR_SOC
00 唐
21 MVDD_VDDCI CONTROLLER
22 REG MVDD
R
23 REG VDDCI
24 REG 0.75V
01 MA 浩
25 REG 1.8V
78 工健
9) 程 )
課
MICRO-STAR INT'L CO.,LTD
MSI MS-V381
Si ze Document Description Rev
Custom 5.0
TOC
Dat e: 2019_11_07 Sheet 1 of 35
(1) NAVI10 PCIe Edge Connector +3.3V_BUS
00
1
C101
0.1uF
6.3V
10%
2
1
M
R100
2
PLACE THESE CAPS AS CLOSE TO C100
0.1uF 10K
PCIE CONNECTOR AS POSSIBLE 6.3V 5%
10% U100
2
0R 3 5
A VCC
1 2
X 1 4
RD 05 SI
30,25 +1.8V_EN R103 5% PERST#_BUF 16,21,30,32
IN 6
B Y
2
OUT
C GND
+3.3V_BUS +3.3V_BUS
74AUP1G57GM
MPCIE1 U1A
DNI
+12V_BUS R1081 2 10K 5%
symbol 1
RESERVE FOR PCIE SLEW RATE
A2 A11 PERST# AV26 PERSTB
+12V PERST# R101 R102
X
1
2
A3 45.3K 45.3K
+12V
(C 36
1% 1%
C110 C118 C103 C104 B1 +12V Q100B R131 0R 5%
10uF 10uF 10uF 10uF B2 B5 SMCLK 6 1 0R 1 2 GPUSMCLK AW28 SMBCLK WAKEB AV27
16V 16V 16V 16V +12V SMCLK BSS138PS 5%
5
DNI
20%
DNI
20% 20% 20%
B3 +12V 1
R136 2
2
+3.3V_BUS
PX_EN_T
C
Q100A R132 0R 5%
X X A9 +3.3V
SMDAT B6 SMDATA 3
1
R137
4 0R
BSS138PS
2 X
5%
X
1 2 GPUSMDAT AV28 SMBDAT PX_EN AT37 R109 1 2 1K 1% PX_EN
OUT 30,32,33
1
A10 +3.3V PCIE_REFCLKP DNI

C105 C106 C107 C108 B8 +3.3V REFCLK+ A13
X
X
2 PCIE_REFCLKN BC22 PCIE_REFCLKP R150
ON
1K
)2 3
10uF 1uF 0.1uF 0.01uF A14 2 BB22 PCIE_REFCLKN 5%
6.3V 6.3V 10V 10V REFCLK-
10%
2
B10 3.3Vaux PCIE_RX0P
A4 GND
PETp0
PETn0
B14
B15
PCIE_RX0N
PCIE_RX1P
BE25
BD25
PCIE_RX0P
PCIE_RX0N
+3.3V_BUS
X
A12 GND PETp1 B19 PCIE_RX1N BG26 PCIE_RX1P
A15 GND PETn1 B20 BF26 PCIE_RX1N
F
A18
02
GND PCIE_RX2P
A20 GND PETp2 B23 PCIE_RX2N BE27 PCIE_RX2P R56
A23 B24 BD27 PCIE_RX2N 10K
GND PETn2 5%
A24 GND PCIE_RX3P CLKREQ#_PCIE
I
CLKREQ# R55
A27 B27 BG28 AW26 2 1
w
GND PETp3 PCIE_RX3N PCIE_RX3P CLKREQB 2
A28
A31
GND
GND
PETn3 B28
PCIE_RX4P
BF28 PCIE_RX3N
X 5% 0R
A34 GND PETp4 B33 PCIE_RX4N BE29 PCIE_RX4P

X
劉 00 ei DE
T hese termination should be as short as possible, neve exceed 500mil A37 GND PETn4 B34 BD29 PCIE_RX4N
A38 GND PCIE_RX5P
CLKREQ#_PCIE A41 GND PETp5 B37 PCIE_RX5N BG30 PCIE_RX5P
R4210 1 242.2R 1%C4200 1 21pF 2 B12 A42 GND PETn5 B38 BF30 PCIE_RX5N
50V PCIE_REFCLKP A45 GND PCIE_RX6P

R4211 1 242.2R 1%C4201 1 0.25pF
21pF 2 A13 A46 GND PETp6 B41 PCIE_RX6N BE31 PCIE_RX6P
50V PCIE_REFCLKN A49 GND PETn6 B42 BD31 PCIE_RX6N
R4212 1 242.2R 1%C4202 1 0.25pF

21pF 2 A14 A51 GND PCIE_RX7P
A54 B45 BG32
巍 52 st NT
50V RSVD_A19 GND PETp7 PCIE_RX7N PCIE_RX7P
R4213 1 242.2R 1%C4203 1 0.25pF

21pF 2 A19 A55 GND PETn7 B46 BF32 PCIE_RX7N
50V A58 GND PCIE_RX8P

R4214 1 242.2R 1%C4204 1 21pF PWRBRK# B30 A59 B50 BE34 PCIE_RX8P
0.25pF 2 GND PETp8 PCIE_RX8N
50V PRSNT2_B31 A62 GND PETn8 B51 BD34 PCIE_RX8N
R4215 1 242.2R 1%C4205 1 0.25pF

21pF 2 B31 A63 GND PCIE_RX9P
50V RSVD_A32 A66 GND PETp9 B54 PCIE_RX9N BG35 PCIE_RX9P
R4216 1 242.2R 1%C4206 1 0.25pF 21pF 2 A32 A67 GND PETn9 B55 BF35 PCIE_RX9N
A70
00 an IA
50V RSVD_A33 GND PCIE_RX10P
R4217 1 242.2R 1%C4207 1 0.25pF 21pF 2 A33 A71 GND PETp10 B58 PCIE_RX10N BE36 PCIE_RX10P
50V PRSNT2_B48 A74 GND PETn10 B59 BD36 PCIE_RX10N
R4218 1 242.2R 1%C4208 1 0.25pF 21pF 2 B48 A75 GND PCIE_RX11P

50V RSVD_A50 A78 GND PETp11 B62 PCIE_RX11N BG37 PCIE_RX11P
R4219 1 242.2R 1%C4209 1 0.25pF 21pF 2 A50 A79 GND PETn11 B63 BF37 PCIE_RX11N
50V A82 GND PCIE_RX12P

R4220 1 242.2R 1%C4210 1 21pF PRESENCE B81 B4 B66 BE38 PCIE_RX12P
0.25pF 2 GND PETp12 PCIE_RX12N
50V RSVD_B82 B7 GND PETn12 B67 BD38 PCIE_RX12N
g( L
1 242.2R 1 21pF B13
(3 2
R4221 1%C4211 0.25pF 2 B82 GND SCHEMATIC PCIE_RX13P
50V PRSNT2_B17 B16 GND PETp13 B70 PCIE_RX13N BG40 PCIE_RX13P
R4222 1 242.2R 1%C4212 1 0.25pF 21pF 2 B17 B18 GND PETn13 B71 BF40 PCIE_RX13N
50V B21 GND PCIE_RX14P

0.25pF
B22 GND PETp14 B74 PCIE_RX14N BE41 PCIE_RX14P
B25 GND PETn14 B75 BD41 PCIE_RX14N

B26 GND PCIE_RX15P
B29 GND PETp15 B78 PCIE_RX15N BG42 PCIE_RX15P
唐
B32 GND PETn15 B79 BF42 PCIE_RX15N
00
B35 GND
B36 GND PCIE_TX0P
B39 A16 PERP0 C125 1 2
0.22uF 25V BA23 PCIE_TX0P
GND PERp0 PCIE_TX0N
B40 A17 PERN0 C126 1 2
0.22uF 25V AY23 PCIE_TX0N
GND PERn0
R
B43 GND PCIE_TX1P
B44 A21 PERP1 C127 1 2
0.22uF 25V BC24 PCIE_TX1P
GND PERp1 PCIE_TX1N
B47 A22 PERN1 C128 1 2
0.22uF 25V BB24 PCIE_TX1N
GND PERn1
B49
01 MA 浩
GND PCIE_TX2P
B52 A25 PERP2 C133 1 2
GND PERp2 PCIE_TX2N
B53 A26 PERN2 C134 1 2
GND PERn2
B56 GND PCIE_TX3P
B57 A29 PERP3 C135 1 2
GND PERp3 PCIE_TX3N
B60 Mechanical Key A30 PERN3 C136 1 2
GND PERn3
B61 GND PCIE_TX4P
B64 A35 PERP4 C137 1 2
GND PERp4 PCIE_TX4N
B65 A36 PERN4 C138 1 2
GND PERn4
78 工健
B68 GND PCIE_TX5P
B69 A39 PERP5 C139 1 2
GND PERp5 PCIE_TX5N
B72 A40 PERN5 C140 1 2
GND PERn5 SYMBOL LEGEND
B73 GND PCIE_TX6P
B76 A43 PERP6 C141 1 2
0.22uF 25V BA29 PCIE_TX6P DN I DO NOT
GND PERp6 PCIE_TX6N 2mA max current
B77 A44 PERN6 C142 1 2
0.22uF 25V AY29 PCIE_TX6N INSTAL L
GND PERn6
B80 GND PCIE_TX7P
A47 PERP7 C143 1 2
0.22uF 25V BC30 PCIE_TX7P b or # ACT I V E
PERp7 PCIE_TX7N
9) 程 )
A48 PERN7 C144 1 2
0.22uF 25V BB30 PCIE_TX7N L OW
PERn7 PCIE_ZVSS
R155
B9 JTAG1 PCIE_TX8P PCIE_ZVSS AY19 1 2
A5 A52 PERP8 C145 1 2
0.22uF 25V BA31 PCIE_TX8P BU O BRING UP
JTAGIO_LOOP JTAG2 PERp8 PCIE_TX8N 200R 1%
A6 A53 PERN8 C146 1 2
0.22uF 25V AY31 PCIE_TX8N ON LY
JTAG3 PERn8
A7 JTAG4 PCIE_TX9P Should minimize the wire
A8 A56 PERP9 C147 1 2
0.22uF 25V BC32 PCIE_TX9P DIGITA L
JTAG5 PERp9 PCIE_TX9N resistance and parasitic
A57 PERN9 C148 1 2
0.22uF 25V BB32 PCIE_TX9N GR OU N D
PERn9 capacitance from external board
PCIE_TX10P device to internal bump.
+3.3V_BUS PRESENCE A1 A60 PERP10 1 2 BA34
課
2 PRSNT2_B17 C149 0.22uF 25V PCIE_TX10N PCIE_TX10P ANAL OG
PRSNT1# PERp10
B17 A61 PERN10 C150 1 2
0.22uF 25V AY34 PCIE_TX10N GR OU N D
2 PRSNT2_B31 PRSNT2#_B17 PERn10 - total trace resistance < 1 ohm
2 PRSNT2_B48 B31 PRSNT2#_B31 PCIE_TX11P - total parasitic capacitance < 10pF
B48 A64 PERP11 C151 1 2
2 PRSNT2#_B48 PERp11 PCIE_TX11N
B81 A65 PERN11 C152 1 2
PRSNT2#_B81 PERn11
R122 PCIE_TX12P
100K A68 PERP12 C153 1 2
5% PERp12 PCIE_TX12N
B11 A69 PERN12 C154 1 2
CLKREQ#_PCIE WAKE# PERn12
2 B12 CLKREQ# PCIE_TX13P
32 GPU_PWRBRK# 1
R121 2 0R2 5%PWRBRK# B30 PWRBRK# PERp13 A72 PERP13 C155 1 2
0.22uF 25V PCIE_TX13N BC37 PCIE_TX13P
OUT A73 PERN13 1 2 BB37
PERn13 C156 0.22uF 25V PCIE_TX13N
RSVD_A19 PCIE_TX14P
X 2
2
RSVD_A32
RSVD_A33
A19
A32
A33
RSVD_A19
RSVD_A32
PERp14
PERn14
A76
A77
PERP14
PERN14
C157 1 2
0.22uF 25V
C158 1 2
0.22uF 25V
PCIE_TX14N BA38
AY38
PCIE_TX14P
PCIE_TX14N
2 RSVD_A50 RSVD_A33 PCIE_TX15P

A50 A80 PERP15 C159 1 2
2 RSVD_B82 RSVD_A50 PERp15 PCIE_TX15N
B82 A81 PERN15 C160 1 2
2 RSVD_B82 PERn15
Navi10 REV 0.91

x16 GEN4 PCIe
X
MSI MS-V381
Custom 5.0
NAVI10 PCIe Interface
Dat e: 2019_11_07 Sheet 2 of 35
00 3
GPIO_5_REG_HOT
0R2
0R2
X
1
R38
1
DNI
R39
VDDGFX_SOC_REG_HOT
MVDD_VDDCI_OCP#
IN
IN
16
21
2 M
DNI
0R2 1
R40 MVDD_VDDCI_REG_HOT 23
IN
U1B
RD 05 SI
3 PINSTRAP_0 AW22 PINSTRAP_0 symbol 2 GPIO_0 AU29
OUT
3 PINSTRAP_1 AV22 PINSTRAP_1 GPIO_1 AT30
OUT AV23 AT29
3 PINSTRAP_2 PINSTRAP_2 GPIO_2
OUT
3 PINSTRAP_3 AW24 PINSTRAP_3 GPIO_3 AR30
OUT
3 PINSTRAP_4 AV24 PINSTRAP_4 GPIO_4 AU31 GPIO_4_PCC 16 VDDCR_SOC & VDDCR_MEM PCC (High)
OUT AV25 AT31
IN
3 PINSTRAP_5 PINSTRAP_5 GPIO_5 GPIO_5_REG_HOT 3 VR HOT
OUT IN
3 PINSTRAP_6 AU25 PINSTRAP_6 GPIO_6 AU32 GPIO_7_ROMSCK USB POWER DETECT
OUT AU26 AU35
3 PINSTRAP_7 PINSTRAP_7 GPIO_7_ROMSCK GPIO_8_ROMSI 3 ROM Control; ROMSCK
(C 36
OUT
GPIO_8_ROMSI AR32 GPIO_9_ROMSO 3 ROM Control; ROMSI
GPIO_9_ROMSO AU34 GPIO_10_ROMCS# 3 ROM Control; ROMSO
GPIO_10_ROMCSB AT34 GPIO_11 3 ROM COntrol; ROMSCB / Pinstrap Note: Internal PU/PD at GPIO pad is ~40k
GPIO_11 AV31 GPIO_12 strength in 14nm design spec
C
3 Pinstr ap
GPIO_12 AW30 GPIO_13 3 Pinstr ap
GPIO_13 AV30 3 Pinstr ap
Internal
GPIO_14 AT32 GPIO_15 +1.8V +3.3V_BUS
Default
GPIO_15 AW32 3 Pinstr ap
User Va l u e Definition
)2 3 ON
GPIO_16 AV32 GPIO_16 3 Pinstr ap
AV34
OUT
GPIO_17 GPIO_17 3 Pinstr ap PINSTRAP_6
OUT STRAP_BIF_GEN4_DIS_A
GPIO_18
GPIO_19
GPIO_20
AW35
AV35
AV36
GPIO_18
GPIO_19
3
OUT 3 Pinstr ap
Pinstr ap 1
X
MR60 210K
1
R60
X 210K 3
0 0: PCIe GEN 4 supported
1: PCIe GEN 4 not supported
PINSTRAP_7
PINSTRAP_BIF_CLK_PM_EN
1
R61
X 210K 3
F
0
1
X
MR61 210K
02
0: CLKREQ# power management capability is disabled
1: CLKREQ# power management capability is enabled
BIF
GPIO_13
PINSTRAP_BIF_LC_TX_SW ING
I
BA20 1
X 210K
w
GENERICA R62 3
0
X
AW13 GENERICB GPIO_SVC0 AT25 SVC0 0R2 1 R42 SVC_GFX_SOC 1
MR62 210K
16
AT24 SVD0 OUT
GPIO_SVD0 0R2 1 R43 SVD_GFX_SOC 16
AY11 AU24 SVT0 OUT
15 HPD1 HPD1 GPIO_SVT0 0R2 1 R41 SVT_GFX_SOC 16
IN IN
劉 00 ei DE
15 GENERICC_HPD2 AY12 GENERICC_HPD2 GPIO_15
IN Overlap pads PINSTRAP_BIF_VGA_DIS
14
IN
GENERICE_HPD4
AY13
BA13
BA16
GENERICD_HPD3
GENERICE_HPD4
GENERICF_HPD5
1
R58
X 210K 1
MR58 210K 1
X
MR63 210K
1
R63
X 210K 3
0 0: VGA controller capacity enabled
1: The device won't be recognised as the system's VGA controller
+3.3V_BUS
13
IN
GENERICG_HPD6 AY17 GENERICG_HPD6 1
R59 210K 1
MR59
X 210K +1.8V
PINSTRAP_5
0 PINSTRAP_AUD_PORT_CONN[2:0]
X
GPIO_SVC1 AT23 SVC1 0R2 1 R49 SVC_MVDD_VDDCI 1
R64 210K
31 3
OUT
X
2 10K 1 GPIO_SVD1 AR24 SVD1 0R2 1 R52 SVD_MVDD_VDDCI 1
MR64 210K
R51 31
2 1 AR23 SVT1 OUT Number of audio-capable display outputs
0R2 1
巍 52 st NT
10K R50 GPIO_SVT1 R53 SVT_MVDD_VDDCI 31 PINSTRAP_4
IN 0
X
REGULATOR_SCL 1 2 0R SCL AU28 SCL 1
R65 210K
16,21,33 R30 3
OUT
X
REGULATOR_SDA 1 2 0R SDA AV29 SDA 1
MR65 210K
21,33,16 R31 0: All endpoints connected 4: 3 endpoints connected
BI
PINSTRAP_3 1: 6 endpoints connected 5: 2 endpoints connected
0
X
DCE
1
R66 210K 3 2: 5 endpoints connected 6: 1 endpoint connected
+1.8V
BE43
BG45
DDCVGACLK
DDCVGADATA
1
X
MR66 210K 3: 4 endpoints connected 7: 0 endpoints connected
SWAPLOCKA AV13
00 an IA
GPIO_12
SWAPLOCKB AV12 1
R67 210K 3
0 PINSTRAP_AUD[1:0]
X
+1.8V +1.8V 1
MR67 210K
R4093 GENLK_CLK AW11 GPIO_11 1: Audio for DisplayPort only
1K GENLK_VSYNC AW12 1
R68 210K 3
0 2: Audio for DisplayPort and HDMI if dongle is detected
R4096
1K
R4092
1K 0R2 1 R11
AT19
AT35
TEST_PG_S5
PS_EN
BL_ENABLE
BL_PWM_DIM
AP10
AP11
1
X
MR68 210K 3: Audio for DisplayPort and native HDMI
DIGON AM11 GPIO_18
g( L
0
1
X 210K
(3 2
TEST_PG SVI2 BOOT UP VOLTAGE (VDDGFX/VDDC) R69 3
Platform
TEST_PG_BACO AR14 TEST_PG 1
MR69 210K
AR18 TEST_PG_BACO BAMACO_EN AR38 BAMACO_EN 30,31 SVC SVD VOLTA G E GPIO_17
OUT 0
Navi10 REV 0.91
R19
DNI
0 0 1.1V 1
X
MR70 210K
1
R70
X 210K 3
X 1K 0
1
1
0
1.0V
0.9V 1
R71 210K
GPIO_16
3
0
1 1 0.8V 1
X
MR71 210K
00 唐
PINSTRAP_2
1
1
X
MR72 210K
1
R72
X 210K 3
R
PINSTRAP_1
0
1
X
MR73 210K
1
R73
X 210K 3
01 MA 浩
PINSTRAP_0
1
1
X
MR74 210K
1
R74
X 210K 3
GPIO_19
PINSTRAP_SMBUS_ADDR
1
R75
X 210K 3
SMU
1
X
MR75 210K 0: 0x41h
1: 0x40h
78 工健
+3.3V_BUS +3.3V_BUS Unprotected FLASH
U3 BIOS1
GPIO_10_ROMCS#
GPIO_9_ROMSO GPIO_9_ROMSO_R 3 WP VDD 8 1
R76 210K 3
PINSTRAP_BIOS_ROM_EN
1
3 GPIO_8_ROMSI RP1B 2 7 33R GPIO_8_ROMSI_R 2 SO HOLD
7
BIOS
X 1
X
MR76 210K 0: Disable the external BIOS ROM device
1
3 GPIO_7_ROMSCK RP1A 1 8 33R GPIO_7_ROMSCK_R 5 SI 1: Enable the external BIOS ROM device
3 GPIO_10_ROMCS# RP1C 3 6 33R GPIO_10_ROMCS#_R 6 SCK C7
RP1D 4 5 33R 1 4 0.1uF
3 CE GND 10V
SCHEMATIC
2
9) 程 )
GD25Q80C
課
MSI MS-V381
Custom 5.0
NAVI10 GPIOs
Dat e: 2019_11_07 Sheet 3 of 35
00
2
RD 05 SI M
(C 36 C
)2 3 ON
02 w F I
劉 00 ei DE
100MHz oscilator option
+1.8V
巍 52 st NT
Y2
100.00000 MHZ
B33 OSC_VDD18
1 2 4 4 2
1
120R VDD GND
C61 C62 C63 3 1 1

R48 2 1K 5%
25%
10uF 0.1uF 2.2uF CLK NC
6.3V 6.3V
10%
6.3V
2
00 an IA
U1E
MY2
OSC_VDD18 OSC_100M
symbol 5 4 4 3 4
MR46 OSC_100M VDD OUT
XTALIN BG24 XTALIN 1 220R 1% 4
1 2
OE GND
NA
XTALOUT BF24 OVERLAP WITH Y2
g( L
+1.8V (Verify rail)
(3 2
100MHz 1.8V CLK chip
R86 1 2 2.2K 1% XTRIG6 AP24 XTRIG6
R85 1 2 2.2K 1% XTRIG7 AP22 XTRIG7
PLLCHARZ1_H
XTRIG* are for debug purpose PLLCHARZ1_H AP38
PLLCHARZ1_L
PLLCHARZ1_L AP37
+3.3V_BUS (Verify rail)
唐
OSC_GAIN2
00
R95 1 2 10K 5% OSC_GAIN1 AV14 OSC_GAIN2
R94 1 2 10K 5% OSC_GAIN0 AW14 OSC_GAIN1
R93 1 2 10K 5% AY14 OSC_GAIN0 ANALOGIO AU14 ANALOGIO 1

R47 216.2K 1%
Navi10 REV 0.91
DNI
R
OSC_GAIN[2:0] = 3'd6
on Production Board
01 MA 浩 Route 50 ohms single-ended/100 ohms diff
78 工健
and keep short
1
C13 2
0.1uF 6.3V 1
R13 251.1R 1%
1
C14 10% 2
0.1uF 6.3V 1
R17 251.1R 1%
10%
9) 程 )
課
MSI MS-V381
Custom 5.0
NAVI10 XTAL
Dat e: 2019_11_07 Sheet 4 of 35
00
NAVI 10 MEM INTERFACE CH A/B
2
RD 05 SI M
(C 36 C
)2 3 ON
U1L U1M
9,5 DQA0_[0..15] DQA0_0 symbol 12 9 DQA1_0 DQA1_[0..15] 9,5 9,5 DQB0_[0..15] DQB0_0 symbol 13 DQB1_0 DQB1_[0..15] 9,5
BI BI BI BI
9 5 0 DQA0_1 BB47 DQA0_0 DQA1_0 BB43 5 DQA1_1 0 9 5 0 DQB0_1 AH45 DQB0_0 DQB1_0 AH41 9 5 DQB1_1 0
9 5 1 DQA0_2 BA44 DQA0_1 DQA1_15
9 BB45 DQA1_2 1 9 5 1 DQB0_2 AG44 DQB0_1 DQB1_1 AG40 9 5 DQB1_2 1
9 5 2 DQA0_3 BA46 DQA0_2 DQA1_25
9 BA42 DQA1_3 2 9 5 2 DQB0_3 AG46 DQB0_2 DQB1_2 AG42 9 5 DQB1_3 2
9 5 3 DQA0_4 AY47 DQA0_3 DQA1_35
9 AY41 DQA1_4 3 9 5 3 DQB0_4 AF47 DQB0_3 DQB1_3 AF43 9 5 DQB1_4 3
F
9 5 4 AV46 DQA1_45
9 AV40 4 9 5 4 AE46 AE40 9 5 4
02
DQA0_5 DQA0_4 DQA1_5 DQB0_5 DQB0_4 DQB1_4 DQB1_5
9 5 5 DQA0_6 AU47 DQA0_5 DQA1_55
9 AU43 DQA1_6 5 9 5 5 DQB0_6 AD45 DQB0_5 DQB1_5 AD43 9 5 DQB1_6 5
9 5 6 DQA0_7 AU45 DQA0_6 DQA1_65
9 AU41 DQA1_7 6 9 5 6 DQB0_7 AD47 DQB0_6 DQB1_6 AD41 9 5 DQB1_7 6
9 5 7 DQA0_8 AT44 DQA0_7 DQA1_75
9 AT40 DQA1_8 7 9 5 7 DQB0_8 AC46 DQB0_7 DQB1_7 AC40 9 5 DQB1_8 7
I
AP46 AP40 AA44 AA40
w
9 5 8 DQA0_9 DQA0_8 DQA1_85
9 DQA1_9 8 9 5 8 DQB0_9 DQB0_8 DQB1_8 9 5 DQB1_9 8
9 5 9 DQA0_10 AM47 DQA0_9 DQA1_95
9 AM43 DQA1_10 9 9 5 9 DQB0_10 Y45 DQB0_9 DQB1_9 Y43 9 5 DQB1_10 9
9 5 10 DQA0_11 AM45 DQA0_10 DQA1_105
9 AM41 DQA1_11 10 9 5 10 DQB0_11 Y47 DQB0_10 DQB1_10 Y41 9 5 DQB1_11 10
9 5 11 DQA0_12 AL44 DQA0_11 DQA1_115
9 AL42 DQA1_12 11 9 5 11 DQB0_12 W46 DQB0_11 DQB1_11 W42 9 5 DQB1_12 11
劉 00 ei DE
9 5 12 DQA0_13 AK45 DQA0_12 DQA1_125
9 AK41 DQA1_13 12 9 5 12 DQB0_13 V47 DQB0_12 DQB1_12 V41 9 5 DQB1_13 12
9 5 13 DQA0_14 AJ44 DQA0_13 DQA1_135
9 AJ42 DQA1_14 13 9 5 13 DQB0_14 U46 DQB0_13 DQB1_13 U42 9 5 DQB1_14 13
9 5 14 DQA0_15 AJ46 DQA0_14 DQA1_145
9 AJ40 DQA1_15 14 9 5 14 DQB0_15 U44 DQB0_14 DQB1_14 U40 9 5 DQB1_15 14
9 5 15 AH47 DQA0_15 DQA1_155
9 AH43 15 9 5 15 T45 DQB0_15 DQB1_15 T43 9 5 15
5,9 CAA0_[0..9] CAA0_0 9 CAA1_0 CAA1_[0..9] 5,9 5,9 CAB0_[0..9] CAB0_0 CAB1_0 CAB1_[0..9] 5,9
OUT 9 5 0 AL34 AL38 5 0
OUT OUT 9 5 0 AD35 AD39 9 5 0
OUT
CAA0_1 CAA0_0 CAA1_0 CAA1_1 CAB0_1 CAB0_0 CAB1_0 CAB1_1
9 5 1 CAA0_2 AF36 CAA0_1 5
9
CAA1_1 AE37 CAA1_2 1 9 5 1 CAB0_2 W34 CAB0_1 CAB1_1 V39 9 5 CAB1_2 1
9 5 2 CAA0_3 AK36 CAA0_2 5
9
CAA1_2 AL37 CAA1_3 2 9 5 2 CAB0_3 AC35 CAB0_2 CAB1_2 AD38 9 5 CAB1_3 2
AE34 AF39 V36 W37
巍 52 st NT
9 5 3 CAA0_4 CAA0_3 5
9
CAA1_3 CAA1_4 3 9 5 3 CAB0_4 CAB0_3 CAB1_3 9 5 CAB1_4 3
9 5 4 CAA0_5 AK35 CAA0_4 5
9
CAA1_4 AJ38 CAA1_5 4 9 5 4 CAB0_5 AC34 CAB0_4 CAB1_4 AB39 9 5 CAB1_5 4
9 5 5 CAA0_6 AG35 CAA0_5 5
9
CAA1_5 AG37 CAA1_6 5 9 5 5 CAB0_6 Y35 CAB0_5 CAB1_5 Y39 9 5 CAB1_6 5
9 5 6 CAA0_7 AE35 CAA0_6 5
9
CAA1_6 AF38 CAA1_7 6 9 5 6 CAB0_7 V35 CAB0_6 CAB1_6 W38 9 5 CAB1_7 6
9 5 7 CAA0_8 AG34 CAA0_7 5
9
CAA1_7 AG38 CAA1_8 7 9 5 7 CAB0_8 Y36 CAB0_7 CAB1_7 Y38 9 5 CAB1_8 7
9 5 8 CAA0_9 AJ35 CAA0_8 5
9
CAA1_8 AJ37 CAA1_9 8 9 5 8 CAB0_9 AB36 CAB0_8 CAB1_8 AB38 9 5 CAB1_9 8
9 5 9 AL35 CAA0_9 5
9
CAA1_9 AK38 9 9 5 9 AD36 CAB0_9 CAB1_9 AC37 9 5 9
WCKA0_0 AR47 WCKA0_0 WCKA1_0 AR43 WCKA1_0
00 an IA
9 BI BI 9
9 WCKA0B_0 AT46 WCKA0B_0 WCKA1B_0 AT42 WCKA1B_0 9 9 WCKB0_0 AB45 WCKB0_0 WCKB1_0 AB43 WCKB1_0 9
BI BI BI BI
9 WCKB0B_0 AC44 WCKB0B_0 WCKB1B_0 AC42 WCKB1B_0 9
BI BI
9 WCKA0_1 AR45 WCKA0_1 WCKA1_1 AR41 WCKA1_1 9
BI BI
9 WCKA0B_1 AP44 WCKA0B_1 WCKA1B_1 AP42 WCKA1B_1 9 9 WCKB0_1 AB47 WCKB0_1 WCKB1_1 AB41 WCKB1_1 9
BI BI BI BI
9 WCKB0B_1 AA46 WCKB0B_1 WCKB1B_1 AA42 WCKB1B_1 9
BI BI
9 EDCA0_0 AV44 EDCA0_0 EDCA1_0 AY43 EDCA1_0 9
BI BI
9 EDCA0_1 AL46 EDCA0_1 EDCA1_1 AK43 EDCA1_1 9 9 EDCB0_0 AE44 EDCB0_0 EDCB1_0 AF41 EDCB1_0 9
BI BI BI BI
9 EDCB0_1 W44 EDCB0_1 EDCB1_1 V43 EDCB1_1 9
g( L
BI BI
AY45 AV42
(3 2
9 DBIA0_0 DBIA0_0 DBIA1_0 DBIA1_0 9
BI BI
9 DBIA0_1 AK47 DBIA0_1 DBIA1_1 AL40 DBIA1_1 9 9 DBIB0_0 AF45 DBIB0_0 DBIB1_0 AE42 DBIB1_0 9
BI BI BI BI
9 DBIB0_1 V45 DBIB0_1 DBIB1_1 W40 DBIB1_1 9
BI BI
9 CABIA0 AJ34 CABIA0 CABIA1 AK39 CABIA1 9
OUT OUT AB35 AC38
9 CABIB0 CABIB0 CABIB1 CABIB1 9
OUT OUT
9 CKEA0 AF35 CKEA0 CKEA1 AH39 CKEA1 9
OUT OUT W35 AA38
9 CKEB0 CKEB0 CKEB1 CKEB1 9
AH36
OUT OUT
9 CKA CKA
OUT
唐
9 CKAB AH35 CKAB 9 CKB AA35 CKB
OUT OUT
00
9 CKBB AA36 CKBB
OUT
R
R3601 49.9R 1% R3602 10R 1% DRAM_RSTA R3611 49.9R 1% R3610 10R 1% DRAM_RSTB
DRAM_RSTB_A 2 1 2 1 AM39 DRAM_RSTB_B 2 1 2 1 AE38
01 MA 浩
9 DRAM_RSTA 9 DRAM_RSTB
OUT OUT
1
1
C3600 R3603 C3603 R3607
120pF 5.1K Navi10 REV 0.91 120pF 5.1K Navi10 REV 0.91
50V
5%
1% 50V
5%
1%
2
2
78 工健
9) 程 )
課
MSI MS-V381
Custom NAVI10 MEM CHAB 5.0
Dat e: 2019_11_07 Sheet 5 of 35

NAVI 10 MEM INTERFACE CH C/D
00
2
RD 05 SI M
(C 36 C U1O
)2 3 ON
U1N DQD0_[0..15] symbol 15 DQD1_[0..15]
10,6 DQD0_0 10 DQD1_0 10,6
BI BI
10,6 DQC0_[0..15] DQC0_0 symbol 14 10 DQC1_0
DQC1_[0..15] 10,6 10 6 0 DQD0_1 C42 DQD0_0 DQD1_0 H36 6 DQD1_1 0
BI BI
10 6 0 DQC0_1 T47 DQC0_0 DQC1_0 T41 6 DQC1_1 0 10 6 1 DQD0_2 D41 DQD0_1 6
10
DQD1_1 E35 DQD1_2 1
10 6 1 DQC0_2 P46 DQC0_1 DQC1_16
10 P42 DQC1_2 1 10 6 2 DQD0_3 B41 DQD0_2 6
10
DQD1_2 G35 DQD1_3 2
10 6 2 DQC0_3 P44 DQC0_2 DQC1_26
10 P40 DQC1_3 2 10 6 3 DQD0_4 A40 DQD0_3 6
10
DQD1_3 F34 DQD1_4 3
10 6 3 DQC0_4 N45 DQC0_3 DQC1_36
10 N43 DQC1_4 3 10 6 4 DQD0_5 B38 DQD0_4 6
10
DQD1_4 G32 DQD1_5 4
10 6 4 DQC0_5 M44 DQC0_4 DQC1_46
10 M40 DQC1_5 4 10 6 5 DQD0_6 A37 DQD0_5 6
10
DQD1_5 H31 DQD1_6 5
10 6 5 DQC0_6 L45 DQC0_5 DQC1_56
10 L43 DQC1_6 5 10 6 6 DQD0_7 C37 DQD0_6 6
10
DQD1_6 F31 DQD1_7 6
F
10 6 6 L47 DQC1_66
10 L41 6 10 6 7 D36 6
10 E30 7
02
DQC0_7 DQC0_6 DQC1_7 DQD0_8 DQD0_7 DQD1_7 DQD1_8
10 6 7 DQC0_8 K46 DQC0_7 DQC1_76
10 K40 DQC1_8 7 10 6 8 DQD0_9 B34 DQD0_8 6
10
DQD1_8 E28 DQD1_9 8
10 6 8 DQC0_9 G44 DQC0_8 DQC1_86
10 F43 DQC1_9 8 10 6 9 DQD0_10 A32 DQD0_9 6
10
DQD1_9 C28 DQD1_10 9
10 6 9 DQC0_10 F45 DQC0_9 DQC1_96
10 E42 DQC1_10 9 10 6 10 DQD0_11 C32 DQD0_10 6
10
DQD1_10 D27 DQD1_11 10
I
F47 F41 D31 H27
w
10 6 10 DQC0_11 DQC0_10 DQC1_106
10 DQC1_11 10 10 6 11 DQD0_12 DQD0_11 6
10
DQD1_11 DQD1_12 11
10 6 11 DQC0_12 E46 DQC0_11 DQC1_116
10 G40 DQC1_12 11 10 6 12 DQD0_13 C30 DQD0_12 6
10
DQD1_12 G26 DQD1_13 12
10 6 12 DQC0_13 B46 DQC0_12 DQC1_126
10 H38 DQC1_13 12 10 6 13 DQD0_14 D29 DQD0_13 6
10
DQD1_13 E26 DQD1_14 13
10 6 13 DQC0_14 A45 DQC0_13 DQC1_136
10 E37 DQC1_14 13 10 6 14 DQD0_15 B29 DQD0_14 6
10
DQD1_14 C26 DQD1_15 14
劉 00 ei DE
10 6 14 DQC0_15 B43 DQC0_14 DQC1_146
10 G37 DQC1_15 14 10 6 15 A28 DQD0_15 6
10
DQD1_15 A26 15
10 6 15 A42 DQC0_15 DQC1_156
10 F36 15 6,10 CAD0_[0..9] CAD0_0 10 CAD1_0
CAD1_[0..9] 6,10
OUT M32 K31
OUT
CAC0_[0..9] CAC0_0 CAC1_[0..9] 10 6 0 CAD0_0 CAD1_0 6 CAD1_1 0
6,10
OUT 10 CAC1_0 OUT 6,10 CAD0_1
10 6 0 CAC0_1 U34 CAC0_0 CAC1_0 U38 6 CAC1_1 0 10 6 1 CAD0_2 P27 CAD0_1 6
10
CAD1_1 K26 CAD1_2 1
10 6 1 CAC0_2 L36 CAC0_1 CAC1_16
10 K34 CAC1_2 1 10 6 2 CAD0_3 P31 CAD0_2 6
10
CAD1_2 L31 CAD1_3 2
10 6 2 CAC0_3 T36 CAC0_2 CAC1_26
10 U37 CAC1_3 2 10 6 3 CAD0_4 M26 CAD0_3 6
10
CAD1_3 J26 CAD1_4 3
10 6 3 CAC0_4 J37 CAC0_3 CAC1_36
10 L34 CAC1_4 3 10 6 4 CAD0_5 N31 CAD0_4 6
10
CAD1_4 K29 CAD1_5 4
10 6 4 CAC0_5 T35 CAC0_4 CAC1_46
10 N39 CAC1_5 4 10 6 5 CAD0_6 N28 CAD0_5 6
10
CAD1_5 K28 CAD1_6 5
M37 N34 N26 L27
巍 52 st NT
10 6 5 CAC0_6 CAC0_5 CAC1_56
10 CAC1_6 5 10 6 6 CAD0_7 CAD0_6 6
10
CAD1_6 CAD1_7 6
10 6 6 CAC0_7 K36 CAC0_6 CAC1_66
10 J35 CAC1_7 6 10 6 7 CAD0_8 M28 CAD0_7 6
10
CAD1_7 K27 CAD1_8 7
10 6 7 CAC0_8 M38 CAC0_7 CAC1_76
10 K35 CAC1_8 7 10 6 8 CAD0_9 N30 CAD0_8 6
10
CAD1_8 L29 CAD1_9 8
10 6 8 CAC0_9 P37 CAC0_8 CAC1_86
10 P38 CAC1_9 8 10 6 9 N32 CAD0_9 6
10
CAD1_9 K30 9
10 6 9 U35 CAC0_9 CAC1_96
10 T38 9
10 WCKD0_0 A35 WCKD0_0 WCKD1_0 H29 WCKD1_0 10

BI BI
10 WCKC0_0 H45 WCKC0_0 WCKC1_0 H43 WCKC1_0 10 10 WCKD0B_0 B36 WCKD0B_0 WCKD1B_0 G30 WCKD1B_0 10
BI BI BI BI
10 WCKC0B_0 K44 WCKC0B_0 WCKC1B_0 K42 WCKC1B_0 10
BI BI
WCKD0_1 C35 WCKD0_1 WCKD1_1 F29 WCKD1_1
00 an IA
10 BI BI 10
10 WCKC0_1 H47 WCKC0_1 WCKC1_1 H41 WCKC1_1 10 10 WCKD0B_1 D34 WCKD0B_1 WCKD1B_1 G28 WCKD1B_1 10
BI BI BI BI
10 WCKC0B_1 G46 WCKC0B_1 WCKC1B_1 G42 WCKC1B_1 10
BI BI
10 EDCD0_0 D38 EDCD0_0 EDCD1_0 H34 EDCD1_0 10
BI BI
10 EDCC0_0 M46 EDCC0_0 EDCC1_0 N41 EDCC1_0 10 10 EDCD0_1 B31 EDCD0_1 EDCD1_1 B27 EDCD1_1 10
BI BI BI BI
10 EDCC0_1 C47 EDCC0_1 EDCC1_1 F38 EDCC1_1 10
BI BI
10 DBID0_0 C40 DBID0_0 DBID1_0 E32 DBID1_0 10
BI BI
10 DBIC0_0 N47 DBIC0_0 DBIC1_0 M42 DBIC1_0 10 10 DBID0_1 A30 DBID0_1 DBID1_1 F27 DBID1_1 10
BI BI BI BI
10 DBIC0_1 C45 DBIC0_1 DBIC1_1 E40 DBIC1_1 10
g( L
BI BI
M30 J30
(3 2
10 CABID0 CABID0 CABID1 CABID1 10
P35 T39
OUT OUT
10 CABIC0 CABIC0 CABIC1 CABIC1 10
OUT OUT N27 J28
10 CKED0 CKED0 CKED1 CKED1 10
OUT OUT
10 CKEC0 L39 CKEC0 CKEC1 M35 CKEC1 10
OUT OUT P29
10 CKD CKD
OUT
10 CKC N36 CKC 10 CKDB N29 CKDB
OUT N37 +VDD_MEM OUT
10 CKCB CKCB
OUT
唐
R3623 MEM_CALRC
00
1% 2
118R 1 W33 MEM_CALR_0
R3615
40.2R
1% R3618 49.9R 1% R3619 10R 1% DRAM_RSTD
R3612 1% 49.9R R3613 1% 10R DRAM_RSTC 10 DRAM_RSTB_D 2 1 2 1 J32 DRAM_RSTD
R
MVREFDC OUT
10 DRAM_RSTB_C 2 1 2 1 V38 DRAM_RSTC MVREFD_0 V33
OUT
1
1
1
C3606 R3620
120pF 5.1K
01 MA 浩
C3604 R3614 C3605 R3616 50V 1%
120pF 5.1K 1uF 100R 5% Navi10 REV 0.91
2
50V
5%
1% Navi10 REV 0.91 6.3V
10%
1%
2
78 工健
9) 程 )
課
20ci203T
MSI MS-V381
Custom 5.0
NAVI10 MEM CHCD
Dat e: 2019_11_07 Sheet 6 of 35
NAVI 10 MEM INTERFACE CH E/F
00
2
RD 05 SI M
(C 36 C ON
U1P
)2 3
U1Q
DQE0_[0..15] DQE0_0 symbol 16 DQE1_[0..15] DQF0_[0..15] symbol 17 DQF1_[0..15]
11,7 BI 11 DQE1_0 BI 11,7 11,7 BI DQF0_0 11 DQF1_0 BI 11,7
11 7 0 DQE0_1 A20 DQE0_0 DQE1_0 A22 7 DQE1_1 0 11 7 0 DQF0_1 A6 DQF0_0 DQF1_0 F12 7 DQF1_1 0
11 7 1 DQE0_2 B19 DQE0_1 7
11
DQE1_1 C22 DQE1_2 1 11 7 1 DQF0_2 B5 DQF0_1 7
11
DQF1_1 G11 DQF1_2 1
11 7 2 DQE0_3 D19 DQE0_2 7
11
DQE1_2 E22 DQE1_3 2 11 7 2 DQF0_3 A3 DQF0_2 7
11
DQF1_2 E11 DQF1_3 2
11 7 3 DQE0_4 C18 DQE0_3 7
11
DQE1_3 G22 DQE1_4 3 11 7 3 DQF0_4 B2 DQF0_3 7
11
DQF1_3 H10 DQF1_4 3
11 7 4 DQE0_5 D17 DQE0_4 7
11
DQE1_4 H21 DQE1_5 4 11 7 4 DQF0_5 E2 DQF0_4 7
11
DQF1_4 G8 DQF1_5 4
11 7 5 DQE0_6 C16 DQE0_5 7
11
DQE1_5 D21 DQE1_6 5 11 7 5 DQF0_6 F1 DQF0_5 7
11
DQF1_5 F7 DQF1_6 5
F
11 7 6 A16 7
11 C20 6 11 7 6 F3 7
11 E6 6
02
DQE0_7 DQE0_6 DQE1_6 DQE1_7 DQF0_7 DQF0_6 DQF1_6 DQF1_7
11 7 7 DQE0_8 B14 DQE0_7 7
11
DQE1_7 E20 DQE1_8 7 11 7 7 DQF0_8 G4 DQF0_7 7
11
DQF1_7 F5 DQF1_8 7
11 7 8 DQE0_9 D12 DQE0_8 7
11
DQE1_8 E18 DQE1_9 8 11 7 8 DQF0_9 K2 DQF0_8 7
11
DQF1_8 K8 DQF1_9 8
11 7 9 DQE0_10 C11 DQE0_9 7
11
DQE1_9 F17 DQE1_10 9 11 7 9 DQF0_10 L1 DQF0_9 7
11
DQF1_9 L7 DQF1_10 9
I
A11 H17 L3 L5
w
11 7 10 DQE0_11 DQE0_10 7
11
DQE1_10 DQE1_11 10 11 7 10 DQF0_11 DQF0_10 7
11
DQF1_10 DQF1_11 10
11 7 11 DQE0_12 B10 DQE0_11 7
11
DQE1_11 G16 DQE1_12 11 11 7 11 DQF0_12 M4 DQF0_11 7
11
DQF1_11 M8 DQF1_12 11
11 7 12 DQE0_13 A8 DQE0_12 7
11
DQE1_12 F14 DQE1_13 12 11 7 12 DQF0_13 N3 DQF0_12 7
11
DQF1_12 N5 DQF1_13 12
11 7 13 DQE0_14 B7 DQE0_13 7
11
DQE1_13 G13 DQE1_14 13 11 7 13 DQF0_14 P4 DQF0_13 7
11
DQF1_13 P8 DQF1_14 13
劉 00 ei DE
11 7 14 DQE0_15 D7 DQE0_14 7
11
DQE1_14 E13 DQE1_15 14 11 7 14 DQF0_15 P2 DQF0_14 7
11
DQF1_14 P6 DQF1_15 14
11 7 15 C6 DQE0_15 7
11
DQE1_15 H12 15 11 7 15 T1 DQF0_15 7
11
DQF1_15 T7 15
CAE0_[0..9] CAE0_0 CAE1_[0..9] CAF0_[0..9] CAF1_[0..9]

7,11
OUT 11 CAE1_0 OUT 7,11 7,11
OUT CAF0_0 11 CAF1_0 OUT 7,11
11 7 0 CAE0_1 M16 CAE0_0 CAE1_0 K17 7 CAE1_1 0 11 7 0 CAF0_1 U14 CAF0_0 CAF1_0 U10 7 CAF1_1 0
11 7 1 CAE0_2 P21 CAE0_1 7
11
CAE1_1 K22 CAE1_2 1 11 7 1 CAF0_2 L12 CAF0_1 7
11
CAF1_1 K14 CAF1_2 1
11 7 2 CAE0_3 P17 CAE0_2 7
11
CAE1_2 L17 CAE1_3 2 11 7 2 CAF0_3 T12 CAF0_2 7
11
CAF1_2 U11 CAF1_3 2
11 7 3 CAE0_4 M22 CAE0_3 7
11
CAE1_3 J22 CAE1_4 3 11 7 3 CAF0_4 J11 CAF0_3 7
11
CAF1_3 L14 CAF1_4 3
11 7 4 CAE0_5 N17 CAE0_4 7
11
CAE1_4 K19 CAE1_5 4 11 7 4 CAF0_5 T13 CAF0_4 7
11
CAF1_4 N9 CAF1_5 4
N20 K20 M11 N14
巍 52 st NT
11 7 5 CAE0_6 CAE0_5 7
11
CAE1_5 CAE1_6 5 11 7 5 CAF0_6 CAF0_5 7
11
CAF1_5 CAF1_6 5
11 7 6 CAE0_7 N22 CAE0_6 7
11
CAE1_6 L21 CAE1_7 6 11 7 6 CAF0_7 K12 CAF0_6 7
11
CAF1_6 J13 CAF1_7 6
11 7 7 CAE0_8 M20 CAE0_7 7
11
CAE1_7 K21 CAE1_8 7 11 7 7 CAF0_8 M10 CAF0_7 7
11
CAF1_7 K13 CAF1_8 7
11 7 8 CAE0_9 N18 CAE0_8 7
11
CAE1_8 L19 CAE1_9 8 11 7 8 CAF0_9 P11 CAF0_8 7
11
CAF1_8 P10 CAF1_9 8
11 7 9 N16 CAE0_9 7
11
CAE1_9 K18 9 11 7 9 U13 CAF0_9 7
11
CAF1_9 T10 9
11 WCKE0_0 C13 WCKE0_0 WCKE1_0 F19 WCKE1_0 11 11 WCKF0_0 H1 WCKF0_0 WCKF1_0 H7 WCKF1_0 11
BI BI BI BI
11 WCKE0B_0 D14 WCKE0B_0 WCKE1B_0 G20 WCKE1B_0 11 11 WCKF0B_0 G2 WCKF0B_0 WCKF1B_0 G6 WCKF1B_0 11
BI BI BI BI
00 an IA
11 WCKE0_1 A13 WCKE0_1 WCKE1_1 H19 WCKE1_1 11 11 WCKF0_1 H3 WCKF0_1 WCKF1_1 H5 WCKF1_1 11
BI BI BI BI
11 WCKE0B_1 B12 WCKE0B_1 WCKE1B_1 G18 WCKE1B_1 11 11 WCKF0B_1 K4 WCKF0B_1 WCKF1B_1 K6 WCKF1B_1 11
BI BI BI BI
11 EDCE0_0 B17 EDCE0_0 EDCE1_0 B21 EDCE1_0 11 11 EDCF0_0 C1 EDCF0_0 EDCF1_0 F10 EDCF1_0 11
BI BI BI BI
11 EDCE0_1 D10 EDCE0_1 EDCE1_1 H14 EDCE1_1 11 11 EDCF0_1 M2 EDCF0_1 EDCF1_1 N7 EDCF1_1 11
BI BI BI BI
11 DBIE0_0 A18 DBIE0_0 DBIE1_0 F21 DBIE1_0 11 11 DBIF0_0 C3 DBIF0_0 DBIF1_0 E8 DBIF1_0 11
BI BI BI BI
11 DBIE0_1 C8 DBIE0_1 DBIE1_1 E16 DBIE1_1 11 11 DBIF0_1 N1 DBIF0_1 DBIF1_1 M6 DBIF1_1 11
g( L
BI BI BI BI
(3 2
11 CABIE0 M18 CABIE0 CABIE1 J18 CABIE1 11 11 CABIF0 P13 CABIF0 CABIF1 T9 CABIF1 11
OUT OUT OUT OUT
11 CKEE0 N21 CKEE0 CKEE1 J20 CKEE1 11 11 CKEF0 L9 CKEF0 CKEF1 M13 CKEF1 11
OUT OUT OUT OUT
11 CKE P19 CKE 11 CKF N12 CKF

OUT N19
OUT N11 +VDD_MEM
11 CKEB CKEB 11 CKFB CKFB
OUT OUT
唐
R3630 MEM_CALRF
00
1% 2
118R 1 W15 MEM_CALR_1
R3634
40.2R
1%
R3625 49.9R 1% R3626 10R 1% DRAM_RSTE R3631 49.9R 1% R3632 10R 1% DRAM_RSTF
R
DRAM_RSTB_E 2 1 2 1 J16 DRAM_RSTE DRAM_RSTB_F 2 1 2 1 V10 DRAM_RSTF MVREFD_1 V15 MVREFDF
11 11
OUT OUT
1
1
01 MA 浩
C3608 R3627 C3610 R3633 C3611 R3635
120pF 5.1K 120pF 5.1K 1uF 100R
50V
5%
1% Navi10 REV 0.91 50V
5%
1% Navi10 REV 0.91 6.3V
10%
1%
2
2
78 工健
9) 程 )
課
MSI MS-V381
Custom 5.0
NAVI10 MEM CHEF
Dat e: 2019_11_07 Sheet 7 of 35
NAVI 10 MEM INTERFACE CH G/H
00
2
RD 05 SI M
(C 36 C
)2 3 ON
U1R
DQG0_[0..15] symbol 18 DQG1_[0..15] U1S
12,8 DQG0_0 12 DQG1_0 12,8
BI BI
12 8 0 DQG0_1 T3 DQG0_0 DQG1_0 T5 8 DQG1_1 0 12,8 DQH0_[0..15] DQH0_0 symbol 19 12 DQH1_0 DQH1_[0..15] 12,8
BI BI
12 8 1 DQG0_2 U4 DQG0_1 8
12
DQG1_1 U8 DQG1_2 1 12 8 0 DQH0_1 AH1 DQH0_0 DQH1_0 AH5 8 DQH1_1 0
12 8 2 DQG0_3 U2 DQG0_2 8
12
DQG1_2 U6 DQG1_3 2 12 8 1 DQH0_2 AJ2 DQH0_1 8
12
DQH1_1 AJ8 DQH1_2 1
12 8 3 DQG0_4 V1 DQG0_3 8
12
DQG1_3 V7 DQG1_4 3 12 8 2 DQH0_3 AJ4 DQH0_2 8
12
DQH1_2 AJ6 DQH1_3 2
F
12 8 4 W2 8
12 W6 4 12 8 3 AK3 8
12 AK7 3
02
DQG0_5 DQG0_4 DQG1_4 DQG1_5 DQH0_4 DQH0_3 DQH1_3 DQH1_4
12 8 5 DQG0_6 Y1 DQG0_5 8
12
DQG1_5 Y7 DQG1_6 5 12 8 4 DQH0_5 AL4 DQH0_4 8
12
DQH1_4 AL6 DQH1_5 4
12 8 6 DQG0_7 Y3 DQG0_6 8
12
DQG1_6 Y5 DQG1_7 6 12 8 5 DQH0_6 AM3 DQH0_5 8
12
DQH1_5 AM7 DQH1_6 5
12 8 7 DQG0_8 AA4 DQG0_7 8
12
DQG1_7 AA8 DQG1_8 7 12 8 6 DQH0_7 AM1 DQH0_6 8
12
DQH1_6 AM5 DQH1_7 6
I
AC2 AC8 AP2 AP8
w
12 8 8 DQG0_9 DQG0_8 8
12
DQG1_8 DQG1_9 8 12 8 7 DQH0_8 DQH0_7 8
12
DQH1_7 DQH1_8 7
12 8 9 DQG0_10 AD1 DQG0_9 8
12
DQG1_9 AD7 DQG1_10 9 12 8 8 DQH0_9 AT4 DQH0_8 8
12
DQH1_8 AT8 DQH1_9 8
12 8 10 DQG0_11 AD3 DQG0_10 8
12
DQG1_10 AD5 DQG1_11 10 12 8 9 DQH0_10 AU3 DQH0_9 8
12
DQH1_9 AU7 DQH1_10 9
12 8 11 DQG0_12 AE2 DQG0_11 8
12
DQG1_11 AE8 DQG1_12 11 12 8 10 DQH0_11 AU1 DQH0_10 8
12
DQH1_10 AU5 DQH1_11 10
劉 00 ei DE
12 8 12 DQG0_13 AF1 DQG0_12 8
12
DQG1_12 AF5 DQG1_13 12 12 8 11 DQH0_12 AV2 DQH0_11 8
12
DQH1_11 AV8 DQH1_12 11
12 8 13 DQG0_14 AG2 DQG0_13 8
12
DQG1_13 AG6 DQG1_14 13 12 8 12 DQH0_13 AY1 DQH0_12 8
12
DQH1_12 AY7 DQH1_13 12
12 8 14 DQG0_15 AG4 DQG0_14 8
12
DQG1_14 AG8 DQG1_15 14 12 8 13 DQH0_14 BA2 DQH0_13 8
12
DQH1_13 BA6 DQH1_14 13
12 8 15 AH3 DQG0_15 8
12
DQG1_15 AH7 15 12 8 14 DQH0_15 BA4 DQH0_14 8
12
DQH1_14 BB3 DQH1_15 14
8,12 CAG0_[0..9] CAG0_0 12 CAG1_0 CAG1_[0..9] 8,12 12 8 15 BB1 DQH0_15 8

12
DQH1_15 BB5 15
OUT 12 8 0 AD13 AD9 8 CAG1_1 0
OUT
CAG0_1 CAG0_0 CAG1_0 8,12 CAH0_[0..9] CAH0_0 CAH1_0 CAH1_[0..9] 8,12
12 8 1 W14 8
12 V9 1
OUT 12 8 0 AL14 12 CAH1_0
8 AL10 0
OUT
CAG0_2 CAG0_1 CAG1_1 CAG1_2 CAH0_1 CAH0_0 CAH1_1
12 8 2 CAG0_3 AC13 CAG0_2 12 CAG1_2
8 AD10 CAG1_3 2 12 8 1 CAH0_2 AF12 CAH0_1 12 CAH1_1
8 AE11 CAH1_2 1
V12 W11 AK12 AL11
巍 52 st NT
12 8 3 CAG0_4 CAG0_3 8
12
CAG1_3 CAG1_4 3 12 8 2 CAH0_3 CAH0_2 12 CAH1_2
8 CAH1_3 2
12 8 4 CAG0_5 AC14 CAG0_4 8
12
CAG1_4 AB9 CAG1_5 4 12 8 3 CAH0_4 AE14 CAH0_3 8
12
CAH1_3 AF9 CAH1_4 3
12 8 5 CAG0_6 Y13 CAG0_5 8
12
CAG1_5 Y9 CAG1_6 5 12 8 4 CAH0_5 AK13 CAH0_4 12 CAH1_4
8 AJ10 CAH1_5 4
12 8 6 CAG0_7 V13 CAG0_6 8
12
CAG1_6 W10 CAG1_7 6 12 8 5 CAH0_6 AG13 CAH0_5 12 CAH1_5
8 AG11 CAH1_6 5
12 8 7 CAG0_8 Y12 CAG0_7 8
12
CAG1_7 Y10 CAG1_8 7 12 8 6 CAH0_7 AE13 CAH0_6 12 CAH1_6
8 AF10 CAH1_7 6
12 8 8 CAG0_9 AB12 CAG0_8 12 CAG1_8
8 AB10 CAG1_9 8 12 8 7 CAH0_8 AG14 CAH0_7 12 CAH1_7
8 AG10 CAH1_8 7
12 8 9 AD12 CAG0_9 12 CAG1_9
8 AC11 9 12 8 8 CAH0_9 AJ13 CAH0_8 12 CAH1_8
8 AJ11 CAH1_9 8
12 8 9 AL13 CAH0_9 12 CAH1_9
8 AK10 9
WCKG0_0 AB1 WCKG0_0 WCKG1_0 AB7 WCKG1_0
00 an IA
12 BI BI 12
12 WCKG0B_0 AA2 WCKG0B_0 WCKG1B_0 AA6 WCKG1B_0 12 12 WCKH0_0 AR3 WCKH0_0 WCKH1_0 AR7 WCKH1_0 12
BI BI BI BI
12 WCKH0B_0 AP4 WCKH0B_0 WCKH1B_0 AP6 WCKH1B_0 12
BI BI
12 WCKG0_1 AB3 WCKG0_1 WCKG1_1 AB5 WCKG1_1 12
BI BI
12 WCKG0B_1 AC4 WCKG0B_1 WCKG1B_1 AC6 WCKG1B_1 12 12 WCKH0_1 AR1 WCKH0_1 WCKH1_1 AR5 WCKH1_1 12
BI BI BI BI
12 WCKH0B_1 AT2 WCKH0B_1 WCKH1B_1 AT6 WCKH1B_1 12
BI BI
12 EDCG0_0 W4 EDCG0_0 EDCG1_0 V5 EDCG1_0 12
BI BI
12 EDCG0_1 AE4 EDCG0_1 EDCG1_1 AF7 EDCG1_1 12 12 DBIH0_0 AK1 DBIH0_0 DBIH1_0 AL8 DBIH1_0 12
BI BI BI BI
12 DBIH0_1 AY3 DBIH0_1 DBIH1_1 AV6 DBIH1_1 12
g( L
BI BI
V3 W8
(3 2
12 DBIG0_0 DBIG0_0 DBIG1_0 DBIG1_0 12
BI BI
12 DBIG0_1 AF3 DBIG0_1 DBIG1_1 AE6 DBIG1_1 12 12 EDCH0_0 AL2 EDCH0_0 EDCH1_0 AK5 EDCH1_0 12
BI BI BI BI
12 EDCH0_1 AV4 EDCH0_1 EDCH1_1 AY5 EDCH1_1 12
BI BI
12 CABIG0 AB13 CABIG0 CABIG1 AC10 CABIG1 12
OUT OUT AJ14 AK9
12 CABIH0 CABIH0 CABIH1 CABIH1 12
OUT OUT
12 CKEG0 W13 CKEG0 CKEG1 AA10 CKEG1 12
OUT OUT AF13 AH9
12 CKEH0 CKEH0 CKEH1 CKEH1 12
AA13
OUT OUT
12 CKG CKG
OUT
唐
12 CKGB AA12 CKGB 12 CKH AH12 CKH
OUT OUT
00
12 CKHB AH13 CKHB
OUT
R
R3637 49.9R 1% R3638 10R 1% DRAM_RSTG
12 DRAM_RSTB_G 2 1 2 1 AE10 DRAM_RSTG R3643 49.9R 1% R3644 10R 1% DRAM_RSTH
OUT 2 1 2 1 AM9
DRAM_RSTB_H
01 MA 浩
12 DRAM_RSTH
OUT
1
1
C3615 R3639
120pF 5.1K
50V 1% C3613 R3645
5% Navi10 REV 0.91 120pF 5.1K
2
50V
5%
1% Navi10 REV 0.91
2
78 工健
9) 程 )
課
MSI MS-V381
Custom 5.0
NAVI10 MEM CHGH
Dat e: 2019_11_07 Sheet 8 of 35
GDDR6x16 CHAB Memory
00
2 M
U2000 U2100
5,9 DQA0_[15..0] DQA0_15 DQA1_10 DQA1_[15..0] 5,9 5,9 DQB0_[15..0] DQB0_15 DQB1_10 DQB1_[15..0] 5,9
BI BI BI BI
RD 05 SI
15 9 5 DQA0_14 G13 M13 9 5 DQA1_9 10 15 9 5 DQB0_14 G13 M13 9 5 DQB1_9 10
DQ15_A DQ15_B DQ15_A DQ15_B
14 9 5 DQA0_12 F13 N13 9 5 DQA1_11 9 14 9 5 DQB0_12 F13 N13 9 5 DQB1_11 9
12 9 5 DQA0_13 E13 P13 9 5 DQA1_8 11 12 9 5 DQB0_13 E13 P13 9 5 DQB1_8 11
11 9 5 DQA0_9 B13 U13 9 5 DQA1_12 13 11 9 5 DQB0_9 B13 U13 9 5 DQB1_12 13
10 9 5 DQA0_8 A12 V12 9 5 DQA1_14 15 10 9 5 DQB0_8 A12 V12 9 5 DQB1_14 15
0 9 5 DQA0_1 G2 M2 9 5 DQA1_6 5 0 9 5 DQB0_1 G2 M2 9 5 DQB1_6 5
1 9 5 DQA0_3 F2 N2 9 5 DQA1_4 6 1 9 5 DQB0_3 F2 N2 9 5 DQB1_4 6
(C 36
5 9 5 DQA0_7 A3 V3 9 5 DQA1_1 0 5 9 5 DQB0_7 A3 V3 9 5 DQB1_2 0
C
7 9 5 B4 U4 9 5 1 7 9 5 B4 U4 9 5 2
5,9 CAA0_[9..0] CAA0_9 CAA1_9 CAA1_[9..0] 5,9 5,9 CAB0_[9..0] CAB0_9 CAB1_9 CAB1_[9..0] 5,9
IN 9 9 5 J3 K3 9 5 9
IN IN 9 9 5 J3 K3 9 5 9
IN
CAA0_8 CAA1_8 CAB0_8 CAB1_8
CA9_A CA9_B CA9_A CA9_B
J4 K4 J4 K4
ON
8 9 5 CAA0_7 9 5 CAA1_7 8 8 9 5 CAB0_7 9 5 CAB1_7 8
)2 3
7 9 5 CAA0_6 J11 K11 9 5 CAA1_6 7 7 9 5 CAB0_6 J11 K11 9 5 CAB1_6 7
6 9 5 CAA0_5 J12 K12 9 5 CAA1_5 6 6 9 5 CAB0_5 J12 K12 9 5 CAB1_5 6
5 9 5 CAA0_4 H10 L10 9 5 CAA1_4 5 5 9 5 CAB0_4 H10 L10 9 5 CAB1_4 5
2 9 5 CAA0_1 G4 M4 9 5 CAA1_1 2 2 9 5 CAB0_1 G4 M4 9 5 CAB1_1 2
1 9 5 CAA0_0 G11 M11 9 5 CAA1_0 1 1 9 5 CAB0_0 G11 M11 9 5 CAB1_0 1
0 9 5 H3 L3 9 5 0 0 9 5 H3 L3 9 5 0
F
5 CKEA0 G10 CKE_N_A CKE_N_B M10 CKEA1 5 5 CKEB0 G10 CKE_N_A CKE_N_B M10 CKEB1 5
02
IN IN IN IN
5 WCKA0_1 D11 WCK1_t_A/NC WCK1_T_B R11 WCKA1_1 5 5 WCKB0_1 D11 WCK1_t_A/NC WCK1_T_B R11 WCKB1_1 5
IN WCKA0B_1 D10 R10 WCKA1B_1
IN IN WCKB0B_1 D10 R10 WCKB1B_1
IN
5 WCK1_c_A/NC WCK1_C_B 5 5 WCK1_c_A/NC WCK1_C_B 5
IN IN IN IN
w I
5 WCKA0_0 D4 WCK0_T_B/NC R4 WCKA1_0 5 5 WCKB0_0 D4 WCK0_T_B/NC R4 WCKB1_0 5
IN WCK0_t_A IN IN WCK0_t_A IN
5 WCKA0B_0 D5 WCK0_C_B/NC R5 WCKA1B_0 5 5 WCKB0B_0 D5 WCK0_C_B/NC R5 WCKB1B_0 5
IN WCK0_c_A IN IN WCK0_c_A IN
5 EDCA0_1 C13 T13 EDCA1_1 5 5 EDCB0_1 C13 T13 EDCB1_1 5
OU T EDC1_A EDC1_B OU T BI EDC1_A EDC1_B BI
EDCA0_0 C2 T2 EDCA1_0 EDCB0_0 C2 T2 EDCB1_0
劉 00 ei DE
5 5 5 5
OU T EDC0_A EDC0_B OU T BI EDC0_A EDC0_B BI
5 DBIA0_1 D13 R13 DBIA1_1 5 5 DBIB0_1 D13 R13 DBIB1_1 5

BI DBI1_A DBI1_B BI OU T DBI1_A DBI1_B OU T
5 DBIA0_0 D2 R2 DBIA1_0 5 5 DBIB0_0 D2 R2 DBIB1_0 5
+VDD_MEM BI DBI0_A DBI0_B BI +VDD_MEM OU T DBI0_A DBI0_B OU T
5 CABIA0 J5 CABI_N_A CABI_N_B K5 CABIA1 5 5 CABIB0 J5 CABI_N_A CABI_N_B K5 CABIB1 5

IN IN IN IN
1
R2007 22.37K 1% VREFC_A 1
R2107 22.37K 1% VREFC_B
1
R2008 25.49K 1% K1 1
R2108 25.49K 1% K1
VREFC VREFC
1
C2000 2
1uF 6.3V 1
C2100 2
1uF 6.3V
ZQ_A0 ZQ_A1 ZQ_B0 ZQ_B1
巍 52 st NT
1
R2006 2120R 1% J14 K14 1
R2013 2120R 1% 1
R2106 2120R 1% J14 K14 1
R2113 2120R 1%
ZQ_A ZQ_B ZQ_A ZQ_B
G5 RFU_A/NC RFU_B/NC M5 G5 RFU_A/NC RFU_B/NC M5
5 CKA J10 5 CKB J10

IN CK_t IN CK_t
5 CKAB K10 5 CKBB K10
IN CK_c IN CK_c
5 DRAM_RSTB_A J1 RESET_n 5 DRAM_RSTB_B J1 RESET_n

IN N5
IN N5
00 an IA
TCK TCK
F10 F10
TDI TDI
N10 N10
TDO TDO
F5 F5
TMS TMS
+VDD_MEM +VDD_MEM
V14 VDD_12 VSS_52

U14 V14 VDD_12 VSS_52
U14
A14 VDD_11 VSS_51
R14 A14 VDD_11 VSS_51
R14
g( L
L13 N14 L13 N14
VDD_10 VSS_50 VDD_10 VSS_50
(3 2
H13 M14 H13 M14
P10 VDD_8 VSS_48
G14 GDDR6 CHA +VDD_MEM Decoupling Caps P10 VDD_8 VSS_48
G14
P5 VDD_7 F14 P5 VDD_7 F14
VSS_47 VSS_47
E10 VDD_6 D14 E10 VDD_6 D14
VSS_46 VSS_46
+VDD_MEM
E5 B14 E5 B14
L2 V13 L2 V13
H2 A13 H2 A13
1
V1 VDD_2 VSS_42
T12 V1 VDD_2 VSS_42
T12
A1 VDD_1 VSS_41
R12 C2040 C2020 C2021 C2022 C2023 C2024 C2025 C2026 C2027 C2028 C2029 A1 VDD_1 VSS_41
R12
唐
N12 10uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF N12
00
VSS_40 4V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V VSS_40
M12 M12
VSS_39 VSS_39
2
2
+VDD_MEM +VDD_MEM
G12 G12
VSS_38 VSS_38
F12 F12
VSS_37 VSS_37
1
1
T14 D12 T14 D12
VDDQ_28 VSS_36 VDDQ_28 VSS_36
R
P14 C12 C2041 C2030 C2031 C2032 C2033 C2034 C2035 C2036 C2037 C2038 C2039 P14 C12
L14 V11 10uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF L14 V11
VDDQ_26 VSS_34 4V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V VDDQ_26 VSS_34
H14 T10 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
H14 T10
2
2
E14 VDDQ_24 VSS_32
P11 E14 VDDQ_24 VSS_32
P11
+VPP
C14 L11 C14 L11
01 MA 浩
K13 H11 K13 H11
J13 E11 J13 E11
1
1
N11 T5 N11 T5
T11 A11 C2042 C2043 C2044 C2045 C2046 T11 A11
U10 V4 10uF 1uF 1uF 1uF 1uF U10 V4
VDDQ_18 VSS_26 4V 6.3V 6.3V 6.3V 6.3V VDDQ_18 VSS_26
T4 C10 T4 C10
VDDQ_17 VDDQ_17
2
2
VSS_25 VSS_25
F11 P4 F11 P4
B10 L4 B10 L4
U5 VDDQ_14 VSS_22
H4 U5 VDDQ_14 VSS_22
H4
78 工健
C11 VDDQ_13 VSS_21
E4 C11 VDDQ_13 VSS_21
E4
C4 C5 C4 C5
B5 A4 B5 A4
N4 T3 N4 T3
F4 R3 F4 R3
K2 N3 GDDR6 CHB +VDD_MEM Decoupling Caps K2 N3
J2 M3 J2 M3
+VDD_MEM
T1 G3 T1 G3
P1 F3 P1 F3
L1 D3 L1 D3
9) 程 )
H1 VDDQ_3 VSS_11
C3 H1 VDDQ_3 VSS_11
C3
1
1
E1 V2 E1 V2
C1 A2 C2140 C2120 C2121 C2122 C2123 C2124 C2125 C2126 C2127 C2128 C2129 C1 A2
U1 10uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF U1
R1 R1
VSS_7 VSS_7
2
2
+VPP +VPP
N1 N1
VSS_6 VSS_6
M1 M1
VSS_5 VSS_5
1
1
V10 G1 V10 G1
VPP_4 VSS_4 VPP_4 VSS_4
A10 F1 C2141 C2130 C2131 C2132 C2133 C2134 C2135 C2136 C2137 C2138 C2139 A10 F1
V5 D1 10uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF V5 D1
課
VPP_2 VSS_2 4V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V VPP_2 VSS_2
A5 VPP_1 GDDR6 VSS_1
B1 A5 VPP_1 GDDR6 VSS_1
B1
2
2
+VPP
1
C2142 C2143 C2144 C2145 C2146

10uF 1uF 1uF 1uF 1uF
4V 6.3V 6.3V 6.3V 6.3V
10% 10% 10% 10% 10%
2
+VDD_MEM
DNI NS2000
2 1 FB_MVDD_1 21
OU T
DNI NS2001
2 1 FB_MVSS_1 21
OU T
DNI NS2002
2 1 FB_MVDD_2 21
OU T
DNI NS2003
2 1 FB_MVSS_2 21
OU T
MSI MS-V381
Size Document Description Re v
Custom 5.0
GDDR6 MEM CHAB
Date: 2019_11_07 Sheet 9 of 35
GDDR6x16 CHCD Memory
00
2 M
U2200 U2300
RD 05 SI
DQC0_[15..0] DQC1_[15..0] DQD0_[15..0] DQD1_[15..0]
6,10
BI 10 DQC0_15 DQC1_10
BI
6,10 6,10
BI 10 DQD0_15 DQD1_9
BI
6,10
15 6 DQC0_14 G13 M13 10 6 DQC1_8 10 15 6 DQD0_14 G13 M13 10 6 DQD1_11 9
10
6 14 DQC0_12 F13 N13 10 6 DQC1_9 8 10
6 14 DQD0_12 F13 N13 10 6 DQD1_10 11
10
6 12
DQC0_13 E13 P13 10 6 DQC1_11 9 10
6 12
DQD0_13 E13 P13 10 6 DQD1_8 10
10
6 13
DQC0_11 E12 P12 10 6 DQC1_13 11 10
6 13
DQD0_11 E12 P12 10 6 DQD1_12 8
10
6 11 DQC0_9 B13 U13 10 6 DQC1_12 13 10
6 11 DQD0_9 B13 U13 10 6 DQD1_13 12
9 10 6 DQC0_10 B12 U12 10 6 DQC1_15 12 9 10 6 DQD0_10 B12 U12 10 6 DQD1_14 13
10
6 10 DQC0_8 A12 V12 10 6 DQC1_14 15 10
6 10
DQD0_8 A12 V12 10 6 DQD1_15 14
0 10 6 DQC0_1 G2 M2 10 6 DQC1_6 5 0 10 6 DQD0_1 G2 M2 10 6 DQD1_6 5
(C 36
1 10 6 DQC0_3 F2 N2 10 6 DQC1_4 6 1 10 6 DQD0_3 F2 N2 10 6 DQD1_4 6
3 10 6 DQC0_2 E2 P2 10 6 DQC1_7 4 3 10 6 DQD0_2 E2 P2 10 6 DQD1_7 4
2 10 6 DQC0_4 E3 P3 10 6 DQC1_2 7 2 10 6 DQD0_4 E3 P3 10 6 DQD1_2 7
C
5 10 6 DQC0_7 A3 V3 10 6 DQC1_1 0 5 10 6 DQD0_7 A3 V3 10 6 DQD1_1 0
7 10 6 B4 U4 10 6 1 7 10 6 B4 U4 10 6 1
6,10 CAC0_[9..0] CAC0_9 CAC1_9 CAC1_[9..0] 6,10 6,10 CAD0_[9..0] CAD0_9 CAD1_9 CAD1_[9..0] 6,10
IN J3 K3
IN IN J3 K3
IN
ON
9 10 6 10 6 9 9 10 6 10 6 9
CAC0_8 CAC1_8 CAD0_8 CAD1_8
)2 3
8 10 6 CAC0_7 J4 K4 10 6 CAC1_7 8 8 10 6 CAD0_7 J4 K4 10 6 CAD1_7 8
5 10 6 CAC0_4 H10 L10 10 6 CAC1_4 5 5 10 6 CAD0_4 H10 L10 10 6 CAD1_4 5
2 10 6 CAC0_1 G4 M4 10 6 CAC1_1 2 2 10 6 CAD0_1 G4 M4 10 6 CAD1_1 2
1 10 6 CAC0_0 G11 M11 10 6 CAC1_0 1 1 10 6 CAD0_0 G11 M11 10 6 CAD1_0 1
0 10 6 H3 L3 10 6 0 0 10 6 H3 L3 10 6 0
02 F
6 CKEC0 G10 CKE_N_A CKE_N_B M10 CKEC1 6 6 CKED0 G10 CKE_N_A CKE_N_B M10 CKED1 6
IN IN IN IN
6 WCKC0_1 D11 WCK1_t_A/NC WCK1_T_B R11 WCKC1_1 6 6 WCKD0_1 D11 WCK1_t_A/NC WCK1_T_B R11 WCKD1_1 6
IN IN IN IN
6 WCKC0B_1 D10 WCK1_c_A/NC WCK1_C_B R10 WCKC1B_1 6 6 WCKD0B_1 D10 WCK1_c_A/NC WCK1_C_B R10 WCKD1B_1 6
I
IN IN IN IN
w
6 WCKC0_0 D4 WCK0_T_B/NC R4 WCKC1_0 6 6 WCKD0_0 D4 WCK0_T_B/NC R4 WCKD1_0 6
6 WCKC0B_0 D5 WCK0_C_B/NC R5 WCKC1B_0 6 6 WCKD0B_0 D5 WCK0_C_B/NC R5 WCKD1B_0 6
EDCC0_1 C13 T13 EDCC1_1 EDCD0_1 C13 T13 EDCD1_1
劉 00 ei DE
6 6 6 6
OU T EDC1_A EDC1_B OU T OU T EDC1_A EDC1_B OU T
6 EDCC0_0 C2 T2 EDCC1_0 6 6 EDCD0_0 C2 T2 EDCD1_0 6
6 DBIC0_1 D13 R13 DBIC1_1 6 6 DBID0_1 D13 R13 DBID1_1 6

BI DBI1_A DBI1_B BI BI DBI1_A DBI1_B BI
6 DBIC0_0 D2 R2 DBIC1_0 6 6 DBID0_0 D2 R2 DBID1_0 6
+VDD_MEM BI DBI0_A DBI0_B BI +VDD_MEM BI DBI0_A DBI0_B BI
6 CABIC0 J5 CABI_N_A CABI_N_B K5 CABIC1 6 6 CABID0 J5 CABI_N_A CABI_N_B K5 CABID1 6

IN IN IN IN
1
R2207 22.37K 1% VREFC_C 1
R2307 22.37K 1% VREFC_D
1
R2208 25.49K 1% K1 1
R2308 25.49K 1% K1
VREFC VREFC
1
C2200 2
1uF 6.3V 1
C2300 2
1uF 6.3V
巍 52 st NT
ZQ_C0 ZQ_C1 ZQ_D0 ZQ_D1
1
R2206 2120R 1% J14 K14 1
R2213 2120R 1% 1
R2306 2120R 1% J14 K14 1
R2313 2120R 1%
ZQ_A ZQ_B ZQ_A ZQ_B
6 CKC J10 6 CKD J10

IN CK_t IN CK_t
6 CKCB K10 6 CKDB K10
IN CK_c IN CK_c
DRAM_RSTB_C J1 DRAM_RSTB_D J1
00 an IA
6 RESET_n 6 RESET_n
IN N5
IN N5
TCK TCK
F10 F10
TDI TDI
N10 N10
TDO TDO
F5 F5
TMS TMS
+VDD_MEM +VDD_MEM
V14 VDD_12 VSS_52

U14 V14 VDD_12 VSS_52
U14
g( L
A14 R14 A14 R14
(3 2
L13 N14 L13 N14
H13 M14 H13 M14
P10 VDD_8
G14 P10 VDD_8
G14
VSS_48 VSS_48
P5 VDD_7 F14 GDDR6 CHC +VDD_MEM Decoupling Caps P5 VDD_7 F14
VSS_47 VSS_47
E10 VDD_6 D14 E10 VDD_6 D14
VSS_46 VSS_46
E5 B14 E5 B14
+VDD_MEM
L2 V13 L2 V13
H2 VDD_3 VSS_43
A13 H2 VDD_3 VSS_43
A13
V1 VDD_2 VSS_42
T12 V1 VDD_2 VSS_42
T12
唐
1
1
A1 R12 A1 R12
00
N12 C2240 C2220 C2221 C2222 C2223 C2224 C2225 C2226 C2227 C2228 C2229 N12
VSS_40 VSS_40
M12 10uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF M12
+VDD_MEM +VDD_MEM
G12 G12
VSS_38 VSS_38
2
2
F12 F12
VSS_37 VSS_37
R
T14 D12 T14 D12
1
1
P14 C12 P14 C12
L14 V11 C2241 C2230 C2231 C2232 C2233 C2234 C2235 C2236 C2237 C2238 C2239 L14 V11
H14 T10 10uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF H14 T10
E14 P11 E14 P11
01 MA 浩
2
2
C14 L11 C14 L11
+VPP
K13 H11 K13 H11
J13 E11 J13 E11
N11 T5 N11 T5
1
1
T11 A11 T11 A11
U10 V4 C2242 C2243 C2244 C2245 C2246 U10 V4
T4 C10 10uF 1uF 1uF 1uF 1uF T4 C10
F11 P4 10% 10% 10% 10% 10%
F11 P4
2
B10 VDDQ_15 VSS_23

L4 B10 VDDQ_15 VSS_23
L4
78 工健
U5 VDDQ_14 VSS_22
H4
C11 E4 C11 E4
C4 C5 C4 C5
B5 A4 B5 A4
N4 T3 N4 T3
F4 R3 F4 R3
K2 N3 GDDR6 CHD +VDD_MEM Decoupling Caps K2 N3
J2 M3 J2 M3
T1 G3 T1 G3
VDDQ_6 VSS_14 +VDD_MEM VDDQ_6 VSS_14
P1 F3 P1 F3
9) 程 )
L1 VDDQ_4 VSS_12
D3 L1 VDDQ_4 VSS_12
D3
H1 C3 H1 C3
1
1
E1 V2 E1 V2
R1 R1
VSS_7 VSS_7
2
2
+VPP +VPP
N1 N1
VSS_6 VSS_6
M1 M1
VSS_5 VSS_5
1
V10
VPP_4 VSS_4
G1 1 V10
VPP_4 VSS_4
G1
A10 F1 A10 F1
課
VPP_3 VSS_3 C2341 C2330 C2331 C2332 C2333 C2334 C2335 C2336 C2337 C2338 C2339 VPP_3 VSS_3
A5 GDDR6 B1 A5 GDDR6 B1
2
+VPP
1
C2342 C2343 C2344 C2345 C2346

4V 6.3V 6.3V 6.3V 6.3V
2
20ci203T
MSI MS-V381
Custom 5.0
GDDR6 MEM CHCD
Date: 2019_11_07 Sheet 10 of 35
GDDR6x16 CHEF Memory
00
2 M
U2400 U2500
RD 05 SI
7,11 DQE1_[15..0] DQE1_6 DQE0_0 DQE0_[15..0] 7,11 7,11 DQF1_[15..0] DQF1_5 DQF0_0 DQF0_[15..0] 7,11
BI BI BI BI
6 11 7 DQE1_4 G13 M13 11 7 DQE0_1 0 5 11 7 DQF1_7 G13 M13 11 7 DQF0_1 0
4 11 7 DQE1_5 F13 N13 11 7 DQE0_3 1 7 11 7 DQF1_6 F13 N13 11 7 DQF0_3 1
5 11 7 DQE1_7 E13 P13 11 7 DQE0_2 3 6 11 7 DQF1_4 E13 P13 11 7 DQF0_2 3
3 11 7 DQE1_2 B13 U13 11 7 DQE0_6 4 2 11 7 DQF1_3 B13 U13 11 7 DQF0_6 4
1 11 7 DQE1_0 A12 V12 11 7 DQE0_7 5 0 11 7 DQF1_1 A12 V12 11 7 DQF0_7 5
11
7 10 DQE1_9 G2 M2 11 7 DQE0_14 15 11
7 10 DQF1_9 G2 M2 11 7 DQF0_14 15
(C 36
9 11 7 DQE1_11 F2 N2 11 7 DQE0_12 14 9 11 7 DQF1_11 F2 N2 11 7 DQF0_12 14
11
7 11 DQE1_8 E2 P2 11 7 DQE0_13 12 11
7 11 DQF1_8 E2 P2 11 7 DQF0_13 12
11
7 13
DQE1_12 B2 U2 11 7 DQE0_9 11 11
7 13 DQF1_12 B2 U2 11 7 DQF0_9 11
11
7 12
DQE1_15 B3 U3 11 7 DQE0_10 9 11
7 12 DQF1_15 B3 U3 11 7 DQF0_10 9
C
11
7 15 DQE1_14 A3 V3 11 7 DQE0_8 10 11
7 15 DQF1_14 A3 V3 11 7 DQF0_8 10
11
7 14 B4 U4 11 7 8 11
7 14 B4 U4 11 7 8
7,11 CAE1_[9..0] CAE1_9 CAE0_9 CAE0_[9..0] 7,11 7,11 CAF1_[9..0] CAF1_9 CAF0_9 CAF0_[9..0] 7,11
IN J3 K3
IN IN J3 K3
IN
ON
9 11 7 11 7 9 9 11 7 11 7 9
CAE1_8 CAE0_8 CAF1_8 CAF0_8
)2 3
8 11 7 CAE1_7 J4 K4 11 7 CAE0_7 8 8 11 7 CAF1_7 J4 K4 11 7 CAF0_7 8
5 11 7 CAE1_4 H10 L10 11 7 CAE0_4 5 5 11 7 CAF1_4 H10 L10 11 7 CAF0_4 5
2 11 7 CAE1_1 G4 M4 11 7 CAE0_1 2 2 11 7 CAF1_1 G4 M4 11 7 CAF0_1 2
1 11 7 CAE1_0 G11 M11 11 7 CAE0_0 1 1 11 7 CAF1_0 G11 M11 11 7 CAF0_0 1
0 11 7 H3 L3 11 7 0 0 11 7 H3 L3 11 7 0
02 F
7 CKEE1 G10 CKE_N_A CKE_N_B M10 CKEE0 7 7 CKEF1 G10 CKE_N_A CKE_N_B M10 CKEF0 7
IN IN IN IN
7 WCKE1_0 D11 WCK1_t_A/NC WCK1_T_B R11 WCKE0_0 7 7 WCKF1_0 D11 WCK1_t_A/NC WCK1_T_B R11 WCKF0_0 7
IN IN IN IN
7 WCKE1B_0 D10 WCK1_c_A/NC WCK1_C_B R10 WCKE0B_0 7 7 WCKF1B_0 D10 WCK1_c_A/NC WCK1_C_B R10 WCKF0B_0 7
I
IN IN IN IN
w
7 WCKE1_1 D4 WCK0_T_B/NC R4 WCKE0_1 7 7 WCKF1_1 D4 WCK0_T_B/NC R4 WCKF0_1 7
7 WCKE1B_1 D5 WCK0_C_B/NC R5 WCKE0B_1 7 7 WCKF1B_1 D5 WCK0_C_B/NC R5 WCKF0B_1 7
EDCE1_0 C13 T13 EDCE0_0 EDCF1_0 C13 T13 EDCF0_0
劉 00 ei DE
7 7 7 7
7 EDCE1_1 C2 T2 EDCE0_1 7 7 EDCF1_1 C2 T2 EDCF0_1 7
7 DBIE1_0 D13 R13 DBIE0_0 7 7 DBIF1_0 D13 R13 DBIF0_0 7

7 DBIE1_1 D2 R2 DBIE0_1 7 7 DBIF1_1 D2 R2 DBIF0_1 7
7 CABIE1 J5 CABI_N_A CABI_N_B K5 CABIE0 7 7 CABIF1 J5 CABI_N_A CABI_N_B K5 CABIF0 7

IN IN IN IN
1
R2407 22.37K 1% VREFC_E 1
R2507 22.37K 1% VREFC_F
1
R2408 25.49K 1% K1 1
R2508 25.49K 1% K1
VREFC VREFC
1
C2400 2
1uF 6.3V 1
C2500 2
1uF 6.3V
巍 52 st NT
ZQ_E1 ZQ_E0 ZQ_F1 ZQ_F0
1
R2406 2120R 1% J14 K14 1
R2413 2120R 1% 1
R2506 2120R 1% J14 K14 1
R2513 2120R 1%
ZQ_A ZQ_B ZQ_A ZQ_B
7 CKE J10 7 CKF J10

IN CK_t IN CK_t
7 CKEB K10 7 CKFB K10
IN CK_c IN CK_c
DRAM_RSTB_E J1 DRAM_RSTB_F J1
00 an IA
7 RESET_n 7 RESET_n
IN N5
IN N5
TCK TCK
F10 F10
TDI TDI
N10 N10
TDO TDO
F5 F5
TMS TMS
+VDD_MEM +VDD_MEM
V14 VDD_12 VSS_52

U14 V14 VDD_12 VSS_52
U14
g( L
A14 R14 A14 R14
(3 2
L13 N14 L13 N14
H13 M14 H13 M14
P10 VDD_8
G14 P10 VDD_8
G14
VSS_48 VSS_48
P5 VDD_7 F14 GDDR6 CHE +VDD_MEM Decoupling Caps P5 VDD_7 F14
VSS_47 VSS_47
E10 VDD_6 D14 E10 VDD_6 D14
VSS_46 VSS_46
E5 B14 E5 B14
+VDD_MEM
L2 V13 L2 V13
H2 VDD_3 VSS_43
A13 H2 VDD_3 VSS_43
A13
V1 VDD_2 VSS_42
T12 V1 VDD_2 VSS_42
T12
唐 1
1
A1 R12 A1 R12
00
N12 C2440 C2420 C2421 C2422 C2423 C2424 C2425 C2426 C2427 C2428 C2429 N12
VSS_40 VSS_40
M12 10uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF M12
+VDD_MEM +VDD_MEM
G12 G12
VSS_38 VSS_38
2
2
F12 F12
VSS_37 VSS_37
R
T14 D12 T14 D12
1
1
P14 C12 P14 C12
L14 V11 C2441 C2430 C2431 C2432 C2433 C2434 C2435 C2436 C2437 C2438 C2439 L14 V11
H14 T10 10uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF H14 T10
E14 P11 E14 P11
01 MA 浩
2
2
C14 L11 C14 L11
+VPP
K13 H11 K13 H11
J13 E11 J13 E11
N11 T5 N11 T5
1
1
T11 A11 T11 A11
U10 V4 C2442 C2443 C2444 C2445 C2446 U10 V4
T4 C10 10uF 1uF 1uF 1uF 1uF T4 C10
F11 P4 10% 10% 10% 10% 10%
F11 P4
2
2
B10 VDDQ_15 VSS_23
L4
78 工健
U5 VDDQ_14 VSS_22
H4
C11 E4 C11 E4
C4 C5 C4 C5
B5 A4 B5 A4
N4 T3 N4 T3
F4 R3 F4 R3
K2 N3 GDDR6 CHF +VDD_MEM Decoupling Caps K2 N3
J2 M3 J2 M3
T1 G3 T1 G3
P1 F3 P1 F3
9) 程 )
L1 VDDQ_4 VSS_12
D3 L1 VDDQ_4 VSS_12
D3
H1 C3 H1 C3
1
1
E1 V2 E1 V2
R1 R1
VSS_7 VSS_7
2
2
+VPP +VPP
N1 N1
VSS_6 VSS_6
M1 M1
VSS_5 VSS_5
1
1
V10 G1 V10 G1
A10 F1 A10 F1
課
VPP_3 VSS_3 C2541 C2530 C2531 C2532 C2533 C2534 C2535 C2536 C2537 C2538 C2539 VPP_3 VSS_3
A5 B1 A5 B1
2
2
+VPP
GDDR6 GDDR6
1
C2542 C2543 C2544 C2545 C2546

4V 6.3V 6.3V 6.3V 6.3V
2
MSI MS-V381
Custom 5.0
GDDR6 MEM CHEF
Date: 2019_11_07 Sheet 11 of 35
GDDR6x16 CHGH Memory
00
8,12
BI
DQG1_[15..0]
5 12
6 12
4 12
7 12
2 12
3 12
0 12
1 12
8
8
8
8
8
8
8
8
2
RD 05 SI
DQG1_5
DQG1_6
DQG1_4
DQG1_7
DQG1_2
DQG1_3
DQG1_0
DQG1_1
DQG1_10
M G13
F13
E13
E12
B13
B12
A12
B11
DQ15_A
DQ14_A
DQ13_A
DQ12_A
DQ11_A
DQ10_A
DQ9_A
DQ8_A
U2600
DQ15_B
DQ14_B
DQ13_B
DQ12_B
DQ11_B
DQ10_B
DQ9_B
DQ8_B
M13
N13
P13
P12
U13
U12
V12
U11
12
12
12
12
12
12
12
12
8
8
8
8
8
8
8
8
DQG0_0
DQG0_1
DQG0_3
DQG0_2
DQG0_4
DQG0_6
DQG0_5
DQG0_7
DQG0_15
0
1
7
DQG0_[15..0]
BI
8,12 8,12
BI
DQH1_[15..0]
5 12
6 12
4 12
7 12
2 12
3 12
0 12
1 12
8
8
8
8
8
8
8
8
DQH1_5
DQH1_6
DQH1_4
DQH1_7
DQH1_2
DQH1_3
DQH1_0
DQH1_1
DQH1_10
G13
F13
E13
E12
B13
B12
A12
B11
DQ15_A
DQ14_A
DQ13_A
DQ12_A
DQ11_A
DQ10_A
DQ9_A
DQ8_A
U2700
DQ15_B
DQ14_B
DQ13_B
DQ12_B
DQ11_B
DQ10_B
DQ9_B
DQ8_B
M13
N13
P13
P12
U13
U12
V12
U11
12
12
12
12
12
12
12
12
8
8
8
8
8
8
8
8
DQH0_0
DQH0_1
DQH0_3
DQH0_2
DQH0_4
DQH0_6
DQH0_5
DQH0_7
DQH0_15
0
1
7
DQH0_[15..0]
BI
8,12
(C 36
12
8 10 DQG1_9 G2 M2 12 8 DQG0_14 15 12
8 10 DQH1_9 G2 M2 12 8 DQH0_14 15
9 12 8 DQG1_11 F2 N2 12 8 DQG0_12 14 9 12 8 DQH1_11 F2 N2 12 8 DQH0_12 14
12
8 11 DQG1_8 E2 P2 12 8 DQG0_13 12 12
8 11 DQH1_8 E2 P2 12 8 DQH0_13 12
8 12 8 DQG1_14 E3 P3 12 8 DQG0_11 13 8 12 8 DQH1_13 E3 P3 12 8 DQH0_11 13
12
8 14 DQG1_12 B2 U2 12 8 DQG0_9 11 12
8 13
DQH1_12 B2 U2 12 8 DQH0_9 11
C
12
8 12 DQG1_15 B3 U3 12 8 DQG0_10 9 12
8 12 DQH1_15 B3 U3 12 8 DQH0_10 9
12
8 15 DQG1_13 A3 V3 12 8 DQG0_8 10 12
8 15
DQH1_14 A3 V3 12 8 DQH0_8 10
12
8 13 B4 U4 12 8 8 12
8 14 B4 U4 12 8 8
ON
8,12 CAG1_[9..0] CAG1_9 CAG0_9 CAG0_[9..0] 8,12 8,12 CAH1_[9..0] CAH1_9 CAH0_9 CAH0_[9..0] 8,12
)2 3
IN 9 12 8 J3 K3 12 8 9
IN IN 9 12 8 J3 K3 12 8 9
IN
CAG1_8 CAG0_8 CAH1_8 CAH0_8
8 12 8 CAG1_7 J4 K4 12 8 CAG0_7 8 8 12 8 CAH1_7 J4 K4 12 8 CAH0_7 8
5 12 8 CAG1_4 H10 L10 12 8 CAG0_4 5 5 12 8 CAH1_4 H10 L10 12 8 CAH0_4 5
2 12 8 CAG1_1 G4 M4 12 8 CAG0_1 2 2 12 8 CAH1_1 G4 M4 12 8 CAH0_1 2
1 12 8 CAG1_0 G11 M11 12 8 CAG0_0 1 1 12 8 CAH1_0 G11 M11 12 8 CAH0_0 1
F
0 12 8 H3 L3 12 8 0 0 12 8 H3 L3 12 8 0
02
8 CKEG1 G10 CKE_N_A CKE_N_B M10 CKEG0 8 8 CKEH1 G10 CKE_N_A CKE_N_B M10 CKEH0 8
IN IN IN IN
8 WCKG1_0 D11 WCK1_t_A/NC WCK1_T_B R11 WCKG0_0 8 8 WCKH1_0 D11 WCK1_t_A/NC WCK1_T_B R11 WCKH0_0 8
I
IN IN IN IN
w
8 WCKG1B_0 D10 WCK1_c_A/NC WCK1_C_B R10 WCKG0B_0 8 8 WCKH1B_0 D10 WCK1_c_A/NC WCK1_C_B R10 WCKH0B_0 8
IN IN IN IN
8 WCKG1_1 D4 WCK0_T_B/NC R4 WCKG0_1 8 8 WCKH1_1 D4 WCK0_T_B/NC R4 WCKH0_1 8
IN WCKG1B_1 D5
WCK0_t_A
R5 WCKG0B_1
IN IN WCKH1B_1 D5
WCK0_t_A
R5 WCKH0B_1
IN
8 WCK0_C_B/NC 8 8 WCK0_C_B/NC 8
劉 00 ei DE
8 EDCG1_0 C13 T13 EDCG0_0 8 8 EDCH1_0 C13 T13 EDCH0_0 8
8 EDCG1_1 C2 T2 EDCG0_1 8 8 EDCH1_1 C2 T2 EDCH0_1 8
8 DBIG1_0 D13 R13 DBIG0_0 8 8 DBIH1_0 D13 R13 DBIH0_0 8

8 DBIG1_1 D2 R2 DBIG0_1 8 8 DBIH1_1 D2 R2 DBIH0_1 8
8 CABIG1 J5 CABI_N_A CABI_N_B K5 CABIG0 8 8 CABIH1 J5 CABI_N_A CABI_N_B K5 CABIH0 8

IN IN IN IN
1
R2607 22.37K 1% VREFC_G 1
R2707 22.37K 1% VREFC_H
1
R2608 25.49K 1% K1 1
R2708 25.49K 1% K1
VREFC VREFC
巍 52 st NT
1
C2600 2
1uF 6.3V 1
C2700 2
1uF 6.3V
ZQ_G1 ZQ_G0 ZQ_H1 ZQ_H0

1
R2606 2120R 1% J14 K14 1
R2613 2120R 1% 1
R2706 2120R 1% J14 K14 1
R2713 2120R 1%
ZQ_A ZQ_B ZQ_A ZQ_B
8 CKG J10 8 CKH J10

IN CK_t IN CK_t
8 CKGB K10 8 CKHB K10
IN CK_c IN CK_c
00 an IA
8 DRAM_RSTB_G J1 8 DRAM_RSTB_H J1
IN RESET_n IN RESET_n
N5 N5
TCK TCK
F10 F10
TDI TDI
N10 N10
TDO TDO
F5 F5
TMS TMS
+VDD_MEM +VDD_MEM
g( L
V14 U14 V14 U14
(3 2
A14 R14 A14 R14
L13 N14 L13 N14
H13 M14 H13 M14
P10 VDD_8
G14 P10 VDD_8
G14
VSS_48 VSS_48
P5 VDD_7 F14 P5 VDD_7 F14
VSS_47 VSS_47
E10 VDD_6 D14 GDDR6 CHG +VDD_MEM Decoupling Caps E10 VDD_6 D14
VSS_46 VSS_46
E5 B14 E5 B14
VDD_5 VSS_45 +VDD_MEM VDD_5 VSS_45
L2 VDD_4 VSS_44
V13 L2 VDD_4 VSS_44
V13
H2 VDD_3 VSS_43
A13 H2 VDD_3 VSS_43
A13
唐
V1 T12 V1 T12
00
A1 R12 A1 R12
1
N12 N12
VSS_40 VSS_40
M12 C2640 C2620 C2621 C2622 C2623 C2624 C2625 C2626 C2627 C2628 C2629 M12
VSS_39 VSS_39
+VDD_MEM 10uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF +VDD_MEM
G12 G12
R
F12 F12
VSS_37 VSS_37
2
2
T14 D12 T14 D12
P14 C12 P14 C12
1
1
L14 VDDQ_26 VSS_34
V11 L14 VDDQ_26 VSS_34
V11
H14 T10 H14 T10
01 MA 浩
VDDQ_25 VSS_33 C2641 C2630 C2631 C2632 C2633 C2634 C2635 C2636 C2637 C2638 C2639 VDDQ_25 VSS_33
E14 P11 10uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF E14 P11
C14 L11 C14 L11
2
2
K13 H11 K13 H11
+VPP
J13 E11 J13 E11
N11 T5 N11 T5
T11 A11 T11 A11
1
1
U10 V4 U10 V4
T4 C10 C2642 C2643 C2644 C2645 C2646 T4 C10
F11 P4 10uF 1uF 1uF 1uF 1uF F11 P4
78 工健
B10 VDDQ_15 VSS_23
L4
2
U5
VDDQ_14 VSS_22
H4 2 U5
VDDQ_14 VSS_22
H4
C11 E4 C11 E4
C4 C5 C4 C5
B5 A4 B5 A4
N4 T3 N4 T3
F4 R3 F4 R3
K2 N3 GDDR6 CHH +VDD_MEM Decoupling Caps K2 N3
J2 M3 J2 M3
T1 G3 T1 G3
9) 程 )
P1 VDDQ_5 VSS_13
F3 P1 VDDQ_5 VSS_13
F3
L1 D3 L1 D3
H1 C3 H1 C3
1
1
E1 V2 E1 V2
R1 R1
VSS_7 VSS_7
2
2
+VPP +VPP
N1 N1
VSS_6 VSS_6
M1 M1
VSS_5 VSS_5
1
1
V10 G1 V10 G1
課
A10 VPP_3 VSS_3
F1 C2741 C2730 C2731 C2732 C2733 C2734 C2735 C2736 C2737 C2738 C2739 A10 VPP_3 VSS_3
F1
A5 B1 A5 B1
2
2
+VPP
GDDR6 GDDR6
1
C2742 C2743 C2744 C2745 C2746

4V 6.3V 6.3V 6.3V 6.3V
2
MSI MS-V381
Custom 5.0
GDDR6 MEM CHGH
Date: 2019_11_07 Sheet 12 of 35
NAVI10 TMDP A/B
00
2 M
+3.3V_BUS
RD 05 SI
R1500 R1501 R1502 R1503
2.2K 2.2K 2.2K 2.2K
5% 5% 5% 5% U1Z
USBPD_I2C_MASTER_SCL symbol 26
USBPD_I2C_MASTER_SDA AW21 USBPD_I2C_MASTER_SCL
U1G AW20 USBPD_I2C_MASTER_SDA

1
R87 22.2K 5% AY16 USB_PD_INTERRUPT
(C 36
symbol 7 USBPD_I2C_SLAVE_SCL
USBC1_RXP2/TX2P_DPB0P BE19 USBPD_I2C_SLAVE_SDA AT21 USBPD_I2C_SLAVE_SCL
AR21 USBPD_I2C_SLAVE_SDA
USBC1_RXN2/TX2M_DPB0N BF19
C
+3.3V_BUS
USBC1_TXP2/TX1P_DPB1P BF18 1
MR80 210K 5% AV16 USB_VAUX_PRESENT
USBC1_TXN2/TX1M_DPB1N BG18
BE17
ON
USBC1_TXP1/USB_0_TXP1/TX0P_DPB2P R82
)2 3
10K
5%
USBC1_TXN1/USB_0_TXN1/TX0M_DPB2N BF17
+3.3V_BUS 1
R81 210K 5% AW17 USB_OCP0 USB_OCP1 AV17
USBC1_RXP1/USB_0_RXP1/TXCBP_DPB3P BF16
USBC1_RXN1/USB_0_RXN1/TXCBM_DPB3N BG16 AY20 USB20_TXRTUNE USB21_TXRTUNE AT20
DDCAUX5P BC14
F
DDCAUX5N BB14
02
BA21 USB20_DP0 USB21_DP0 AT22
Navi10 REV 0.91 AY21 USB20_DM0 USB21_DM0 AR22
w I
Navi10 REV 0.91
劉 00 ei DE
巍 52 st NT U1F
symbol 6
USBC0_RXP2/TX2P_DPA0P BE23
USBC0_RXP2_TX2P_DPA0P C1801
2 1 0.1uF 6.3V 13
DPA_0P
1
J1801
ML_Lane_0p DP_PWR 20
+3.3V_DPA
2
F1801
1
+3.3V_BUS
1
USBC0_RXN2_TX2M_DPA0N DPA_0N
00 an IA
C1802 1.5A
USBC0_RXN2/TX2M_DPA0N BF23 2 1 0.1uF 6.3V 13 3 ML_Lane_0n C1811 C1812
22uF 100uF
USBC0_TXP2_TX1P_DPA1P C1803 DPA_1P 6.3V 6.3V
USBC0_TXP2/TX1P_DPA1P BF22 2 1 0.1uF 6.3V 13 4 ML_Lane_1p
2
USBC0_TXN2_TX1M_DPA1N C1804 DPA_1N
USBC0_TXN2/TX1M_DPA1N BG22 2 1 0.1uF 6.3V 13 6 ML_Lane_1n
USB1_ZVSS USBC0_TXP1_TX0P_DPA2P C1805 DPA_2P
R1735 1 2 200R 1% AY18 USB1_ZVSS USBC0_TXP1/USB_0_TXP0/TX0P_DPA2P BE21 2 1 0.1uF 6.3V 13 7 ML_Lane_2p
USB0_ZVSS USBC0_TXN1_TX0M_DPA2N C1806 DPA_2N
R1736 1 2 200R 1% BA18 USB0_ZVSS USBC0_TXN1/USB_0_TXN0/TX0M_DPA2N BF21 2 10% 1 0.1uF 6.3V 13 9 ML_Lane_2n
g( L
USBC0_RXP1_TXCAP_DPA3P C1807 DPA_3P
(3 2
USBC0_RXP1/USB_0_RXP0/TXCAP_DPA3P BF20 2 1 0.1uF 6.3V 13 10 ML_Lane_3p
USBC0_RXN1_TXCAM_DPA3N C1808 DPA_3N
USBC0_RXN1/USB_0_RXN0/TXCAM_DPA3N BG20 2 1 0.1uF 6.3V 13 12 ML_Lane_3n
DPA_AUXP
DDCAUX6P BD16 DDCAUX6P R1809 1 2 100R 1% 2
C1809 1 0.1uF 6.3V 13 15 AUX_CHp
R1803 2 1 100K 5% DPA_AUXN
DDCAUX6N BC16 DDCAUX6N R1810 1 2 100R 1% 2
C1810 1 0.1uF 6.3V 13 17 AUX_CHn
R1804 2 1 100K 5% +3.3V_DPA
Navi10 REV 0.91 +12V_BUS_B +12V_BUS_B +3.3V_BUS
Q1806A Q1806B 10%
唐
1
2N7002DW 2N7002DW
00
C1813 C1814 4 3 6 1 PWR_RTN 19
3
47pF 47pF G1
50V 50V Q1807B Q1807A DPA_HPD G1
Q1803B 5 R1805 1 210K 5% 13 18 G2
2N7002DW 2N7002DW R1801 R1802 Hot_Det G2
2
1 6 3 4 10K 10K G3
5% 5% MMDT3904-7 G3
5
R
3 GENERICG_HPD6 R1806 1 2
10K 5% G4 G4
OU T
4
GND_0 2
3
AUX3_BYPSS_EN DPA_DONGLE_DET GND_1 5
6
1 13 13 CONFIG 1 GND_2 8
Q1803A 2 11 SCREW1801
01 MA 浩
GND_3
Q1804 R1807 2 11M 5% 14 16
MMDT3904-7 CONFIG 2 GND_6 SCR E W
2
2N7002E
1
DP_RECEPTACLE_W/TAB
DPA_CONFIG2
R1808 5.1M 5%
78 工健
9) 程 )
D1801 D1802
DPA_3N DPA_1N
13 1 3 13 1 3
DPA_3P DPA_1P
13 2 8 13 2 8
DPA_2N DPA_0N
4 4
課
13 13
DPA_2P 6 DPA_0P 6
13 5 7 13 5 7
9 9
DNI 10 DNI 10
ESD8004 ESD8004
DNI MD1804
1 2
ESD131-B1-W0201
DNI D1804 DPA_HPD
D1803 2 1
DPA_AUXN 13
13 1 3
DPA_AUXP ESD5V3U1U-02LRH
13 2 8
4
DPA_DONGLE_DET 6
13 5 7
9
DNI 10
20ci203T
ESD8004
MSI MS-V381
Custom 5.0
NAVI10 TMDPA - DP
Date: 2019_11_07 Sheet 13 of 35
00
NAVI10 TMDP C/D
2 M
U1I
symbol 9
TX2P_DPD0P BE14
RD 05 SI
TX2M_DPD0N BF14
TX1P_DPD1P BF13
TX1M_DPD1N BG13
TX0P_DPD2P BE12
TX0M_DPD2N BF12
(C 36
TXCDP_DPD3P BF11
TXCDM_DPD3N BG11
C
DDCAUX3P BC10
DDCAUX3N BB10
Navi10 REV 0.91
)2 3 ON
02 w F I
U1H
symbol 8
TX2P_DPC0P BD20 DPC0P 1

C1870 2
0.1uF
<PositionInPackage>
6.3V
<PositionInPackage> 1 2 100nH 1
R1870 2499R 1%
<PositionInPackage> 1
R1880 23.3R 1% 14 CTX2P 1 TMDS Data 2+
J1850
+5V Pwr 18
+5V_VESA
1
BC20 DPC0N 1
C1871 2
0.1uF 6.3V L1880 1
R1881 23.3R 1% 14 CTX2N 3
劉 00 ei DE
TX2M_DPC0N <PositionInPackage> TMDS Data 2-
<PositionInPackage> 1 5%
2 100nH 1
R1871 2499R 1% C1850
BC19 DPC1P 1
C1872 2
0.1uF 6.3V L1881 1
R1882 23.3R 1% 14 CTX1P 4 1uF
TX1P_DPC1P <PositionInPackage> TMDS Data 1+ 16V
<PositionInPackage> 1 5%
2 100nH 1
R1872 2499R 1%
2
TX1M_DPC1N BB19 DPC1N 1
C1873 2
0.1uF 6.3V L1882 1
R1883 23.3R 1% 14 CTX1N 6
<PositionInPackage> TMDS Data 1-
<PositionInPackage> 1 5% 2 100nH 1
R1873 2499R 1%
TX0P_DPC2P BD18 DPC2P 1

C1874 2
0.1uF 6.3V L1883 1
R1884 23.3R 1% 14 CTX0P 7
<PositionInPackage> TMDS Data 0+
<PositionInPackage> 1 5% 2 100nH 1
R1874 2499R 1%
TX0M_DPC2N BC18 DPC2N 1

C1875 2
0.1uF 6.3V L1884 1
R1885 23.3R 1% 14 CTX0N 9
10% <PositionInPackage> TMDS Data 0-
DPC_ZVSS <PositionInPackage> 1 5%
2 100nH 1
R1875 2499R 1%
巍 52 st NT
R1730 1 2 200R 1% BC11 DPC_ZVSS TXCCP_DPC3P BC17 DPC3P 1
C1876 2
0.1uF 6.3V L1885 <PositionInPackage> 1
R1886 23.3R 1% 14 CTXCP 10 TMDS Clock+
DPD_ZVSS <PositionInPackage> 1 5%
2 100nH 1
R1876 2499R 1%
R1731 1 2 200R 1% BD11 DPD_ZVSS TXCCM_DPC3N BB17 DPC3N 1
C1877 2
0.1uF 6.3V L1886 <PositionInPackage> 1
R1887 23.3R 1% 14 CTXCN 12 TMDS Clock-
DPE_ZVSS
1 5%
2 100nH 1
R1877 2499R 1%
DDCAUX4P +12V_BUS_B
R1732 1 2 200R 1% BB12 DPE_ZVSS DDCAUX4P BD13 L1887
DPF_ZVSS 5% DPC_GND
R1734 1 2 200R 1% BC12 DPF_ZVSS DDCAUX4N BC13 DDCAUX4N
<PositionInPackage>
Navi10 REV 0.91 R1888
100K
00 an IA
5%
3
DVI_HDMI_EN DDC4CLK_HDMI
1 Q1850 14 15 DDC Clock
1
<PositionInPackage> 2N7002L DDC4DAT_HDMI
C1878 14 16 DDC Data D0 Shld 8
2
0.1uF 5
16V D1 Shld
+3.3V_BUS +5V_VESA
10%
D2 Shld 2
2
Clk Shld 11
+3.3V_BUS
HPD_HDMI GND (+5V) 17
14 19 Hot Plog Detect
g( L
<PositionInPackage>
<PositionInPackage> <PositionInPackage>
<PositionInPackage> CASE 20 SCREW1850
(3 2
R1851 R1852 Q1852B R1853 R1854 14 NC CASE 21
2
10K 10K 2.2K 2.2K 22
5% 5% 2N7002DW 5% 5% CASE SCR E W
13 CEC CASE 23
1 6
HDMI_W/TAB
4 3
+3.3V_BUS
Q1852A
+3.3V_BUS
2N7002DW
5
00 唐
3
<PositionInPackage>
Q1851 1 1
R1855 210K 5%
MMBT3904 <PositionInPackage>
3 GENERICE_HPD4 1
R1856 210K 5%
2
OU T
R
OPTIONAL ESD PROTECTION DIODES
14
14
CTXCN
CTXCP
01 MA 浩 1
2
D1850
8
14
14
CTX1N
CTX1P
1
2
D1851
78 工健
14
CTX0N 4 14
CTX2N 4
6 6
14 CTX0P 5 7 14 CTX2P 5 7
9 9
10 10
ESD8104MUTAG ESD8104MUTAG
9) 程 )
DNI MD1853
1 2
ESD131-B1-W0201
DNI D1853 HPD_HDMI
D1852 2 1 14
1 3
ESD5V3U1U-02LRH
課
2 8
DDC4DAT_HDMI
14 4
DDC4CLK_HDMI 6
14 5 7
9
10
ESD8104MUTAG
MSI MS-V381
Custom 5.0
NAVI10 TMDPC - HDMI
Date: 2019_11_07 Sheet 14 of 25
(9) NAVI10 TMDP E/F
00
U1K
symbol 11
TX2P_DPF0P BD6
2
RD 05 SI M DPF_C0P
2
C1901 1 0.1uF 6.3V 15
DPF_0P
1
J1901
ML_Lane_0p DP_PWR 20
+3.3V_DPF
2
F1901
1
+3.3V_BUS
1
DPF_C0N DPF_0N 1.5A
TX2M_DPF0N BE5 2
C1902 10% 1 0.1uF 6.3V 15 3 ML_Lane_0n C1911 C1912
22uF 100uF
DPF_C1P DPF_1P 6.3V 6.3V
TX1P_DPF1P BG5 2
C1903 1 0.1uF 6.3V 15 4 ML_Lane_1p
2
DPF_C1N DPF_1N
TX1M_DPF1N BG3 2
C1904 1 0.1uF 6.3V 15 6 ML_Lane_1n
(C 36
DPF_C2P DPF_2P
TX0P_DPF2P BE3 2
C1905 1 0.1uF 6.3V 15 7 ML_Lane_2p
DPF_C2N DPF_2N
TX0M_DPF2N BF2 2
C1906 1 0.1uF 6.3V 15 9 ML_Lane_2n
DPF_3P
C
DPF_C3P
TXCFP_DPF3P BC2 2
C1907 10% 1 0.1uF 6.3V 15 10 ML_Lane_3p
DPF_C3N DPF_3N
TXCFM_DPF3N BE1 2
C1908 1 0.1uF 6.3V 15 12 ML_Lane_3n
DPF_AUXP
BC7 1 2 2 1 15
ON
DDCAUX1P AUX1P R1909 100R 1% C1909 0.1uF 6.3V 15 AUX_CHp
)2 3
R1903 2 1 100K 5% DPF_AUXN
DDCAUX1N BB7 AUX1N R1910 1 2 100R 1% 2
C1910 1 0.1uF 6.3V 15 17 AUX_CHn
1
R1904 2 1 100K 5% +3.3V_DPF
C1913 C1914 Q1906A Q1906B
47pF 47pF
50V 50V 2N7002DW 2N7002DW
4 3 6 1 PWR_RTN 19
2
3
Q1907B Q1907A DPF_HPD G1 G1
Q1903B 5 R1905 1 210K 5% 15 18 G2
1 6 3 4 10K 10K G3
5% 5% MMDT3904-7 G3
2
F
3 HPD1 R1906 1 2
10K 5% G4 G4
02
4
OU T
GND_0 2
3
AUX1_BYPSS_EN DPF_DONGLE_DET GND_1 5
6
1 15 13 CONFIG 1 GND_2 8
Q1903A 2 11 SCREW1901
GND_3
w I
Q1904 R1907 2 11M 5% 14 16
MMDT3904-7 CONFIG 2 GND_6 SCR E W
2
2N7002E
1
DP_RECEPTACLE_W/TAB
DPF_CONFIG2
R1908 5.1M 5%
劉 00 ei DE
U1J +3.3V_DPE
J1911 +3.3V_BUS
DPE_C0P DPE_0P F1911

symbol 10
TX2P_DPE0P BE10 2
C1921 1 0.1uF 6.3V 15 1 ML_Lane_0p DP_PWR 20 2 1
1
DPE_C0N DPE_0N 1.5A
TX2M_DPE0N BF10 2
C1922 10% 1 0.1uF 6.3V 15 3 ML_Lane_0n C1931 C1932
22uF 100uF
DPE_C1P DPE_1P 6.3V 6.3V
巍 52 st NT
TX1P_DPE1P BF8 2
C1923 1 0.1uF 6.3V 15 4 ML_Lane_1p
2
DPE_C1N DPE_1N
TX1M_DPE1N BG8 2
C1924 1 0.1uF 6.3V 15 6 ML_Lane_1n
DPE_C2P DPE_2P
TX0P_DPE2P BE7 2
C1925 1 0.1uF 6.3V 15 7 ML_Lane_2p
DPE_C2N DPE_2N
TX0M_DPE2N BF7 2
C1926 1 0.1uF 6.3V 15 9 ML_Lane_2n
DPE_C3P DPE_3P
TXCEP_DPE3P BF6 2
C1927 10% 1 0.1uF 6.3V 15 10 ML_Lane_3p
DPE_3N
00 an IA
DPE_C3N
TXCEM_DPE3N BG6 2
C1928 1 0.1uF 6.3V 15 12 ML_Lane_3n
DPE_AUXP
DDCAUX2P BD8 AUX2P R1929 1 2 100R 1% 2
C1929 1 0.1uF 6.3V 15 15 AUX_CHp
R1923 2 1 100K 5% DPE_AUXN
DDCAUX2N BC8 AUX2N R1930 1 2 100R 1% 2
C1930 1 0.1uF 6.3V 15 17 AUX_CHn
1
R1924 2 1 100K 5% +3.3V_DPE

C1933 C1934 Q1926A Q1926B
47pF 47pF
50V 50V 2N7002DW 2N7002DW
4 3 6 1 PWR_RTN 19
2
3
g( L
Q1927B Q1927A DPE_HPD G1 G1
(3 2
Q1923B 5 R1925 1 210K 5% 15 18 G2
1 6 3 4 10K 10K G3
5% 5% MMDT3904-7 G3
5
3 GENERICC_HPD2 R1926 1 2
10K 5% G4 G4
4
OU T
GND_0 2
3
AUX2_BYPSS_EN DPE_DONGLE_DET GND_1 5
2
5 1 15 13 CONFIG 1 GND_2 8
6
11 SCREW1911
GND_3
Q1923A 2 Q1924 R1927 2 11M 5% 14 16
CONFIG 2 GND_6 SCR E W
2
MMDT3904-7 2N7002E
00 唐
1
DP_RECEPTACLE_W/TAB
DPE_CONFIG2
R1928 5.1M 5%
6140073700G
DPF_3N
D1901
R
01 MA 浩 DPF_1N
D1902
DPE_3N
D1911
DPE_1N
D1912
78 工健
15 1 3 15 1 3 15 1 3 15 1 3
DPF_3P DPF_1P DPE_3P DPE_1P
15 2 8 15 2 8 15 2 8 15 2 8
DPF_2N DPF_0N DPE_2N DPE_0N
15 4 15 4 15 4 15 4
DPF_2P 6 DPF_0P 6 DPE_2P 6 DPE_0P 6
15 5 7 15 5 7 15 5 7 15 5 7
9 9 9 9
DNI 10 DNI 10 DNI 10 DNI 10
9) 程 )
ESD8004 ESD8004 ESD8004 ESD8004
DNI MD1904 DNI MD1914

1 2 1 2
課
ESD131-B1-W0201 ESD131-B1-W0201
DNI D1904 DPF_HPD DNI D1914 DPE_HPD
D1903 2 1 D1913 2 1
DPF_AUXN 15 DPE_AUXN 15
15 1 3 15 1 3
DPF_AUXP ESD5V3U1U-02LRH DPE_AUXP ESD5V3U1U-02LRH
15 2 8 15 2 8
4 4
DPF_DONGLE_DET 6 DPE_DONGLE_DET 6
15 5 7 15 5 7
9 9
DNI 10 DNI 10
ESD8004 ESD8004
MSI MS-V381
Custom 5.0
NAVI10 TMDPEF - DP DP
Date: 2019_11_07 Sheet 15 of 35
+3.3V_BUS
00
SOC_RCS_P R11-4871T12-W08 1 R500 2
20
IN
4.02K
1
1%
R11-4021T12-W08
R501 C500 C11-5601012-S02
4.87K 56pF
1% 50V
2
20 SOC_RCS_N 1 R502 2
IN
M
4.02K
2
R11-0101T12-W08 1%
20 SOC_LOC_P 1 R503 2 R11-4021T12-W08
IN
100R 1%
R11-0000062-W08
1
1 R504 2
RD 05 SI
28 FB_VDDCR_SOC
IN
NS500 DNI FB_VSS_SOC 0R R11-0000062-W08 C501 C11-3322822-S02
28,16
IN
FB_VSS_A
X
1 2 1 R505
0R
2 0.0033uF
50V
2
<New PN> C11-475A312-M09
R11-0101T12-W08
SOC_LOC_N NS_VIA 1 R506 2
20
IN
1
100R 1%
GFX_RCS_P 1 R507 2 R11-0102T12-W08R11-0103T12-W08
17 C502 C503
IN 2.37K 4.7uF 0.1uF
(C 36
6.3V 16V
1
1% C11-1042012-M09
R11-2371T12-R01
2
R508 C504 R11-0103T12-W08 R509 R510 R511 R512 R11-0103T12-W08
R11-0282T12-W08 2.8K 100pF 10K 1K 10K 10K
38
1% 50V U500 DNI 1% 1% 1% 1%
C
C11-1011042-M09
2
1 2
VCC
17 GFX_RCS_N R513 RCS_P_L2 IR35217M
IN 2.32K 40 28
RCS_M_L2 RCSP_L2 PWM1 GFX_PWM1 18
1%
39 29
OUT
RCSM_L2 PWM2
R11-2371T12-R01
17 GFX_LOC_P 1 R514 2 VSEN_L2 PWM3 30 GFX_PWM2 17
ON
IN OUT
)2 3
100R 1% VRTN_L2 37 VSEN_L2 PWM4 31
R11-0101T12-W08 36 VRTN_L2 PWM5 32 GFX_PWM3 19
OUT
1
28 FB_VDDCR_GFX 1 R515 2 RCS_P_L1 PWM6 33

IN 2
0R C505 RCS_M_L1 RCSP GFX_PWM4 18
1 2R11-0000062-W08 0.0033uF 3 35
OUT
28,16 FB_VSS_A R516 RCSM PWM1_L2/PWM8
IN 50V
34
0R VSEN_L1 PWM2_L2/PWM7 GFX_PWM5 17
C11-3322822-S02
2
R11-0000062-W08 5
OUT
VRTN_L1 VSEN
17 GFX_LOC_N 1 R517 2 6 VRTN GFX_PWM6 20

IN OUT
F
11
02
100R 1% DNI VRDY1
18 GFX_I1_P R11-0101T12-W08 54 ISEN1 SOC_PWM1 20

IN C506 OUT
18
IN
GFX_I1_N X
1
22pF 50V
2 55
52
IRTN1
ISEN2
VRDY2 4
GFX_PWM7
OUT 19
I
<New
DNIPN> 53 13
w
IRTN2 NC#13
17 GFX_I2_P 50 ISEN3 NC#15 15

IN C507
17
IN
GFX_I2_N X
1
22pF 50V
2 51
48
IRTN3
ISEN4
NC#41 41
VDDCR_GFX_PWR_GOOD
OUT
劉 00 ei DE
<New
DNIPN> 49 IRTN4
19 GFX_I3_P 46 ISEN5 VRHOT_ICRIT# 20

IN C508
19
IN
GFX_I3_N X
1
22pF 50V
<New
DNIPN>
2 47
1
56
IRTN5
ISEN6
IRTN6 SM_ALERT# 23
VDDGFX_SOC_REG_HOT
OUT 3
GFX_I4_P
X
18 GFX_IMON
IN C509
18
IN
GFX_I4_N
1
0R
R518 DNI2
X
1
22pF 50V
2 42
43
ISEN1_L2/ISEN8
IRTN1_L2/IRTN8
IMON 7
1
<New PN> <New
DNIPN> 44
巍 52 st NT
ISEN2_L2/ISEN7 DNI
17
17
IN
GFX_I5_P
GFX_I5_N
1
X
0R
R519 DNI2
X
1
C511
22pF 50V
2
45
9
IRTN2_L2/IRTN7
TSEN1 SVT/SV_ALERT# 17
X C510
1000pF
50V
<New PN>
2
IN <New PN> <New
DNIPN>
20 GFX_I6_P 27 TSEN2/VAUXSEN
IN C512
20
IN
GFX_I6_N
1
X
0R
R520 DNI2
<New PN>
X
1
22pF 50V
<New
DNIPN>
2
14 VINSEN
IOUT_ALERT#/PIN_ALERT# 26
SVT_GFX_SOC
OUT 3
00 an IA
20 SOC_I1_P 24 SM_DIO CFILT 10
IN
1
C513
20
IN
SOC_I1_N X
1
22pF 50V
<New
DNIPN>
2 25
16
SM_CLK
VDDIO/SV_ADDR
TH
TH
57
58
C514
1000pF
50V
C515
1uF
6.3V
1 R521
0R
2 GPIO_4_PCC
OUT 3
19 GFX_I7_P TH 59 R11-0000062-W08
C11-1022012-M09 C11-105A312-M09
2
IN C516
19
IN
GFX_I7_N
1
X
0R
R522 DNI2
<New PN>
X
1
22pF 50V
<New PN>
2
18
19
SVC/SV_CLK
SVD/SV_DIO
TH
TH
TH
60
61
62
g( L
R11-1332T12-W08 63
(3 2
17 GFX_TSEN_P TH
IN
1
12 PWROK/EN_L2/CATFLT TH 64
C517 TH 65
100pF C11-1011042-M09 TH 66
R523 50V
13.3K 8 I_IN TH 67
2
1%
TH 68
R11-0000062-W08
17 GFX_TSEN_N 1 R524 2 TH 70
IN
1
0R 21 EN TH 69
唐
TH 71 C531 R530 R526
00
SOC_TSEN_P 22 ADDR_PROT TH 72 1uF 10K 10K
20
IN 6.3V 5% 5%
1
C11-1052312-M09
2
C11-1032822-M09 I32-352172C-I08
C518 R11-0103012-W08 R11-0103012-W08
1
100pF C11-1011042-M09
R525 Force PWM
R
50V
13.3K
C519
2
1% C525
R11-0000062-W08 0.01uF 1 2
50V R527 R11-8450T12-W08
SOC_TSEN_N 1 R528 2 845R
20 +5V_GATE_DRV
2
IN R11-1332T12-W08
1%
0.1uF 25V L500
01 MA 浩
0R 10%
C11-1042023-M09 1 C11-1042042-M09
2 C11-1069624-M09 C11-1069624-M09
1
+12V_EXT_A R11-2612T12-W08 4.7uH
1 R533 2 U501 20%
23
22
21
20
19
18
C698
1
1
0.01uF L04-47A71T0-T15
26.1K 1% 10V DNI
X
10% C691
VIN
PGND
BOOT
SS
LX
VCC
+12V_EXT_B R11-2612T12-W08 C523 C692 C693 C694 C695 C526
2
R535 0.01uF GFX_SOC_CONFIG C11-1032012-M09 0.1uF 10uF 10uF 10uF 10uF 100uF
1 R534 2 VEN_H 2.5V 1
1K 50V
C11-1032082-M09 POK 10V 16V 16V 16V 16V 6.3V
1% 2 R536 1 2 17
X
26.1K 1% C11-1032822-M09 C11-1069624-M09 C11-1069624-M09 <New PN>
2
2
+12V_BUS_B EN LX
5.1K 3 16
X
DNI R537 R538
78 工健
BIOS PFM LX
1
R11-0103T12-W08 10K 10K R11-0103T12-W08 5%
1 R539 2 4 AGND 15 DNI DNI
1% 1% R11-0512012-W08 PGND
26.1K
<New PN>
1% R11-0102T12-W08 C532
0.01uF
16V DNI
5
6
FB
TON
PGND
PGND
14
13 X X R626
10K
5%
C696
470pF
50V
3,21,33 REGULATOR_SDA
X
R540 12
<New PN>
2
IN PGND
2
<New PN> 10K
<New PN> NS501
AIN
VIN
VIN
5%
1
LX
LX
<New PN>
X
REGULATOR_SCL AMD BIOS
3,21,33 DNI DNI
IN
1
GS9230-ATQ C520
VDDIO_SVI0 DNI DNI R531 <New PN>
X C697 1
X 2 DNI
7
8
9
10
11
X X
+12V_BUS_B 7.5K 470pF 150pF 50V
C527 C528 I9C-S92300C-N03
1
5% 50V
9) 程 )
1
+1.8V 47pF 47pF

R11-0752012-Y01 <New PN> 10%
<New PN>
2
50V 50V
1 R542 2 C530 1 R529 2 NS_VIA
<New PN> <New PN>
2
0.01uF C11-1052523-M09 10.5K

0R 50V R624
442K C521 1%
R11-0000062-W08 1 R532 2 1 2
C11-1032822-M09 R11-1052T12-W08
2
1%
2.2R 1uF 16V R541
VOUT = 5V
5% C11-1042013-M09 1.87K
R11-022A013-W08 1%
1
3 SVC_GFX_SOC
IN R11-4423T22-W08
600KHz C524 C529 C522 R11-1871T12-W08
10uF 1uF 0.1uF
課
3 SVD_GFX_SOC
IN C11-1069624-M09
16V 16V
10%
16V
10%
I_IN
2
C11-1052523-M09
1
DNI DNI DNI DNI
X
<New PN>
C534
47pF
50V X
<New PN>
C535
47pF
50V X R543
10K
1% X
<New PN>
C533
1000pF
50V SN74AHC1G09DBV
2
<New PN>
1
DNI DNI U502B

1
30
IN
VDDGFX_VDDC_EN X R544
100K
1% X
<New PN>
C536
1000pF
50V C537 C11-1032822-M09
0.01uF
2
50V
<New PN> R545
2
10K
3
1%
T33-01G0909-T07
U502A
2,21,30,32 PERST#_BUF 1 VDDGFX_SOC_PWROK
IN R11-0103T12-W08
4
2
SN74AHC1G09DBV
T33-01G0909-T07
MSI MS-V381
Custom 5.0
GFX & SOC CONTROLLER
Dat e: 2019_11_07 Sheet 16 of 25
+12V_EXT_A
00
2 M
GFX_LOC_P 16
OUT
1
DNI GFX_LOC_N 16
OUT
+
X
RD 05 SI
C562 C563 C564 C565 C566 C567 C568
270uF 10uF 10uF 10uF 10uF 1uF 0.1uF
16V 16V 16V 16V 16V 25V 16V L505
1 DNI3
X
0.15uH
2
2
2 4
XX
+VDDCR_GFX
NS509
2
DNI
+5V_GATE_DRV
NS510
DNI
1
1 R564 2 L506
1
2.2R GFX_PH2 1 0.15uH 3
(C 36
1
2 4
29
10
11
U505
8
9
+ + + + + + +
R565 C569 C570 C571 C572 C573 C574 C575
6
VDRV
VCIN
VIN1
VIN2
VIN3
VIN4
10K 1 R566 2 820uF 820uF 820uF 820uF 820uF 820uF 820uF
C
2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V
BOOT 5 1R
2
5% C576
1 R567 2 1 2
C577
2 ZCD_EN* PHASE 7 1 2 1.24K 0.22uF 16V
1%
0.22uF 25V
ON
1
)2 3
16 C578 C579 C580 C581 C582 C583 C584 C585 C586 C587 C588 C589 C590 C591
DNI SW1
NS511
NS512
1
1
17 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF
X X
R568 SW2
10K 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V
SW3 18 DNI DNI
2
SW4 19
2
X
20 R569
SW5 2.2R
1
SW6 21 DNI DNI DNI DNI DNI DNI DNI DNI DNI DNI DNI DNI DNI DNI
DNI
16
IN
GFX_PWM2 1 PWM SW7 22
X X X X X X X X X X X X X X
C592 C593 C594 C595 C596 C597 C598 C599 C600 C601 C602 C603 C604 C605
F
23
X 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF
02
SW8 DNI R570
1
0R 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V
SW9 24
2
X
25 C606
SW10
SW11 26 1000pF
1
I
50V
2
6 DNI C608 C609 C610 C611 C612 C613 C614 C615 C616 C617 C618 C619 C620 C621
R571 C607 SiC620ArCD GH
10K 4.7uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF
6.3V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V
GL1 27
2
1
劉 00 ei DE
DNI
GL2 33 C622
X R572
1
4.7uF 10K
6.3V
C400 C401 C402 C403 C404 C405 C406 C407 C408 C409 C410 C411 C412 C413
GFX_THWN_PH2
2
THWN 30 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF
4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V
2
16 GFX_DIS_N 20 19 18 17 31 DSBL_N PLACE BETWEEN OUTPUT BULK CAP AND ASIC
OUT
巍 52 st NT
GFX_I2_N 16
OUT
1
DNI
CGND1
CGND2
PGND1
PGND2
PGND3
PGND4
PGND5
X
2 NC500
0.01uF
25V
GFX_I2_P
OUT 16
4
32
12
13
14
15
28
X
1DNI R4224 2
00 an IA
0R
5%
1
Colay 302045
R573
10K
1%
GFX_THWN GFX_RCS_P
17,18,19,20 16
2
OUT OUT
GFX_RCS_N 16
g( L
OUT
(3 2
DNI
17,18,19,20 GFX_THWN 1 R574 2
IN
OTP 8.66K 1% GFX_TSEN_P 16
OUT
X
1DNI R627
0R
2
GFX_TSEN_N
OUT 16
1
5%
GFX_THWN R575
X
1DNI R4223 2
OUT 17,18,19,20
47K
1% B-Constant 4050
唐
0R
2
00
+12V_EXT_A 5%
Colay 302045
1
DNI
R
+
C623
270uF
16V
C624
10uF
16V X C625
10uF
16V
C626
10uF
16V
C627
10uF
16V
C628
1uF
25V
C629
0.1uF
16V
1
L507
DNI3
X
0.15uH
2
01 MA 浩
2 4 +VDDCR_GFX
+5V_GATE_DRV
6
1 R576 2 L508
2.2R GFX_PH5 1 0.15uH 3
2 4
29
10
11
U506
3
8
9
R577
78 工健
5
6
VDRV
VCIN
VIN1
VIN2
VIN3
VIN4
10K 1 R578 2
BOOT 5 1R
5% C630
1 R579 2 1 2
C631
2 ZCD_EN* PHASE 7 1 2 1.24K 0.22uF 16V
1%
0.22uF 25V
DNI SW1 16
NS514
NS515
1
1
17
X X
R580 SW2
9) 程 )
10K 18
SW3 DNI DNI
SW4 19
2
16 GFX_PWM5 1 PWM
SW5
SW6
SW7
20
21
22
X R581
2.2R
DNI
GFX_I5_N 16
IN OUT
SW8 23 DNI
X R582
1
24 0R
SW9
X
25 C632 GFX_I5_P
SW10 16
26
OUT
課
DNI SW11 1000pF
1
50V
2
X R583 C633
10K 4.7uF
6.3V
SiC620ArCD GH
GL1
6
27
DNI
GFX_THWN
OUT 17,18,19,20
2
DNI Colay 302045

GL2 33
GFX_THWN_PH5
C634
4.7uF
6.3V X R584
10K
2
16 GFX_DIS_N 20 19 18 17 31 DSBL_N
THWN 30
X
1DNI R4225
0R
5%
2
OUT
1
DNI
CGND1
CGND2
PGND1
PGND2
PGND3
PGND4
PGND5
X NC501
0.01uF
25V
2
4
32
12
13
14
15
28
MSI MS-V381
Custom 5.0
VDDCR_GFX PHASES 2 and 5
Dat e: 2019_11_07 Sheet 17 of 25
00
+VDDGFX_SOURCE1
1
DNI
+
C538
270uF
16V X C539
10uF
16V
C540
10uF
16V
C541
10uF
16V
C542
10uF
16V
C543
1uF
25V
C544
0.1uF
16V
1
L501
DNI3
X
0.15uH
2
2 M
2 4 +VDDCR_GFX
+5V_GATE_DRV
6
1 2
RD 05 SI
R546 L502
2.2R GFX_PH1 1 0.15uH 3
2 4
29
10
11
U503
8
9
R547
6
VDRV
VCIN
VIN1
VIN2
VIN3
VIN4
10K 1 R548 2
BOOT 5 1R
5% C545
1 R549 2 1 2
C546
2 ZCD_EN* PHASE 7 1 2 1.24K 0.22uF 16V
(C 36
1%
0.22uF 25V
DNI SW1 16
NS503
NS504
1
1
17
X X
C
R550 SW2
10K 18
SW3 DNI DNI
SW4 19
2
SW5
SW6
20
21 X R551
2.2R
)2 3 ON
DNI
16 GFX_PWM1 1 PWM SW7 22 GFX_I1_N 16
IN OUT
SW8 23 DNI
X R552
1
24 0R
SW9
X
25 C547 GFX_I1_P
SW10 16
26
OUT
DNI SW11 1000pF
1
50V
2
X R553 C548
10K 4.7uF
6.3V
SiC620ArCD GH 6 DNI
GFX_THWN
OUT 17,18,19,20
F
27
02
GL1
1
DNI
Colay 302045
GL2 33 C549
4.7uF
6.3V X
R554
10K
w I
GFX_THWN_PH1
2
16 GFX_DIS_N 20 19 18 17 31 DSBL_N
THWN 30
X
1DNI R4226
0R
5%
2
OUT
劉 00 ei DE 1
DNI
CGND1
CGND2
PGND1
PGND2
PGND3
PGND4
PGND5
X NC502
0.01uF
25V
4
32
12
13
14
15
28
巍 52 st NT
00 an IA
+12V_EXT_A
1
DNI
+
C550
270uF
C551
10uF
X C552
10uF
C553
10uF
C554
10uF
C555
1uF
C556
0.1uF
L503
g( L
16V 16V 16V 16V 16V 25V 16V
1 DNI3
(3 2
X
0.15uH
2
2 4 +VDDCR_GFX
+5V_GATE_DRV
6
1 R555 2 L504
2.2R GFX_PH4 1 0.15uH 3
唐
2 4
29
10
11
U504
00
3
8
9
R556
6
VDRV
VCIN
VIN1
VIN2
VIN3
VIN4
10K 1 R557 2
BOOT 5 1R
5% C557
1 R558 2 1 2
R
C558
2 ZCD_EN* PHASE 7 1 2 1.24K 0.22uF 16V
1%
0.22uF 25V
16
01 MA 浩
DNI SW1
NS506
NS507
1
1
17
X X
R559 SW2
10K 18
SW3 DNI DNI
SW4 19
2
X
20 R560
SW5 2.2R
SW6 21
DNI
IN OUT
SW8 23
X
DNI R561
1
24 0R
SW9
78 工健
X
25 C559 GFX_I4_P
SW10 16
26
OUT
DNI SW11 1000pF
1
50V
2
X R562 C560
10K 4.7uF
6.3V
SiC620ArCD GH
GL1
6
27
DNI
GFX_THWN
OUT 17,18,19,20
2
DNI Colay 302045

GL2 33 C561
X R563
9) 程 )
4.7uF 10K
6.3V
GFX_THWN_PH4
2
16 GFX_DIS_N 20 19 18 17 31 DSBL_N
THWN 30
X
1DNI R4227
0R
5%
2
OUT
1
課
DNI
CGND1
CGND2
PGND1
PGND2
PGND3
PGND4
PGND5
X NC503
0.01uF
25V
2
4
32
12
13
14
15
28
MSI MS-V381
Custom 5.0
Dat e: 2019_11_07 Sheet 18 of 25
00
+VDDGFX_SOURCE3
1
DNI
X
+
C635 C636 C637 C638 C639 C640 C641
16V 16V 16V 16V 16V 25V 16V L509
1 DNI3
X
0.15uH
2
2 M
2 4 +VDDCR_GFX
+5V_GATE_DRV
6
1 2
RD 05 SI
R585 L510
2.2R GFX_PH3 1 0.15uH 3
2 4
29
10
11
U507
8
9
R586
6
VDRV
VCIN
VIN1
VIN2
VIN3
VIN4
10K 1 R587 2
BOOT 5 1R
5% C642
1 R588 2 1 2
C643
2 ZCD_EN* PHASE 7 1 2 1.24K 0.22uF 16V
(C 36
1%
0.22uF 25V
DNI SW1 16
NS517
NS518
1
1
17
X X
C
R589 SW2
10K 18
SW3 DNI DNI
SW4 19
2
SW5
SW6
20
21 X R590
2.2R
)2 3 ON
DNI
IN OUT
SW8 23 DNI
X R591
1
24 0R
SW9
X
25 C644 GFX_I3_P
SW10 16
26
OUT
DNI SW11 1000pF
1
50V
2
X R592 C645
10K 4.7uF
6.3V
SiC620ArCD GH 6 DNI
GFX_THWN
OUT 17,18,19,20
F
27
02
GL1
1
DNI
Colay 302045
GL2 33 C646
4.7uF
6.3V X
R593
10K
w I
GFX_THWN_PH3
2
16
GFX_DIS_N
GFX_DIS_N 20 19 18 17 31 DSBL_N
THWN 30
X
1DNI R4228
0R
5%
2
OUT
劉 00 ei DE
CGND1
CGND2
PGND1
PGND2
PGND3
PGND4
PGND5
1
DNI
X NC504
0.01uF
4
32
12
13
14
15
28
25V
巍 52 st NT
00 an IA
+12V_EXT_B
1
DNI
+
C647
270uF
X C648
10uF
C649
10uF
C650
10uF
C651
10uF
C652
1uF
C653
0.1uF
L511
g( L
16V 16V 16V 16V 16V 25V 16V
1 DNI3
(3 2
X
0.15uH
2
2 4 +VDDCR_GFX
+5V_GATE_DRV
6
1 R594 2 L512
2.2R GFX_PH7 1 0.15uH 3
唐
2 4
29
10
11
U508
00
3
8
9
R595
6
VDRV
VCIN
VIN1
VIN2
VIN3
VIN4
10K 1 R596 2
BOOT 5 1R
5% C654
1 R597 2 1 2
R
C655
2 ZCD_EN* PHASE 7 1 2 1.24K 0.22uF 16V
1%
0.22uF 25V
16
01 MA 浩
DNI SW1
NS520
NS521
1
1
17
X X
R598 SW2
10K 18
SW3 DNI DNI
SW4 19
2
16 GFX_PWM7 1 PWM
SW5
SW6
SW7
20
21
22
X R599
2.2R
DNI
GFX_I7_N 16
IN OUT
SW8 23
X
DNI R600
1
24 0R
SW9
78 工健
X
25 C656 GFX_I7_P
SW10 16
26
OUT
DNI SW11 1000pF
1
50V
2
X R601 C657
10K 4.7uF
6.3V
SiC620ArCD GH
GL1
6
27
DNI
GFX_THWN
OUT 17,18,19,20
2
DNI
Colay 302045
GL2 33 C658
X R602
9) 程 )
4.7uF 10K
6.3V
GFX_THWN_PH7
2
16
GFX_DIS_N
GFX_DIS_N 20 19 18 17 31 DSBL_N
THWN 30
X
1DNI R4229
0R
5%
2
OUT
1
課
DNI
CGND1
CGND2
PGND1
PGND2
PGND3
PGND4
PGND5
X NC505
0.01uF
25V
2
4
32
12
13
14
15
28
MSI MS-V381
Custom 5.0
Dat e: 2019_11_07 Sheet 19 of 35
00
+VDDGFX_SOURCE6
1
DNI
+
C659
270uF
16V X C660
10uF
16V
C661
10uF
16V
C662
10uF
16V
C663
10uF
16V
C664
1uF
25V
C665
0.1uF
16V
1
L513
0.15uH DNI3
2
X
2 M
2 4 +VDDCR_GFX
+5V_GATE_DRV
6
1 2
RD 05 SI
R603 L514
2.2R GFX_PH6 1 0.15uH 3
2 4
29
10
11
U509
8
9
R604
6
VDRV
VCIN
VIN1
VIN2
VIN3
VIN4
10K 1 R605 2
BOOT 5 1R
5% C666
1 R606 2 1 2
C667
2 ZCD_EN* PHASE 7 1 2 1.24K 0.22uF 16V
(C 36
1%
0.22uF 25V
DNI SW1 16
NS523
NS524
1
1
17
X X
C
R607 SW2
10K 18
SW3 DNI DNI
SW4 19
2
SW5
SW6
20
21 X R608
2.2R
)2 3 ON
DNI
IN OUT
SW8 23 DNI
X R609
1
24 0R
SW9
X
25 C668 GFX_I6_P
SW10 16
26
OUT
DNI SW11 1000pF
1
50V
2
X R610 C669
10K 4.7uF
6.3V
SiC620ArCD GH 6 DNI
GFX_THWN
OUT 17,18,19
F
27
02
GL1
1
DNI
Colay 302045
GL2 33 C670
4.7uF
6.3V X
R611
10K
w I
GFX_THWN_PH6
2
16 GFX_DIS_N 19 18 17 31 DSBL_N
THWN 30
X
1DNI R4230
0R
5%
2
OUT
劉 00 ei DE 1
DNI
CGND1
CGND2
PGND1
PGND2
PGND3
PGND4
PGND5
X NC506
0.01uF
25V
4
32
12
13
14
15
28
巍 52 st NT
1
R612
10K
1%
SOC_RCS_P 16
2
OUT
SOC_RCS_N 16
OUT
00 an IA
+VDDSOC_SOURCE
SOC_LOC_P 16
OUT
1
DNI SOC_LOC_N 16
OUT
+
C671
270uF
C672
10uF
X C673
10uF
C674
10uF
C675
10uF
C676
1uF
C677
0.1uF
ML516 DNI
g( L
16V 16V 16V 16V 16V 25V 16V
1 3
(3 2
X
0.47uH
2
2 4 +VDDCR_SOC
2
XX
+5V_GATE_DRV
NS526
NS527
DNI
DNI
1 R613 2 L516
1
2.2R SOC_PH 1 0.33uH 3
1
唐
2 4
29
10
11
U510 DNI DNI DNI DNI
00
3
8
9
C678 C679 C680 C681 C682 C683 +

R614 C684
6
VDRV
VCIN
VIN1
VIN2
VIN3
VIN4

4V 4V 4V 4V 4V 4V 2.5V
BOOT 5 1R
2
5% C685
1 R616 2 1 2
X X X
R
C686
2 ZCD_EN* PHASE 7 1 2 1.15K 0.22uF 16V
1%
0.22uF 25V
16
01 MA 浩
DNI VSWH1
NS528
NS529
1
1
17
X X
R617 VSWH2
10K 18
VSWH3 DNI DNI
VSWH4 19
2
16 SOC_PWM1 1 PWM
VSWH5
VSWH6
VSWH7
20
21
22
X R618
2.2R
DNI
SOC_I1_N 16
IN OUT
VSWH8 23
X
DNI R619
1
24 0R
VSWH9
78 工健
X
25 C687 SOC_I1_P
VSWH10 16
26
OUT
VSWH11 1000pF
1
50V
2
6 DNI
R620 C688 NC1
10K 4.7uF
6.3V
GL1 27
2
SIC632ACD-T1-GE3 DNI
GL2 33 C689
X R621
9) 程 )
4.7uF 10K
6.3V
SOC_THWN DNI
2
THWN 30 1 R622 2
DNI 8.66K 1%
31 DSBL_N 1
X
R628
0R
5%
2
DNI
SOC_TSEN_P
OUT 16
1
X
R625 2 SOC_TSEN_N
OUT 16
1
0R
1
5%
課
DNI R623
CGND1
CGND2
PGND1
PGND2
PGND3
PGND4
PGND5
X
47K
NC507 1%
0.01uF
2
25V
2
4
32
12
13
14
15
28
MSI MS-V381
Custom 5.0
VDDCR_GFX PHASES 6 and VDDCR_SOC
Dat e: 2019_11_07 Sheet 20 of 35
00
+3.3V_BUS
3,21 MVDD_VDDCI_OCP# 1 R773 2

OUT
10K
5%
R11-0103012-W08
M
MVDD_PGOOD 2 R701 1
2
21
OUT
10K
5%
R11-0103012-W08
21 VDDCI_PGOOD 2 R700 1
OUT
RD 05 SI
10K
5%
R11-0103012-W08
+3.3V_BUS
(C 36 C
5
NC7SZ08P5X U700B
U700A
1
1
2,16,30,32 PERST#_BUF
NC7SZ08P5X
ON
IN
)2 3
MVDD_PGOOD MVDD_VDDCI_PWRGD 4 C700
1 2 2
21 R702
0.1uF
6.3V +5V_GATE_DRV +12V_BUS_B
0RR11-0000062-W08
2
C11-1042312-M09
X
VDDCI_PGOOD T70-7SZ0850-F01 T70-7SZ0850-F01
21 1 R703 2 1 R704 2
1
DNI DNI
0RR11-0000062-W08
X C808
6.3V
<New PN>
3.3R R712 R705
1%
1K
F
+1.8V R11-033A023-Y01 R11-0102T12-W08
02
2
<New PN>
0R
R707
1
2.2R
R708 2
VDDIO_SVI1
MVDD_VDDCI_DRON 47K R11-0473U12-W08
22,23 MVDD_CSSUM
5%
21 VCC1 OUT 1 2 MVDD_ISENP1
21 R706 22,21
IN
1
I
R11-022A012-W08
w
MVDD_PWM1 22
R11-0000062-W08 OUT
1
0.1%
C701 MVDD_CSCOMP R11-0473U12-W08
1uF
AGND1
1 2 1 2 1 R709 2 1 2 1 2 MVDD_ISENP2
6.3V 4.7uF C703 C704 0.01uF R714 R715 MVDD_ISENN1
IN 22,21 21 R710 R711
IN 22,21
1
C11-105A312-M09 10K 1%
0R 47K 100K 47K
0.1% R11-0473U12-W08
2
10V 25V 5% 0.1% 1%
劉 00 ei DE
R11-0103T12-W08 C705 R11-0000062-W08 R713 R11-0104T22-W08
C11-4757422-S02 C11-1032082-M09
1
C702
1 2 1 2
MVDD_VDDCI_PWROK
DNI 0.01uF
50V
50V
820pF
11
13
31 C707 R717 C11-1032822-M09
2
OUT U701 1 2 C11-8212822-M09
0.1uF 1%
25V
R718 MVDD_ISENP1
IN 22,21 MVDD_ILM 100K
1% C706
VCC
VRMP
SVD_MVDD_VDDCI_VR 1 1 R716 2 1 2
31 BI PWROK C11-1042612-W08 2.49K 21 R51-0104T12-M09
2
1%
2 32 AGND1
1 2
VR_SVT1
3
SVD DRON
31
<New PN> R11-2491T12-W08 23.7K
1% 50V
31
OUT
SVT_MVDD_VDDCI_VR R721 SVT PWM1/SR R11-2372T12-W08 1000pF
0RR11-0000062-W08
4
5
SVC CSN1 34
33 X C11-1022012-M09
巍 52 st NT
31 SVC_MVDD_VDDCI_VR VDDIO CSP1 R719 R720 DNI
IN
AGND1
1 2
R724
1K
1% 3.4K1
1% DNI
C708 10R R11-0100T12-W08
24.9K XR722 21
X 2 1 R723 2 MVDD_ISENN1
IN 22,21
1
1%
30 VDD_MEM_VDDCI_EN 10 EN R11-2492T12-W08
IN R11-0342T12-W08 1%
R11-0102T12-W08 1%
29 <New PN> 50V
C11-6811812-M09
MVDD_PGOOD
9
PWM2/IMAXNB
38 1 2 VCC1
C709 <New PN>
1
10R 2 MVDD_ISENN2
680pF R11-0100T12-W08 21 VDD_PWRGD CSN2 R737 21 MVDD_DROOP 0.0022uF
50V
R725
IN 22,21
1
AGND1
37 1 2
MVDD_FB 10R CSP2
2K 21 C11-2222832-M09 R727 1%
2
C713 1%
R729
100K X C712 21 1 R730 2 1 2 1 R731 2
R11-475AT12-W08
330pF R11-6811T12-W08
0.0022uF 50 37.4K
R11-0202T12-W08
MVDD_PWM2
0R
R11-0000062-W08
R11-0100T12-W08
00 an IA
DNI 1% DIFF 22 MVDD_CSREF
1% 50V OUT
AGND1
<New PN> 50V 30 1 2
R11-0104T22-W08 DNI 47.5R 6.81K PWM3/IMAX R736 21
2
1
C715 C716
<New PN> 1 R733 2 1 R734 21 2 1 R735 21 2 47 COMP CSN3 36
X0.0056uF
C717
16V
24.9K1%
R11-2492T12-W08
1%
1K C11-3312012-M09
50V 1%
47pF
C11-2222832-M09
50V
CSP3 35
1%
R11-3742T12-R01
0.01uF 0R
1 R726 2 MVDD_ISENN2
IN 22,21
C714
1000pF
50V
1
48 R11-0000062-W08
C11-5622612-M09 R11-0102T12-W08 FB DNI C11-1022012-M09
2
2
1
C718
1 R738
1%
2
DNI
1
MVDD_FB 50V
2 2%
49 TRBST
PWM4/ADD
CSN4
28
39
0.1uF
C711 R728
DNI C710
50V
1
X R751
1%
2
<New PN>
VCC1
21
9 FB_MVDD_1 1 R825 2 AGND1 1

XR845 2 21 C11-4701862-M09 CSP4 40
1% C11-1032822-M09 2.49K AGND1
g( L
2
IN 25V
1 R732 2
(3 2
MVDD_ISENP2
0R 1% C11-1042612-W08 22,21
2
IN
9
IN
FB_MVDD_2 R11-0000062-W08
1 R823
X 2 DNI AGND1 <New PN>
FB_MVDD_VR MVDD_CSSUM <New PN>
R11-2491T12-W08
DNI
AGND1
1%
28
IN
FB_VDDIO_MEM <New PN>
DNI 1
X
R821 2
1 R819
1K
2
FB_MVDD_VSS_VR
51 VDD CSSUM 43
MVDD_CSCOMP
21
X
AGND1 1
X
R741 2
1
<New PN> 0.1%

52 44 <New PN>
R11-0102U12-Y01 DNI VSS CSCOMP 21 45.3K
1
AGND1
28
9
IN
FB_VSS_B
FB_MVSS_1 1 R824 2
DNI 1
<New PN> X
R822 2 R818
2K
0.1%
C11-3312012-M09
C720
50V
330pF
DNI C721 DNI C722 1
24.9K
R745 2
R11-2492T12-W08
42 IOUT ILIM 46
MVDD_ILM
21
1 R743 2
R11-4532T12-W08
1%
2
IN 16V 16V 1% C723
唐
1 R820 2 1 2
0R R11-0202U12-R01 <New PN> <New PN>
2
00
9
IN
FB_MVSS_2 1
X R826
<New PN>
2
DNI
R11-0000062-W08
0R
R11-0000062-W08
X
AGND1 X
AGND1
AGND1 0.1uF
21
16V C11-1042012-M09
VDDCI_PGOOD
8 VDDNB_PWRGD
DROOP 45
MVDD_DROOP
MVDD_CSREF
21 1
2K
R748
R11-0202012-Y01
2 VCC1
21
21
VDDCI_CSSUM
1
47K
R746 2 VDDCI_ISENP1 23,21
IN
AGND1
CSREF 41 21
R
R11-0473U12-W08
VDDCI_FB 680pF
C725 10R 330pF 17 DIFFNB VDDCI_CSCOMP 47K
0.1%
R11-0473U12-W08
21
X
1
DNI
R753 2 1
C11-6811812-M09
2 1 R754
1%
2
47.5R
1 R755 21
C726
2 1
6.81K
R756 21
0.0022uF
C727
2 19 COMPNB
10K
21 1 R749 2 1
100K
R750
1%
2
1
50V 0.1%
<New PN> R11-0100T12-W08 27 VDDCI_PWM1 R11-0104T22-W08
01 MA 浩
1%
R11-475AT12-W08 C11-2222832-M09 PWM1NB/SRNB 23 R752
OUT
AGND1
C11-3312012-M09
50V 1%
R11-6811T12-W08 50V C724
C729 1 R758 2 CSN1NB 26 1 R759 2 1 2 1 2
1% 47pF CSP1NB 25 1% 50V
1000pF
16V
0.0056uF 24.9K
R11-2492T12-W08 1 R760 2 1
C730
2 2% 16 FBNB R11-0103T12-W08 VDDCI_ILM 16.5K2 100K C11-1022012-M09
2
1
C11-5622612-M09 C11-4701862-M09 1%
R51-0104T12-M09 C728
1 R757 1 2
1K 1%
R11-0102T12-W08 21
50V
VDDCI_FB
18
0.01uF 10R
1 R763 2 VDDCI_ISENN1
21
50V
TRBSTNB VDDCI_CSSUM C731
IN 23,21 R11-1652T12-W08 1000pF
1
1%
24 C11-1022012-M09
AGND1 CSSUMNB 21 0.1uF DNI 50V 1% R11-0342T12-W08
VDDCI_CSCOMP C733
X R767 C11-1032822-M09 R11-0100T12-W08 3.4K
2
22 1 R768 2
0R FB_VDDNB CSCOMPNB 21 VDDCI_ISENP1 23,21 R761 R762 DNI
78 工健
25V 1% IN
28 FB_VDDCI_MEM 1 R769 2 15 VDDNB
C11-1042612-W08
2.49K 1K DNI 10R
2
IN 1% 1%
1
1% C732
R11-0000062-W08
1 R770 2
<New PN>
AGND1 R11-2491T12-W08 R11-0102T12-W08
1
XR765 21
X 2 1 R766 2 VDDCI_ISENN1
IN 23,21
AGND1
1
X
+VDDCI_MEM 23
DNI NS702 FB_VDDCI_LOC DNI C735
25.5K
1%
IOUTNB VDDCI_ILM 1% 1%
X
2 1 1 2 20 <New PN> 50V R11-0100T12-W08
R764
16V
1
R11-2552T12-W08
C737
2
ILIMNB 21 0.0022uF C734 <New PN>
<New PN> <New PN> VDDCI_DROOP
C11-2222832-M09 0R
2
50V
100R
5%
R11-0101012-W08 0.1uF 16V 21 1 R771 2
1
C11-1042012-M09 6 SCL VDDCI_DROOP R11-0000062-W08
3,16,33 REGULATOR_SCL AGND1 7 SDA DROOPNB 21 21 C736
IN
9) 程 )
14 OCP_L 1000pF 50V
REGULATOR_SDA C11-1022012-M09
3,33,16 BI
2
AGND_59
AGND_57
AGND_55
AGND_54
AGND_56
AGND_58
AGND_60
AGND_1
MVDD_VDDCI_OCP#
ROSC
3 21
AGND1
NCP81022 NS700 DNI

12
59
57
55
53
54
56
58
60
I32-810220C-O05
X
1 2
課
<New PN>
NS701 DNI
30K
R774
1% X
1 2
<New PN>
R11-0303T12-W08
AGND1
AGND1 AGND1
MSI MS-V381
Custom 5.0
MVDD_VDDCI CONTROLLER
Dat e: 2019_11_07 Sheet 21 of 35
+12V_BUS_B
00
2 M
C11-106A524-M09 C11-1042012-M09
1
DNI
+
X
RD 05 SI
C738 C739 C740 C741 C742 C743 C744
10uF
270uF
16V 10uF
16V 16V 10uF
16V 10uF
16V 1uF
25V 0.1uF
16V
1
L700 DNI
3
X
C11-1062537-S02 C11-105A612-M09 0.47uH
2
2
C71-27117Z1-AO5 2 4 +VDD_MEM
C11-106A524-M09
+5V_GATE_DRV
6
1 R775 2 L701
1 3
2.2R MVDD_PH1
0.33uH
(C 36
R11-022A013-W08
1
2 4
29
10
11
U702 DNI DNI DNI DNI DNI DNI
8
9
R776
X C745 C746
X X X
C747 C748 C749 C750 C751
X
C752 C753
X C754 C755 C756 +

C757
+
C758
6
VDRV
VCIN
VIN1
VIN2
VIN3
VIN4
1 2
10K R777 22uF
22uF 22uF 22uF 22uF
22uF 22uF 22uF
22uF 22uF
22uF 22uF 820uF 820uF
C
L04-33B7410-T15 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 2.5V 2.5V
5
BOOT
1R C11-226A224-M09 C11-226A224-M09
C11-226A224-M09 C11-226A224-M09 C11-226A224-M09
C11-226A224-M09
C71-82103F1-AO5
C71-82103F1-AO5
2
5%
R11-0103012-W08 R11-0010023-Y01
C760
2 ZCD_EN* PHASE 7 1 2
25V
0.22uF
)2 3 ON
C11-224A612-M09
DNI SW1 16
NS704
NS705
1
1
X R779
10K
SW2
SW3
SW4
17
18
19 DNI
XX DNI
2
X
20 R780
SW5 2.2R
SW6 21
DNI
21 MVDD_PWM1 1 PWM SW7 22
IN
F
23
X
02
SW8 DNI R781
1
24 0R
SW9
X
25 C761
SW10
SW11 26 1000pF
1
I
50V
w
DNI
2
X 6 DNI
R782 C762 GH
10K
4.7uF
6.3V
SiC620ArCD
GL1 27
C11-475A312-M09
1
劉 00 ei DE
DNI
Colay 302045
GL2 33 C763
4.7uF
6.3V X
C11-475A312-M09
R783
10K MVDD_ISENN1
OUT 21
2
THWN 30
MVDD_ISENP1 21
OUT
21,22,23
IN
MVDD_VDDCI_DRON 1 R827
0R
5%
2
X
1DNI R4231
0R
5%
2 31 DSBL_N
巍 52 st NT
R11-0000062-W08 MVDD_THWN
22,23
OUT
1
DNI
CGND1
CGND2
PGND1
PGND2
PGND3
PGND4
PGND5
X
2 C809
0.01uF
25V
4
32
12
13
14
15
28
I33-302150C-O05
00 an IA OTP
g( L
1
X 2
(3 2
R842
100R
5%
00 唐
+12V_BUS_B
1
DNI
R
+
C764
270uF
16V
C765
10uF
16V X C766
10uF
16V
C767
10uF
16V 10uF
16V
C768 C769
1uF
25V
C770
0.1uF
16V
1
L702 DNI
3
X
C71-27117Z1-AO5 C11-1062537-S02 C11-106A524-M09
C11-106A524-M09
C11-105A612-M09
C11-1042012-M09 0.47uH
2
01 MA 浩
2 4 +VDD_MEM
+5V_GATE_DRV
6
1 R787 2 L703
1 3
2.2R
R11-022A013-W08
MVDD_PH2
0.33uH
2 4
29
10
11
U703
3
8
9
R788
78 工健
5
6
VDRV
VCIN
VIN1
VIN2
VIN3
VIN4
1 2
10K 5
R789
L04-33B7410-T15
BOOT
1R
5%
R11-0103012-W08 R11-0010023-Y01
C772
25V
0.22uF
C11-224A612-M09
DNI VSWH1 16
NS707
NS708
1
1
X R791 VSWH2 17
XX
9) 程 )
10K 18
VSWH3
VSWH4 19 DNI DNI
2
21 MVDD_PWM2 1 PWM
VSWH5
VSWH6
VSWH7
20
21
22
X R792
2.2R
DNI
MVDD_ISENN2 21
IN OUT
VSWH8 23 DNI
X R793
1
24 0R
VSWH9
X
25 C773 MVDD_ISENP2
VSWH10 21
26
OUT
課
VSWH11 1000pF
1
50V
DNI
2
X R794
10K
C774
4.7uF
6.3V
C11-475A312-M09
NC1
GL1
6
27
DNI
MVDD_THWN
OUT 22,23
2
DNI
SIC632ACD-T1-GE3
Colay 302045
GL2 33 C775
4.7uF
6.3V X
C11-475A312-M09
R795
10K
2
THWN 30
21,22,23
IN
MVDD_VDDCI_DRON 1 R828
0R
5%
2
R11-0000062-W08
X
1DNI R4232
0R
5%
2 31 DSBL_N
1
DNI
CGND1
CGND2
PGND1
PGND2
PGND3
PGND4
PGND5
X C810
0.01uF
25V
2
4
32
12
13
14
15
28
I33-302150C-O05

MS-V381
1
X R843
100R
5%
2
MSI
Custom 5.0
REG MVDD
Dat e: 2019_11_07 Sheet 22 of 35
00
2 M
+12V_BUS_B
1
RD 05 SI
DNI
+
C776 C777 C778 C779 C780 C781 C782
16V 16V 16V 16V 16V 25V 16V
L704 DNI
2
2
1 0.47uH 3
+VDDCI_MEM
+5V_GATE_DRV 2 4
6
1 R797 2
(C 36
2.2R VDDCI_PH 1 L705 3
1
2 4
29
10
11
U704 0.33uH DNI DNI DNI DNI
8
9
C783 C784 C785 C786 C787 C788 +
C
R798 C789
6
VDRV
VCIN
VIN1
VIN2
VIN3
VIN4
4V 4V 4V 4V 4V 4V 2.5V
BOOT 5 1R
2
5%
C791
)2 3 ON
0.22uF 25V
DNI SW1 16
NS712
NS713
1
1
R801 SW2 17
10K 18
SW3
SW4 19 DNI DNI
2
20 R802
SW5 2.2R
SW6 21
F
DNI
VDDCI_PWM1 1 22 VDDCI_ISENN1
02
21 PWM SW7 21
IN 23
OUT
SW8 DNI R803
1
24 0R
SW9
25 C792 VDDCI_ISENP1
SW10 21
OUT
I
26
w
DNI SW11 1000pF
1
50V
SiC620ArCD
2
6 DNI
R804 C793 GH
10K 4.7uF
6.3V
劉 00 ei DE
GL1 27
1
DNI
GL2 33 C794 R805
Colay 302045 4.7uF 10K
6.3V
2
THWN 30 VDDCI_THWN 23
OUT
21,22
IN
MVDD_VDDCI_DRON 1 R829 2
X
1DNI R4233 2 31 DSBL_N
巍 52 st NT
0R 0R
5% 5%
1
DNI
CGND1
CGND2
PGND1
PGND2
PGND3
PGND4
PGND5
C811
0.01uF
25V
2
4
32
12
13
14
15
28
00 an IA
(3 2 g( L 1 R841
100R
5%
2
1 MR839
0R
5%
2
+1.8V +3.3V_BUS
00 唐
DNI
1 R839 2
0R
5%
R
R837
15.4K
1%
01 MA 浩
R834 1 R838 2
10K 57.6K
1%
5
1%
1
U2 R840
1 10K
DNI R835 1%
MVDD_THWN 1 R830 2 100K
V+
22
IN 10K
1%
4
Place@HOT SPOT LMV331 MVDD_VDDCI_REG_HOT 3
78 工健
2
1% OUT
DNI DNI
V-
23 VDDCI_THWN 1 R831 2 1 R832 2 3
IN
1
10K 57.6K
1% 1%
C807
1
1uF
2
6.3V
R833 R836 C805 C806
2
10K 4.75K 1000pF 1000pF
1% 1% 50V
10%
50V
10%
2
9) 程 ) 1
DNI
2
課
R844
0R
5%
MSI MS-V381
Custom 5.0
REG VDDCI
Dat e: 2019_11_07 Sheet 23 of 35
00
2
RD 05 SI M FB_0V75_N
FB_0V75_P
(C 36 C
X
)2 3 ON
+12V_BUS_B
B900 DNI
1 2
+3.3V_BUS 30R
1
B901
1 2 C900 C901 C902 C903 C928
F
30R 10uF 10uF 10uF 10uF 0.1uF
02
16V 16V 16V 16V 16V
+12V_BUS_B
2
+3.3V_BUS
w I
0V75_CSP
劉 00 ei DE
R900
1R
C904 1% R901
0.033uF 10K
16V 1%
0V75_CSN
2
1
C905 R902 +0.75V_PG 30

0.047uF 3.01K OUT
16V 1%
1
2
巍 52 st NT
C906
10uF
16V
R903
2
301K
1%
15
1
U901
+0.75V_PH
VCC
13 CSP PGOOD 6 C907
10uF
16V
12 1 R905 2 1 R906 2
00 an IA
CSN
2
VCCP 1 24.3K 1% 2K 1%
2
0V8 DNI DNI
NS900
NS901
1
C908
1 2 10 VSEN
4 Q900
BOOT C909
1
47pF 50V 0.22uF 9 +0.75V
25V
6
8 COMP 4 2 4
X X
2
C910
1 R907 2 1 2 UG 5 3
1
3.01K 1% 68nF 50V 2 1 3
g( L
9 1
(3 2
C929 R908 FB L900 2.2uH
1
1000pF 12.4K C930
1 2DNI PHASE 3 10 DNI
50V 0.1%
470pF 50V 5 + +
DNI C911 C931 C932 C912 C913
2
11 6 0.1uF 22uF 22uF 330uF 330uF

FBG
X X 4V 4V 4V 2V 2V
LG 2 8 7
2
14 ROSC/EN THM
THM
17
18
PE642DT X
唐
THM 19
00
7 20
GND
R909 SYNC THM

41.2K
R925 1%
100K
16
1%
3
GS7260
R910
R
5 Q903A 0R
5%
2N7002DW
6
+0.75V_EN 2 Q903B
01 MA 浩
30
IN
2N7002DW
R926
1
1
49.9K
1% DNI
R927 C941
100K 100pF
1% 50V
DNI
X
2
78 工健
9) 程 )
課
MSI MS-V381
Custom 5.0
REG 0.75V
Dat e: 2019_11_07 Sheet 24 of 35
00
2
RD 05 SI M FB_1.8V_N
FB_1.8V_P
(C 36 C
)2 3 ON
DNI
+12V_BUS_B
X
B902
1 2
+3.3V_BUS 30R
1
B903
1 2 C914 C915 C916 C917 C933
F
30R 10uF 10uF 10uF 10uF 0.1uF
02
16V 16V 16V 16V 16V
+12V_BUS_B
2
+3.3V_BUS
w I
1V8_CSP
劉 00 ei DE
R911
1R
C918 1% R912
0.033uF 10K
16V 1%
1V8_CSN
2
1
C919 R913 1.8V_PWR_GOOD 30

0.047uF 3.01K OUT
16V 1%
1
2
巍 52 st NT
C920
1uF
16V
R914
2
301K
1%
15
1
U902
+1.8V_PH
VCC
13 CSP PGOOD 6 C921
1uF
16V
12 1 R916 2 1 R917 2
00 an IA
CSN
2
VCCP 1 24.3K 1% 2K 1%
2
0V8 DNI DNI
NS902
NS903
1
C922
1 2 10 VSEN
4 Q902
BOOT C923
1
47pF 50V 0.22uF 9 +1.8V
L902
25V
6
8 COMP 4 2 4 DNI
X X
2
C924
1 R918 2 1 2 UG 5 3 1 2
1
3.01K 1% 68nF 50V 2 1 3 0.47uH
g( L
9 1
(3 2
C934 R919 FB L901 2.2uH Co-l ay
1
1000pF 1.5K C935
1 DNI2 PHASE 3 10 DNI 1 R920 2
50V 1%
470pF 50V 5 + +
DNI C925 C936 C937 C926 C927 0R
2
11 6 0.1uF 22uF 22uF 470uF 100uF

FBG
X X LG 2 8 7
4V 4V 4V 2.5V 4V
1 R921 2
2
14 ROSC/EN THM
THM
17
18
PE642DT X 0R
唐
R915 THM 19
00
100K 7 20
GND
1% R922 SYNC THM

3
41.2K
1%
5 Q904A
16
GS7260
2N7002DW R923
R
6
0R
4
5%
+1.8V_EN 2 Q904B
30,2
IN
2N7002DW
01 MA 浩
R928
1
1
49.9K
1%
R929 C940 DNI
100K 100pF
1% 50V
DNI
X
2
78 工健
9) 程 )
課
MSI MS-V381
Custom 5.0
REG 1.8V
Dat e: 2019_11_07 Sheet 25 of 35
00
2
RD 05 SI M REGULATOR FOR +5V RAILS
IOUT = 50mA
(C 36 C
)2 3 ON +12V_BUS_B +5V_VESA
F
U303
02
F400
3 IN VR5V OUT 2 1 2
1
200mA
24V
GND
TAB
w I
C431 C425 C426 C430
10uF 1uF 10uF 1uF
4
16V
20%
6.3V 16V
20%
6.3V
10%
2
AZ1117CH-5.0
劉 00 ei DE
巍 52 st NT
00 an IA
+3.3V_BUS
+3.3V_BUS
+5V_GATE_DRV
DNI
1
X
MR700 2 R808
g( L
10K
(3 2
0R
2 R809 1 VPP_PWR_GOOD 30
OUT
1R
1
1%
C795 +VPP
10uF
6.3V
2
U705
00 唐
10 VDD POK 1
NS715
1
9 EN VOUT 3 DNI
R
VOUT 4 2
6 VIN1 VOUT 5
1
7
8
VIN2
2
VPP_FB
X C798
01 MA 浩
VIN3 FB C796 C797
VPP_EN 10uF 10uF 0.1uF
30
IN 6.3V 6.3V
1
1
16V
11 TH1 TH3 13 DNI
2
C800 12 TH2 TH4 14 R810 C801
10uF 2.4K OHM 0.0012uF
6.3V 1% 50V
1
GS7162TD-R
2
C799
0.01uF
16V X
78 工健
2
R471
1.2K OHM
1%
9) 程 )
課
MSI MS-V381
Custom 5.0
SMALL RAIL REGULATORS
Dat e: 2019_11_07 Sheet 26 of 35
00 +VDDCI_MEM decoupling caps (1uF - 0402) +VDDCI_MEM decoupling caps (22uF - 0805)
2 M
C1540 - C1549
+VDDCI_MEM +VDDCI_MEM
C1684 - C1687 C1640 - C1642
RD 05 SI
1
+VDDCR_GFX +VDDCR_GFX decoupling caps (1uF - 0402)
C1670 C1671 C1672 C1673 C1674 C1675 C1676 C1677 C1678 C1679 C1686 C1640 C1641
C1200 - C1329 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 22uF 22uF 22uF
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 4V 4V 4V
2
1
1
C1200 C1202 C1203 C1204 C1205 C1207 C1208 C1209
1
10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF
4V 4V 4V 4V 4V 4V 4V 4V C1697 C1696 C1695 C1694 C1693 C1692
(C 36
2
2
+VDDIO_MEM decoupling caps (1uF - 0402) 1uF 1uF 1uF 1uF 1uF 1uF
1
1
+VDD_MEM 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2
C1210 C1211 C1215 C1216 C1217 C1218 C1219 C1450 - C1509
10uF 10uF 10uF 10uF 10uF 10uF 10uF
1
4V 4V 4V 4V 4V 4V 4V
2
2
C1452 C1454 C1455 C1463 C1458 C1459
1
1
1uF 1uF 1uF 1uF 1uF 1uF
C1220 C1221 C1222 C1226 C1227 C1228 C1257 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V +VDDCI_MEM
ON
2
)2 3
10uF 10uF 10uF 10uF 10uF 10uF 10uF
4V 4V 4V 4V 4V 4V 4V
2
1
1
1
C1330 C1331 C1332 C1333 C1334 C1335 C1336 C1337 C1338 C1339
C1239 C1241 C1242 C1243 C1245 C1246 C1247 C1249 C1254 C1255 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF
4V 4V 4V 4V 4V 4V 4V 4V 4V 4V
10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF
2
4V 4V 4V 4V 4V 4V 4V 4V 4V 4V
2
F
1
1
02
C1260 C1261 C1262 C1263 C1264 C1265 C1266 C1267 C1268 C1269
C1340 C1341 C1342 C1343 C1344 C1345 C1346 C1347 C1348 C1349
10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF
4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V
2
2
w I
1
1
C1270 C1271 C1272 C1273 C1278 C1279 +VDDCI_MEM decoupling caps (10uF - 0402)
4V 4V 4V 4V 4V 4V
劉 00 ei DE
2
2
1
C1280 C1281 C1282 C1283 C1284 C1285 C1286 C1287 C1288 C1289
4V 4V 4V 4V 4V 4V 4V 4V 4V 4V
2
2
1
C1290 C1291 C1292 C1293 C1294 C1295 C1296 C1297 C1298 C1299
巍 52 st NT
4V 4V 4V 4V 4V 4V 4V 4V 4V 4V
2
2
1
+VDDIO_MEM decoupling caps (22uF)

C1301 C1302 C1303 C1304 C1305 C1306 C1307 C1308 C1309
10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF C1510 - C1539
4V 4V 4V 4V 4V 4V 4V 4V 4V
2
+VDD_MEM 080 5
00 an IA
1
C1310 C1311 C1312 C1313 C1314 C1315 C1316 C1317 C1318 C1319
1
4V 4V 4V 4V 4V 4V 4V 4V 4V 4V
2
C1487 C1698
1
22uF 22uF
C1320 C1321 C1322 C1323 C1324 C1325 C1326 C1327 C1328 C1329 4V 4V
2
g( L
4V 4V 4V 4V 4V 4V 4V 4V 4V 4V
(3 2
2
00 R 唐
01 MA 浩
+VDDIO_MEM decoupling caps (1uF)
+VDDCR_SOC
C1650 - C1669 020 1
+VDD_MEM
1
78 工健
C1683 C1682 C1681 C1680
080 5 22uF 22uF 22uF 22uF
1
1
4V 4V 4V 4V
2
C1650 C1651 C1652 C1653 C1654 C1655 C1656 C1657 C1658 C1659
4V 4V 4V 4V 4V 4V 4V 4V 4V 4V
2
9) 程 )
1
C1660 C1661 C1662 C1663 C1664 C1665 C1666 C1667 C1668 C1669
4V 4V 4V 4V 4V 4V 4V 4V 4V 4V
2
2
1
C1644 C1645 C1646 C1647 C1648 C1649
課
+VDDCR_SOC decoupling caps (1uF - 0402) 4V 4V 4V 4V 4V 4V
2
+VDDCR_SOC
1
C1370 C1371 C1372 C1373 C1374 C1375 C1376 C1377 C1231 C1232
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2
MSI MS-V381
Custom 5.0
NAVI10 DECAPS
Dat e: 2019_11_07 Sheet 27 of 35
00
+VDDCR_GFX +VDDCR_SOC +VDDCI_MEM +VDD_MEM
U1T U1U +3.3V_BUS +3.3V_BUS
AM32 AP31 U1V

VDDCR_GFX#136 VDDCR_SOC#25 symbol 21
symbol 20
AM29 VDDCR_GFX#134 VDDCR_SOC#24 AP30 R30 VDDCI_MEM#18 VDDIO_MEM#1 L13 BA8 VDDIO_33#1 symbol 22 VDD_33_S5#1 BA10
1
AM25 AP27 R29 L16 BB8 BA11
M
VDDCR_GFX#132 VDDCR_SOC#23 VDDCI_MEM#17 VDDIO_MEM#2 VDDIO_33#2 VDD_33_S5#2
2
AM20 VDDCR_GFX#130 VDDCR_SOC#22 AP21 R27 VDDCI_MEM#16 VDDIO_MEM#3 L18 C2 C3 C4 C5 C1570 C1571 C1572 C1573
AM16 AP20 R26 L20 1uF 1uF 1uF 1uF AY10 1uF 1uF 1uF 1uF
VDDCR_GFX#128 VDDCR_SOC#21 VDDCI_MEM#15 VDDIO_MEM#4 6.3V 6.3V 6.3V 6.3V VDD_33_S5P 6.3V 6.3V 6.3V 6.3V
AL30 VDDCR_GFX#126 VDDCR_SOC#20 AP18 R22 VDDCI_MEM#14 VDDIO_MEM#5 L23
2
AL26 VDDCR_GFX#124 VDDCR_SOC#19 AP17 R21 VDDCI_MEM#13 VDDIO_MEM#6 L25
RD 05 SI
AL21 VDDCR_GFX#122 VDDCR_SOC#17 AN33 R19 VDDCI_MEM#12 VDDIO_MEM#7 L28
AL17 VDDCR_GFX#120 VDDCR_SOC#15 AN31 R18 VDDCI_MEM#11 VDDIO_MEM#8 L30
+1.8V +1.8V
AK31 VDDCR_GFX#118 VDDCR_SOC#13 AN28 R16 VDDCI_MEM#10 VDDIO_MEM#9 L32
AK27 VDDCR_GFX#116 VDDCR_SOC#11 AN26 R15 VDDCI_MEM#9 VDDIO_MEM#10 L35
AK22 VDDCR_GFX#114 VDDCR_SOC#9 AN22 P32 VDDCI_MEM#8 VDDIO_MEM#11 M12 AT12 VDD_18#1 VDD_18_S5#1 AR19
1
AK18 VDDCR_GFX#112 VDDCR_SOC#7 AN20 P25 VDDCI_MEM#7 VDDIO_MEM#12 M36 AT16 VDD_18#2 VDD_18_S5#2 AR20
AJ32 VDDCR_GFX#110 VDDCR_SOC#5 AN17 P24 VDDCI_MEM#6 VDDIO_MEM#13 P14 C117 C116 C132 AT17 VDD_18#3 C1574 C1575 C1576 C1577
AJ28 AN15 P23 P34 10uF 10uF 10uF AU19 AU18 1uF 1uF 1uF 1uF
VDDCR_GFX#108 VDDCR_SOC#3 VDDCI_MEM#5 VDDIO_MEM#14 4V 4V 4V VDD_18#4 VDD_18_S5P 6.3V 6.3V 6.3V 6.3V
AJ23 VDDCR_GFX#106 VDDCR_SOC#1 AM15 P16 VDDCI_MEM#4 VDDIO_MEM#15 T11 AU20 VDD_18#5
2
AJ19 VDDCR_GFX#104 VDDCR_SOC#2 AM33 N25 VDDCI_MEM#3 VDDIO_MEM#16 T37 AV18 VDD_18#6
1
(C 36
AH32 VDDCR_GFX#102 VDDCR_SOC#4 AN16 N24 VDDCI_MEM#2 VDDIO_MEM#17 V14 AW19 VDD_18#7
1
AH29 VDDCR_GFX#100 VDDCR_SOC#6 AN19 N23 VDDCI_MEM#1 VDDIO_MEM#18 V34 C111 C112 C113 C114 C115
AH25 AN21 R32 Y14 1uF 1uF 1uF 1uF 1uF
VDDCR_GFX#98 VDDCR_SOC#8 VDDCI_MEM#19 VDDIO_MEM#19 C1578 C1579
6.3V 6.3V 6.3V 6.3V 6.3V
AH20 AN25 R33 Y34 10uF 10uF
VDDCR_GFX#96 VDDCR_SOC#10 VDDCI_MEM#20 VDDIO_MEM#20
4V 4V
2
AH16 VDDCR_GFX#94 VDDCR_SOC#12 AN27 T14 VDDCI_MEM#21 VDDIO_MEM#21 AB11 10% 10%
2
AG30 VDDCR_GFX#92 VDDCR_SOC#14 AN29 T15 VDDCI_MEM#22 VDDIO_MEM#22 AB37
AG26 VDDCR_GFX#90 VDDCR_SOC#16 AN32 T33 VDDCI_MEM#23 VDDIO_MEM#23 AD11
AG21 VDDCR_GFX#88 VDDCR_SOC#18 AP16 T34 VDDCI_MEM#24 VDDIO_MEM#24 AD37
AG17 VDDCR_GFX#86 Y15 VDDCI_MEM#25 VDDIO_MEM#25 AF11
+0.75V +0.75V
AF31 Y33 AF37
ON
VDDCR_GFX#84 VDDCI_MEM#26 VDDIO_MEM#26
)2 3
AF27 VDDCR_GFX#82 AA15 VDDCI_MEM#27 VDDIO_MEM#27 AH11
AF22 VDDCR_GFX#80 AA33 VDDCI_MEM#28 VDDIO_MEM#28 AH37 AR25 VDD_075#1 VDDCR_075_S5#1 AV20
1
AF18 VDDCR_GFX#78 AB15 VDDCI_MEM#29 VDDIO_MEM#29 AK11 AR26 VDD_075#2 VDDCR_075_S5#2 AV21
AE32 VDDCR_GFX#76 AB33 VDDCI_MEM#30 VDDIO_MEM#30 AK37 C180 C181 C182 AR27 VDD_075#3 C1580 C1581 C1582 C1583
AE28 AC15 AM14 10uF 10uF 10uF AR28 AU22 1uF 1uF 1uF 1uF
VDDCR_GFX#74 VDDCI_MEM#31 VDDIO_MEM#31 VDD_075#4 VDDCR_075_S5P
4V 4V 4V 6.3V 6.3V 6.3V 6.3V
AE23 VDDCR_GFX#72 AC33 VDDCI_MEM#32 VDDIO_MEM#32 AM34 AR29 VDD_075#5
2
AE19 VDDCR_GFX#70 AE15 VDDCI_MEM#33 AR31 VDD_075#6
AC32 VDDCR_GFX#68 AE33 VDDCI_MEM#34 AU30 VDD_075#7
1
AC29 VDDCR_GFX#66 AF14 VDDCI_MEM#35
F
AC27 VDDCR_GFX#65 AF15 VDDCI_MEM#36 C119 C120 C121 C122 C123 C1584 C1585
02
AC22 AF33 1uF 1uF 1uF 1uF 1uF AU23 10uF 10uF
VDDCR_GFX#63 VDDCI_MEM#37 VDD_075
6.3V 6.3V 6.3V 6.3V 6.3V 4V 4V
AC18 VDDCR_GFX#61 AF34 VDDCI_MEM#38
2
AB32 VDDCR_GFX#59 AH15 VDDCI_MEM#39
AB28 VDDCR_GFX#57 AH33 VDDCI_MEM#40
w I
+0.75V
AB23 VDDCR_GFX#55 AJ15 VDDCI_MEM#41 FB_VDDIO_MEM AP13 FB_VDDIO_MEM 21
OU T
AB19 VDDCR_GFX#53 AJ33 VDDCI_MEM#42 FB_VDDCI_MEM AM12 FB_VDDCI_MEM 21
OU T
AA32 VDDCR_GFX#51 AK14 VDDCI_MEM#43
1
AA25 AK33 AM13 FB_VSS_B
劉 00 ei DE
VDDCR_GFX#47 VDDCI_MEM#45 FB_VSS_B 21 C109
OU T 1uF
6.3V
AA16 VDDCR_GFX#43
2
Navi10 REV 0.91
Y30 VDDCR_GFX#41
Y26 VDDCR_GFX#39
Y21 VDDCR_GFX#37
Y17 VDDCR_GFX#35
W31 VDDCR_GFX#33
W27 VDDCR_GFX#31
W22 VDDCR_GFX#29
巍 52 st NT
W18 VDDCR_GFX#27
V32 VDDCR_GFX#25
V28 VDDCR_GFX#23
V23 VDDCR_GFX#21 VSS AT13
V19 VDDCR_GFX#19
U32 VDDCR_GFX#17
U29 VDDCR_GFX#15
U25 VDDCR_GFX#13
U20 VDDCR_GFX#11
Navi10 REV 0.91
T21
00 an IA
VDDCR_GFX#3
T23 VDDCR_GFX#4
T26 VDDCR_GFX#5
T19 VDDCR_GFX#2
T17 VDDCR_GFX#1
T28 VDDCR_GFX#6
T30 VDDCR_GFX#7
T32 VDDCR_GFX#8
U16 VDDCR_GFX#9
U18 VDDCR_GFX#10
g( L
U22 VDDCR_GFX#12
(3 2
U27 VDDCR_GFX#14
U31 VDDCR_GFX#16
V17 VDDCR_GFX#18
V21 VDDCR_GFX#20
V26 VDDCR_GFX#22
V30 VDDCR_GFX#24
W16 VDDCR_GFX#26
W20 VDDCR_GFX#28
W25 VDDCR_GFX#30
唐
W29 VDDCR_GFX#32
00
W32 VDDCR_GFX#34
Y19 VDDCR_GFX#36
Y23 VDDCR_GFX#38
Y28 VDDCR_GFX#40
R
Y32 VDDCR_GFX#42
AA18 VDDCR_GFX#44
AA22 VDDCR_GFX#46
AA27 VDDCR_GFX#48
AA31
01 MA 浩
VDDCR_GFX#50
AB17 VDDCR_GFX#52
AB21 VDDCR_GFX#54
AB26 VDDCR_GFX#56
AB30 VDDCR_GFX#58
AC16 VDDCR_GFX#60
AC20 VDDCR_GFX#62
AC25 VDDCR_GFX#64
AC31 VDDCR_GFX#67
AE17 VDDCR_GFX#69
78 工健
AE21 VDDCR_GFX#71
AE26 VDDCR_GFX#73
AE30 VDDCR_GFX#75
AF16 VDDCR_GFX#77
AF20 VDDCR_GFX#79
AF25 VDDCR_GFX#81
AF29 VDDCR_GFX#83
AF32 VDDCR_GFX#85
AG19 VDDCR_GFX#87
AG23 VDDCR_GFX#89
9) 程 )
AG28 VDDCR_GFX#91
AG32 VDDCR_GFX#93
AH18 VDDCR_GFX#95
AH22 VDDCR_GFX#97
AH27 VDDCR_GFX#99
AH31 VDDCR_GFX#101
AJ17 VDDCR_GFX#103
AJ21 VDDCR_GFX#105
AJ26 VDDCR_GFX#107
AJ30
課
VDDCR_GFX#109
AK16 VDDCR_GFX#111
AK20 VDDCR_GFX#113
AK25 VDDCR_GFX#115
AK29 VDDCR_GFX#117
AK32 VDDCR_GFX#119
AL19 VDDCR_GFX#121
AL23 VDDCR_GFX#123
AL28 VDDCR_GFX#125
AL32 VDDCR_GFX#127
AM18 VDDCR_GFX#129
AM22 VDDCR_GFX#131
AM27 VDDCR_GFX#133
AM31 VDDCR_GFX#135
FB_VDDCR_SOC AP35 FB_VDDCR_SOC 16

OU T
FB_VDDCR_GFX AM37 FB_VDDCR_GFX 16

OU T
FB_VSS_A AM36 FB_VSS_A 16

OU T
Navi10 REV 0.91
MSI MS-V381
Custom 5.0
NAVI10 POWER
Date: 2019_11_07 Sheet 28 of 35
BA17 VSS#658 VSS#742 BE42
BA14 VSS#657 symbol 25 VSS#744 BF5
U1W BA12 VSS#656 VSS#746 BF27
BA7 U1Y BF31
U1X VSS#655 VSS#748
H26 VSS#137 symbol 23 VSS#250 T27 AF2 VSS#421 VSS#488 AJ27 BA5 VSS#654 VSS#759 BG14
symbol 24
H22 VSS#136 VSS#249 T25 AE47 VSS#420 VSS#487 AJ25 BA3 VSS#653 VSS#761 BG19
00
H20 VSS#135 VSS#248 T22 AE45 VSS#419 VSS#486 AJ22 BA1 VSS#652 VSS#760 BG17
H18 VSS#134 VSS#247 T20 AE43 VSS#418 VSS#485 AJ20 AY46 VSS#651 VSS#765 BG27
H8 VSS#130 VSS#243 T6 AE31 VSS#414 VSS#481 AJ9 AY37 VSS#647 VSS#750 BF36
H6 VSS#129 VSS#242 T4 AE29 VSS#413 VSS#480 AJ7 AY35 VSS#646 VSS#749 BF34
H4 VSS#128 VSS#241 T2 AE27 VSS#412 VSS#479 AJ5 AY32 VSS#645 VSS#741 BE40
H2 VSS#127 VSS#240 R31 AE25 VSS#411 VSS#478 AJ3 AY30 VSS#644 VSS#740 BE37
G47 R28 AE22 AJ1 AY28 BE35
M
VSS#126 VSS#239 VSS#410 VSS#477 VSS#643 VSS#739
2
G45 VSS#125 VSS#238 R25 AE20 VSS#409 VSS#476 AH46 AY26 VSS#642 VSS#738 BE32
RD 05 SI
G36 VSS#121 VSS#234 P47 AE9 VSS#405 VSS#472 AH38 AY6 VSS#638 VSS#734 BE24
G29 VSS#118 VSS#231 P41 AE3 VSS#402 VSS#469 AH28 AW36 VSS#635 VSS#731 BE18
G27 VSS#117 VSS#230 P39 AE1 VSS#401 VSS#468 AH26 AW34 VSS#634 VSS#730 BE16
G21 VSS#116 VSS#229 P36 AD46 VSS#400 VSS#467 AH23 AW31 VSS#633 VSS#729 BE13
G12 VSS#112 VSS#225 P22 AD34 VSS#396 VSS#463 AH14 AW23 VSS#629 VSS#725 BD42
(C 36
G5 VSS#109 VSS#222 P12 AD6 VSS#393 VSS#460 AH6 AV47 VSS#626 VSS#722 BD35
C
F46 VSS#106 VSS#219 P5 AC47 VSS#390 VSS#457 AG47 AV41 VSS#623 VSS#719 BD28
F37 VSS#103 VSS#216 N46 AC41 VSS#387 VSS#454 AG41 AV11 VSS#620 VSS#716 BD23
F35 N44 AC39 AG39 AV7 BD22
ON
)2 3
F26 VSS#98 VSS#211 N35 AC26 VSS#382 VSS#449 AG29 AU46 VSS#615 VSS#711 BD14
F16 VSS#94 VSS#207 N6 AC17 VSS#378 VSS#445 AG20 AU36 VSS#611 VSS#707 BC47
F
02
F8 VSS#91 VSS#204 M47 AC7 VSS#375 VSS#442 AG15 AU16 VSS#608 VSS#704 BC38
E47 VSS#88 VSS#201 M41 AC1 VSS#372 VSS#439 AG7 AU8 VSS#605 VSS#701 BC31
w I
E45 VSS#87 VSS#200 M39 AB46 VSS#371 VSS#438 AG5 AU6 VSS#604 VSS#700 BC29
E38 VSS#84 VSS#197 M29 AB40 VSS#368 VSS#435 AF46 AT47 VSS#601 VSS#697 BC23
E36 M27 AB34 AF44 AT45 BC21
劉 00 ei DE
E21 VSS#78 VSS#191 M19 AB22 VSS#362 VSS#429 AF26 AT14 VSS#595 VSS#691 BB46
巍 52 st NT
E7 VSS#72 VSS#185 M3 AB6 VSS#356 VSS#423 AF6 AR46 VSS#589 VSS#685 BB31
E5 VSS#71 VSS#184 M1 AB4 VSS#355 VSS#422 AF4 AR44 VSS#588 VSS#684 BB29
E3 VSS#70 VSS#183 L46 AB2 VSS#354 VSS#276 U45 AR42 VSS#587 VSS#683 BB27
E1 VSS#69 VSS#182 L44 AA47 VSS#353 VSS#275 U43 AR40 VSS#586 VSS#682 BB25
D42 VSS#68 VSS#181 L42 AA45 VSS#352 VSS#274 U41 AR37 VSS#585 VSS#681 BB23
D32 L24 AA37 U30 AR16 BB16
00 an IA
D20 VSS#59 VSS#172 L4 AA23 VSS#343 VSS#265 U19 AR4 VSS#576 VSS#672 BA47
D18 VSS#58 VSS#171 L2 AA21 VSS#342 VSS#264 U17 AR2 VSS#575 VSS#671 BA45
D16 VSS#57 VSS#170 K47 AA19 VSS#341 VSS#263 U15 AP47 VSS#574 VSS#670 BA43
g( L
(3 2
C43 VSS#52 VSS#165 K37 AA7 VSS#336 VSS#258 U3 AP36 VSS#569 VSS#665 BA32
C41 VSS#51 VSS#164 K32 AA5 VSS#335 VSS#257 U1 AP34 VSS#568 VSS#664 BA30
C38 VSS#50 VSS#163 K16 AA3 VSS#334 VSS#256 T46 AP32 VSS#567 VSS#663 BA28
C36 VSS#49 VSS#162 K11 AA1 VSS#333 VSS#255 T44 AP29 VSS#566 VSS#662 BA26
C34 VSS#48 VSS#161 K10 Y46 VSS#332 VSS#254 T42 BG12 VSS#758 VSS#661 BA24
C27 VSS#45 VSS#158 K3 Y40 VSS#329 VSS#251 T29 BG2 VSS#755 VSS#565 AP28
唐
C21 VSS#44 VSS#157 K1 Y37 VSS#328 VSS#500 AK8 BF47 VSS#754 VSS#564 AP26
00
C19 VSS#43 VSS#156 J36 Y31 VSS#327 VSS#499 AK6 BF43 VSS#753 VSS#563 AP23
C12 VSS#40 VSS#153 J29 Y25 VSS#324 VSS#496 AJ47 BG29 VSS#766 VSS#560 AP12
R
B47 VSS#36 VSS#149 J17 Y16 VSS#320 VSS#492 AJ39 BG38 VSS#770 VSS#556 AP3
B42 J14 Y11 AJ36 BG41 AP1
01 MA 浩
B40 VSS#34 VSS#147 J12 Y8 VSS#318 VSS#490 AJ31 BG43 VSS#772 VSS#554 AN30
B37 VSS#33 VSS#146 H46 Y6 VSS#317 VSS#489 AJ29 BG46 VSS#773 VSS#553 AN23
B35 VSS#32 VSS#145 H44 Y4 VSS#316 BF1 VSS#743 VSS#552 AN18
B32 VSS#31 VSS#144 H42 Y2 VSS#315 VSS#551 AM46
B30 VSS#30 VSS#143 H40 W47 VSS#314 VSS#550 AM44
78 工健
B16 VSS#24 W30 VSS#308 VSS#544 AM28
B13 VSS#23 W28 VSS#307 VSS#543 AM26
B11 VSS#22 W26 VSS#306 VSS#542 AM23
B8 VSS#21 W23 VSS#305 VSS#541 AM21
B6 VSS#20 W21 VSS#304 VSS#540 AM19
B1 VSS#19 W19 VSS#303 VSS#539 AM17
A46 VSS#18 W17 VSS#302 VSS#538 AM10
A43 VSS#17 W12 VSS#301 VSS#537 AM8
A41 VSS#16 W9 VSS#300 VSS#536 AM6
9) 程 )
A38 VSS#15 W7 VSS#299 VSS#535 AM4
A36 VSS#14 W5 VSS#298 VSS#534 AM2
A34 VSS#13 W3 VSS#297 VSS#533 AL47
A31 VSS#12 W1 VSS#296 VSS#532 AL45
A29 VSS#11 V46 VSS#295 VSS#531 AL43
A27 VSS#10 V44 VSS#294 VSS#530 AL41
A21 VSS#9 V42 VSS#293 VSS#529 AL39
A19 VSS#8 V40 VSS#292 VSS#528 AL36
A17 VSS#7 V37 VSS#291 VSS#527 AL33
A14 V31 AL31
課
VSS#6 VSS#290 VSS#526
A12 VSS#5 V29 VSS#289 VSS#525 AL29
A10 VSS#4 V27 VSS#288 VSS#524 AL27
A7 VSS#3 V25 VSS#287 VSS#523 AL25
A5 VSS#2 V22 VSS#286 VSS#522 AL22
A2 VSS#1 V20 VSS#285 VSS#521 AL20
Navi10 REV 0.91
V18 VSS#284 VSS#520 AL18
V16 VSS#283 VSS#519 AL16
V11 VSS#282 VSS#518 AL15
V8 VSS#281 VSS#517 AL12
V6 VSS#280 VSS#516 AL9
U47 VSS#277 VSS#513 AL3
Navi10 REV 0.91 VSS#512 AL1
VSS#511 AK46
VSS#510 AK44
VSS#509 AK42
VSS#508 AK40
VSS#507 AK30
VSS#506 AK28
VSS#505 AK26
VSS#504 AK23
VSS#503 AK21
VSS#502 AK19
VSS#501 AK17
VSS#747 BF29
VSS#745 BF25
Navi10 REV 0.91
MSI MS-V381
Custom 5.0
Date: 2019_11_07 Sheet 29 of 35

+3.3V_BUS
HW default power up sequence
R1105
32,30 CTF_PWRB 1 2 0R 5%
IN
R1010
1K
1%
+12V_BUS 1 .8 V
+12V_BUS_B +3.3V_BUS
00
20%
L1002 0 .7 5 V
1 2
0.47uH +1.8V_EN 2,25
OU T
1
+12V_BUS_B
C102PCIE R1003 VDD C R _ GFX

10uF 5.11K
16V 1%
6
20%
2
R1004 2 Q1000A VDDC R _ SOC
1
11.3K MMDT3904
M
1%
6
C1005
1
0.1uF
2 Q1001A 16V
MMDT3904 10% VP P
2
+12V_EXT_A
1
RD 05 SI
R1005
1K
1%
MVD D C
+12V_EXT_A_CON
R1006
+12V_EXT_A 11.3K
1%
MVD D Q
3
J1000 L1000
+12V 6 1 1 2 5 Q1001B
+12V 7 0.56uH
MMDT3904 VD D C I_ ME M
+12V 8 C1000 20%
4
1
47pF
50V R1068
1K
(C 36
5%
C1001 1%
2
10uF
16V
20%
2
GND 1
GND 2
C
GND 4
SENSE_1 3 8P_SENSE_A SENSE_A POWER UP SEQUENCE

R1001
SENSE_2 5 1 2
ON
0R 5% BUS RAILS (3.3V/12V UP) -> +1.8V -> 0.75V -> VDDGFX/VDDSOC
)2 3
POWER_HEADER -> VPP -> VDDCI/MVDD
POWCONN_D8_10
1
COMMON 12V_BUS and 12V_EXT_A power-up sequence
VVVV381100 C1002
N93-08M0361-W06 47pF
50V
DNI
5%
2 25 1.8V_PWR_GOOD 1
R1007 2 0R 5% +0.75V_EN 24
IN OU T
02 F
+12V_EXT_A
32,30
IN
CTF_PWRB 1
R1008
X 2 0R 5%
w I
+3.3V_BUS
24,30 +0.75V_PG 1
R1009 2 0R 5% VPP_EN 26
IN OU T
R1023
10K +3.3V_BUS
劉 00 ei DE
1%
3
R1024 5 Q1000B
2.32K MMDT3904 +3.3V_BUS
1%
1
R1013
4
2 10K
Q1021A C1026
5%
MMDT3904 0.1uF VDDGFX_VDDC_EN 30,16
16V
10%
OU T
R1035
2
10K
R1025 5%
3
1K +12V_EXT_B
1%
巍 52 st NT
+12V_EXT_B_CON +12V_EXT_B Q1026
1
MMBT3904T
3
J1001 L1001
2
4 1 2 +0.75V_PG 1
R1034 2 0R 5% 1 Q1024
R1026 24,30
IN
1
1
+12V-1 11.3K
5 0.56uH 1% DNI 2N7002L
3
X
+12V-2 6 20%
C1022 C1023
2
1
+12V-3 47pF R1012 1uF

50V
5 Q1021B DNI
0R 6.3V
MEC1 5% MMDT3904 5%
MEC1 C1021
2
2
10uF
MEC2 MEC2 16V
4
20%
00 an IA
R1027
2
1K
GND-1
GND-2
1
3
1%
X
2 6P_SENSE_B DNI
SENSE_B
SENSE R1022
1 2
0R 5% 26 VPP_PWR_GOOD 1
R1042 2 0R 5% VDD_MEM_VDDCI_EN 21
IN OU T
1
PWRCONN6P_BLACK-RH-9
COMMON
C1003
g( L
47pF
VVVV381100 50V
(3 2
DNI
N93-06M0461-C67 5% 3.3V_BUS and 12V_EXT_B (6PIN/8PIN) power-up sequence
2
POWCONN_D6_15
00 唐
+3.3V_BUS
IN BACO MODE
TURN OFF VDDCR_GFX, VDDCR_SOC, VDDCI, VPP and MVDD
R
DNI
IN BAMACO MODE X R1056

10K
1%
TURN OFF VDDCR_GFX, VDDCR_SOC, VDDCI(turn off by SVI2)
01 MA 浩
+0.75V_PG 24,30
OU T
3
2,32,33 PX_EN R1014 2 1 10K 5% 5 Q1019B
IN MMDT3904
+3.3V_BUS
4
6
2
X 1 2
X
3,31 BAMACO_EN R1028 10K 5% Q1019A R1015 DNI
IN
78 工健
MMDT3904 10K
5%
1
DNI
X R1055
1
10K
X C1024
1uF
6.3V
5%
VDDGFX_VDDC_EN 30,16
2
OU T
6
R1047 1 2
5.1K 5% 2 Q1018A
MMDT3904
9) 程 )
1
+12V_EXT_A +VDDGFX_SOURCE3 +12V_EXT_A +VDDGFX_SOURCE6 +12V_EXT_A +VDDGFX_SOURCE1 +12V_EXT_A +VDDSOC_SOURCE
X R1021
10K
5%
R1099 1 2 0R 5% R1095 1
X 2 0R 5% R1090 1 2 0R 5% R1089 1 2 0R 5%
R1098 1 2 0R 5% R1094 1
X 2 0R 5% R1091 1 2 0R 5% R1088 1 2 0R 5%
課
VDDGFX_PH3 OPT IONAL1 VDDGFX_PH6 OPT IONAL1 VDDGFX_PH1 OPT IONAL1 VDDSOC OPT IONAL1
3
R1016
X
2,16,21,32 PERST#_BUF 2 1 5 Q1018B R1018
IN MMDT3904 0R
1% 10K 5%
+12V_EXT_B +VDDGFX_SOURCE3 +12V_EXT_B +VDDGFX_SOURCE6 +12V_BUS_B +VDDGFX_SOURCE1 +12V_EXT_B +VDDSOC_SOURCE
4
MR10991
X 2 0R
DNI
5%
DNI MR10951
X 2 0R
DNI
5%
DNI MR1090 1
X 2 0R
DNI
5%
DNI MR10891
X 2 0R
DNI
5%
DNI X R1017
10K
1%
MR10981
VDDGFX_PH3
X OPT IONAL2
2 0R 5% MR10941
VDDGFX_PH6
X 2
OPT IONAL2
0R 5% MR1091
VDDGFX_PH1
1
X
2
OPT IONAL2
0R 5% MR10881
VDDSOC
X
OPT IONAL2
2 0R 5%
MSI MS-V381
Custom 5.0
POWER MANAGEMENT
Date: 2019_11_07 Sheet 30 of 35
00
2
RD 05 SI M
(C 36
Resistor could be placed inside the analog switch.
C
DNI
R1060
1 2
0R 5%
+3.3V_BUS +1.8V
)2 3 ON
DNI
1
U1002
C1016 R1061
0.1uF 8 7 10K
16V VCC OE1 5%
3 SVT_MVDD_VDDCI
10%
2 1B OE2 3
2
IN 6 1
2B 1A SVT_MVDD_VDDCI_VR 21
4 5
OUT
GND 2A
02 F
NC7WB66K8X
Isolation for SVT w hen 1.8V to GPU is off during BOMACO
劉 00 ei DEw I Resistor be placed close the analog switch.
+3.3V_BUS
1
0R
1
0R
R1048
R1049
5%
5%
2
2
DNI
DNI
巍 52 st NT
1
MVDDC/VDDCI_MEM VOLTAGE CONTROL
U1000
C1014
0.1uF 8 7
16V VCC OE1
3 SVC_MVDD_VDDCI
10%
2 1B OE2 3
2
IN 6 1
3 SVD_MVDD_VDDCI 2B 1A SVC_MVDD_VDDCI_VR 21
IN 4 5
OUT
GND 2A SVD_MVDD_VDDCI_VR 21
BI
+3.3V_BUS
00 an IA
NC7WB66K8X
R1066 R1029
+3.3V_BUS Overlap pads
100R 100R 1
R1038 210K 5% 1
MR1038 210K 5%
5% 5%
3
R1067 1
R1039 210K 5% 1
MR1039 210K 5% +1.8V
10K 2 Q1004B 5 Q1004A
5% R1037
10K
2N7002DW 2N7002DW 5%
D1000 MACO_EN#
4
T=51us 1
g( L
6
3
(3 2
R1063 Q1003B R1032 Q1003A
21 MVDD_VDDCI_PWROK 1 2 2 3,30 BAMACO_EN 1 2 2 3 5
IN IN
0R 5% DNI 2N7002DW 0R 5% 2N7002DW SVI2 BOOT UP VOLTAGE (VDDCI_MEM/MVDD)
1
1
BAT54C
DNI
1
4
R1064 C1012 NA R1033 C1013 SVC SVD VOLTA G E
10K 22pF 1 MR1032 2 10K 22pF
5% 50V
10%
5% 50V
10%
0R 5% 0 0 1.1V
2
2
0 1 1.0V
唐
DNI 1 0 0.9V
00
1 1 0.8V
R1046
2 1
3
5% 0R
1 Q1006
R1045
R
2N7002E
0R SVC/SVD need to pull high during MACO mode
5%
2
R1065
100K
01 MA 浩
5%
78 工健
9) 程 )
課
MSI MS-V381
Custom 5.0
SVI2 & BAMACO
Dat e: 2019_11_07 Sheet 31 of 35
J18 J17
MT200 MT204 MT207
3 1
4 2 +12V_EXT_B +12V_EXT_A +12V_BUS_B
FM1 FM2 FM3 FM4 impedence X_PIN1*2
NA NA NA
1
00
2
1 8
7 2
1 8
7 2
1 8
7
OPT
F_PAD_X
OPT
F_PAD_X
OPT
F_PAD_X
OPT
F_PAD_X
MB200
X 220R
DNI
25%
X NB200
220R
DNI
25%
B200
220R
25%
3
4
5
6
3
4
5
6
3
4
5
6
2
X X X FANOUT_P
1
MT209 MT210 MT212 MT213 MT214 MT216 FM5 FM6 FM7 FM8 J19
J16 MC200
3 1 10uF
16V R240
4 2 20% 20K
M
5%
2
2
2
impedence
NA NA NA NA NA NA OPT OPT OPT OPT X_PIN1*2 1
F_PAD_X F_PAD_X F_PAD_X F_PAD_X
2
1 2 7
1 8 8
7 2
1 2 7
1 8 2 7
1 8 8
7 2
1 8
7
Q211
AO3415L X R213
0R
5%
DNI
RD 05 SI
R243
20K
X X X X X X
5%
3
4
5
6
3
4
5
6
3
4
5
6
3
4
5
6
3
4
5
6
3
4
5
6
3
+3.3V_BUS
6
CTF_OUT
R246 Q212A
32 20K 2
5% MMDT3904-7 R272
Fiji_fansinks Fiji_fansinks Fiji_fansinks Fiji_fansinks 20K
HS201A HS201B HS201C HS201D 5%
1
(C 36
6
R205 Q213A
2,30,33 PX_EN 20K 2
IN
3
5% MMDT3904-7
+3.3V_BUS Q212B
5
1
MMDT3904-7
4
1
C208 2
0.1uF 6.3V
3
R274 Q213B
20K5
)2 3 ON
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
X X X X 5% MMDT3904-7
4
R218
0R U201 +3.3V_BUS
5%
DNI
1 A VCC 8
2 B Rext/Cext 7
MR218 R249
PERST#_BUF 1
X 2 3 6 1 2 2 1
2,16,21,30,32 CLR Cext 10uF C2106.3V
IN 4 5
0R 5% GND Q 5% 1M
NA NA
F
MT217 MT218
02
SN74LVC1G123DCT NA
ASSY201 BAV99
3
SCHEMATIC SCHEMATIC
1 2
I
BRACK E T
w
+3.3V_BUS +3.3V_BUS +12V_BUS_B +3.3V_BUS
DUAL
D203
For 4-WIRE FAN ONLY

2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
8020058200G LM96 external GPU
X X X X
temperature sensor
劉 00 ei DE
R207 R208 R266
X R206
10K
DNI
5%
PWM_FAN
10K
5%
10K
5%
MJ201
5.1K
5% FAN_IN FAN_TACH
4
R209 1K FANOUT_P_Q 3
3
1%
2
1
R210 1K 1 Q200 1
6
X X
MMBT3904T
5% C211 R211
R258
1
1 2 2 Q201A 0.1uF 3.83K
FAN_OUT 16V 1% HEADER_1X4_SHROUDED
2
巍 52 st NT
5% 0R 2 R212 1 10K 5% MMDT3904-7 C204 Fan Connector
2
10uF
16V
1
DNI
2
OVERLAP J201 AND MJ201
3
PERST#_BUF_R
00 an IA
DNI
R214 Q201B
2,16,21,30,32
IN
PERST#_BUF 1
10K X 2
5%
DNI
5
MMDT3904-7 R215
0R
5%
4
X R216
2.61K
1%
+3.3V_BUS
(3 2 g( L
+3.3V_BUS +3.3V_BUS U250
FAN_IN 3 5 FAN_IN_ASIC
A VCC
32 1 4 1
R260 2 0R 5% 32 33
B Y
1
6 GND 2
C
R227 C268
20K 0.1uF
5% 74AUP1G57GM 6.3V
2
2
1 Q207
唐
MMBT3906T
00
1
R259
X 2 0R 5%
3
R229
3
20K
5% CTF_OUT
1 R236
32 2 1
R220 22.2K 5% 1 Q204
R
0R
MMBT3904T
5%
2
3
1 Q210 R232
20K
01 MA 浩
MMBT3904T 5%
2
R233 4.7K R234 47K CTF_PWRB 30

OU T
5% 5%
3
Place close to its CTLR
1
1
MR230 22.2K1 5% Q209
R235
1
100K
5% C209 MMBT3904T
0.01uF
10V
2
78 工健
D202 3
2
BAT54S
NA
X R239
2
1K
5%
2,16,21,30,32 PERST#_BUF
IN
9) 程 )
2
IN
CTF
GPU_PWRBRK#
AR36
AW37
AV37
AR39
AT38
AU39
ALERT_L
PWRBRKB
TEMPIN
課
PROCHOT_L
CTF
TEMPINRETURN
U1D
symbol 4 TS_A
DPLUS
DMINUS
FANIN
FANOUT
PUMPIN
PUMPOUT
AP25
BC43
BC42
BF46
BE45
BE47
BC46
TS_A
Differential
FAN_IN_ASIC
FAN_OUT
Rout ing
32
X
33
SCHEMATIC
TP12
32
Navi10 REV 0.91
R262
10K
5%
X R341
10K
5%
MSI MS-V381
Custom 5.0
MECHANICAL & THERMAL
Date: 2019_11_07 Sheet 32 of 35
00
2
RD 05 SI M
(C 36
J4003
3,16,21 REGULATOR_SCL 1
IN
X
3,21,16 REGULATOR_SDA 2
BI 3
1
1
DNI DNI
HEADER_1X3
X C4004
X C4005
C
47pF 47pF
50V 50V
5% 5%
2
)2 3 ON
02 w F I
劉 00 ei DE
巍 52 st NT
00 an IA
+1.8V
+1.8V
R4109
R4074 R4075 R4076 R4077 1K
10K 10K 10K 10K 5%
5% 5% 5% 5%
U1C
BP_0
(3 2 g( L
BP_1 AT28 BP_0 symbol3 TCK AU9
BP_2 AT27 BP_1 TMS AT11
BP_3 AU27 AT10
BP_2 TDI
AT26 BP_3 TDO AR10
TRST_L AU12 GPU_TESTEN
TESTEN AR9 GPU_DBREQ#
DBREQ_L AR12 33R HDT_DBREQ#
1 5% 2
R4115 R4108
R270
1
1 2 DIECRACKMON AT36 TEST6 1K
0R 5% 5% C4103
0.01uF
6.3V
唐
Navi10 REV 0.91
00
2
R
01 MA 浩
78 工健
9) 程 )
RADEON Lightbar header
課
MSI MS-V381
Size Document Description Rev
Custom 5.0
DEBUG
Date: 2019_11_ 0 7 Sheet 33 of 35
00
2
RD 05 SI M
(C 36 C
External Connector
)2 3 ON
+1 2 V_ EXT_ A/ B
02 F
JTAG/I 2 C
Deb u g
w I
Debug Header
T MD PA DP
劉 00 ei DE
POWER REGULATORS D BGD ATA[7 : 0 ]
TMD P B
From +12V EXT_A/B

Regulator HOT
GPIO5
+VDDCR_GFX, VDDCR_SOC
PCC HDMI
巍 52 st NT
GPIO4 TMD P C
From +12V EXT_B/+3.3AUX Straps GPIOs

0.75V _S5 1.8V _S5
TMD P D
USB_5V V BUS_PWR_USB C0
00 an IA
BIOS ROM
From +12V_BUS TMD P E

Therm al DP
Speed control D D C VGA
+MVDD, +VDDCI_MEM, FAN
(3 2 g( L
& temperature INTERR U P T
PR OC H OT_ L
TMD P F
FAN sens e Temp. Sensing D+/D - DP
From +12V_BUS
Built-in PWM FAN _ OU T
+5 V +5 V_ VE S A FAN _ IN
00 唐
SVI2/I2C/Power Management
R
From +3.3V Direct:
POWER DELIVERY
VDDRN_33, +VPP
01 MA 浩
1.8V, 0.75V
1 0 0 MH z
78 工健
REFC L K Cloc k
Temperature Critical
CTF
PCI-Expres s
Power Sequencing
9) 程 )
and Control Circuit
+3.3V_BU S
PCI-Express Bus
課
+12V_BU S
NAVI10 CR
MSI MS-V381
Custom 5.0
BLOCK DIAGRAM
Date: 2019_11_07 Sheet 34 of 35
8 7 6 5 4 3 2 1
AMD
TITLE:
NAVI10 G6X16mode DP DP HDMI DP DOCUMENT NUMBER: 105_D199xx_00B DATE: Fri Jun 21 03:44:58 2019 SHEET NUMBER: 35 OF 35 REV: 1.00
00
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC. C 2018 Advanced Micro Devices
ENGINEER: NOTES :
This AMD Board schematic and design is the exclusive property of AMD, and is provided only to entities under a non-disclosure agreement with AMD
AMD - PLATFORM HARDWARE ENG
for evaluation purposes. Further distribution or disclosure is strictly prohibited. Use of this schematic and design for any purpose other than No.669, HUANKE ROAD
REVISION HISTORY Peak, Dong NOTE evaluation requires a Board Technology License Agreement with AMD. AMD makes no representations or warranties of any kind regarding this
schematic and design, including, not limited to, any implied warranty of merchantability or fitness for a particular purpose, and disclaims
SHANGHAI, CHINA 201203
M
responsibility for any consequences resulting from use of the information included herein.
2
SCH PCB
Date REVISION DESCRIPTON
Rev Rev
RD 05 SI
1 -00A
D FEB 11 -00A schemactics D
2019
JUN 21
(C 36
2 -00B 2019 ADD PULL HIGH ON THE PWRBRKB
)2 3 C ON
02 F
2019_11_07 GFX_MEM_SOC_VDDCI Co-Lay 302045 and Power PIN fix to 8+6 reverse type Only
劉 00 ei DEw I
2019_11_11 Add Fan_IN output back Page 32, Change Footprint con_dp_astron_r6890020_tab >
2019_11_14 add Cross Light point , Remove Page 2 TP detect point, Remove lightbar header, Remove CTF & J4100 debug Pin
con_tab , edgecon_pci_express_gen4_16 > edgecon_16 , Remove MT203, MT 211, MT208 Screw Hole
巍 52 st NT
00 an IA
(3 2 g( L
B
00 R 唐 B
01 MA 浩
78 工健
9) 程 )
A
課 A
8 7 6 5 4 3 2 1

V381 50 (00205363) Decrypt

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00

3 NAVI10 GPIOs 28 NAVI10 POWER

5 NAVI10 MEM CHAB 30 POWER MANAGEMENT

6 NAVI10 MEM CHCD 31 SVI2 & BAMACO

7 NAVI10 MEM CHEF 32 MECHANICAL & THERMAL

9 GDDR6 MEM CHAB 34 BLOCK DIAGRAM

10 GDDR6 MEM CHCD 35 REVISION HISTORY

11 GDDR6 MEM CHEF

14 NAVI10 TMDPC - HDMI

18 VDDCR_GFX PHASES 1 and 4

19 VDDCR_GFX PHASES 3 and 7

20 VDDCR_GFX PHASES 6 and VDDCR_SOC

A10 +3.3V PCIE_REFCLKP DNI

B10 3.3Vaux PCIE_RX0P

A34 GND PETp4 B33 PCIE_RX4N BE29 PCIE_RX4P

50V PCIE_REFCLKP A45 GND PCIE_RX6P

50V PCIE_REFCLKN A49 GND PETn6 B42 BD31 PCIE_RX6N

R4212 1 242.2R 1%C4202 1 0.25pF

R4213 1 242.2R 1%C4203 1 0.25pF

50V A58 GND PCIE_RX8P

R4215 1 242.2R 1%C4205 1 0.25pF

50V PRSNT2_B48 A74 GND PETn10 B59 BD36 PCIE_RX10N

R4218 1 242.2R 1%C4208 1 0.25pF 21pF 2 B48 A75 GND PCIE_RX11P

50V A82 GND PCIE_RX12P

50V B21 GND PCIE_RX14P

B25 GND PETn14 B75 BD41 PCIE_RX14N

2 RSVD_A50 RSVD_A33 PCIE_TX15P

Navi10 REV 0.91

DIGON AM11 GPIO_18

C61 C62 C63 3 1 1

R85 1 2 2.2K 1% XTRIG7 AP22 XTRIG7

R94 1 2 10K 5% OSC_GAIN0 AW14 OSC_GAIN1

R93 1 2 10K 5% AY14 OSC_GAIN0 ANALOGIO AU14 ANALOGIO 1

01 MA 浩 Route 50 ohms single-ended/100 ohms diff

WCKA0_0 AR47 WCKA0_0 WCKA1_0 AR43 WCKA1_0

Dat e: 2019_11_07 Sheet 5 of 35

10 WCKD0_0 A35 WCKD0_0 WCKD1_0 H29 WCKD1_0 10

CAE0_[0..9] CAE0_0 CAE1_[0..9] CAF0_[0..9] CAF1_[0..9]

11 CKE P19 CKE 11 CKF N12 CKF

8,12 CAG0_[0..9] CAG0_0 12 CAG1_0 CAG1_[0..9] 8,12 12 8 15 BB1 DQH0_15 8

WCKG0_0 AB1 WCKG0_0 WCKG1_0 AB7 WCKG1_0

5 DBIA0_1 D13 R13 DBIA1_1 5 5 DBIB0_1 D13 R13 DBIB1_1 5

5 CABIA0 J5 CABI_N_A CABI_N_B K5 CABIA1 5 5 CABIB0 J5 CABI_N_A CABI_N_B K5 CABIB1 5

ZQ_A0 ZQ_A1 ZQ_B0 ZQ_B1

5 CKA J10 5 CKB J10

5 DRAM_RSTB_A J1 RESET_n 5 DRAM_RSTB_B J1 RESET_n

V14 VDD_12 VSS_52

C2142 C2143 C2144 C2145 C2146

6 DBIC0_1 D13 R13 DBIC1_1 6 6 DBID0_1 D13 R13 DBID1_1 6

6 CABIC0 J5 CABI_N_A CABI_N_B K5 CABIC1 6 6 CABID0 J5 CABI_N_A CABI_N_B K5 CABID1 6

6 CKC J10 6 CKD J10

V14 VDD_12 VSS_52

B10 VDDQ_15 VSS_23

C2342 C2343 C2344 C2345 C2346

7 DBIE1_0 D13 R13 DBIE0_0 7 7 DBIF1_0 D13 R13 DBIF0_0 7

7 CABIE1 J5 CABI_N_A CABI_N_B K5 CABIE0 7 7 CABIF1 J5 CABI_N_A CABI_N_B K5 CABIF0 7

7 CKE J10 7 CKF J10

V14 VDD_12 VSS_52

C2542 C2543 C2544 C2545 C2546

MICRO-STAR INT'L CO.,LTD

8 DBIG1_0 D13 R13 DBIG0_0 8 8 DBIH1_0 D13 R13 DBIH0_0 8

8 CABIG1 J5 CABI_N_A CABI_N_B K5 CABIG0 8 8 CABIH1 J5 CABI_N_A CABI_N_B K5 CABIH0 8

ZQ_G1 ZQ_G0 ZQ_H1 ZQ_H0