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Thapar Institute of Engineering and Technology, Patiala

Department of Electronics and Communication Engineering
B. E. 2nd year, Auxiliary Exam Course Code: UEC612
Course Name: Digital System Design 3rd March, 2023
Time: 3 Hours, M. Marks: 100 Instructor: Dr. Alpana Agarwal & Dr. Manu Bansal

Note: Attempt all part of a question at one place. Else, only first attempt will be evaluated.
Make suitable assumptions, if required

1 Design a combinational circuit with three inputs x, y, and z, and three outputs A, 20
B, and C. When the binary input is 0, 1, 2, or 3, the binary output is one greater
than the input. When the binary input is 4, 5, 6, or 7, the binary output is one less
than the input.
2 (a) Design a combinational circuit using ROM. Write the size of ROM used. 12
A(x, y, z) = E(1,2,4,6); B(x, y, z) = E(0,1,6,7);
C(x, y, z) = E(2,6); D(x, y, z) = E(1,2,3,5,7)
2 (b) Implement a 2-input XOR gate using 2:1 MUX. 8

3 (a) Design a JK flip flop using D Flip-flop. 8

3 (b) Design a synchronous counter that has the sequence 1, 3, 5, 7 and repeat. The 12
undesired states must go to 1 on next cycle.

4 (a) Draw the Venn diagram of a FSM for detecting the every occurrence of '0110' in a 10
stream of input bit sequence. State the assumptions, if any.
4 (b) Design a 3-bit Universal Shift Register and explain its operation. 10
5 (a) Draw and explain the Totem-Pole arrangement of 3-inout TTL NAND gate. 10
5 (b) Calculate the Noise Margins of the logic families: 4000B and 74LS. 6
5 (c) Which logic family from Table 1 can drive the most inputs of the same series? 4

Table 1: Typical IC Characteristics

74 745 74LS 74AS 74ALS 74F 4000B
Voltage Parameters (V)
Voilmln) 2.4 2.7 2.7 2.5 2.5 2.5 4.95
VOL(max) 0.4 0.5 0.5 0.5 0.5 0.5 0.05
%/minim) 2.0 2.0 2.0 2.0 2.0 2.0 3.5
VIL(max) 0.8 0.8 0.8 0.8 0.8 0.8 1.5
Current Parameters
IOH -0.4 mA - 1 mA -0.4 mA -2 mA -0.4 mA -1 mA 0.4 mA
icn. 16 mA 20 mA 8 mA 20mA 8 mA 20 mA 0.4 mA
Iiii 40 µA 50 µA 20 µA 20 µA 20 µA 20 µA 1µA
IIL -1.6 mA - 2 mA -0.4 mA -0.5 mA -0.1 mA -0.6 mA 1µA