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L.D. COLLEGE OF
ENGINEERING
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SUB: VLSI Labwork – 2
NAME: SIDDHARTH C. DOSHI
ENROLLMENT NO. : 210280111015
1.Implement CMOS 2-input NAND gate
Paper Work

Microwind Layout: Width: 4 lemda, Length: 20 lemda(n diff.)

 Width: 10 lemda, Length: 20 lemda(p diff.

2D view:
Graph: Voltage Vs. Time

Graph: Voltage and Current

Graph: Voltage Vs. Voltage
 2. Implement CMOS 2-input NOR gate
Paper Work:
Microwind Layout: Width: 4 lemda, Length: 20 lemda(n diff.)
Width: 10 lemda, Length: 20 lemda(p diff.)
2D view:

Graph: Voltage Vs. Time

Graph: Voltage and Current

Graph: Voltage Vs. Voltage

3. Implement CMOS 2-input XOR gate

Paper Work:
Microwind Layout: Width: 4 lemda, Length: 36 lemda(n diff.)
Width: 10 lemda, Length: 36 lemda(p diff.)
2D view:

Graph: Voltage Vs. Time

Graph: Voltage and Current

Graph: Voltage Vs. Voltage

4. Implement CMOS Half Adder Design

Paper Work:
Microwind Layout: Width: 4 lemda, Length: 20 lemda(n diff.)
(For every NOR ) Width: 10 lemda, Length: 20 lemda(p diff.)
2D view:

Graph: Voltage Vs. Time

Graph: Voltage and Current
 5. Implement CMOS 1 bit Full Adder Design
Paper Work:
Gate level after rearranging
Microwind Layout:
Carry:
Width: 4 lemda, Length: 44 lemda(n diff.)
Width: 10 lemda, Length: 44 lemda(p diff.)

Sum:
Width: 4 lemda, Length: 60 lemda(n diff.)
Width: 10 lemda, Length :60 lemda(p diff.)
Carry Layout:
Sum Layout:

2D view:
Graph: Voltage Vs. Time

Graph: Voltage and Current