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Mosfet Transistors

Small Signal Modeling and Analysis

David Johns

When studying transistors, there are 2 main analysis methods used:

(1) Large signal analysis

(2) Small signal analysis

Large signal analysis is used when the voltage/current values changes are large such that the non-linear
behavior of the transistor must be accounted for. Large signal analysis is mainly used for finding the bias
conditions of a circuit. The bias condition of a circuit is the set of voltage/current values that occur in a
circuit when all input signals are set to a fixed dc value. For example, if the circuit is a microphone amplifier,
then the dc bias conditions for that amplifier is the set of voltage/current values for that amplifier when there
is no audio signal on the microphone.

Small signal analysis is used when one wants to ignore the non-linear behaviour of the transistor and
instead look at variations in the voltage/current values from their bias conditions. As an example, this is
useful when looking at how a microphone amplifier responds to a small audio signal.

This summary will go over the small signal models that are used for small signal analysis for Mosfet tran-
sistors.

NMOS Mosfet transistors small signal modelling

The small signal model for a transistor is a linear model that replaces the transistor in the circuit for small
signal analysis. When doing small signal analysis, we are finding the variations in voltage/current from their
bias values due to an input signal. Since independent sources (used to put the transistors in their bias
condition) do not change their values, all independent sources (both voltage and current) are set to zero for
small signal analysis. Of course, the independent source for the input signal of interest does not get set to
zero.

There are different small signal models depending on the region of operation of the transistor.

To find the small signal models shown below, the derivatives dID /dVGS and dID /dVDS are taken in the
different regions of operation.

Cutoff Region

In the case the transistor is in the cutoff region, ID = 0 which results the following small signal model
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G D
G vgs

VGS

S S

NMOS - cutoff small-signal model - cutoff

In the cutoff region, the transistor is essentially an open circuit for all the nodes.

Triode Region

If the transistor is in the triode region, the small signal model is to have a fixed resistor, rds , between the
drain/source nodes as shown below.

G D
G vgs rds

VGS

S S

NMOS - triode small-signal model - triode

The value of rds is determined by the dc bias voltage Vov .

rds = (µn Cox (W /L)Vov )−1

This triode model is valid when the dc bias voltage VDS is a small value. As VDS increases in value, the
model moves closer to the active region model.

Active Region

For the active region, the small signal model is to have a voltage-controlled current-source between the
drain and source as well as a resistor, ro that models the increase in the drain current as the drain/source
voltage increases.
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G D
G vgs gm vgs ro
VGS

S S
NMOS - active small-signal model - active

The value for ro is given by

ro = (λn ID )−1
The value for gm can be written in 3 ways (all of which are equivalent)
gm = µn Cox (W /L)Vov

gm = 2ID /Vov
p
gm = 2µn Cox (W /L)ID
The 3 different ways of writing gm gives some insight into how gm relates do different design parameters.
For example, if a circuit designer decides to keep Vov a constant value (which is often done), then we can
see from the second equation that gm is proportional to the dc current through the transistor.

An alternate small signal model that can be useful for hand analysis is the T-model as shown below

D
D

is
G ro
G
is rs
VGS
rs = 1/gm
S
S
NMOS - active small-signal T-model - active

This model makes use of a current-controlled current-source where the controlling current is is (the current
through rs ). One can verify that the gate current here is still zero since the drain current is forced to be
equal to the source current. This model can be useful for rapid hand analysis when there are resistors in
the source lead (known as resistor degeneration) or when a common-drain amplifier is being used.

PMOS Mosfet transistors small signal modelling

It turns out the small signal models for PMOS transistors is the same as for NMOS transistors without any
sign changes except that |λp | should be used (since λp < 0) and ro should remain positive.
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λ is a function of channel length

When λ is given for a transistor, it is given for a specific channel length L. In general, the channel length
modulation parameter λ is inversely proportional to the gate length, L. So we can define a new parameter
λ0 as
λ0 ≡ λL
such that λ is now written as
λ0
λ=
L
The units of λ0 are [m/V ].

Making use of the above definition, we now have the following equation for ro

L
ro =
λ0 ID

So now we can give a single channel length modulation parameter, λ0 , that is valid for a multiple transistor
lengths that a circuit designer might use.

We see here that ro is proportional to channel length. Since an ideal transistor would have ro → ∞, we see
that a longer channel length makes a more ideal transistor in terms of output impedance. Unfortunely, a
longer channel length has other disadvantages such as reduced speed and more power dissipation. This
tradeoff will be discussed when looking at the frequency response of transistors.

Example 1

For the circuit below, find vo /vi . Voltage VG is used to set the dc bias conditions while vi is a small signal
voltage.

Vtn = 0.3V
VDD = 2V µn Cox = 240µA/V2
W = 4µm
L = 200nm
RD λ0n = 50nm/V
1kΩ
vi vo
VG M1
0.6V

Here we have VGS = VG since the source is at ground. We can then find Vov and ID so that we can find the
small signal parameters, gm and ro .

Vov = VGS − Vtn = (0.6) − (0.3) = 0.3V

2
ID = 0.5 ∗ µn Cox ∗ (W /L) ∗ Vov 2 = 0.5 ∗ (240e − 6) ∗ ((4e − 6)/(200e − 9)) ∗ (0.3) = 216µA
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gm = 2 ∗ ID /Vov = 2 ∗ (216e − 6)/(0.3) = 1.44e − 3

ro = L/(λ0n ∗ ID ) = (200e − 9)/((50e − 9) ∗ (216e − 6)) = 18.52kΩ
We now have the following small signal circuit where independent sources have been set to zero.

RD

vo

vi vgs gm vgs ro

Here we see that

vo = −gm vgs × (RD ||ro )
and since vgs = vi , we find

vo /vi = −gm ∗ (RD ||ro ) = −(1.44e − 3) ∗ ((1e3)||(18.52e3)) = −1.366V/V

Example 2

For the circuit below, find vo /vi , Rin , and Rout . Capacitor C is shown as a large value such that it can be
considered an open circuit for dc bias analysis and a short circuit for small signal analysis (we assume here
that the small signal analysis will be done at a frequency such that the capacitor impedance is so small, it
can be ignored).
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Vtn = 0.3V
VDD = 2V µn Cox = 240µA/V2
W = 10µm
L = 200nm
RS λ0n = 50nm/V

M1 C (large value)
vi 1kΩ Rin vo
Rout RL
500µA
1kΩ

VSS = −2V

For dc analysis, we set vi = 0 and we find M1 is in the active region with Vov = 0.2887V, VS = −0.5887V,
and ID = 500µA.

With the above dc values, we find the following small signal parameters

gm = 2 ∗ ID /Vov = 2 ∗ (500e − 6)/(0.2887) = 3.464mA/V

rs = 1/gm = 1/(3.464e − 3) = 288.7Ω
ro = L/(λ0n ∗ ID ) = (200e − 9)/((50e − 9) ∗ (500e − 6)) = 8kΩ

For small signal analysis, we set all independent voltages (VD D, VS S and the 500µA current source) to zero
as well as short the capacitor as discussed above. We then have the following circuit to analyze

RS
M1
vi Rin vo
Rout
RL

and then we substitute the T-model for M1 to get

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RS is
vg
ro
vi Rin rs
is
vo
Rout
RL

From the above circuit, we can find the gain from vin to vg as
 
Rin
vg = × vin
Rin + RS

and since the gate current is zero, we see that Rin goes to infinity resulting in

vg = vin

Next, we see that there is a resistive divider between vg and vo

 
RL ||ro
vo = × vg
(RL ||ro ) + rs

Combining these 2 results we have

RL ||ro (1e3)||(8e3)
vo /vin = = = 0.7549V/V
(RL ||ro ) + rs ((1e3)||(8e3)) + (288.7)

Finally, when finding Rout , we set all independent sources to zero, so we set vin to zero which results in
vg = 0. As a result,
Rout = rs ||ro = (288.7)||(8e3) = 278.6Ω

Example 3

For the circuit below, find vo /vi , Rin , and Rout . Capacitors values are all shown as infinity so that they can
be considered an open circuit for dc bias analysis and a short circuit for small signal analysis.
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VDD = 2V

Vtp = −0.3V
I1 µp Cox = 120µA/V2
∞ W = 10µm
500µA
L = 200nm
R2 λ0p = 0m/V
1kΩ
RS ∞
M1 ∞
vi 1kΩ vo
Rin RG RD Rout RL
10kΩ 3kΩ 10kΩ

VSS = −2V

For dc analysis, we set vi = 0 and we find M1 is in the active region with Vov = 0.4082V, VS = 0.7082V, and
ID = 500µA.

With the above dc values, we find the following small signal parameters

gm = 2 ∗ ID /Vov = 2 ∗ (500e − 6)/(0.4082) = 2.449mA/V

rs = 1/gm = 1/(2.449e − 3) = 408.2Ω
ro = L → ∞
ro approaches infinity since it is given that λ0p = 0m/V

This leads to the following small signal circuit where capacitors have been shorted and independent sources
have been set to zero.

R2
RS
M1
vi vo
Rin RG Rout
RD RL

and replacing M1 with its small signal model, we have

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R2

RS is rs
vg

is
vi
Rin RG vo
Rout
RD RL

For Rin , since the gate current is zero, Rin = RG .

For Rout , we set vi = 0 which results in is = 0. As a result,

Rout = RD = (3e3) = 3kΩ

For vo /vi , first find vg /vi which we see is a resistive divider, so

vg /vi = RG /(RG + RS ) = (10e3)/((10e3) + (1e3)) = 0.9091V/V

Now find, vo /vg , which we find as

vo = −is × (RD ||RL )
is = vg /(rs + R2 )
Combining the above 2 equations, we have

vo /vg = −1 ∗ (RD ||RL )/(rs + R2 )) = −1 ∗ ((3e3)||(10e3))/((408.2) + (1e3))) = −1.639V/V

and combinging this result with vg /vi we have

vo vo vg
= = −1.49V/V
vi vg vi