A Switch-Capacitor Converter with LC resonator
and bypassed inductor during off-state
Doan Minh Tien1, Tran Hong Quan1, Nguyen Minh Tan1, Pham Xuan Thanh1
1
Faculty of Electronics Engineering, Ha Noi University of Industry
Abstract— This paper presents a resonant switched-
capacitor voltage regulator combined with a LC resonator to
reduce off-chip passive components usage thereby achieving
a fully integrated voltage regulation scheme. A simple bypass
scheme for the inductor during off-state is also proposed
aiming at reducing power losses in off time of the device. The
voltage regulator is designed using 180nm CMOS process,
achieving up to 95% power stage efficiency at 2.4V input and
a peak efficiency of 89% for close loop utilization.
Keywords—: DC-DC converters, voltage regulator,
resonant converters, switched-capacitor
I. INTRODUCTION
The advancement in semiconductor scaling described
by Moore’s law has make us seen the introduction of low-
power and high performing designs in all sorts of
applications. We now see a plethora of electronics devices
with greatly enhanced functionality and yet with ever
decreasing size over the years. The problem being, passive
components governed by Maxwell’s law struggle with
materials physical properties and therefore are lagging
behind the scaling potential of semiconductor devices.
And as a result, in the realm of power electronics where
passive components are heavily relied on have seen a
major issue of keeping energy efficiency while also
decreasing devices size.
The problem above has shown the need of new
architectures to further harness power and energy density
of passive components and delving deeper into the
physical level technologies, finding new integration
strategy in order to leverage synergies afforded by
Maxwell’s equations [1].
When it comes to passive components, inductors
suffer the most in scaling down to smaller sizes. Using
spiral magnetics is an option since it is convenient due to
planar processing but for power conversions [2]-[4], but
proves to be problematic for having limitations in
handling large currents and have a low operating
frequency. Moreover, spiral structures tend to direct
magnetic fields into the substrate, resulting in eddy
current losses and planar spiral magnetics also have to
deal with current crowding at the inner edges of loops
thereby increasing the AC resistance combined with the
fact that its vertical dimension is thin resulting in even
more resistance.
In this work, we introduced a straightforward
bypassing scheme for the on-chip flying inductors, aiming
to address several key challenges efficiently. By
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implementing this simple solution, notable benefits
emerge, especially in the reduction of power losses during
off-states of the converter operation and the mitigation of
current spikes caused by leakage currents. Additionally,
the bypassing scheme plays an important role in avoiding
the necessity of utilizing additional voltages to bias the
NMOS's bulk. This approach not only simplifies the
overall circuit design but also contributes to enhanced
efficiency and reliability, aligning with the goal of
optimizing performance while minimizing complexity.
II. TWO-PHASE RESONANT SWITCH-CAPACITOR
CONVERTER
Fig. 1 Overview of the converter structure with integrated
OTM control scheme and on-chip passive components
Fig. 2 Inductor bypass scheme during off-time
Fig. 3 Schematic of interleaved converter phases and its
voltage and current waveforms
Fig. 1 shows the entire concept of the schematic
implementation in this paper. The circuit comprise of 2
separate gate driver schemes for dual phase operation
connected with a VCO, OTA and the Switched-Capacitor
power stage which is interfacing with the merged LC
resonator. The power stage switches only use NMOS
exclusively with an integrated feedback loop supported by
the VCO and OTA mentioned above to control the
switching time and maintain appropriate regulation during
transients.
Fig. 3 shows the interleaving phases of power stage
along with the corresponding currents and voltages
waveforms. The converter showcases a 2:1 conversion
ratio, employing two switching phases for each cycle with
2π
the switching period Tsw = . Phases are
√ Leff . C fly
symmetrically arranged 180 degrees out of phase for
optimizing the use of on-chip bypass capacitance while
lowering the voltage ripple. As detailed in [8], using
symmetric two-phase interleaving significantly reduces
output volage ripple down to 1/5th comparing to a single-
phase design with the same bypass capacitance. Also if
the same ripple is to be maintained, that allows us to
greatly decrease the bypass capacitance down to 5 times
less than what a single-phase design would require. But it
is noteworthy that there is a trade-off, as coupling
capacitance between interleaving phases create losses.
This effect can become greatly problematic when it comes
to higher voltage swings and high switching frequencies,
therefore need to be considered when using interleaving
phases.
Bypass capacitances are fully integrated, dividing
equally between Vin - Vout and Vout - gnd. This equal
separation will maintain symmetry of two switching
phases provide that resonant frequencies are also equal.
This will benefit us in canceling out the ripple at the input
without needing more bypass capacitance.
As depicted in Fig. 3, using interleaved operation
creates currents that fluctuate over time in sync but with
reverse directions. The arrangement above allows for
coupling magnetic fields and give us higher inductance
with the same space needed by the self-inductances of
each phase [7], [9]. Therefore, consolidating inductors
into one contruct reduces the operating frequency as well
as improve the overall efficiency and power density when
compared to the same implemention minus the coupling
part.
A simple inductor bypass scheme is also employed to
mitigate the ringing noise caused by the LC resonator.
Two power switches will be placed to provide an
unconstricted path for the current when the converter enter
Off-time as shown in Fig. 2.1, each are controlled by a
NOR logic gate so that when both control clock signal are
absent the resonator’s ringing is reduced, energy
consumption during Off-state will be lowered therefore
increasing the overall efficiency of the converter.
Fig. 4 Gate driver schematic for a single phase
Fig. 4 is the simplified schematic of the gate driver for
one phase of the converter. As mentioned above, for using
NMOS for all switches, we will need a bootstrap scheme
for the highside switches. Once clka rises, it undergoes
level shifting to turn on M1 and M3, this connects the
source terminals of M2 and M4 to gnd and Vout,
respectively. Charging our resonator through Cin. In the
opposite phase, M2 and M4 turns on when clkb rises and
discharge the resonator via C out and supply Vout. More
details will be available in section IV.
III. CIRCUIT IMPLEMENTATION
A. Control scheme
Fig. 6 Clock generator control scheme
The converter employs a voltage-mode control style
off-time modulation (OTM) scheme. Figure below shows
the clock generation circuit and its waveforms. The “On-
time” of the circuit is determined by the frequency of the
LC tank while “Off-time” is use to regulate the delay
between resonant pulses. An Operational
Transconductance Amplifier (OTA), which compare the
output voltage to a reference to generate a current signal
in proportion to the error then is injected to a Voltage
Controlled Oscillator (VCO). This current will adjust the
discharge rate of Vc,off so we can interfere with the time it
takes for the flip flop to change states. The same thing
happen on the Vc,on side.
Different from the “Off-time”, the “On-time” is fixed
by an external voltage supply so that it equal half of the
resonant period so we can achieve zero-current switching
(ZCS). With this OTM scheme, the switching frequency
will be adjusted through Off-time, resulting in less
switching losses and linear scaling for the converter’s
effective resistance. For a give Off-time we will the
expression of Reff = 1 + (tON/tOff) * Reff,full resonant
It’s important to remember that this a linear regulation
scheme therefore when the conversion ratio gets lower
and lower the voltage ripple will be significant since the
Toff is being stretched too long which is very problematic
in scenarios where bypass capacitance is limited. But still
this OTM scheme has offered enhanced efficiency during
light-load and fast regulation.
B. Gate Driver
Fig. 7 Bootstrapped gate drive circuit with level shifter
Fig. 8 Deadtime generation schematic
Fig. 9 Level shift and buffer chain to deliver gate charge
Each converter phase comprises two complementary
switch pairs. In the higher voltage domain pair, V pos and
Vneg is coupled to Vin and Vout, respectively. While the
lower domain pair has V pos linked to Vout and Vneg
connected to gnd. All low sides switches are referenced to
ground and Vout, whereas high side switches remain
floating and require bootstrapping to operate properly.
Fig. 8 shows the deadtime generation scheme by using
digital logics, deadtime will be inserted between clk a and
clkb in order to create high side and low side gate signals
as well as the bootstrap enable signal. Bootstrap
capacitors are charged from external voltage sources, V gdG
and VgdL, which is 1.2V referenced to Vout and gnd.
Fig. 9 shows the level shifter used in the gate driver, to
minimized propagation delay to less than 800ps while
maintaining low current consumption, switches M1 and
M2 sink capacitive gate charge from diode-connected
devices M3 and M4 through roughly 5V cascodes at M 5,
M6. M3 and M4 use long-channel devices to increase C gs
and decrease propagation delay while used up minimal
current. The current signal will be amplified and
digitalized to generate the level-shifted voltage from V L to
VH. VL connects to the source of respective power switch
while VH is linked to the supply of the gate driver. As
shown in Fig. 9 the level-shifted signal then pass through
a simple buffer chain consists of NOT logic gates.
IV. SIMULATION RESULTS
This paper proposed a design of a dual-phase switched-
capacitor converter with on-chip merged LC resonator and
a inductor bypassing scheme implemented in 180nm
CMOS technology. The converter operates in two phases
using on-chip passive components and NMOS exclusively
in the power stage, providing enhanced efficiency with a
peak performance efficiency of 89% with an operating
frequency of 43.5 MHz to reduce passive components size.
As you can see with the Load to Efficiency plot, this work
is best suited for applications of light load or ultra-light
load conditions.

Fig 10 The reduced Vout ripple when reaching 1:2 CR (V in

= 2.4V)

Fig 11 Layout of the converter


Table 1 Comparison with similar works
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