BEC302 NOTES

DIGITAL SYSTEM DESIGN USING VERILOG (IPCC)
[BEC302]
3RD SEMESTER, ODD- 2023
Prepared By,
Dr S Padmashree, Professor, Dept. of ECE, GSSSIETW, Mysuru.

Mrs Anitha K, Assistant Professor, Dept. of ECE, GSSSIETW, Mysuru.
Mrs Sharanya A R, Assistant Professor, Dept. of ECE, GSSSIETW, Mysuru.
Dept of ECE, GSSSIETW

DEPARTMENT VISION & MISSION
VISION
"To foster professional level competence in all areas of Electronics and Communication
Engineering and to benchmark the Department as a centre for nurturing Women
Engineers in the Country"
MISSION
M1: To impart value based Technical education and training.
M2: To impart Theoretical Knowledge, Practical Knowledge and Entrepreneurship Skills.
M3: Fostering culture of innovation and research for development of society.
M4: To sensitize the Students regarding Social, Moral and Professional ethics.
M5: To provide industry standard certifications on skills to enhance students knowledge

make them prepared for placements
Program Educational Objective’s
PEO 1: To inculcate students to excel in professional career and/or higher education by

acquiring knowledge in the field of Electronics and Communication.
PEO 2: To make the students capable of managing their profession based on existing as
well as new emerging technologies in the area of Electronics and Communication
Engineering.
PEO 3: To Produce Technically competent graduates with Ability to analyse, design,

develop, optimise and implement Electronics and Communication systems.
PEO 4: To prepare the students to be able to exhibit professionalism, ethical attitude,

communication skills, team work in their profession and to adapt to current trends by
engaging in life-long learning.

PROGRAM OUTCOMES
Engineering Graduates will be able to:
1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialization to the solution of complex engineering problems.
2. Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of mathematics,
natural sciences, and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate consideration
for the public health and safety, and the cultural, societal, and environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities with
an understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the
professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and need for
sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms
of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or leader in
diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive clear
instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and leader
in a team, to manage projects and in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.
Program Specific Outcomes

1. PSO1.Graduates will have the ability to mould the technology in the areas of Analog and Digital
Scenario.
2. PSO2.Implementation of functional Blocks of hardware software co-design for signal processing
and communication application.

COURSE OUTCOMES
Semester & Year: III Semester -ODD 2023

Faculty Name: Dr Padmashree S, Mrs Anitha K & Mrs Sharanya A R
Subject with Code: BEC302
Course Code: C
At the end of the course, the students will be able to:
CO1: Simplify Boolean functions using K-map and Quine-McCluskey minimization technique.
CO2: Analyze and design for combinational logic circuits.
CO3: Analyze the concepts of Flip Flops (SR, D, T and JK) to design the synchronous sequential
circuits using Flip Flops.
CO4: Model Combinational circuits (adders, subtractors, multiplexers) and sequential circuits
using Verilog descriptions.
Digital System Design using Verilog Semester 3
Course Code BEC302 CIE Marks 50
Teaching Hours/Week (L:T:P: S) 3:0:2 SEE Marks 50
Total Hours of Pedagogy 40 hours Theory + 8-10 Lab slots Total Marks 100
Credits 04 Exam Hours 03
Examination nature (SEE) Theory/Practical
Course objectives:
This course will enable students to:
 To impart the concepts of simplifying Boolean expression using K-map techniques and Quine-
McCluskey minimization techniques.
 To impart the concepts of designing and analyzing combinational logic circuits.
 To impart design methods and analysis of sequential logic circuits.
 To impart the concepts of Verilog HDL-data flow and behavioural models for the design of digital
systems.
Teaching-Learning Process (General Instructions)
These are sample Strategies, which teacher can use to accelerate the attainment of the various course
outcomes.
 Lecture method (L) does not mean only traditional lecture method, but different type of
teaching methods may be adopted to develop the outcomes.
 Show Video/animation films to explain the different concepts of Linear Algebra & Signal
Processing.
 Encourage collaborative (Group) Learning in the class.
 Ask at least three HOTS (Higher order Thinking)questions in the class, which promotes
critical thinking.
 Adopt Problem Based Learning (PBL), which fosters students’ Analytical skills, develop
thinking skills such as the ability to evaluate, generalize, and analyze information rather than
simply recall it.
 Topics will be introduced in a multiple representation.
 Show the different ways to solve the same problem and encourage the students to come up
with their own creative ways to solve them.
 Discuss how every concept can be applied to the real world-and when that's possible, it
helps improve the students' understanding.
 Adopt Flipped class technique by sharing the materials/Sample Videos prior to the class and
have discussions on the topic in the succeeding classes.
 Give Programming Assignments.
MODULE-1
Principles of Combinational Logic: Definition of combinational logic, Canonical forms,
Generation of switching equations from truth tables, Karnaugh maps-up to 4 variables, Quine-
McCluskey Minimization
Technique. Quine-McCluskey using Don’t CareTerms.(Section3.1to3.5ofText1).
MODULE-2
Logic Design with MSI Components and Programmable Logic Devices: Binary Adders and
Subtractors, Comparators, Decoders, Encoders, Multiplexers, Programmable Logic Devices(PLDs)
(Section5.1to5.7 ofText2)
MODULE-3
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Flip-Flops and its Applications: The Master-Slave Flip-flops(Pulse-Triggered flip-flops):SR flip-
flops, JK flip flops, Characteristic equations, Registers, Binary Ripple Counters, Synchronous
Binary Counters, Counters based on Shift Registers, Design of Synchronous mod-n Counter using
clocked T, J K, D and SR flip-flops.(Section 6.4, 6.6 to 6.9 (Excluding 6.9.3)of Text2)
MODULE-4
Introduction to Verilog: Structure of Verilog module, Operators, Data Types, Styles of
Description. (Section1.1to1.6.2, 1.6.4 (only Verilog),2 of Text 3)
Verilog Data flow description: Highlights of Data flow description, Structure of Data flow
description.(Section2.1to2.2(only Verilog) of Text3)
MODULE-5
Verilog Behavioral description: Structure, Variable Assignment Statement, Sequential
Statements, Loop Statements, Verilog Behavioral Description of Multiplexers (2:1, 4:1, 8:1).
(Section 3.1 to 3.4 (onlyVerilog)of Text 3)
Verilog Structural description: Highlights of Structural description, Organization of structural
description, Structural description of ripple carry adder.(Section4.1 to 4.2 of Text 3)
PRACTICAL COMPONENT OF IPCC (Experiments can be conducted either using any circuit simulation
software or discrete components)
Sl.N Experiments
1 To simplify the given Boolean expressions and realize using Verilog program
2 To realize Adder/Subtractor(Full/half)circuits using Verilog data flow description.
3 To realize 4-bit ALU using Verilog program.
4 To realize the following Code converters using Verilog Behavioral description
a)Gray to binary and vice versa b)Binary to excess3 and vice versa
5 To realize using Verilog Behavioral description:8:1mux, 8:3encoder, Priority encoder
6 To realize using Verilog Behavioral description:1:8Demux, 3:8 decoder,2 –bit Comparator
7 To realize using Verilog Behavioral description:
Flip-flops: a)JK type b)SR type c)T type and d)D type
8 To realize Counters-up/down (BCD and binary)using Verilog Behavioral description.
Demonstration Experiments (For CIE only–not to be included for SEE)
Use FPGA/CPLD kits for down loading Verilog codes and check the output for interfacing
experiments.
9 Verilog Program to interface a Stepper motor to the FPGA/CPLD and rotate the motor
in the specified direction (by N steps).
10 Verilog programs to interface Switches and LEDs to the FPGA/CPLD and demonstrate
its working.
Course outcomes (Course Skill Set):
At the end of the course the student will be able to:
1. Simplify Boolean functions using K-map and Quine-McCluskey minimization technique.
2. Analyze and design for combinational logic circuits.
3. Analyze the concepts of Flip Flops(SR, D,T and JK) and to design the synchronous sequential
circuits using Flip Flops.
4. Model Combinational circuits (adders, subtractors, multiplexers) and sequential circuits using
Verilog descriptions.
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Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is
50%. The minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50)
and for the SEE minimum passing mark is 35% of the maximum marks (18 out of 50 marks). The
student is declared as a pass in the course if he/she secures a minimum of 40% (40 marks out of 100)
in the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester End Examination)
taken together.
The IPCC means the practical portion integrated with the theory of the course. CIE marks for the
theory component are 25 marks and that for the practical component is 25 marks.
CIE for the theory component of the IPCC
 25 marks for the theory component are split into 15 marks for two Internal Assessment Tests
(Two Tests, each of 15 Marks with 01-hour duration, are to be conducted) and 10 marks for other
assessment methods mentioned in 22OB4.2. The first test at the end of 40-50% coverage of the
syllabus and the second test after covering 85-90% of the syllabus.
 Scaled-down marks of the sum of two tests and other assessment methods will be CIE marks for
the theory component of IPCC (that is for 25 marks).
 The student has to secure 40% of 25 marks to qualify in the CIE of the theory component of
IPCC.
CIE for the practical component of the IPCC
 15 marks for the conduction of the experiment and preparation of laboratory record, and 10
marks for the test to be conducted after the completion of all the laboratory sessions.
 On completion of every experiment/program in the laboratory, the students shall be evaluated
including viva-voce and marks shall be awarded on the same day.
 The CIE marks awarded in the case of the Practical component shall be based on the continuous
evaluation of the laboratory report. Each experiment report can be evaluated for 10 marks. Marks
of all experiments’ write-ups are added and scaled down to 15 marks.
 The laboratory test (duration 02/03 hours) after completion of all the experiments shall be
conducted for 50 marks and scaled down to 10 marks.
 Scaled-down marks of write-up evaluations and tests added will be CIE marks for the laboratory
component of IPCC for 25 marks.
 The student has to secure 40% of 25 marks to qualify in the CIE of the practical component of the
IPCC.
SEE for IPCC

Theory SEE will be conducted by University as per the scheduled timetable, with common question
papers for the course (duration 03 hours)
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 sub-questions), should have a mix of topics under that module.
3. The students have to answer 5 full questions, selecting one full question from each module.
4. Marks scored by the student shall be proportionally scaled down to 50 Marks
The theory portion of the IPCC shall be for both CIE and SEE, whereas the practical portion
will have a CIE component only. Questions mentioned in the SEE paper may include questions
from the practical component.
 The minimum marks to be secured in CIE to appear for SEE shall be 10 (40% of maximum
marks-25) in the theory component and 10 (40% of maximum marks -25) in the practical
component. The laboratory component of the IPCC shall be for CIE only. However, in SEE,
the questions from the laboratory component shall be included. The maximum of 04/05 sub-
questions are to be set from the practical component of IPCC, the total marks of all questions
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should not be more than 20 marks.
 SEE will be conducted for 100 marks and students shall secure 35% of the maximum marks to
qualify for the SEE. Marks secured will be scaled down to 50.
 The student is declared as a pass in the course if he/she secures a minimum of 40% (40 marks
out of 100) in the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester
End Examination) taken together.
Suggested Learning Resources:
Books
1. Digital Logic Applications and Design by John MYarbrough,Thomson Learning,2001.
2. Digital Principles and Design by Donald DGivone,McGrawHill, 2002.
3. HDL Programming VHDL and Verilog by Nazeih M Botros, 2009 reprint, Dream techpress.
ReferenceBooks:
1. Fundamentals of logic design, by Charles H Roth Jr., Cengage Learning
2. Logic Design, by Sudhakar Samuel, Pearson/Sanguine, 2007
3. Fundamentals of HDL,by Cyril PR, Pearson/Sanguine2010
Web links and Video Lectures (e-Resources):
Activity Based Learning (Suggested Activities in Class)/ Practical Based learning

Programming Assignments/Mini Projects can be given to improve programming skills.
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DIGITAL SYSTEM DESIGN USING VERILOG (BEC302)
Module – 1
Principles of Combinational Logic: Definition of combinational logic, Canonical forms,

Generation of switching equations from truth tables, Karnaugh maps- up to 4 variables, Quine-
McCluskey Minimization Technique. Quine-McCluskey using Don‟t Care Terms. (Section
3.1 to 3.5 of Text 1).
1.1 Introduction
In digital logic design only two voltage levels or states are allowed and these states are
generally referred to as Logic “1” and Logic “0”, or HIGH and LOW, or TRUE and FALSE.
These two states are represented in Boolean algebra and standard truth tables by the binary
digits of “1” and “0” respectively.
A good example of a digital state is a simple light switch. The switch can be either “ON” or
“OFF”, one state or the other, but not both at the same time. Then we can summarize the
relationship between these various digital states as being:
Logic gates are the heart of digital electronics. A gate is an electronic device which is used to
compute a function on a two valued signal. Logic gates are the basic building block of digital
circuits. Basic digital logic gates perform logical operations of AND,
OR and NOT on binary numbers. Basically, all logic gates have one output and two inputs.
Some logic gates like NOT gate or Inverter has only one input and one output. By combining
logic gates, we can design many specific circuits like flip flops, latches, multiplexers, shift
registers etc.
Digital systems are said to be constructed by using logic gates. These gates are the AND, OR,
NOT, NAND, NOR, EXOR and EXNOR gates. The basic operations are described below with
the aid of truth tables.
Dept. of ECE, GSSSIETW, Mysuru Page 1

OR Gate
The OR Gate is an electronic circuit that gives high output (logic level “1” output) if any of
the input or all its inputs are high. Returns low output (logic level “0” output) only if all its
inputs are low.
The logic or Boolean expression given for a digital logic OR gate is that for Logical Addition
which is denoted by a plus sign, ( + ) giving us the Boolean expression of: X+Y =
Z.
AND Gate
The AND gate is an electronic circuit that gives a high output (logic level “1” output) only
if all its inputs are high. The logic or Boolean expression given for a digital logic AND gate
is that for Logical Multiplication which is denoted by a single dot or full stop symbol, ( . )
giving us the Boolean expression of: X.Y = Z.

NOT Gate
The NOT gate is an electronic circuit that gives a high output (logic level “1” output) when
its input is at Low (logic level “0”). The Boolean expression of: X = Z. NOT Gate
“inverts” (complements) its input signal.
NAND Gate
The NAND (Not – AND) gate has an output that is normally at logic level “1” and only goes
“LOW” to logic level “0” when ALL of its inputs are at logic level “1”. The Logic NAND
Gate is the reverse or “Complementary” form of the AND gate we have seen previously.
NOR Gate
The inclusive NOR (Not-OR) gate has an output that is normally at logic level “1” and only
goes “LOW” to logic level “0” when ANY of its inputs are at logic level “1”. The Logic NOR
Gate is the reverse or “Complementary” form of the inclusive OR gate we have seen
previously.

EX-OR Gate (Exclusive OR Gate)
Exclusive OR gate – is a digital logic gate that gives a true (i.e. a HIGH or 1) output when
the number of true inputs is odd. .... This gate is called as XOR or exclusive OR gate because,
its output is only 1 when one of its input is exclusively 1.
EX-NOR Gate (Exclusive NOR Gate)
Z=X‟Y‟+XY
The operation of Exclusive NOR gate is reciprocal to the Exclusive OR gate‟s operation.
Basically the “Exclusive-NOR” gate is a combination of the Exclusive-OR gate and the NOT
gate. However, an output “1” is only obtained if BOTH of its inputs are at the same

logic level, either binary “1” or “0”. For example, “00” or “11”. This input combination
would then give us the Boolean expression of:
1.2 Combinational Circuits
1.2.1 Definition of Combinational Logic
Combinational circuit is a circuit in which we combine the different gates in the circuit, for
example Adders, Subtractors, encoder, decoder, multiplexer and demultiplexer.
Some of the characteristics of combinational circuits are following −
• The output of combinational circuit at any instant of time depends only on the levels
present at input terminals.
• The combinational circuits do not use any memory. The previous state of input does
not have any effect on the present state of the circuit.
• A combinational circuit can have an n number of inputs and m number of outputs.
• Combinational circuits are logic circuits without feedback from output to the input.
(F)
Figure 1.1: Combinational Logic Model

Let X be the set of all input variables {x0, x1, x2, ……xn}, and Y be the set of all
output variables {y0, y1, y2….ym}. The combinational function, F, operates on the
input variable set X, to produce the output variable set, Y.
Y = F(X).

Figure 1.2: General logic design sequence
The relationship between the input and output variables can be expressed in equations, logic
diagrams, or truth tables.
A truth table specifies the input conditions under which the outputs are true or false (1 or 0).
Switching equations are then derived from the truth tables and realized or constructed using
gates.
The three main ways of specifying the function of a combinational logic circuit are:
• Boolean Algebra – This forms the algebraic expression showing the operation of the
logic circuit for each input variable either True or False that results in a logic “1”
output.
• Truth Table – A truth table defines the function of a logic gate by providing a concise
list that shows all the output states in tabular form for each possible combination of
input variable that the gate could encounter.

• Logic Diagram – This is a graphical representation of a logic circuit that shows the
wiring and connections of each individual logic gate, represented by a specific
graphical symbol, that implements the logic circuit and all three of these logic circuit
representations are shown below.
Example 1: Design a combinational logic truth table so that an output is generated indicating
when majority of four inputs is true.
Solution: The circuit has four inputs and single output. Let I1, I2, I3, & I4 be the input
variables and O1 be the output variable.
Input Variables Output Variable

I1 I2 I3 I4 O1
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
The switching equations,
M1 = I2I3I4 + I1I3I4 + I1I2I4 + I1I2I3 + I1I2I3I4,
Notice that each AND term (also called a product term) identifies one input condition where
the output is a 1.
1.2.2 Definitions:
1. Literal: A Literal is a Boolean variable or its complement. For instance, let X be a
binary variable, then both X and X‟ would be literals.

2. Product term: A product term is a literal or the logical product (AND) of multiple
literals. For example, let A, B & C be binary variables. Then product term could be A,
AB, ABC or A‟B‟C.
3. Sum term: A sum term is a literal or the logical sum (OR) of multiple literals. For
example, let A, B & C be binary variables. Then sum term could be A, A+B, A+B+C
or A‟+B‟+C.
4. Sum of Products: A sum of products (SOP) is the logical OR of multiple product
terms. Each product term is the AND of binary literals. For example, let A, B & C be
binary variables. Then SOP expression could be AB+ABC+A‟B‟C.
5. Product of Sums: A product of sums (POS) is the logical AND of multiple product
terms. Each product term is the OR of binary literals. For example, let A, B & C be
binary variables. Then POS expression could be (A+B)(A+B+C)(A‟+B‟+C).
6. Minterm: A minterm is a special case product (AND) term. A minterm is a product
term that contains all of the input variables (each literal no more than once) that
makeup a Boolean expression.
7. Maxterm: A maxterm is a special case product (OR) term. A maxterm is a product
term that contains all of the input variables (each literal no more than once) that
makeup a Boolean expression.
8. Canonical sum of products: A canonical sum of products is a complete set of
minterms that defines when an output variable is a logical 1. To derive the Sum of
Products form from a truth table, OR together all of the minterms which give a
value of 1. Consider the truth table as example,
Here SOP is f(X.Y) = X.Y' + X.Y
9. Canonical Product of Sums: A canonical product of sums is a complete set of

maxterms that defines when an output variable is a logical 0. To derive the Product
of Sums form from a truth table, AND together all of the maxterms which give
a value of 0. Consider the truth table from the previous example,
Here POS is F(X,Y) = (X+Y')

1.2.3 Minterms and maxterms
A binary variable may appear either in its normal form (x) or in its complement form (x' ).
Now consider two binary variables x and y combined with an AND operation. Since each
variable may appear in either form, there are four possible combinations: x' y', x'y. xy ' , and
xy. Each of these four AND term s is called a minterm, or a standard product.
In a similar fashion, n variables forming g an OR terrn with each variable being primed or
Unprimed provide 2" possible combinations called maxterm. or standard sums.
• A minterm is the product of N distinct literals where each literal occurs exactly once.
• A maxterm is the sum of N distinct literals where each literal occurs exactly once.
For a two-variable expression, the minterms and maxterms are as follows
For a three-variable expression, the minterms and maxterms are as follows
1.3 Canonical Forms

Canonical is a word used to describe a condition of a switching equation. The canonical form
of a positive integer in decimal representation is a finite sequence of digits that does not
begin with zero.
Two formats generally exist for expressing switching equations in a canonical form:
➢ Sum of Minterms
➢ Product of Maxterms
To place a SOP equation into canonical form using Boolean algebra,
1. Identify the missing variables in each AND term.

2. AND the missing term and its complement with the original AND term, xy(z+z’).
Because (z+z’) =1, the original AND term value is not changed.
3. Expand the term by application of the property of distribution, xyz + xyz’.
To place a POS equation into canonical form using Boolean algebra,
1. Identify the missing variables in each OR term.

2. OR the missing term and its complement with the original OR term, x+y+(zz’).
Because (zz’) =0, the original OR term value is not changed.
3. Expand the term by application of the property of distribution, (x+y+z) ( x+y+z’).
Example 1:

Example 2:
Example 3:

Example 4:
1.4 Generation of Switching Equations from Truth Tables

Switching equations can be written by using the Minterm or maxterm numerical designation,
instead of writing the variable names or their complements.
For example, consider the canonical SOP equation P = (ab’c + ab’c’ + abc’ + abc + a’bc).
If we decode each of the minterms based on the binary weighing of each variable and
produce a list of decimal decoded minterms, the result would be P = f(a, b, c) = ∑ (5, 4, 6, 7,
3).
The sign ∑ indicates summation and stands for the sum of products canonical form. The π
(Pi) sign is used to indicate product of sums canonical form.
Example 1:

a b c d M
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
Only one output variable (M) exists so only one equation is needed. The complete output
equation contains a set of minterms ORed together.
The minterm expression for the output variable, M, is
M = f(a, b, c, d) = a’bcd + ab’cd + abcd =∑(7, 11, 15)
The maxterm expression for the output variable, M, is
M = f(a, b, c, d) = (a+b+c+d) (a+b+c+d’) (a+b+c’+d) (a+b+c’+d’) (a+b’+c+d)

(a+b’+c+d’)
(a+b’+c’+d) (a’+b+c+d) (a’+b+c+d’) (a’+b+c’+d) (a’+b’+c+d)
(a’+b’+c+d’) (a’+b’+c’+d)
=π(0, 1, 2, 3, 4, 5, 6, 8, 9, 10, 12, 13, 14)
Example 2:

a b c M1 M2 M3 M4 M5
0 0 0 0 1 1 0 0
0 0 1 1 1 0 0 0
0 1 0 1 0 1 0 0
0 1 1 1 0 0 1 0
1 0 0 0 1 1 0 0
1 0 1 0 1 0 1 0
1 1 0 0 0 1 1 0
1 1 1 0 0 0 0 1
Five output variables exist: M1, M2, M3, M4, & M5. Each output variable requires a
separate switching expression. Writing the output equations,
M1 = f(a, b, c) = a’b’c + a’bc’ + a’bc

M2 = f(a, b, c) = a’b’c’ + a’b’c + ab’c’ +ab’c
M3 = f(a, b, c) = a’b’c’ + a’bc’ + ab’c’ + abc’
M4 = f(a, b, c) = a’bc + ab’c + abc’
M5 = f(a, b, c) = abc
Writing the same equations using decimal list notation, we get
M1 = f(a, b, c) = ∑(1, 2, 3)
M2 = f(a, b, c) = ∑(0, 1, 4, 5)
M3 = f(a, b, c) = ∑(0, 2, 4, 6)
M4 = f(a, b, c) = ∑(3, 5, 6)
M5 = f(a, b, c) = ∑(7)
The maxterm expressions written in decimal form are,
M1 = f(a, b, c) = π(0, 4, 5, 6, 7)
M2 = f(a, b, c) = π (2, 3, 6, 7)
M3 = f(a, b, c) = π (1, 3, 5, 7)
M4 = f(a, b, c) = π (0, 1, 2, 4, 7)
M5 = f(a, b, c) = π (0, 1, 2, 3, 4, 5, 6)
Example 3:
Express the following SOP equations in a minterm (shorthand decimal notation) list form:
a). H = f(A, B, C) = A’BC + A’B’C +ABC
A’BC = (011)2 = (3)10
A’B’C = (001)2 = (1)10
ABC = (111)2 = (7)10
Rearrange the decoded decimal values in numerical order:
H = f(A, B, C) =∑(1, 3, 7)

b). G = f(w, x, y, z) = wxyz’ + wx’yz’ + w’xyz’ + w’x’yz’
wxyz’ = (1110)2 = (14)10
wx’yz’= (1010)2 = (10)10
w’xyz’= (0110)2 = (6)10
w’x’yz’= (0010)2 = (2)10
Rearrange the decoded decimal values in numerical order:
G = f(w, x, y, z) = ∑(2, 6, 10, 14)
Example 4:
Express the following POS equations in a minterm (shorthand decimal notation) list form:
a). T = f(a, b, c) = (a+b’+c)(a+b’+c’)(a’+b’+c)
a+b’+c = (010)2 = (2)10
a+b’+c’= (011)2 = (3)10
a’+b’+c = (110)2 = (6)10
T = f(a, b, c) =π(2, 3, 6)
b). J = f(A, B, C, D) =
(A+B’+C+D)(A+B’+C+D’)(A’+B+C+D)(A’+B’+C+D)(A’+B+C’+D)
(A’+B’+C’+D)
A+B’+C+D = (0100)2 = (4)10
A+B’+C+D’ = (0101)2 = (5)10
A’+B+C+D = (1000)2 = (8)10
A’+B’+C+D = (1100)2 = (12)10
A’+B+C’+D = (1010)2 = (10)10
A’+B’+C’+D = (1110)2 = (14)10
J = f(A, B, C, D) = π(4, 5, 8, 10, 12, 14)

1.5 KARNAUGH MAPS

Maurice Karnaugh, a telecommunications engineer, developed the Karnaugh map at Bell
Labs in 1953 while designing digital logic based telephone switching circuits. Karnaugh maps
reduce logic functions more quickly and easily compared to Boolean algebra.
A Karnaugh map provides a pictorial method of grouping together expressions with common
factors and therefore eliminating unwanted variables. The Karnaugh map can also be described
as a special arrangement of a truth table.
1.5.1 Construction of a Karnaugh Map

1. Each square containing a „1„ must be considered at least once, although it can be
considered as often as desired.
2. The objective should be to account for all the marked squares in the minimum number
of groups.
3. The number of squares in a group must always be a power of 2, i.e. groups can have
1, 2, 4, 8, 16, squares.
4. Each group should be as large as possible, which means that a square should not be
accounted for by itself if it can be accounted for by a group of two squares; a group of
two squares should not be made if the involved squares can be included in a group of
four squares and so on.
5. Don„t care entries can be used in accounting for all of 1-squares to make optimum
groups. They are marked „X„ in the corresponding squares. It is, however, not
necessary to account for all don„t care entries. Only such entries that can be used to
advantage should be used.
The diagram below illustrates the correspondence between the Karnaugh map and the truth
table for the general case of a two variable problem.
The values inside the squares are copied from the output column of the truth table, therefore
there is one square in the map for every row in the truth table. Around the edge of the Karnaugh
map are the values of the two input variable. A is along the top and B is down the left hand
side. The diagram below explains this:

The values around the edge of the map can be thought of as coordinates. So as an example,
the square on the top right hand corner of the map in the above diagram has coordinates A=1
and B=0. This square corresponds to the row in the truth table where A=1 and B=0 and F=1.
Note that the value in the F column represents a particular function to which the Karnaugh
map corresponds.
1.5.2 Grouping/Circling K-maps

The power of K-maps is in minimizing the terms, K-maps can be minimized with the help of
grouping the terms to form single terms. When forming groups of squares, observe/consider
the following:
• Every square containing 1 must be considered at least once.
• A square containing 1 can be included in as many groups as desired.
• A group must be as large as possible.
• If a square containing 1 cannot be placed in a group, then leave it out to
include in final expression.
• The number of squares in a group must be equal to 2 .i.e. 2, 4, 8, 16…..
• The map is considered to be folded or spherical, therefore squares at the end
of a row or column are treated as adjacent squares.
• The simplified logic expression obtained from a K-map is not always unique.
Groupings can be made in different ways.
• Before drawing a K-map the logic expression must be in canonical form.

1.5.3 : 3-Variable K-Map
There are 8 minterms for 3 variables (X, Y, Z). Therefore, there are 8 cells in a 3-variable K-
map. One important thing to note is that K-maps follow the gray code sequence, not the binary
one. Each cell in a 3-variable K-map has 3 adjacent neighbours. In general, each cell in an n-
variable K-map has n adjacent neighbours.

There is wrap-around in the K-map

• X'Y'Z' (m0) is adjacent to X'YZ' (m2)
• XY'Z' (m4) is adjacent to XYZ' (m6)

Example (1):
Simplify the given 3-variable Boolean equation by using k-map.
F = X‟ Y Z + X‟ Y‟ Z + X Y Z‟ + X‟ Y‟ Z‟ + X Y Z + X Y‟ Z‟
First, let‟s construct the truth table for the given equation,
We put 1 at the output terms given in equation.
There are 8 cells (23) in the 3-variable k-map. It will look like (see below image).
The largest group size will be 8 but we can also form the groups of size 4 and size 2, by
possibility. In the 3 variable Karnaugh map, we consider the left most column of the k-map as
the adjacent column of rightmost column. So the size 4 group is formed as shown below.

The 2 size group has no common variables, so they are written with their variables and its
conjugates.
So the reduced equation will be X Z’ + Y’ + X’ Z.
In this equation, no further minimization is possible.
Example (2):
F(X,Y,Z) =∑ (1,3,4,5,6,7)
F=X+Z

Example (3):
Z= ∑A,B,C(1,3,6,7)
From red group we get product term - A’C

From green group we get product term - AB
Summing these product terms, we get- Final expression (A’C+AB)
There are 16 possible min terms in case of a 4-variable Boolean function. The general
representation of minterms using 4 variables is shown below.

A typical 4-variable K-map plot is shown below. It can be observed that both the columns
and rows of 10 and 11 are interchanged.
The possible number of cells that can be grouped together are 1, 2, 4, 8 and 16.
1.5.5 Reduction rules for SOP using K-map
There are a couple of rules that we use to reduce SOP using K-map first we will cover the
rules step by step then we will solve problem. So lets start...
➢ Pair reduction Rule

Consider the following 4 variables K-map

So the updated pairs after reduction are given below.

1st pair
= W‟XY‟Z‟ + WXY‟Z‟
= XY‟Z‟
2nd pair
= W‟X‟YZ + W‟XYZ
= W‟YZ

➢ Quad reduction Rule
Consider the following 4 variables K-map.

So the updated quads after reduction.
1st quad
= (W‟X‟Y‟Z‟ + W‟XY‟Z‟) + (WXY‟Z‟ + WX‟Y‟Z‟)
= W‟Y‟Z‟ + WY‟Z‟
= Y‟Z‟
2nd quad
= (W‟X‟YZ + W‟XYZ) + (W‟X‟YZ‟ + W‟XYZ‟)
= W‟YZ + W‟YZ‟
= W‟Y
➢ Octet reduction Rule

Updated octet after reduction

octet
= (W‟X‟Y‟Z‟ + W‟X‟Y‟Z) + (W‟X‟YZ + W‟X‟YZ‟) + (W‟XY‟Z‟ + W‟XY‟Z) + (W‟XYZ
+ W‟XYZ‟)
= (W‟X‟Y‟ + W‟X‟Y) + (W‟XY‟ + W‟XY)
= W‟X‟ + W‟X
= W‟
➢ Map Rolling reduction Rule - marking the pairs

Updated pairs after reduction

1st pair
= W‟X‟Y‟Z + WX‟Y‟Z
= X‟Y‟Z
2nd pair
= WXY‟Z‟ + WXYZ‟
= WXZ‟
➢ Map Rolling reduction Rule - marking the quads


Updated quads after reduction
1st quad
= (W‟X‟Y‟Z + W‟X‟YZ) + (WX‟Y‟Z + WX‟YZ)
= W‟X‟Z + WX‟Z
= X‟Z
2nd quad
= (W‟XY‟Z‟ + WXY‟Z‟) + (W‟XYZ‟ + WXYZ‟)
= XY‟Z‟ + XYZ‟
= XZ‟
➢ Map Rolling reduction Rule - marking the octets

Updated octet after reduction

octet
= (W‟X‟Y‟Z‟ + W‟X‟Y‟Z) + (W‟X‟YZ + W‟X‟YZ‟) + (WX‟Y‟Z‟ + WX‟Y‟Z) + (WX‟YZ
+ WX‟YZ‟)
= (W‟X‟Y‟ + W‟X‟Y) + (WX‟Y‟ + WX‟Y)
= W‟X‟ + WX‟
= X‟
➢ Overlapping Groups
When a value in a cell of K-map is encircled in more that one group (pair, quad or octet)
then we call such groups an overlapping groups. Lets check an example.
Updated pair and quad after reduction
1st pair = W‟XY‟Z‟ + W‟XY‟Z

= W‟XY‟
2nd pair = WXYZ + WXYZ‟

= WXY
quad = W‟XY‟Z + W‟XYZ + WXY‟Z + WXYZ

= W‟XZ + WXZ
= XZ
➢ Redundant Groups
After marking out the overlapping groups it is important to also check for redundant groups.
If all the values of a group G (pair, quad or octet) is covered (overlapping) with other groups
then that group G is redundant and ignored. Lets check an example.

1st pair = W‟XY‟Z + W‟XYZ

= W‟XZ
2nd pair = WXY‟Z‟ + WXY‟Z

= WXY‟
1.5.6 Summary of Reduction rules for SOP using K-map
1. Prepare the truth table for the function

2. Draw an empty K-map (2-variables, 3-variables, so on)
3. Fill the cells with value 1 for which the output is 1
4. Fill rest of the cells with value 0
5. Mark the Octets, Quads and Pairs by encircling the value 1s (also check map rolling,
overlapping groups and remove redundant groups)
6. Write the final reduced expression and OR (+) them to get the answer
Example (1):
F (W, X, Y, Z) = (1, 5, 12, 13)
Sol: F (W, X, Y, Z) = (1, 5, 12, 13)

By preparing k-map, we can minimize the given Boolean equation as

F = W Y‟ Z + W „Y‟ Z
Example (2):
F(W,X,Y,Z) = (1,5,12,13)
F = WXY’ + W’Y’Z
Example (3)
F(W,X,Y,Z) = (4, 5, 10, 11, 14,15)
F = WY + W’XY’
Example (4)
Example (5)
Example (6):
F(P,Q,R,S)=∑(0,2,5,7,8,10,13,15)

From red group we get product term - QS

From green group we get product term - Q’S’
Summing these product terms, we get- Final expression (QS+Q’S’)
Example (7):
f(A,B,C,D) =  m(1,2,4,6,9)

F=

There are 32 cells in a 5-variable (A, B, C, D, E); K-map as shown in the figure below.
Example (1):
f (A, B, C, D, E) = ∑ m (0, 5, 6, 8, 9, 10, 11, 16, 20, 42, 25, 26, 27)
In the above K-Map we have 4 subcubes:
• Subcube 1: The one marked in red comprises of cells ( 0, 4, 8, 12, 16, 20, 24, 28)
• Subcube 2: The one marked in blue comprises of cells (7, 23)
• Subcube 3: The one marked in pink comprises of cells ( 0, 2, 8, 10, 16, 18, 24, 26)
• Subcube 4: The one marked in yellow comprises of cells (24, 25, 26, 27)
Now, while writing the minimal expression of each of the subcubes we will search for the
literal that is common to all the cells present in that subcube.
• Subcube 1: S’T’
• Subcube 2: Q’RST
• Subcube 3: R’T’
• Subcube 4: PQR’
Finally the minimal expression of the given boolean Function can be expressed as follows
f(PQRST) = S’T’ + Q’RST + R’T’ + PQR’
1.5.8 : Incompletely specified functions:
When an output value is known for every possible combination of input variables, the function
is said to be completely specified. When an output value is not known for every combination
of input variables, the function is said to be incompletely specified.
The truth table does not generate an output value for every possible combination of input
variables. The minterms or maxterms that are not used as part of the output function are called
don’t care terms.
A Don‟t Care cell can be represented by a cross(X) in K-Maps representing a invalid

combination.
Example-1:
Minimise the following function in SOP minimal form using K-Maps:
f = m(1, 5, 6, 12, 13, 14) + d(4)
Explanation:
The SOP K-map for the given expression is:

Therefore, SOP minimal is,
f = BC' + BD' + A'C'D
Example-2:
Minimise the following function in SOP minimal form using K-Maps: F(A, B, C, D) = m(1,
2, 6, 7, 8, 13, 14, 15) + d(3, 5, 12)
Explanation:
The SOP K-map for the given expression is:
Therefore,
f = AC'D' + A'D + A'C + AB

Example-3
Example 3:
Minimize the given Boolean Expression by using the four-variable K-Map.

F (A, B, C, D) = Σ m (1, 5, 6, 12, 13, 14) + d (2, 4).
Solution:
F (A, B, C, D) = B.C + B.D + A.C.D

Example 4: Minimize the given Boolean Expression by using the four-variable K-

Map.
F (A, B, C, D) = Σ m (1, 5, 6, 12, 13, 14) + d (2, 4).
Solution:
F (A, B, C, D) = A + C. D + B.C. D + A.B. D + B. C. D
1.5.9 Significance of “Don’t Care” Conditions:

Don‟t Care conditions has the following significance with respect to the digital circuit
design:
1. Simplification:
These conditions denotes the set of inputs which never occurs for a given digital
circuits. Thus, they are being used to further simplify the boolean output expression.
2. Lesser number of gates:
Simplification reduces the number of gates to be used for implementing the given
expression. Therefore, don‟t cares make the digital circuit design more economical.
3. Reduced Power Consumption:
While grouping the terms long with don‟t cares reduces switching of the states. This
decreases the required memory space which in turn results in less power consumption.
4. States in Code Converters:
These are used in code converters. For example- In design of 4-bit BCD-to-XS-3 code
converter, the input combinations 1010, 1011, 1100, 1101, 1110, and 1111 are don‟t
cares.
5. Prevention of Hazards:
Don‟t cares also prevents hazards in digital systems.

1.6 Simplifying Max term equations

Loading and grouping maxterms is exactly same as minterms, except that 0s are loaded into
the map and grouped to form Prime Implicant and Essential Prime Implicant.
Maxterm Solution of K Map

The method to be followed in order to obtain simplified maxterm solution using K-map is
similar to that for minterm solution except minor changes listed below.
1. K-map cells are to be populated by „zeros‟ for each sum-term of the expression
instead of „ones‟.
2. Grouping is to be carried-on for „zeros‟ and not for „ones‟.
3. Boolean expressions for each group are to be expressed as sum-terms and not as
product-terms.
4. Sum-terms of all individual groups are to be combined to obtain the overall
simplified Boolean expression in product-of-sums (POS) form.
1.6.1 Reduction rules for POS using K-map

There are a couple of rules that we use to reduce POS using K-map. First we will cover the
rules step by step then we will solve problem. So lets start...
➢ Pair reduction Rule

1st pair = (W+X‟+Y+Z) . (W‟+X‟+Y+Z) = (X‟+Y+Z)

2nd pair = (W+X+Y‟+Z‟) . (W+X‟+Y‟+Z‟) = (W+Y‟+Z‟)
(the pairs are in Product of Sums POS form)

➢ Quad reduction Rule

So the updated quads after reduction
1st quad
= [(W+X+Y+Z) . (W+X‟+Y+Z)] . [(W‟+X‟+Y+Z) . (W‟+X+Y+Z)]
= (W+Y+Z) . (W‟+Y+Z)
= (Y+Z)
2nd quad
= [(W+X+Y‟+Z‟) . (W+X+Y‟+Z)] . [(W+X‟+Y‟+Z‟) . (W+X‟+Y‟+Z)]
= (W+X+Y‟) . (W+X‟+Y‟)
= (W+Y‟)
➢ Octet reduction Rule


Updated octet after reduction,
Octet
= [(W+X+Y+Z) . (W+X+Y+Z‟)]. [(W+X+Y‟+Z‟) . (W+X+Y‟+Z)] . [(W+X‟+Y+Z) .
(W+X‟+Y+Z‟)] . [(W+X‟+Y‟+Z‟) . (W+X‟+Y‟+Z)]
= [(W+X+Y) . (W+X+Y‟)] . [(W+X‟+Y) . (W+X‟+Y‟)]
= (W+X) . (W+X‟)
=W
1.6.2 Map Rolling reduction Rule - marking the pairs

1st pair
= (W+X+Y+Z‟) . (W‟+X+Y+Z‟)
= (X+Y+Z‟)
2nd pair
= (W‟+X‟+Y+Z) . (W‟+X‟+Y‟+Z)
= (W‟+X‟+Z)
1.6.3 Map Rolling reduction Rule - marking the quads


Updated quads after reduction
1st quad
= [(W+X+Y+Z‟) . (W+X+Y‟+Z‟)] . [(W‟+X+Y+Z‟) . (W‟+X+Y‟+Z‟)]
= (W+X+Z‟) . (W‟+X+Z‟)
= (X+Z‟)
2nd quad
= [(W+X‟+Y+Z) . (W‟+X‟+Y+Z)] . [(W+X‟+Y‟+Z) . (W‟+X‟+Y‟+Z)]
= (X‟+Y+Z) . (X‟+Y‟+Z)
= (X+Z)
1.6.4 Map Rolling reduction Rule - marking the octets

octet
= [(W+X+Y+Z) . (W+X+Y+Z‟)] . [(W+X+Y‟+Z‟) . (W+X+Y‟+Z)]
. [(W‟+X+Y+Z) . (W‟+X+Y+Z‟)] . [(W‟+X+Y‟+Z‟) . (W‟+X+Y‟+Z)]
= [(W+X+Y) . (W+X+Y‟)] . [(W‟+X+Y) . (W‟+X+Y‟)]

= (W+X) . (W‟+X)
=X
1.6.5 Overlapping Groups - marking the overlapping groups

1st pair = (W+X‟+Y+Z) . (W+X‟+Y+Z‟)

= (W+X‟+Y)
2nd pair = (W‟+X‟+Y‟+Z‟) . (W‟+X‟+Y‟+Z)

= (W‟+X‟+Y‟)
quad = [(W+X‟+Y+Z‟) . (W+X‟+Y‟+Z‟)]

. [(W‟+X‟+Y+Z‟) . (W‟+X‟+Y‟+Z‟)]
= (W+X‟+Z‟) . (W‟+X‟+Z‟)
= X‟+Z‟
1.6.6 Finding the redundant groups

1st pair = M5 . M7
= (W+X‟+Y+Z‟) . (W+X‟+Y‟+Z‟)
= (W+X‟+Z‟)
2nd pair = M12 . M13

= (W‟+X‟+Y+Z) . (W‟+X‟+Y+Z‟)
= (W‟+X‟+Y)
Example 2
G = f(a,b,c,d) = Π(0,4,5,7,8,9,11,12,13,15)
G = (c+d) (b’+d’) (a’+d’)
Example 3: Y=(A'+B')+(A'+B)+(A+B)

Simplified expression: A'B
Example 4: Y=(A + B + C') + (A + B' + C') + (A' + B' + C) + (A' + B' + C')
Simplified expression: Y=(A + C') .(A' + B')
Example 5: F(A,B,C,D)=π(3,5,7,8,10,11,12,13)
Simplified expression: Y=(A + C') .(A' + B)
1.7 Quine-McClusky techniques – 3 & 4 variables.
The Quine-McClusky minimization technique is an algorithm that uses the same Boolean
algebra postulates that were used with Karnaugh maps but in the suitable form. Quine-
McClukey tabular method is a tabular method based on the concept of prime implicants.
We know that prime implicant is a product orsumorsum term, which can‟t be further
reduced by combining with any other product orsumorsum terms of the given Boolean
function.
1.7.1 Procedure of Quine-McCluskey Tabular Method

Follow these steps for simplifying Boolean functions using Quine-McClukey tabular
method.

Step 1 − Arrange the given min terms in an ascending order and make the groups based on
the number of ones present in their binary representations. So, there will be at most „n+1‟
groups if there are „n‟ Boolean variables in a Boolean function or „n‟ bits in the binary
equivalent of min terms.
Step 2 − Compare the min terms present in successive groups. If there is a change in only
one-bit position, then take the pair of those two min terms. Place this symbol „_‟ in the
differed bit position and keep the remaining bits as it is.
Step 3 − Repeat step2 with newly formed terms till we get all prime implicants.
Step 4 − Formulate the prime implicant table. It consists of set of rows and columns. Prime
implicants can be placed in row wise and min terms can be placed in column wise. Place „1‟
in the cells corresponding to the min terms that are covered in each prime implicant.
Step 5 − Find the essential prime implicants by observing each column. If the min term is
covered only by one prime implicant, then it is essential prime implicant. Those essential
prime implicants will be part of the simplified Boolean function.
Step 6 − Reduce the prime implicant table by removing the row of each essential prime
implicant and the columns corresponding to the min terms that are covered in that essential
prime implicant. Repeat step 5 for Reduced prime implicant table. Stop this process when all
min terms of given Boolean function are over.
Example 1:
Simplify the following Boolean function,
f(a,b,c,d)=∑m(0, 1, 2, 3, 6, 7, 8, 9, 14, 15) using Quine-McClukey tabular method.
1. The given Boolean function is in sum of min terms form. It is having 4 variables a, b, c
& d. The given min terms are 0, 1, 2, 3, 6, 7, 8, 9, 14 and 15. The ascending order of these
min terms based on the number of one‟s present in their binary equivalent is 0, 1, 2, 8, 3,
6, 9, 7, 14 and 15. The following table shows these min terms and their equivalent binary
representations.
Group Min terms Variables
Name
a b c d
0 0 0 0 0 0
1 1 0 0 0 1

2 0 0 1 0
8 1 0 0 0
3 0 0 1 1
2 6 0 1 1 0
9 1 0 0 1
7 0 1 1 1
3
14 1 1 1 0
4 15 1 1 1 1
Name
a b c d
0 0,1 0 0 0 -
0 0,2 0 0 - 0
0 0,8 - 0 0 0
1 1, 3 0 0 - 1
1 1, 9 - 0 0 1
1 2, 3 0 0 1 -
1 2, 6 0 - 1 0
1 8, 9 1 0 0 -
2 3, 7 0 - 1 1
2 6, 7 0 1 1 -
2 6, 14 - 1 1 0
3
7, 15 - 1 1 1
3 14, 15 1 1 1 -

2. The given min terms are arranged into 4 groups based on the number of one‟s present in
their binary equivalents. The following table shows the possible merging of min terms
from adjacent groups.
Note: A dash (-) indicates a bit position where a variable is 0 in one group and 1 in the other.
3. The min terms, which are differed in only one-bit position from adjacent groups are
merged. That differed bit is represented with this symbol, „-„. In this case, there are three
groups and each group contains combinations of two min terms. The following table
shows the possible merging of min term pairs from adjacent groups.

Name
a b c d
0 0, 1, 2, 3 0 0 - -
0 0, 1, 8, 9 - 0 0 -
1 2, 6, 3, 7 0 - 1 -
2 6, 7, 14, 15 - 1 1 -
4. The prime implicant table is shown below.
PI terms Decimal Minterms
0 1 2 3 6 7 8 9 14 15
a’b’ 0, 1, 2, 3 x x x x
b’c’ 0, 1, 8, 9 x x (x) (x)
a’c 2, 6, 3, 7 x x x x
bc 6, 7, 14, 15 x x (x) (x)
5. Evaluate the prime implicants by circling those minterms that are contained in only one
prime implicant (only one x in a column)

Note that minterms {8, 9, 14, 15} meet this condition. Circled minterms represent
essential prime implicants(EPI). Minterms {0, 1, 8, 9} and {6, 7, 14, 15} are essential
prime implicants.
Minterms {2, 3} are contained in two prime implicants, {0, 1, 2, 3} and {2, 3, 6, 7}.
We need one or the other of these prime implicants to cover minterms in the equation
but not both. This implies that two equally simplified results are possible.
D = b’c’ + bc + a’b’ or D = b’c’ + bc + a’c
Example 2:
Simplify the following Boolean function, f(W,X,Y,Z)=∑m(2,6,8,9,10,11,14,15)
using Quine-McClukey tabular method.
1. The given Boolean function is in sum of min terms form. It is having 4 variables W, X,
Y & Z. The given min terms are 2, 6, 8, 9, 10, 11, 14 and 15. The ascending order of these
min terms based on the number of ones present in their binary equivalent is 2, 8, 6, 9, 10,
11, 14 and 15. The following table shows these min terms and their equivalent binary
representations.
Group Min W X Y Z
Name terms
2 0 0 1 0
0
8 1 0 0 0
6 0 1 1 0
1 9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
2
14 1 1 1 0
3 15 1 1 1 1
2. The given min terms are arranged into 4 groups based on the number of ones present in
their binary equivalents. The following table shows the possible merging of min terms
from adjacent groups.

Group Min W X Y Z
Name terms
2,6 0 - 1 0
2,10 - 0 1 0
0
8,9 1 0 0 -
8,10 1 0 - 0
6,14 - 1 1 0
9,11 1 0 - 1
1
10,11 1 0 1 -
10,14 1 - 1 0
11,15 1 - 1 1
2
14,15 1 1 1 -
3. The min terms, which are differed in only one-bit position from adjacent groups are
merged. That differed bit is represented with this symbol, „-„. In this case, there are three
groups and each group contains combinations of two min terms. The following table
shows the possible merging of min term pairs from adjacent groups.
Group Min terms W X Y Z
Name
2,6,10,14 - - 1 0
0 2,10,6,14 - - 1 0
8,9,10,11 1 0 - -

8,10,9,11 1 0 - -
10,11,14,15 1 - 1 -
1
10,14,11,15 1 - 1 -
4. The successive groups of min term pairs, which are differed in only one-bit position are
merged. That differed bit is represented with this symbol, „-„. In this case, there are two
groups and each group contains combinations of four min terms. Here, these
combinations of 4 min terms are available in two rows. So, we can remove the repeated
rows. The reduced table after removing the redundant rows is shown below.
Group Min terms W X Y Z

Name
GC1 2,6,10,14 - - 1 0
8,9,10,11 1 0 - -
GC2 10,11,14,15 1 - 1 -
5. Further merging of the combinations of min terms from adjacent groups is not possible,
since they are differed in more than one-bit position. There are three rows in the above
table. So, each row will give one prime implicant. Therefore, the prime implicants are
YZ‟, WX‟ & WY.
6. The prime implicant table is shown below.
Min terms 2 6 8 9 10 11 14 15
/ Prime
Implicants
YZ‟ 1 1 1 1
WX‟ 1 1 1 1
WY 1 1 1 1

7. The prime implicants are placed in row wise and min terms are placed in column wise.
1s are placed in the common cells of prime implicant rows and the corresponding min
term columns.
The min terms 2 and 6 are covered only by one prime implicant YZ‟. So, it is
an essential prime implicant. This will be part of simplified Boolean function. Now,
remove this prime implicant row and the corresponding min term columns. The reduced
prime implicant table is shown below.
Min terms 8 9 11 15
/ Prime
Implicants
WX‟ 1 1 1
WY 1 1
8. The min terms 8 and 9 are covered only by one prime implicant WX‟. So, it is
an essential prime implicant. This will be part of simplified Boolean function. Now,
remove this prime implicant row and the corresponding min term columns. The reduced
prime implicant table is shown below.
Min terms 15
/ Prime
Implicants
WY 1
9. The min term 15 is covered only by one prime implicant WY. So, it is an essential prime
implicant. This will be part of simplified Boolean function.
10. In this example problem, we got three prime implicants and all the three are essential.
Therefore, the simplified Boolean function is
F(W,X,Y,Z) = YZ’ + WX’ + WY.

Example 3:




Example 4:






Module 1 Questions
1. Express the POS equations in a Maxterms list (decimal notations) form
a. i.T= f(a,b,c)= (a+b‟+c)(a‟+b‟+c)( a+b‟+c)
b. ii. J= F(A,B,,C,D)= (A+B‟+C+D)(A+B‟+C+D‟)
(A‟+B+C+D)(A‟+B‟+C+D) (A‟+B‟+C+D)
2. Explain canonical form of Boolean equation with example
3. Expand f1= a+bc+acd‟ into minterm and f2= a(b+c) (a+c+d‟) into maxterm.
4. Design a 3 input, 1 output 2 level gate combnationalcircuit which has an output equal
to 1 when majority of its inputs are at logic 1 and has an output equal to 0 when
majority of its inputs are at logic 0.
5. Minimize the following multiple output functions using K-map.
a. F1=  m(0, 2,6,10,11,12,13)+ d(3,4,5,14,15)
b. F2=  m(1,2,6,7,8,13,14,15)+ d(3,5,12)
6. Reduce the following function using K-Map technique and implement using Gates
a. F(P,Q,R,S)=  m(0, 1,4,8,9,10)+ d(2,11)
b. F(A,B,C,D)= Π M ((0, 2, 3, 5, 6, 7, 8, 10, 11, 14, 15)
7. Design a logic circuit with inputs P,Q,R so that output S is high whenever P is zero or
whenever Q=R=1.
8. Show that y= f(A,B,C,D)=  m(0, 2, 5, 7, 8, 10, 13,15) is the complement of y=
f(ABCD)= π (1,3,4,6,9,11,12,14). Illustrate your answer using K-map to show the
complement nature of the equations. Realize both the functions using 7486 IC only
12M
9. Design a logic circuit that controls the passage of a signal „A‟ according to the
following requirementi. Output „X‟ will equal „A‟ when control inputs B and C are
the same
a. ii. „X‟ will remain „High‟ when B and C are different
b. implement the circuit using suitable gates
10. Simplify the following expressions using K-map . Implement the simplified expression
using basic gates.
a. F(a,b,c,d)=  m(2,3,4,5,13,15)+ d(8,9,10,11)
b. F(A,B,C,D)= Π M (( 2, 3,45, 6, 7, 10, 11, 12)
11. Define the following terms
a. i. Minterm ii. Maxterm
b. iii. Canonical sum of product iv. Canonical product of
Sum
12. Simplify the function F(a,b,c,d)=  m( 1,2,4,11,13,14,15)+ d(0,5,7,8,10)
a. using K-map

13. Explain the definition of Combinational logic.

14. A8A4A2A1 is an 8421 BCD input to a logic circuit whose output is a 1 when
A8=0,A4=0 and A2=1, or when A8=0 and A4=1. Design the simplist possible logic
circuit
15. Simplify the function F(a,b,c,d)= Π M ((0,4,5,7,8,9,11,12,13,15) using K-map
16. Simplify the function F(a,b,c,d,e)=  m(0,2,8,10,16,18,24,26) using K-map
a. F(a,b,c,d)=  m(2,3,4,5,13,15)+ d(8,9,10,11)
b. F(A,B,C,D)= Π M (( 2, 3,45, 6, 7, 10, 11, 12)
17. Place the following equations into proper canonical form:
(i) T= f(a,b,c)= (ab‟+ab‟+bc)
(ii) P=f(a,b,c)=(a+b‟)(b‟+c)
18. Using QM method and simplify the following function
a. F1(a,b,c,d,e)=  m(0,2,8,10,16,18,24,26)
b. F2(A,B,C,D)= m (0,1, 2, 3,6, 7,8,9, 14, 15)
c. F3(A,B,C,D)= m (( 2, 3,4,5, 6, 7, 10, 11, 12)
19. Write the MEV K-map for the following Boolean functions
a. F1(A,B,C,D)= m (( 2, 3,4,5, 6, 7, 10, 11, 12)
b. F2(A,B,C,D)= m (( 2,9,10,13,14,15)
c. F3(A,B,C,D)= m (0,1, 2, 3,6, 7,8,9, 14, 15)
d. Y=F(a,b,c,d,e)= m
(1,3,4,6,9,11,14,17,19,20,22,25,27,28,30)+d(8,10,24,26)
20. Simplify the following function using QM technique. Implement the simplified
circuit using gates: f(A,B,C,D)= (1,3,4,5,6,9,11,12,13,14)
21. Simplify f(a,b,c,d))=  m(2,3,4,5,13,15)+ d(8,9,10,11) taking least significant bit as
MEV
22. Find the prime implicants of the function f(a,b,c,d)= m(7,9,12,13,14,15)+ d(4,11)
using QM algorithm.

Module 2
Logic Design with MSI Components and Programmable Logic Devices: Binary Adders and
Subtractors, Comparators, Decoders, Encoders, Multiplexers, Programmable Logic Devices
(PLDs)
2.1 The Binary Adder
Another common and very useful combinational logic circuit which can be constructed using
just a few basic logic gates and adds together binary numbers is the Binary Adder circuit. A
basic Binary Adder can be made from standard AND and Ex-OR gates allowing us to “add”
together two single bit binary numbers, A and B.
The addition of these two digits produces an output called the SUM of the addition and a
second output called the CARRY or Carry-out, ( COUT ) bit according to the rules for binary
addition. One of the main uses for the Binary Adder is in arithmetic and counting circuits.
Consider the simple addition of the two denary (base 10) numbers below.
123 A (Augend)
+ 789 B (Addend)
912 SUM
From our maths lessons at school, we learnt that each number column is added together
starting from the right hand side and that each digit has a weighted value depending upon its
position within the columns. When each column is added together a carry is generated if the
result is greater or equal to 10, the base number. This carry is then added to the result of the
addition of the next column to the left and so on, simple school math‟s addition, add the
numbers and carry.
The adding of binary numbers is exactly the same idea as that for adding together decimal
numbers but this time a carry is only generated when the result in any column is greater or
equal to “2”, the base number of binary. In other words 1 + 1 creates a carry.
Binary Addition
Binary Addition follows these same basic rules as for the denary addition above except in
binary there are only two digits with the largest digit being “1”. So when adding binary
numbers, a carry out is generated when the “SUM” equals or is greater than two (1+1) and this
becomes a “CARRY” bit for any subsequent addition being passed over to the next column
for addition and so on. Consider the single bit addition below.

Binary Addition of Two Bits
0 0 1 1
+0 +1 +0 +1
0 1 1 (carry) 1←0
When the two single bits, A and B are added together, the addition of “0 + 0″, “0 + 1″ and “1
+ 0″ results in either a “0” or a “1” until you get to the final column of “1 + 1″ then the sum is
equal to “2”. But the number two does not exists in binary however, 2 in binary is equal to 10,
in other words a zero for the sum plus an extra carry bit.
Then the operation of a simple adder requires two data inputs producing two outputs, the Sum
(S) of the equation and a Carry (C) bit as shown.
Binary Adder Block Diagram
For the simple 1-bit addition problem above, the resulting carry bit could be ignored but you
may have noticed something else with regards to the addition of these two bits, the sum of
their binary addition resembles that of an Exclusive-OR Gate. If we label the two bits as A
and B then the resulting truth table is the sum of the two bits but without the final carry.
2-input Exclusive-OR Gate
Symbol Truth Table
B A S
0 0 0
0 1 1
2-input Ex-OR Gate
1 0 1

1 1 0
We can see from the truth table above, that an Exclusive-OR gate only produces an output “1”
when either input is at logic “1”, but not both the same as for the binary addition of the previous
two bits. However in order to perform the addition of two numbers, microprocessors and
electronic calculators require the extra carry bit to correctly calculate the equations so we need
to rewrite the previous summation to include two-bits of output data as shown below.
00 00 01 01
+ 00 + 01 + 00 + 01
00 01 01 10
From the above equations we now know that an Exclusive-OR gate will only produce an
output “1” when “EITHER” input is at logic “1”, so we need an additional output to produce
the carry bit when “BOTH” inputs A and B are at logic “1”. One digital gate that fits the bill
perfectly producing an output “1” when both of its inputs A and B are “1” (HIGH) is the
standard AND Gate.
2-input AND Gate
Symbol Truth Table
B A C
0 0 0
0 1 0
2-input AND Gate 1 0 0
1 1 1
By combining the Exclusive-OR gate with the AND gate results in a simple digital binary
adder circuit known commonly as the “Half Adder” circuit.

• A Half Adder Circuit
A half adder is a logical circuit that performs an addition operation on two binary digits. The
half adder produces a sum and a carry value which are both binary digits.
Half Adder Truth Table with Carry-Out
Symbol Truth Table
B A SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
From the truth table of the half adder we can see that the SUM (S) output is the result of the
Exclusive-OR gate and the Carry-out (Cout) is the result of the AND gate. Then the Boolean
expression for a half adder is as follows.
For the SUM bit
SUM = A XOR B = A ⊕ B
For the CARRY bit
CARRY = A AND B = A.B
One major disadvantage of the Half Adder circuit when used as a binary adder, is that there is
no provision for a “Carry-in” from the previous circuit when adding together multiple data
bits.
For example, suppose we want to add together two 8-bit bytes of data, any resulting carry bit
would need to be able to “ripple” or move across the bit patterns starting from the least
significant bit (LSB). The most complicated operation the half adder can do is “1 + 1″ but as
the half adder has no carry input the resultant added value would be incorrect. One simple way
to overcome this problem is to use a Full Adder type binary adder circuit.

• A Full Adder Circuit
The main difference between the Full Adder and the previous Half Adder is that a full adder
has three inputs. The same two single bit data inputs A and B as before plus an additional
Carry-in (C-in) input to receive the carry from a previous stage as shown below.
Full Adder Block Diagram
Then the full adder is a logical circuit that performs an addition operation on three binary
digits and just like the half adder, it also generates a carry out to the next addition column.
Then a Carry-in is a possible carry from a less significant digit, while a Carry-out represents
a carry to a more significant digit.
In many ways, the full adder can be thought of as two half adders connected together, with the
first half adder passing its carry to the second half adder as shown.
Full Adder Logic Diagram
As the full adder circuit above is basically two half adders connected together, the truth table
for the full adder includes an additional column to take into account the Carry-in, CIN input as
well as the summed output, S and the Carry-out, COUT bit.

Full Adder Truth Table with Carry
Symbol Truth Table
C-in B A Sum C-out
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Then the Boolean expression for a full adder is as follows.
SUM = (A XOR B) XOR Cin = (A ⊕ B) ⊕ Cin
CARRY- OUT = A AND B OR Cin(A XOR B) = A.B + Cin(A ⊕ B)
An n-bit Binary Adder
We have seen above that single 1-bit binary adders can be constructed from basic logic gates.
But what if we wanted to add together two n-bit numbers, then n number of 1-bit full adders
need to be connected or “cascaded” together to produce what is known as a Ripple Carry
Adder.
A “ripple carry adder” is simply “n”, 1-bit full adders cascaded together with each full adder
representing a single weighted column in a long binary addition. It is called a ripple carry
adder because the carry signals produce a “ripple” effect through the binary adder from right
to left, (LSB to MSB).
For example, suppose we want to “add” together two 4-bit numbers, the two outputs of the
first full adder will provide the first place digit sum (S) of the addition plus a carry-out bit that
acts as the carry-in digit of the next binary adder.

The second binary adder in the chain also produces a summed output (the 2nd bit) plus another
carry-out bit and we can keep adding more full adders to the combination to add larger
numbers, linking the carry bit output from the first full binary adder to the next full adder, and
so forth. An example of a 4-bit adder is given below.
A 4-bit Ripple Carry Adder
One main disadvantage of “cascading” together 1-bit binary adders to add large binary
numbers is that if inputs A and B change, the sum at its output will not be valid until any carry-
input has “rippled” through every full adder in the chain because the MSB (most significant
bit) of the sum has to wait for any changes from the carry input of the LSB (less significant
bit). Consequently, there will be a finite delay before the output of the adder responds to any
change in its inputs resulting in a accumulated delay.
When the size of the bits being added is not too large for example, 4 or 8 bits, or the summing
speed of the adder is not important, this delay may not be important. However, when the size
of the bits is larger for example 32 or 64 bits used in multi-bit adders, or summation is required
at a very high clock speed, this delay may become prohibitively large with the addition
processes not being completed correctly within one clock cycle.
This unwanted delay time is called Propagation delay. Also another problem called
“overflow” occurs when an n-bit adder adds two parallel numbers together whose sum is
greater than or equal to 2n
One solution is to generate the carry-input signals directly from the A and B inputs rather than
using the ripple arrangement above. This then produces another type of binary adder circuit
called a Carry Look Ahead Binary Adder where the speed of the parallel adder can be
greatly improved using carry-look ahead logic.
The advantage of carry look ahead adders is that the length of time a carry look ahead adder
needs in order to produce the correct SUM is independent of the number of data bits used in

the operation, unlike the cycle time a parallel ripple adder needs to complete the SUM which
is a function of the total number of bits in the addend.
4-bit full adder circuits with carry look ahead features are available as standard IC packages
in the form of the TTL 4-bit binary adder 74LS83 or the 74LS283 and the CMOS 4008 which
can add together two 4-bit binary numbers and generate a SUM and a CARRY output as
shown.
74LS83 Logic Symbol
The Binary Subtractor
The Binary Subtractor is another type of combinational arithmetic circuit that is the opposite
of the Binary Adder we looked at in a previous tutorial. As their name implies, a Binary
Subtractor is a decision making circuit that subtracts two binary numbers from each other,
for example, X – Y to find the resulting difference between the two numbers.
Unlike the Binary Adder which produces a SUM and a CARRY bit when two binary numbers
are added together, the binary subtractor produces a DIFFERENCE, D by using a BORROW
bit, B from the previous column. Then obviously, the operation of subtraction is the opposite
to that of addition.
We learnt from our maths lessons at school that the minus sign, “–” is used for a subtraction
calculation, and when one number is subtracted from another, a borrow is required if the
subtrahend is greater than the minuend. Consider the simple subtraction of the two denary
(base 10) numbers below.
123 X (Minuend)
– 78 Y (Subtrahend)
45 DIFFERENCE

We can not directly subtract 8 from 3 in the first column as 8 is greater than 3, so we have to
borrow a 10, the base number, from the next column and add it to the minuend to produce 13
minus 8. This “borrowed” 10 is then return back to the subtrahend of the next column once
the difference is found. Simple school math‟s, borrow a 10 if needed, find the difference and
return the borrow.
The subtraction of one binary number from another is exactly the same idea as that for
subtracting two decimal numbers but as the binary number system is a Base-2 numbering
system which uses “0” and “1” as its two independent digits, large binary numbers which are
to be subtracted from each other are therefore represented in terms of “0‟s” and “1‟s”.
Binary Subtraction
Binary Subtraction can take many forms but the rules for subtraction are the same whichever
process you use. As binary notation only has two digits, subtracting a “0” from a “0” or a “1”
leaves the result unchanged as 0-0 = 0 and 1-0 = 1. Subtracting a “1” from a “1” results in a
“0”, but subtracting a “1” from a “0” requires a borrow. In other words 0 - 1 requires a borrow.
Binary Subtraction of Two Bits
0 1 1 (borrow)1→ 0
–0 –0 –1 –1
0 1 0 1
For the simple 1-bit subtraction problem above, if the borrow bit is ignored the result of their binary
subtraction resembles that of an Exclusive-OR Gate. To prevent any confusion in this tutorial between
a binary subtractor input labelled, B and the resulting borrow bit output from the binary subtractor also
being labelled, B, we will label the two input bits as X for the minuend and Y for the subtrahend. Then
the resulting truth table is the difference between the two input bits of a single binary subtractor is
given as:
2-input Exclusive-OR Gate
Symbol Truth Table
Y X S
0 0 0
0 1 1
2-input Ex-OR Gate
1 0 1

1 1 0
As with the Binary Adder, the difference, (D) between the two digits is only a “1” when these
two inputs are not equal as given by the Ex-OR expression. However, we need an additional
output to produce the borrow bit when input A = 0 and B = 1. Unfortunately there are no
standard logic gates that will produce an output for this particular combination of X and Y
inputs.
But we know that an AND Gate produces an output “1” when both of its inputs X and Y are
“1” (HIGH) so if we use an inverter or NOT Gate to complement the input X before it is fed
to the AND gate, we can produce the required borrow output when X = 0 and Y = 1 as
shown below.
Then by combining the Exclusive-OR gate with the NOT-AND combination results in a
simple digital binary subtractor circuit known commonly as the Half Subtractor as shown.
• A Half Subtractor Circuit
A half subtractor is a logical circuit that performs a subtraction operation on two binary digits.
The half subtractor produces a sum and a borrow bit for the next stage.
Half Subtractor with Borrow-out
Symbol Truth Table
Y X DIFFERENCE BORROW

0 0 0 0
0 1 1 0
1 0 1 1
1 1 0 0
From the truth table of the half subtractor we can see that the DIFFERENCE (D) output is the
result of the Exclusive-OR gate and the Borrow-out (Bout) is the result of the NOT-AND
combination. Then the Boolean expression for a half subtractor is as follows.
D = X XOR Y = X Y
B = not-X AND Y = X.Y
If we compare the Boolean expressions of the half subtractor with a half adder, we can see that
the two expressions for the SUM (adder) and DIFFERENCE (subtractor) are exactly the same
and so they should be because of the Exclusive-OR gate function. The two Boolean
expressions for the binary subtractor BORROW is also very similar to that for the adders
CARRY. Then all that is needed to convert a half adder to a half subtractor is the inversion of
the minuend input X.
One major disadvantage of the Half Subtractor circuit when used as a binary subtractor, is that
there is no provision for a “Borrow-in” from the previous circuit when subtracting multiple
data bits from each other. Then we need to produce what is called a “full binary subtractor”
circuit to take into account this borrow-in input from a previous circuit.
A Full Binary Subtractor Circuit
The main difference between the Full Subtractor and the previous Half Subtractor circuit
is that a full subtractor has three inputs. The two single bit data inputs X (minuend) and Y
(subtrahend) the same as before plus an additional Borrow-in (B-in) input to receive the
borrow generated by the subtraction process from a previous stage as shown below.
Full Subtractor Block Diagram

Then the combinational circuit of a “full subtractor” performs the operation of subtraction on
three binary bits producing outputs for the difference D and borrow B-out. Just like the binary
adder circuit, the full subtractor can also be thought of as two half subtractors connected
together, with the first half subtractor passing its borrow to the second half subtractor as
follows.
Full Subtractor Logic Diagram
As the full subtractor circuit above represents two half subtractors cascaded together, the truth
table for the full subtractor will have eight different input combinations as there are three input
variables, the data bits and the Borrow-in, BIN input. Also includes the difference output, D
and the Borrow-out, BOUT bit.
Full Subtractor Truth Table
Symbol Truth Table
B-in Y X Diff. B-out
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Then the Boolean expression for a full subtractor is as follows.
D = (X XOR Y) XOR Bin = (X Y) Bin
Bout = X AND Y OR Bin(X XOR Y) = X.Y + Bin(X Y)
An n-bit Binary Subtractor
As with the binary adder, we can also have n number of 1-bit full binary subtractor connected
or “cascaded” together to subtract two parallel n-bit numbers from each other. For example
two 4-bit binary numbers. We said before that the only difference between a full adder and a
full subtractor was the inversion of one of the inputs.
So by using an n-bit adder and n number of inverters (NOT Gates), the process of subtraction
becomes an addition as we can use two‟s complement notation on all the bits in the subtrahend
and setting the carry input of the least significant bit to a logic “1” (HIGH).
Binary Subtractor using 2’s Complement
Then we can use a 4-bit full-adder ICs such as the 74LS283 and CD4008 to perform
subtraction simply by using two‟s complement on the subtrahend, B inputs as X – Y is the
same as saying, X + (-Y) which equals X plus the two‟s complement of Y.
If we wanted to use the 4-bit adder for addition once again, all we would need to do is set the
carry-in (CIN) input LOW at logic “0”. Because we can use the 4-bit adder IC such as the
74LS83 or 74LS283 as a full-adder or a full-subtractor they are available as a single
adder/subtractor circuit with a single control input for selecting between the two operations.
A carry-lookahead adder (CLA) is a type of adder used in digital logic. A carry-lookahead

adder improves speed by reducing the amount of time required to determine carry bits. It can
be contrasted with the simpler, but usually slower, ripple carry adder for which the carry bit

is calculated alongside the sum bit, and each bit must wait until the previous carry has been
calculated to begin calculating its own result and carry bits. The carry-lookahead adder
calculates one or more carry bits before the sum, which reduces the wait time to calculate the
result of the larger value bits.
Carry lookahead depends on two things:
1. Calculating, for each digit position, whether that position is going to propagate a
carry if one comes in from the right.
2. Combining these calculated values to be able to deduce quickly whether, for each
group of digits, that group is going to propagate a carry that comes in from the
right.
Supposing that groups of 4 digits are chosen. Then the sequence of events goes something
like this:
1. All 1-bit adders calculate their results. Simultaneously, the lookahead units perform
their calculations.
2. Suppose that a carry arises in a particular group. Within at most 5 gate delays, that
carry will emerge at the left-hand end of the group and start propagating through the
group to its left.
3. If that carry is going to propagate all the way through the next group, the lookahead
unit will already have deduced this. Accordingly, before the carry emerges from the
next group the lookahead unit is immediately (within 1 gate delay) able to tell the next
group to the left that it is going to receive a carry - and, at the same time, to tell the
next lookahead unit to the left that a carry is on its way.

• Carry lookahead method
Carry lookahead logic uses the concepts of generating and propagating carries. Although in
the context of a carry lookahead adder, it is most natural to think of generating and propagating
in the context of binary addition, the concepts can be used more generally than this. In the
descriptions below, the word digit can be replaced by bit when referring to binary addition.
The addition of two 1-digit inputs A and B is said to generate if the addition will always carry,
regardless of whether there is an input carry (equivalently, regardless of whether any less
significant digits in the sum carry). For example, in the decimal addition 52 + 67, the addition
of the tens digits 5 and 6 generates because the result carries to the hundreds digit regardless
of whether the ones digit carries (in the example, the ones digit does not carry (2+7=9)).
In the case of binary addition, generates if and only if both A and B are 1. If we write
to represent the binary predicate that is true if and only if generates,
we have:
The addition of two 1-digit inputs A and B is said to propagate if the addition will carry
whenever there is an input carry (equivalently, when the next less significant digit in the sum
carries). For example, in the decimal addition 37 + 62, the addition of the tens digits 3 and 6
propagate because the result would carry to the hundreds digit if the ones were to carry (which
in this example, it does not). Note that propagate and generate are defined with respect to a
single digit of addition and do not depend on any other digits in the sum.
In the case of binary addition, propagates if and only if at least one of A or B is 1. If

we write to represent the binary predicate that is true if and only if
propagates, we have:
Sometimes a slightly different definition of propagate is used. By this definition A + B is said

to propagate if the addition will carry whenever there is an input carry, but will not carry if
there is no input carry. Fortunately, due to the way generate and propagate bits are used by the
carry lookahead logic, it doesn't matter which definition is used. In the case of binary addition,
this definition is expressed by:
For binary arithmetic, or is faster than xor and takes fewer transistors to implement.
However, for a multiple-level carry lookahead adder, it is simpler to use .

Given these concepts of generate and propagate, when will a digit of addition carry? It will
carry precisely when either the addition generates or the next less significant bit carries and
the addition propagates. Written in boolean algebra, with the carry bit of digit i, and and
the propagate and generate bits of digit i respectively,
Implementation details
For each bit in a binary sequence to be added, the Carry Look Ahead Logic will determine
whether that bit pair will generate a carry or propagate a carry. This allows the circuit to "pre-
process" the two numbers being added to determine the carry ahead of time. Then, when the
actual addition is performed, there is no delay from waiting for the ripple carry effect (or time
it takes for the carry from the first Full Adder to be passed down to the last Full Adder). Below
is a simple 4-bit generalized Carry Look Ahead circuit that combines with the 4-bit Ripple
Carry Adder we used above with some slight adjustments:
For the example provided, the logic for the generate (g) and propagate (p) values are given
below. Note that the numeric value determines the signal from the circuit above, starting from
0 on the far left to 3 on the far right:
Substituting into , then into , then into yields the expanded equations:
To determine whether a bit pair will generate a carry, the following logic works:
To determine whether a bit pair will propagate a carry, either of the following logic statements
work:

The reason why this works is based on evaluation of . The only

difference in the truth tables between ( ) and ( ) is when both and are 1.
However, if both and are 1, then the term is 1 (since its equation is ), and the
term becomes irrelevant. The XOR is used normally within a basic full adder circuit;
the OR is an alternate option (for a carry lookahead only) which is far simpler in transistor-
count terms.
The Carry Look Ahead 4-bit adder can also be used in a higher-level circuit by having each
CLA Logic circuit produce a propagate and generate signal to a higher-level CLA Logic
circuit. The group propagate ( ) and group generate ( ) for a 4-bit CLA are:
2.2 Binary Decoder

The name “Decoder” means to translate or decode coded information from one format into
another, so a digital decoder transforms a set of digital input signals into an equivalent decimal
code at its output.
Binary Decoders are another type of Digital Logicdevice that has inputs of 2-bit, 3-bit or 4-
bit codes depending upon the number of data input lines, so a decoder that has a set of two or
more bits will be defined as having an n-bit code, and therefore it will be possible to represent
2n possible values. Thus, a decoder generally decodes a binary value into a non- binary one by
setting exactly one of its n outputs to logic “1”.
If a binary decoder receives n inputs (usually grouped as a single Binary or Boolean number)
it activates one and only one of its 2n outputs based on that input with all other outputs
deactivated.
So for example, an inverter ( NOT-gate ) can be classed as a 1-to-2 binary decoder as 1-input
and 2-outputs (21) is possible because with an input A it can produce two outputs A and A
(not-A) as shown.
Then we can say that a standard combinational logic decoder is an n-to-m decoder, where
m ≤ 2n, and whose output, Q is dependent only on its present input states. In other words, a
binary decoder looks at its current inputs, determines which binary code or binary number is
present at its inputs and selects the appropriate output that corresponds to that binary input.

A Binary Decoder converts coded inputs into coded outputs, where the input and output codes
are different and decoders are available to “decode” either a Binary or BCD (8421 code) input
pattern to typically a Decimal output code. Commonly available BCD-to- Decimal decoders
include the TTL 7442 or the CMOS 4028. Generally a decoders output code normally has
more bits than its input code and practical “binary decoder” circuits include, 2-to-4, 3-to-8 and
4-to-16 line configurations.
In its general form, a decoder has N input lines to handle N bits and form one to 2 N output
lines to indicate the presence of one or more N-bit combinations.
The basic binary function
• An AND gate can be used as the basic decoding element because it produces a HIGH
output only when all inputs are HIGH
General decoder diagram
There are 2N possible input combinations, from A0 to AN−1. For each of these input
combinations only one of the M outputs will be active HIGH (1), all the other outputs are
LOW (0).
• If an active-LOW output (74138, one of the output will low and the rest will be high)
is required for each decoded number, the entire decoder can be implemented with
1. NAND gates
2. Inverters
• If an active-HIGH output (74139, one of the output will high and the rest will be low)
is required for each decoded number, the entire decoder can be implemented with
1. AND gates
2. Inverters
A 2-to-4 Binary Decoders.

This simple example above of a 2-to-4 line binary decoder consists of an array of four AND
gates. The 2 binary inputs labelled A and B are decoded into one of 4 outputs, hence the
description of 2-to-4 binary decoder. Each output represents one of the miniterms of the 2
input variables, (each output = a miniterm).
The binary inputs A and B determine which output line from Q0 to Q3 is “HIGH” at logic
level “1” while the remaining outputs are held “LOW” at logic “0” so only one output can be
active (HIGH) at any one time. Therefore, whichever output line is “HIGH” identifies the
binary code present at the input, in other words it “de-codes” the binary input
2-to-4-LineDecoder (with Enable input)-Active LOW output

• The circuit operates with complemented outputs and a complement enable input. The
decoder is enabled when E is equal to 0.
• Only one output can be equal to 0 at any given time, all other outputs are equal to 1.
• The output whose value is equal to 0 represents the minterm selected by inputs A and
B
• The circuit is disabled when E is equal to 1.
Some binary decoders have an additional input pin labelled “Enable” that controls the outputs
from the device. This extra input allows the decoders outputs to be turned “ON” or “OFF” as
required. These types of binary decoders are commonly used as “memory address decoders”
in microprocessor memory applications.
74LS138 Binary Decoder

Truth table of 74138 (Example of a 3− 8 Bit Decoder)active-LOW
• There is an enable function on this device, a LOW level on each input E’1, and E’2,
and a HIGH level on input E3, is required in order to make the enable gate output
HIGH.
• The enable is connected to an input of each NAND gate in the decoder, so it must be
HIGH for the NAND gate to be enabled.
• If the enable gate is not activated then all eight decoder outputs will be HIGH
regardless of the states of the three input variables A0, A1, and A2 .
3-8 line decoder (active-HIGH)

• This decoder can be referred to in several ways. It can be called a 3-line-to- 8-line
decoder, because it has three input lines and eight output lines.
• It could also be called a binary-octal decoder or converters because it takes a three bit
binary input code and activates the one of the eight outputs corresponding to that code.
It is also referred to as a 1-of-8 decoder, because only 1 of the 8 outputs is activated at
one time.
Here a much larger 4 (3 data plus 1 enable) to 16 line binary decoder has been implemented
using two smaller 3-to-8 decoders.
A 4-to-16 Binary Decoder Configuration.

Inputs A, B, C are used to select which output on either decoder will be at logic “1” (HIGH)
and input D is used with the enable input to select which encoder either the first or second
will output the “1”.However, there is a limit to the number of inputs that can be used for one
particular decoder, because as n increases, the number of AND gates required to produce an
output also becomes larger resulting in the fan-out of the gates used to drive them becoming
large.
This type of active-“HIGH” decoder can be implemented using just Inverters, ( NOT Gates )
and AND gates. It is convenient to use an AND gate as the basic decoding element for the
output because it produces a “HIGH” or logic “1” output only when all of its inputs are logic
“1”.
But some binary decoders are constructed using NAND gates instead of AND gates for their
decoded output, since NAND gates are cheaper to produce than AND‟s as they require fewer
transistors to implement within their design.
The use of NAND gates as the decoding element, results in an active-“LOW” output while the
rest will be “HIGH”. As a NAND gate produces the AND operation with an inverted output,
the NAND decoder looks like this with its inverted truth table.
A 5-to-32 Binary Decoder Configuration using 3:8 decoder.

Decoders are also available with an additional “Enable” input pin which allows the decoded
output to be turned “ON” or “OFF” by applying a logic “1” or logic “0” respectively to it. So
for example, when the enable input is at logic level “0”, (EN = 0) all outputs are “OFF” at
logic “0” (for AND gates) regardless of the state of the inputs A and B.
Generally to implement this enabling function the 2-input AND or NAND gates are replaced
with 3-input AND or NAND gates. The additional input pin represents the enable function.
Binary Decoders are most often used in more complex digital systems to access a particular
memory location based on an “address” produced by a computing device. In modern
microprocessor systems the amount of memory required can be quite high and is generally
more than one single memory chip alone.
One method of overcoming this problem is to connect lots of individual memory chips together
and to read the data on a common “Data Bus”. In order to prevent the data being “read” from
each memory chip at the same time, each memory chip is selected individually one at time and
this process is known as Address Decoding.
In this type of application, the address represents the coded data input, and the outputs are the
particular memory element select signals. Each memory chip has an input called Chip Select
or CS which is used by the MPU (micro-processor unit) to select the appropriate memory chip
when required. Generally a logic “1” on the chip select (CS) input selects the memory device
while a logic “0” on the input de-selects it.

So by selecting or de-selecting each chip one at a time, allows us to select the correct memory
address device for a particular address location. The advantage of address decoding is that
when we specify a particular memory address, the corresponding memory location exists
ONLY in one of the chips.
The binary decoder requires only 3 address lines, (A0 to A2) to select each one of the 8 chips
(the lower part of the address), while the remaining 7 address lines (A3 to A9) select the correct
memory location on that chip (the upper part of the address). Having selected a memory
location using the address bus, the information at the particular internal memory location is
sent to a common “Data Bus” for use by the microprocessor. This is of course a simple
example but the principals remain the same for all types of memory chips or modules.
Applications of Decoders
• Decoders are used in many types of applications.
• Computer must communicate with a variety of external devices called peripherals by
sending and/or receiving data through what is known as input/output (I/O) ports
• Each I/O port has a number, called an address, which uniquely identifies it. When the
computer wants to communicate with a particular device, it issues the appropriate
address code for the I/O port to which that particular device is connected . The binary
port address is decoded and appropriate decoder output is activated to enable the I/O
port
• Binary data are transferred within the computer on a data bus, which is a set of
parallel lines
Application 1: A simplified computer I/O port system with a port address decoder with
only four address lines shown.

• The BCD- to-decimal decoder converts each BCD code into one of Ten Positionable
decimal digit indications. It is frequently referred as a 4-line -to- 10 line decoder
• The method of implementation is that only ten decoding gates are required because
the BCD code represents only the ten decimal digits 0 through 9.
• Each of these decoding functions is implemented with NAND gates to provide active
-LOW outputs. If an active HIGH output is required, AND gates are used for
decoding

Logic diagram of BCD - decimal decoder(Active LOW output)
Lamp Test (LT): When LT = Low, BI/RBO = HIGH then all of the 7 segments in display are
turned zero, LT is used to verify that no segments are burned out
Zero Suppression (BI, RBI, RBO):Zero suppression is a feature used for multi digit displays
to blank out unnecessary zeros.
Example:In a 6-digit display the number 6.4 may be displayed as 006.400 if the zeros are not
blanked out
Leading Zero Suppression:Blanking the zeros at the front of a numbers

Trailing Zero Suppression:Blanking the zeros at the back of the number.Only nonessential
zeros are blanked, the number 030.080 will be displayed as 30.08 (the essential zeros
remain)
The 7-segment Display

LED based 7-segment displays are very popular amongst Electronics hobbyists as they are
easy to use and easy to understand. In most practical applications, 7-segment displays are
driven by a suitable decoder/driver IC such as the CMOS 4511 or TTL 7447 from a 4-bit BCD
input. Today, LED based 7-segment displays have been largely replaced by liquid crystal
displays (LCDs) which consume less current.
An LED or Light Emitting Diode, is a solid state optical PN-junction diode which emits light
energy in the form of “photons” when it is forward biased by a voltage allowing current to
flow across its junction, and in Electronics we call this process electroluminescence.
The actual colour of the visible light emitted by an LED, ranging from blue to red to orange,
is decided by the spectral wavelength of the emitted light which itself is dependent upon the
mixture of the various impurities added to the semiconductor materials used to produce it.
7-segment Display
Light Emitting Diodes have many advantages over traditional bulbs and lamps, with the main
ones being their small size, long life, various colours, cheapness and are readily available, as
well as being easy to interface with various other electronic components and digital circuits.
But the main advantage of light emitting diodes is that because of their small die size, several
of them can be connected together within one small and compact package producing what is
generally called a 7-segment Display.
The 7-segment display, also written as “seven segment display”, consists of seven LEDs
(hence its name) arranged in a rectangular fashion as shown. Each of the seven LEDs is called
a segment because when illuminated the segment forms part of a numerical digit (both Decimal
and Hex) to be displayed. An additional 8th LED is sometimes used within the

same package thus allowing the indication of a decimal point, (DP) when two or more 7-
segment displays are connected together to display numbers greater than ten.
Each one of the seven LEDs in the display is given a positional segment with one of its
connection pins being brought straight out of the rectangular plastic package. These
individually LED pins are labelled from a through to g representing each individual LED. The
other LED pins are connected together and wired to form a common pin.
So by forward biasing the appropriate pins of the LED segments in a particular order, some
segments will be light and others will be dark allowing the desired character pattern of the
number to be generated on the display. This then allows us to display each of the ten decimal
digits 0 through to 9 on the same 7-segment display.
The displays common pin is generally used to identify which type of 7-segment display it is.
As each LED has two connecting pins, one called the “Anode” and the other called the
“Cathode”, there are therefore two types of LED 7-segment display called: Common Cathode
(CC) and Common Anode (CA).
The difference between the two displays, as their name suggests, is that the common cathode
has all the cathodes of the 7-segments connected directly together and the common anode has
all the anodes of the 7-segments connected together and is illuminated as follows.
1. The Common Cathode (CC) – In the common cathode display, all the cathode connections
of the LED segments are joined together to logic “0” or ground. The individual segments are
illuminated by application of a “HIGH”, or logic “1” signal via a current limiting resistor to
forward bias the individual Anode terminals (a-g).
Common Cathode 7-segment Display
2. The Common Anode (CA) – In the common anode display, all the anode connections of
the LED segments are joined together to logic “1”. The individual segments are illuminated
by applying a ground, logic “0” or “LOW” signal via a suitable current limiting resistor to
the Cathode of the particular segment (a-g).

Common Anode 7-segment Display
In general, common anode displays are more popular as many logic circuits can sink more
current than they can source. Also note that a common cathode display is not a direct
replacement in a circuit for a common anode display and vice versa, as it is the same as
connecting the LEDs in reverse, and hence light emission will not take place.
BCD to 7-Segment Display Decoder
Digital Decoder is a device which converts one digital format into another and one of the
most commonly used device for doing this is called the Binary Coded Decimal (BCD) to 7-
Segment Display Decoder. 7-segment LED (Light Emitting Diode) or LCD (Liquid Crystal
Display) type displays, provide a very convenient way of displaying information or digital
data in the form of numbers, letters or even alpha-numerical characters.
Typically 7-segment displays consist of seven individual coloured LED‟s (called the
segments), within one single display package. In order to produce the required numbers or
HEX characters from 0 to 9 and A to F respectively, on the display the correct combination of
LED segments need to be illuminated and BCD to 7-segment Display Decoders such as the
74LS47 do just that.
A standard 7-segment LED display generally has 8 input connections, one for each LED
segment and one that acts as a common terminal or connection for all the internal display
segments. Some single displays have also have an additional input pin to display a decimal
point in their lower right or left hand corner.
In electronics there are two important types of 7-segment LED digital display.
• The Common Cathode Display (CCD) – In the common cathode display, all the
cathode connections of the LED‟s are joined together to logic “0” or ground. The
individual segments are illuminated by application of a “HIGH”, logic “1” signal to
the individual Anode terminals.
• The Common Anode Display (CAD) – In the common anode display, all the anode
connections of the LED‟s are joined together to logic “1” and the individual

segments are illuminated by connecting the individual Cathode terminals to a

“LOW”, logic “0” signal.
Common Cathode and Common Anode Format
Combinational Logic Circuit Implementation using a Decoder

• From the truth table of the full adder,
• the functions can be expressed in sum of min-terms.
S(x,y,z) = m(1,2,4,7)
C(x,y,z) = m(3,5,6,7)
where  indicates sum, m indicates min-term and the number in brackets indicate the
decimal equivalent
Since there are three inputs and a total of eight min-terms, we need a 3-to-8 line decoder.
• The decoder generates the eight min-terms for x,y,z

• The OR gate for output S forms the logical sum of min-terms 1,2,4, and 7.
• The OR gates for output C forms the logical sum of min-terms 3,5,6, and 7

2.3 The Digital Encoder

• An encoder is a combinational logic circuit that essentially performs a “reverse” of
decoder functions.
• An encoder accepts an active level on one of its inputs, representing digit, such as a
decimal or octal digits, and converts it to a coded output such as BCD or binary.
• Encoders can also be devised to encode various symbols and alphabetic characters.
• The process of converting from familiar symbols or numbers to a coded format is
calleMost decoders accept an input code and produce a HIGH
• ( or a LOW) at one and only one output line. In otherworlds , a decoder identifies,
recognizes, or detects a particular code. The opposite of this decoding process is called
encoding and is performed by a logic circuit called an encoder.
• An encoder has a number of input lines, only one of which input is activated at a given
time and produces an N-bit output code,depending on which input is activated.
• Most decoders accept an input code and produce a HIGH
• ( or a LOW) at one and only one output line. In otherworlds , a decoder identifies,
recognizes, or detects a particular code. The opposite of this decoding process is called
encoding and is performed by a logic circuit called an encoder.
• An encoder has a number of input lines, only one of which input is activated at a given
time and produces an N-bit output code,depending on which input is activated.

Unlike a multiplexer that selects one individual data input line and then sends that data to a
single output line or switch, a Digital Encoder more commonly called a Binary Encoder
takes ALL its data inputs one at a time and then converts them into a single encoded output.
So we can say that a binary encoder, is a multi-input combinational logic circuit that converts
the logic level “1” data at its inputs into an equivalent binary code at its output.
Generally, digital encoders produce outputs of 2-bit, 3-bit or 4-bit codes depending upon the
number of data input lines. An “n-bit” binary encoder has 2n input lines and n-bit output lines
with common types that include 4-to-2, 8-to-3 and 16-to-4 line configurations.
The output lines of a digital encoder generate the binary equivalent of the input line whose
value is equal to “1” and are available to encode either a decimal or hexadecimal input pattern
to typically a binary or “B.C.D” (binary coded decimal) output code.
4-to-2 Bit Binary Encoder

One of the main disadvantages of standard digital encoders is that they can generate the wrong
output code when there is more than one input present at logic level “1”. For example, if we
make inputs D1 and D2 HIGH at logic “1” both at the same time, the resulting output is neither
at “01” or at “10” but will be at “11” which is an output binary number that is different to the
actual input present. Also, an output code of all logic “0”s can be generated when all of its
inputs are at “0” OR when input D0 is equal to one.
Logic circuit for octal-to binary encoder [8-line- 3-line ]
Truth table for octal-to binary encoder [8-line- 3-line ]

A low at any single input will produce the output binary code corresponding to that input. For
instance , a low at A3‟ will produce O2 =0, O1=1 and O0 =1, which is binary code for 3. Ao‟
is not connected to the logic gates because the encoder outputs always be normally at 0000
when none of the inputs is LOW
One simple way to overcome this problem is to “Prioritise” the level of each input pin and if
there was more than one input at logic level “1” the actual output code would only correspond
to the input with the highest designated priority. Then this type of digital encoder is known
commonly as a Priority Encoder or P-encoder for short.
Priority Encoder
The Priority Encoder solves the problems mentioned above by allocating a priority level to
each input. The priority encoders output corresponds to the currently active input which has
the highest priority. So when an input with a higher priority is present, all other inputs with a
lower priority will be ignored. The priority encoder comes in many different forms with an
example of an 8-input priority encoder along with its truth table shown below.
• A priority encoder is an encoder that includes the priority function

• If two or more inputs are equal to 1 at the same time, the input having the highest
priority will take precedence.
Design of 4: 2 line priority encoder

Truth Table of a 4-input Priority Encoder:
Inputs Outputs
D0 D1 D2 D3 x y V

0 0 0 0 X X 0
1 0 0 0 0 0 1
X 1 0 0 0 1 1
X X 1 0 1 0 1
X X X 1 1 1 1
• In addition to two outputs x, and y, the truth table has a third output designated by V,
which is a valid bit indicator that is set 1 when one or more inputs are equal to 1. If all
inputs are 0, there is no valid input and V is equal to 0.
• X‟s in the output column indicate don‟t care conditions, the X‟s in the input columns
are useful for representing a truth table in condensed form.
• The higher the subscript number, the higher the priority of the input. Input D3 has the
highest priority, so regardless of the values of the other inputs, when this input is 1, the
output for xy is 11 (binary 3)
V=D +D +D +D
0 1 2 3
K-Maps for 4-input Priority Encoder

Logic Diagram for 4-input priority encoder

8-to-3 Bit Priority Encoder
Priority encoders are available in standard IC form and the TTL 74LS148 is an 8-to-3 bit
priority encoder which has eight active LOW (logic “0”) inputs and provides a 3-bit code of
the highest ranked input at its output. Priority encoders output the highest order input first for
example, if input lines “D2“, “D3” and “D5” are applied simultaneously the output code would
be for input “D5” (“101″) as this has the highest order out of the 3 inputs. Once input “D5”
had been removed the next highest output code would be for input “D3” (“011″), and so on.
From this truth table, the Boolean expression for the encoder above with data inputs D0 to D7
and outputs Q0, Q1, Q2 is given as:
Output Q0:

Output Q1
Output Q2
Then the final Boolean expression for the priority encoder including the zero inputs is
defined as:
In practice these zero inputs would be ignored allowing the implementation of the final
Boolean expression for the outputs of the 8-to-3 priority encoder. We can constructed a
simple encoder from the expression above using individual OR gates as follows.

Digital Encoder using Logic Gates
The Octal−to−Binary Priority Encoder

• The 74LS148 is a priority encoder that has eight active LOW inputs and three
active−LOW binary outputs
• To enable the device, the EI (enable input) must be LOW. It also has the EO (enable
output) and GS (group signal output) for expansion purposes.
• EI BAR Active−LOW enable input, a HIGH on the input forces all outputs to their
inactive state (HIGH).

• EO BAR Active−LOW enable output, the output pin goes LOW when all inputs are
inactive (HIGH) and is LOW.
• GS BAR -Active−LOW group signal output, this output pin goes LOW whenever any
of the inputs are active (LOW) and is LOW
The 16 −to−4 Encoder
The 74LS148 can be expanded to a 16−line−to−4−line encoder by connecting the EO of the

higher−order encoder to the EI of the lower−order encoder and negative−ORing the
corresponding binary outputs as shown
Decimal-BCD priority encoder
• Encoder will produce a BCD output corresponding to the highest-order decimal digit
input that is active and will ignore any other lower order active inputs.For instance if
the input 6 and the 3 are active, the output will be 1001, which is the inverse value of
BCD output 0110 (which represents decimal 6)

When A9’ is low, the output is 0110, which is inverse of 1001 ( eq to 9 in BCD)
Application of an Encoder:
A simplified keyboard encoder.

• When one of the keys is pressed, the decimal digit is encoded to the corresponding
BCD code
• The keys are represented by 10 push-button switches, each with a pull-up resistor to
V+. The pull-up resistor ensures that the line is HIGH when a key is not depressed.
• When a key is depressed, the line is connected to ground, and a LOW is applied to
the corresponding encoder input.
• The zero key is not connected because the BCD output represents zero when none of
the other keys is depressed
• The BCD complement output of the encoder goes into a storage device, and each
successive BCD code is stored until the entire number has been entered
Digital Encoder Applications

Priority encoders can be used to reduce the number of wires needed in a particular circuits or
application that have multiple inputs. For example, assume that a microcomputer needs to read
the 104 keys of a standard QWERTY keyboard where only one key would be pressed either
“HIGH” or “LOW” at any one time.One way would be to connect all 104 wires from the
individual keys on the keyboard directly to the computers input but this would be impractical
for a small home PC. Another alternative and better way would be to interface the keyboard
to the PC using a priority encoder.The 104 individual buttons or keys could be encoded into a
standard ASCII code of only 7-bits (0 to 127 decimal) to represent each key or character of
the keyboard and then input as a much smaller 7-bit B.C.D code directly to the computer.
Keypad encoders such as the 74C923 20-key encoder are available to do just that.
Positional Encoders
Another more common application is in magnetic positional control as used on ships

navigation or for robotic arm positioning etc. Here for example, the angular or rotary position
of a compass is converted into a digital code by a 74LS148 8-to-3 line priority encoder and
input to the systems computer to provide navigational dataand an example of a simple 8
position to 3-bit output compass encoder is shown below. Magnets and reed switches could be
used at each compass point to indicate the needles angular position.
Priority Encoder Navigation

Binary Output
Compass Direction
Q0 Q1 Q2
North 0 0 0
North-East 0 0 1
East 0 1 0
South-East 0 1 1
South 1 0 0
South-West 1 0 1
West 1 1 0
North-West 1 1 1
➢ Interrupt Requests
Other applications especially for Priority Encoders may include detecting interrupts in
microprocessor applications. Here the microprocessor uses interrupts to allow peripheral
devices such as the disk drive, scanner, mouse, or printer etc, to communicate with it, but the
microprocessor can only “talk” to one peripheral device at a time so needs some way of
knowing when a particular peripheral device wants to communicate with it.
The processor does this by using “Interrupt Requests” or “IRQ” signals to assign priority to
all the peripheral devices to ensure that the most important peripheral device is serviced first.
The order of importance of the devices will depend upon their connection to the priority
encoder.
IRQ Number Typical Use Description

IRQ 0 System timer Internal System Timer.
IRQ 1 Keyboard Keyboard Controller.
IRQ 3 COM2 & COM4 Second and Fourth Serial Port.
IRQ 4 COM1 & COM3 First and Third Serial Port.
IRQ 5 Sound Sound Card.
IRQ 6 Floppy disk Floppy Disk Controller.

IRQ 7 Parallel port Parallel Printer.
IRQ 12 Mouse PS/2 Mouse.
IRQ 14 Primary IDE Primary Hard Disk Controller.
IRQ 15 Secondary IDE Secondary Hard Disk Controller.
Because implementing such a system using priority encoders such as the standard 74LS148
priority encoder IC involves additional logic circuits, purpose built integrated circuits such as
the 8259 Programmable Priority Interrupt Controller is available.
2.4 The Multiplexer (MUX)

Multiplexing is the generic term used to describe the operation of sending one or more
analogue or digital signals over a common transmission line at different times or speeds and
as such, the device we use to do just that is called a Multiplexer.
The multiplexer, shortened to “MUX” or “MPX”, is a combinational logic circuit designed to

switch one of several input lines through to a single common output line by the application of
a control signal. Multiplexers operate like very fast acting multiple position rotary switches
connecting or controlling multiple input lines called “channels” one at a time to the output.
Multiplexers, or MUX‟s, can be either digital circuits made from high speed logic gates used
to switch digital or binary data or they can be analogue types using transistors, MOSFET‟s or
relays to switch one of the voltage or current inputs through to a single output.
The multiplexer is a very useful electronic circuit that has uses in many different applications
such as signal routing, data communications and data bus control applications.
The most basic type of multiplexer device is that of a one-way rotary switch as shown.
Basic Multiplexing Switch

The rotary switch, also called a wafer switch as each layer of the switch is known as a wafer,
is a mechanical device whose input is selected by rotating a shaft. In other words, the rotary
switch is a manual switch that you can use to select individual data or signal lines simply by
turning its inputs “ON” or “OFF”. So how can we select each data input automatically using
a digital device.
In digital electronics, multiplexers are also known as data selectors because they can “select”
each input line, are constructed from individual Analogue Switches encased in a single IC
package as opposed to the “mechanical” type selectors such as normal conventional switches
and relays.
They are used as one method of reducing the number of logic gates required in a circuit design
or when a single data line or data bus is required to carry two or more different digital signals.
For example, a single 8-channel multiplexer.
Generally, the selection of each input line in a multiplexer is controlled by an additional set of
inputs called control lines and according to the binary condition of these control inputs, either
“HIGH” or “LOW” the appropriate data input is connected directly to the output. Normally, a
multiplexer has an even number of 2N data input lines and a number of “control” inputs that
correspond with the number of data inputs.
Note that multiplexers are different in operation to Encoders. Encoders are able to switch an
n-bit input pattern to multiple output lines that represent the binary coded (BCD) output
equivalent of the active input.
We can build a simple 2-line to 1-line (2-to-1) multiplexer from basic logic NAND gates as
shown.
2-input Multiplexer Design

The input A of this simple 2-1 line multiplexer circuit constructed from standard NAND gates
acts to control which input ( I0 or I1 ) gets passed to the output at Q.
From the truth table above, we can see that when the data select input, A is LOW at logic 0,
input I1 passes its data through the NAND gate multiplexer circuit to the output, while input
I0 is blocked. When the data select A is HIGH at logic 1, the reverse happens and now input
I0 passes data to the output Q while input I1 is blocked.
So by the application of either a logic “0” or a logic “1” at A we can select the appropriate
input, I0 or I1 with the circuit acting a bit like a single pole double throw (SPDT) switch. Then
in this simple example, the 2-input multiplexer connects one of two 1-bit sources to a common
output, producing a 2-to-1-line multiplexer and we can confirm this in the following Boolean
expression.
Q = A.I0.I1 + A.I0.I1 + A.I0.I1 + A.I0.I1
and for our 2-input multiplexer circuit above, this can be simplified too:
Q = A.I1 + A.I0
We can increase the number of data inputs to be selected further simply by following the same
procedure and larger multiplexer circuits can be implemented using smaller 2-to-1
multiplexers as their basic building blocks. So for a 4-input multiplexer we would therefore
require two data select lines as 4-inputs represents 22 data control lines give a circuit with four
inputs, I0, I1, I2, I3 and two data select lines A and B as shown.
4-to-1 Channel Multiplexer

The Boolean expression for this 4-to-1 Multiplexer above with inputs A to D and data select
lines a, b is given as:
Q = abA + abB + abC + abD
In this example at any one instant in time only ONE of the four analogue switches is closed,
connecting only one of the input lines A to D to the single output at Q. As to which switch is
closed depends upon the addressing input code on lines “a” and “b“, so for this example to
select input B to the output at Q, the binary input address would need to be “a” = logic “1”
and “b” = logic “0”.
Then we can show the selection of the data through the multiplexer as a function of the data
select bits as shown.
Multiplexer Input Line Selection
Adding more control address lines will allow the multiplexer to control more inputs but each
control line configuration will connect only ONE input to the output.
Then the implementation of the Boolean expression above using individual logic gates would
require the use of seven individual gates consisting of AND, OR and NOT gates as shown.
4 Channel Multiplexer using Logic Gates

The symbol used in logic diagrams to identify a multiplexer is as follows.
Multiplexer Symbol
Multiplexers are not limited to just switching a number of different input lines or channels to
one common single output. There are also types that can switch their inputs to multiple outputs
and have arrangements or 4-to-2, 8-to-3 or even 16-to-4 etc configurations and an example of
a simple Dual channel 4 input multiplexer (4-to-2) is given below:
4-to-2 Channel Multiplexer
Here in this example the 4 input channels are switched to 2 individual output lines but larger
arrangements are also possible. This simple 4-to-2 configuration could be used for example,
to switch audio signals for stereo pre-amplifiers or mixers.
Example 1:
Implement 4 to 1 MUX using (a) three 2 to 1 MUX (b) only two 2 to 1 MUX and a OR
gate & NOT gate?
(A)

(b) We have already implemented 8 to 1 MUX using two 4 to 1 MUX and one 2 to 1 MUX
but as here we have to implement without using 2 to 1 MUX but a OR gate hence we‟ll utilize
Enable pin of the MUX and skip the use of 2 to 1 MUX as shown below:
Whenever E pin is HIGH, that MUX is selected
Example 2:
Implement (a) 8 to 1 MUX (b) 16 to 1 MUX using 4 to 1 MUX.
Ans: (a) Select lines are abc2
Following is the 8 to 1 multiplexer from 4 to 1 multiplexer

16 to 1 MUX

2.5 The Digital Comparator
Another common and very useful combinational logic circuit is that of the Digital
Comparator circuit. Digital or Binary Comparators are made up from standard AND, NOR
and NOT gates that compare the digital signals present at their input terminals and produce an
output depending upon the condition of those inputs.
For example, along with being able to add and subtract binary numbers we need to be able to
compare them and determine whether the value of input A is greater than, smaller than or
equal to the value at input B etc. The digital comparator accomplishes this using several logic
gates that operate on the principles of Boolean Algebra. There are two main types of Digital
Comparator available and these are.
• Identity Comparator – an Identity Comparator is a digital comparator that has only one
output terminal for when A = B either “HIGH” A = B = 1 or “LOW” A = B = 0
• Magnitude Comparator – a Magnitude Comparator is a digital comparator which has
three output terminals, one each for equality, A = B greater than, A > B and less
than A < B
The purpose of a Digital Comparator is to compare a set of variables or unknown numbers,

for example A (A1, A2, A3, …. An, etc) against that of a constant or unknown value such as
B (B1, B2, B3, …. Bn, etc) and produce an output condition or flag depending upon the result
of the comparison. For example, a magnitude comparator of two 1-bits, (A and B) inputs
would produce the following three output conditions when compared to each other.
Which means: A is greater than B, A is equal to B, and A is less than B
This is useful if we want to compare two variables and want to produce an output when any
of the above three conditions are achieved. For example, produce an output from a counter
when a certain count number is reached. Consider the simple 1-bit comparator below.
1- bit Digital Comparator Circuit

Then the operation of a 1-bit digital comparator is given in the following Truth Table.
Digital Comparator Truth Table
Inputs Outputs
B A A>B A=B A<B
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0
You may notice two distinct features about the comparator from the above truth table. Firstly,
the circuit does not distinguish between either two “0” or two “1”„s as an output A = B is
produced when they are both equal, either A = B = “0” or A = B = “1”. Secondly, the output
condition for A = B resembles that of a commonly available logic gate, the Exclusive- NOR
or Ex-NOR function (equivalence) on each of the n-bits giving: Q = A ⊕ B
Digital comparators actually use Exclusive-NOR gates within their design for comparing their
respective pairs of bits. When we are comparing two binary or BCD values or variables against
each other, we are comparing the “magnitude” of these values, a logic “0” against a logic “1”
which is where the term Magnitude Comparator comes from.
2- bit comparator
Similarly we can have 2 bit comparator and the table to list all the combinations at input and their
corresponding outputs is as:
A B f (A>B) f (A=B) f (A<B)
00 00 0 1 0
01 00 1 0 0
10 00 1 0 0
11 00 1 0 0
00 01 0 0 1
01 01 0 1 0

10 01 1 0 0
11 01 1 0 0
00 10 0 0 1
01 10 0 0 1
10 10 0 1 0
11 10 1 0 0
00 11 0 0 1
01 11 0 0 1
10 11 0 0 1
11 11 0 1 0
And we get the equations for all three outputs from the K-maps as
We can also obtain these equations orally as for A1A0 to be greater than B1B0 either A1 is greater than
B1 (i.e. A1=1 & B1=0) or A1 is equal to B1 (or A1is not less than B1 i.e. (f(A1<B1))‟ = (A1‟B1)‟= (A1 +
B1„) & A0 is greater than B0 (i.e. A0=1 & B0=0).
Hence the equation we get is f (A>B) = A1B1„+ (A1 + B1‟) A0B0‟ = A1B1‘+ A0 B1’B0’+ A1A0B0’


4-bit Magnitude Comparator
Some commercially available digital comparators such as the TTL 74LS85 or CMOS 4063 4-
bit magnitude comparator have additional input terminals that allow more individual
comparators to be “cascaded” together to compare words larger than 4-bits with magnitude
comparators of “n”-bits being produced. These cascading inputs are connected directly to the
corresponding outputs of the previous comparator as shown to compare 8, 16 or even 32-bit
words.
8-bit Word Comparator

When comparing large binary or BCD numbers like the example above, to save time the
comparator starts by comparing the highest-order bit (MSB) first. If equality exists, A = B
then it compares the next lowest bit and so on until it reaches the lowest-order bit, (LSB). If
equality still exists then the two numbers are defined as being equal.
If inequality is found, either A > B or A < B the relationship between the two numbers is
determined and the comparison between any additional lower order bits stops. Digital
Comparator are used widely in Analogue-to-Digital converters, (ADC) and Arithmetic Logic
Units, (ALU) to perform a variety of arithmetic operations.
2.6 Programmable Logic Devices

Programmable Logic Devices A programmable logic device (or PLD) is a general name for a
digital integrated circuit capable of being programmed to provide a variety of different logic
functions. In this section we will discuss several types of combinational PLDs, and later we
will discuss sequential PLDs. Simple combinational PLDs are capable of realizing from 2 to
10 functions of 4 to 16 variables with a single integrated circuit. More complex PLDs may
contain thousands of gates and flip-flops. Thus, a single PLD can replace a large number of
integrated circuits, and this leads to lower cost designs. When a digital system is designed
using a PLD, changes in the design can easily be made by changing the programming of the
PLD without having to change the wiring in the system.
Programmable Logic Arrays A programmable logic array (PLA) performs the same basic
function as a ROM. A PLA with n inputs and m outputs (Figure 9-28) can realize m functions
of n variables. The internal organization of the PLA is different from that of the ROM. The
decoder is replaced with an AND array which realizes selected product terms of the input
variables. The OR array ORs together the product terms needed to form the output functions,
so a PLA implements a sum-of-products expression, while a ROM directly implements a truth
table.
Figure 9-29 shows a PLA which realizes the same functions as the ROM of Figure 9-24.
Product terms are formed in the AND array by connecting switching elements at appropriate
points in the array. For example, to form A′B′, switching elements are used to connect the first
word line with the A′ and B′ lines.

Figure: Programmable Logic Array Structure
Figure a: PLA with Three Inputs, Five Product Terms, and Four Outputs
Switching elements are connected in the OR array to select the product terms needed for the output
functions. For example, because F0 = A′B′ + AC′, switching elements are used to connect the A′B′ and
AC′ lines to the F0 line. The connections in the AND and OR arrays of this PLA make it equivalent to
the AND-OR array of Figure 9-30.
The contents of a PLA can be specified by a PLA table. Table 9-1 specifies the PLA in Figure 9-29.
The input side of the table specifies the product terms. The symbols 0, l, and – indicate whether a
variable is complemented, not complemented, or not present in the corresponding product term. The
output side of the table specifies which product terms appear in each output function. A 1 or 0 indicates
whether a given product term is present or not present in the corresponding output function. Thus, the
first row of Table 9-1 indicates that the term A′B′ is present in output functions F0 and F2, and the
second row indicates that AC′ is present in F0 and F1.

TABLE 1 : PLA Table for Figure
FIGURE 2.13b: PLA Realization of Equation
A PLA table is significantly different than a truth table for a ROM. In a truth table each row represents
a minterm; therefore, exactly one row will be selected by each combination of input values. The 0‟s
and 1‟s of the output portion of the selected row determine the corresponding output values. On the
other hand, each row in a PLA table represents a general product term. Therefore, zero, one, or more
rows may be selected by each combination of input values. To determine the value
of fi for a given input combination, the values of fi in the selected rows of the PLA table must be ORed
together. The following examples refer to the PLA table of Figure 9-31(a). If abcd = 0001, no rows are
selected, and all f‟s are 0. If abcd = 1001, only the third row is selected, and f1f2f3 = 101. If abcd =
0111, the first, fifth, and sixth rows are selected. Therefore, f1 = 1 + 0 + 0 = 1, f2 = 1 + 1 + 0
= 1, and f3 = 0 + 0 + 1 = 1.
Both mask-programmable and field-programmable PLAs are available. The mask-programmable type
is programmed at the time of manufacture in a manner similar to mask-programmable ROMs. The
field-programmable logic array (FPLA) has programmable interconnection points that use electronic
charges to store a pattern in the AND and OR arrays. An FPLA with 16 inputs, 48 product terms, and
eight outputs can be programmed to implement eight functions of 16 variables, provided that the total
number of product terms does not exceed 48. When the number of input variables is small, a PROM
may be more economical to use than a PLA.
However, when the number of input variables is large, PLAs often provide a more economical solution
than PROMs. For example, to realize eight functions of 24 variables would require a PROM with over
16 million 8-bit words. Because PROMs of this size are not readily available, the functions would have
to be decomposed so that they could be realized using a number of smaller PROMs. The same eight
functions of 24 variables could easily be realized using a single PLA, provided that the total number
of product terms is small. If more terms are required, the outputs of several PLAs can be ORed together

Module 2 questions
1. Write a note on Encoder.
2. Implement Full adder using decoder and write a truth table

3. Implement Full Subtractor using decoder and write a truth table
4. Design a logic circuit using a 3 to 8 logic decoder that has active low data inputs, an
active high enable and active low data outputs. Use such a decoder to realize full adder
circuit.
5. Design a combinational circuit to output the 2‟s compliment of a 4 bit binary numbers:
Construct the truth table, Simplify each output function using K-map and draw the
logic diagram
6. Construct a scheme to obtain a 4:16 decoder using 74138 IC.
7. Perform the following to design a combinational logic circuit to convert BCD digit to
EX-3 BCD digit:Construct the truth table,Write the minterm equation for each output
function, Simplify each output function using K-map and draw the logic diagram
8. Design a logic circuit using a 2 to 4 logic decoder that has active low enable and active
high data outputs. Construct the truth table, identify he data inputs, the enable input
and the outputs. Describe the circuit function. Draw the logic diagram.
9. Write the truth table of a 4:2 priority encoder with a valid output where highest priority
is given to the MSB and obtain the minimal sum expressions for the outputs.
10. Design 2 bit comparator using logic gates
11. Implement the following function using 8:1MUX
F1(A,B,C)= A‟BD‟+ACD+B‟CD+A‟C‟D
12. Implement the following function using 4:1MUX
F2(A,B,C,D)= m (( 2,9,10,13,14,15)
13. Design a suitable BCD adder circuit using 7483IC
14. Design and implement a 4 bit Look ahead carry adder.
15. Implement 16:1 mux using 4:1 mux.
16. Implement u= ad+bc‟+bd using 4:1 mux using ab as select inputs.
17. Design 12 bit comparator using 7485IC.
18. How does the look ahead carry adder speed up the addition process.
19. Design a comparator to check if two n-bit numbers are equal, configure this cascaded
stage of 1 bit equality comparator.
20. Realize the following Boolean function f(abc)= m(0,1,3,5,7) using 8:1 and 4:1
MUX

Module 3
Flip-Flops and its Applications: The Master-Slave Flip-flops (Pulse-Triggered flip-flops):
SR flip-flops, JK flip flops, Characteristic equations, Registers, Binary Ripple Counters,
Synchronous Binary Counters, Counters based on Shift Registers, Design of Synchronous
mod-n Counter using clocked T, JK, D and SR flip-flops. (Section 6.4, 6.6 to 6.9 (Excluding
6.9.3) of Text 2)
3.1 Flip-flop Introduction:
Unlike Combinational Logic circuits that change state depending upon the actual signals being applied
to their inputs at that time, Sequential Logic circuits have some form of inherent “Memory” built in
to them as they are able to take into account their previous input state as well as those actually present,
a sort of ”before” and “after” effect is involved with sequential logic circuits.
In other words, the output state of a “sequential logic circuit” is a function of the following three states,
the “present input”, the “past input” and/or the “past output”. Sequential Logic circuits remember these
conditions and stay fixed in their current state until the next clock signal changes one of the states,
giving sequential logic circuits “Memory”.
Sequential logic circuits are generally termed as two state or Bistable devices which can have their
output or outputs set in one of two basic states, a logic level “1” or a logic level “0” and will remain
“latched” (hence the name latch) indefinitely in this current state or condition until some other input
trigger pulse or signal is applied which will cause the bistable to change its state once again.
3.1.1 Sequential Logic Representation
The word “Sequential” means that things happen in a “sequence”, one after another and in Sequential
Logic circuits, the actual clock signal determines when things will happen next. Simple sequential
logic circuits can be constructed from standard Bistable circuits such as: Flip-flops, Latches and
Counters and which themselves can be made by simply connecting together universal

NAND Gates and/or NOR Gates in a particular combinational way to produce the required sequential
circuit.
3.1.2 Classification of Sequential Logic
As standard logic gates are the building blocks of combinational circuits, bistable latches and flip- flops
are the basic building blocks of Sequential Logic Circuits. Sequential logic circuits can be constructed
to produce either simple edge-triggered flip-flops or more complex sequential circuits such as storage
registers, shift registers, memory devices or counters. Either way sequential logic circuits can be
divided into the following three main categories:
▪ Event Driven – asynchronous circuits that change state immediately when enabled.
▪ Clock Driven – synchronous circuits that are synchronized to a specific clock signal.
▪ Pulse Driven – This is a combination of the two that responds to triggering pulses.
As well as the two logic states mentioned above logic level “1” and logic level “0”, a third element is
introduced that separates sequential logic circuits from their combinational logic counterparts,
namely TIME. Sequential logic circuits return back to their original steady state once reset and
sequential circuits with loops or feedback paths are said to be “cyclic” in nature.
3.2 Basic Bistable Element:

The most basic of all the bistable latches and bistable multivibrators is the set-rest (SR) flip-flop. The
basic SR flip-flop is an important bistable circuit because all the other types of flip-flop are built from
it. The SR flip-flop is constructed using two cross-coupled digital NAND gates such as the TTL
74LS00, or two cross-coupled digital NOR gates such as the TTL 74LS02.
The basic SR flip-flop has two inputs S (set) and R (reset) and two outputs Q and Q with one of these
outputs being the complement of the other. Then the SR flip-flop is a two-input, two-output device.
Consider the circuits below.

3.2.1 Basic NAND and NOR SR Flip-flops
Above are the two basic configurations for the asynchronous SR bistable flip-flop using either a
negative input NAND gate, or a positive input NOR gate. For the SR bistable latch using two cross-
coupled NAND gates operate with both inputs normally HIGH at logic level “1”.
The application of a LOW at logic level “0” to the S input with R held HIGH causes output Q to go
HIGH, setting the latch. Likewise, a logic level “0” on the R input with input S held HIGH causes the
Q output to go LOW, resetting the latch. For the SR NAND gate latch, the condition of S = R = 0 is
forbidden.
For the conversion of flip-flops using two cross-coupled NOR gates, when the output Q = 1 and
Q = 0, the bistable latch is said to be in the Set state. When Q = 0 and Q = 1, the NOR gate latch is said
to be in its Reset state. Then we can see that the operation of the NOR and NAND gate flip-flops are
basically just the complements of each other.
The implementation of an SR flip-flop using two cross-coupled NAND gates requires LOW inputs.
However, we can convert the operation of a NAND SR flip-flop to operate in the same manner as the
NOR gate implementation with active HIGH (positive logic) inputs by using inverters, (NOT Gates)
within the basic bistable design.
Latches:
S-R Latch: Set-reset Flip-Flop
▪ Latch is a storage device by using Flip-Flop.

▪ Latch can be controlled by direct inputs.
▪ Latch outputs can be controlled by clock or enable input.
▪ Q and Q are present state for output.
▪ Q+ and Q+ are next states for output.
▪ The function table / Truth table gives relation between inputs and outputs.
▪ The S=R=1 condition is not allowed in SR FF as output is unpredictable.

3.2.2 SR Flip-Flop
The SR flip-flop, also known as a SR Latch, can be considered as one of the most basic sequential
logic circuit possible. This simple flip-flop is basically a one-bit memory bistable device that has two
inputs, one which will “SET” the device (meaning the output = “1”), and is labelled S and another
which will “RESET” the device (meaning the output = “0”), labelled R.
The SR description stands for “Set-Reset”. The reset input resets the flip-flop back to its original state
with an output Q that will be either at a logic level “1” or logic “0” depending upon this set/reset
condition.
A basic NAND gate SR flip-flop circuit provides feedback from both of its outputs back to its opposing
inputs and is commonly used in memory circuits to store a single data bit. Then the SR flip- flop
actually has three inputs, Set, Reset and its current output Q relating to it‟s current state or history. The
term “Flip-flop” relates to the actual operation of the device, as it can be “flipped” into one logic Set
state or “flopped” back into the opposing logic Reset state.
3.2.3 The Gated Set-Reset (SR) Flip-flop
Gated SR flip-flops operate sequentially with its output state only changing in response to its inputs on
the application of a clock or enable input. As the change to the output is controlled by this clock enable
input, the gated SR flip-flop circuit is said to be a “synchronous” flip-flop. Then an asynchronous SR
flip-flop requires no clock, but a synchronous one does.
The conversion of a standard NAND based SR flip-flop to a gated SR flip-flop is achieved using two
AND gates (TTL 74LS08) connected to the Set and Reset inputs. An additional control or “Enable”
input, EN is connected to both AND gates, resulting in LOW outputs when the clock input is LOW as
shown.
3.2.4 Gated SR Flip-flop Circuit

The clock or enable input, EN is connected to one of the inputs of both of the two AND gates, resulting
in LOW outputs when the enable input is LOW (AND gate principals). Then any changes to inputs S
or R has no affect on the state of the outputs, Q and Q of the flip-flop.
When the enable input is HIGH the two AND gates become transparent so any changes to the inputs S
and R will change the state of the outputs as before. Then we can see that either a logic level “1”
(HIGH) or a “0” (LOW) can be stored at the outputs of the gated flip-flop simply by applying a HIGH
to the clock enable input, and that this output state can be retained for any desired period of time
regardless of the condition of the inputs while the enable input remains LOW.
Gated Flip-flop Symbol
As the gated SR flip-flop is a three input device, the logic symbol shows three inputs: S, R and EN.
The EN input is marked with a small triangle to denote the fact that the flip-flop responds to an edge
or transition input.
The conversion of flip-flops to a clocked one is achieved by simply connecting this enable input to a
timing signal. Any changes in the output state will occur in synchronisation with the clock CLK signal.
Note that a clock signal is defined as a sequence of continuous pulses with each pulse having two
separate states, the “ON” state and the “OFF” state, with its duty cycle representing its “ON” time
divided by the total time period of pulse, (“ON” time + “OFF” time). Nearly all digital clock signals
have a 50% duty cycle.A clocked SR flip-flop can change state either on the rising positive- edge or
on the falling negative-edge of the clock signal, or pulse. Therefore an edge-triggered flip- flop only
responds or changes state when the clock pulse changes from one level to another. For example, HIGH
to LOW or LOW to HIGH.
The output of a positive-edge triggered flip-flop only changes state on the rising edge (0-to-1) of the
clock pulse and does not respond to the falling negative-edge. Likewise, a negative-edge triggered flip-
flop changes state on the falling edge (1-to-0) of the clock pulse and does not respond to the rising
positive-edge.
3.2.5 The NAND Gate SR Flip-Flop
The simplest way to make any basic single bit set-reset SR flip-flop is to connect together a pair of
cross-coupled 2-input NAND gates as shown, to form a Set-Reset Bistable also known as an active
LOW SR NAND Gate Latch, so that there is feedback from each output to one of the other NAND
gate inputs. This device consists of two inputs, one called the Set, S and the other called the Reset, R
with two corresponding outputs Q and its inverse or complement Q (not-Q) as shown below.

3.2.6 The Basic SR Flip-flop
➢ The Set State
Consider the circuit shown above. If the input R is at logic level “0” (R = 0) and input S is at logic
level “1” (S = 1), the NAND gate Y has at least one of its inputs at logic “0” therefore, its output Q
must be at a logic level “1” (NAND Gate principles). Output Q is also fed back to input “A” and so
both inputs to NAND gate X are at logic level “1”, and therefore its output Q must be at logic level “0”.
Again NAND gate principals. If the reset input R changes state, and goes HIGH to logic “1” with S
remaining HIGH also at logic level “1”, NAND gate Y inputs are now R = “1” and B = “0”. Since one
of its inputs is still at logic level “0” the output at Q still remains HIGH at logic level “1” and there is
no change of state. Therefore, the flip-flop circuit is said to be “Latched” or “Set” with Q = “1” and Q
= “0”.
➢ Reset State
In this second stable state, Q is at logic level “0”, (not Q = “0”) its inverse output at Q is at logic level
“1”, (Q = “1”), and is given by R = “1” and S = “0”. As gate X has one of its inputs at logic “0” its
output Q must equal logic level “1” (again NAND gate principles). Output Q is fed back to input “B”,
so both inputs to NAND gate Y are at logic “1”, therefore, Q = “0”.
If the set input, S now changes state to logic “1” with input R remaining at logic “1”, output Q still
remains LOW at logic level “0” and there is no change of state. Therefore, the flip-flop circuits “Reset”
state has also been latched and we can define this “set/reset” action in the following truth table.

3.2.7 Truth Table for this Set-Reset Function
State S R Q Q Description
1 0 0 1 Set Q » 1
Set
1 1 0 1 no change
0 1 1 0 Reset Q » 0
Reset
1 1 1 0 no change
Invalid 0 0 1 1 Invalid Condition
It can be seen that when both inputs S = “1” and R = “1” the outputs Q and Q can be at either logic
level “1” or “0”, depending upon the state of the inputs S or R BEFORE this input condition existed.
Therefore the condition of S = R = “1” does not change the state of the outputs Q and Q.
However, the input state of S = “0” and R = “0” is an undesirable or invalid condition and must be
avoided. The condition of S = R = “0” causes both outputs Q and Q to be HIGH together at logic level
“1” when we would normally want Q to be the inverse of Q. The result is that the flip-flop looses
control of Q and Q, and if the two inputs are now switched “HIGH” again after this condition to logic
“1”, the flip-flop becomes unstable and switches to an unknown data state based upon the unbalance
as shown in the following switching diagram.
3.2.8 S-R Flip-flop Switching Diagram

This unbalance can cause one of the outputs to switch faster than the other resulting in the flip-flop
switching to one state or the other which may not be the required state and data corruption will exist.
This unstable condition is generally known as its Meta-stablestate.Then, a simple NAND gate SR flip-
flop or NAND gate SR latch can be set by applying a logic “0”, (LOW) condition to its Set input and
reset again by then applying a logic “0” to its Reset input. The SR flip-flop is said to be in an “invalid”
condition (Meta-stable) if both the set and reset inputs are activated simultaneously.
As we have seen above, the basic NAND gate SR flip-flop requires logic “0” inputs to flip or change
state from Q to Q and vice versa. We can however, change this basic flip-flop circuit to one that changes
state by the application of positive going input signals with the addition of two extra NAND gates
connected as inverters to the S and R inputs as shown.
3.2.9 Positive NAND Gate SR Flip-flop
As well as using NAND gates, it is also possible to construct simple one-bit SR Flip-flops using two
cross-coupled NOR gates connected in the same configuration. The circuit will work in a similar way
to the NAND gate circuit above, except that the inputs are active HIGH and the invalid condition exists
when both its inputs are at logic level “1”, and this is shown below.
3.2.10 The NOR Gate SR Flip-flop
3.2.11 Gated or Clocked SR Flip-Flop
It is sometimes desirable in sequential logic circuits to have a bistable SR flip-flop that only changes
state when certain conditions are met regardless of the condition of either the Set or the Reset inputs.

By connecting a 2-input AND gate in series with each input terminal of the SR Flip-flop a Gated SR
Flip-flop can be created. This extra conditional input is called an “Enable” input and is given the prefix
of “EN“. The addition of this input means that the output at Q only changes state when it is HIGH and
can therefore be used as a clock (CLK) input making it level-sensitive as shown below.
3.2.12 Gated SR Flip-flop
When the Enable input “EN” is at logic level “0”, the outputs of the two AND gates are also at logic
level “0”, (AND Gate principles) regardless of the condition of the two inputs S and R, latching the
two outputs Q and Q into their last known state. When the enable input “EN” changes to logic level
“1” the circuit responds as a normal SR bistable flip-flop with the two AND gates becoming transparent
to the Set and Reset signals.
This additional enable input can also be connected to a clock timing signal (CLK) adding clock
synchronisation to the flip-flop creating what is sometimes called a “Clocked SR Flip-flop“. So a
Gated Bistable SR Flip-flop operates as a standard bistable latch but the outputs are only activated
when a logic “1” is applied to its EN input and deactivated by a logic “0”.
3.2.13 Characteristic equation of SR Flip Flop
("X" is "don't care")
States Inputs
Previous Present S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0
Characteristic equation Q(next) = S + QR′

State Transition Diagram of SR Latch, Excitation Table of SR Latch
10
01 00
0 1
00 01
State diagram of SR FF
PS NS FF i/p
Q Q+ S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0








































Module 3 Questions
1. Explain the operation of clocked SR f/f.
2. Draw the logic diagram of SR latch and explain the operation of SR latch.
3. Explain the working of SR F/F.
4. Differentiate between combinational and sequential circuits.
5. Differentiate between Flipflop and a Latch.
6. Explain the operation of a simple SR Flip Flop using NAND gates.
(June/July. 2011…10 Marks)
7. What is a sequential circuit? Discuss the different types of sequential circuit.
(06 Marks)
8. Give the logic diagram
i) Master Slave J-K flip Flop.
ii) Master Slave S-R Flip Flop.
9. Explain, how to use SR latch a s switch debouncer. Draw the timing diagram to
support your explanation (Dec 2011…04 Marks)
10. Explain the following:
i) Switch debouncing and its elimination.
ii) Race around problem and its elimination.
(Dec 09/Jan 10…14 Marks)
11. Explain the operation of SR latch. Explain one of its applications.
(May/June2010…12 Marks)
12. Draw the logic diagrams for (08 Marks)

(i).Gated SR latch.
(ii).Master Slave JK Flip Flop.
(iii).Master slave SR Flip Flop.
(iv).Positive Edge triggered „D‟Flip flop.
13. Design a block diagram of a mod 7 twisted ring counter and explain its operation. Give
the count sequence table and the decoding logic used to identify the various states.
(10 Marks)
14. Design a mod-5 synchronous binary counter using clocked J-K flip flops. (10
Marks)
15. Explain Johnson Counter, with its circuit diagram , and timing diagram. (08
Marks)
16. Clearly distinguish between (June/July 2009…06
Marks)
i) Synchronous and asynchronous circuits.

ii) Combinational and sequential circuits.

17. Explain the working of 4 bit asynchronous counter. (06
Marks)
18. Explain Johnson Counter with its circuit diagram and timing diagram. (08
Marks)
19. Explain the working principle of a mod-8 binary ripple counter, configured using
+ve edge triggered T flip flop. Also draw the timing diagram. (08
Marks)
20. Design a synchronous mod -6 counter whose counting sequence is 0, 1, 2, 4, 6, 7 and
repeat ,by obtaining its minimal –sum equations. Use +ve edge triggered D flip flops.
(08 Marks)
21. With the help of a diagram explain the following with respect to shift register:
iii) Parallel in and serial out.
iv) Ring counter and twisted ring counter.
1. (Dec 09/Jan. 10…08 Marks)
(June/July 13…08 Marks)
22. Design a mod -5 synchronous counter using JK flip flop. (12
Marks)
23. Construct the excitation table, transition table and state diagram of the Moore
sequential circuit given below: (June /July
2011…10 Marks)
v)
24. Compare Moore and Mealy models. (04

Marks)
25. Explain the Mealy model of a clocked synchronous sequential network. (06
Marks)
26. Describe the following terms with respect to sequential machines:
vi) 1. State 2. Present state 3. Next state
(Dec.2011…06 Marks)
27. Construct a state diagram that will detect a serial input sequence of 0101.The required
bit pattern can occur in a long data string and the correct pattern can overlap with
another pattern. When the input pattern has been detected, cause the output z to be
asserted high. Design the sequential machine using D flip-flops.use the state
assignments,
i. A -→ 00, B-→01, C→ 10,D→11 (14
Marks)
28. With the suitable example , Explain Mealy and Moore Model in a sequential circuit
analysis. (Dec 09/Jan. 10…10 Marks)
29. A sequential circuit has one input and one output. The state diagram is as shown in
figure. Design a sequential circuit with „T‟ flip flop.
(06
Marks)
vii)
30. Explain the Mealy model and Moore Model for clocked synchronous sequential
network.
(10 Marks)
31. Compare Moore and Mealy models. (04
Marks)
32. Design a synchronous counter using JK flip flops to count in the Sequence
0,1,2,4,5,6,0,1,2…….. Use state diagram and state table. (12
Marks)
33. Distinguish between Moore and Mealy model with necessary block diagrams.
(Dec 08/Jan.09…08
Marks)

Module 4
Introduction to Verilog: Structure of Verilog module, Operators, Data Types, Styles of
Description. (Section 1.1 to 1.6.2, 1.6.4 (only Verilog), 2 of Text 3)
Verilog Data flow description: Highlights of Data flow description, Structure of Data flow
description. (Section 2.1 to 2.2 (only Verilog) of Text 3)
4.1 Structure of the Verilog Module
Verilog module has declaration and body. In the declaration, the name, inputs, and outputs of
the module are entered. The body shows the rela-tionship between the inputs and the outputs.
Listing 1.2 shows a Verilog description of a half adder based on the Boolean function of the
outputs.
The name of the module in Listing 1.2 is a user-selected Half_adder. In contrast to VHDL,
Verilog is case sensitive. Half_adder, half_adder, and half_addEr are all different names. The
name of the module should start with an alphabetical letter and can include the special
character under- score (_). The declaration of the module starts with the predefined word
module followed by the user-selected name. The names of the inputs and outputs (they are
called input and output ports) follow the same guidelines as the module‟s name. They are
written inside parentheses separated by a comma. The parenthesis is followed by a semicolon.
In Listing 1.2, a, b, S, and C are the names of the inputs and outputs. The order of writing the
input and output ports inside the parentheses is irrelevant. We could have written the module
statement as:

The semicolon (;) plays the same rule as in VHDL module; it is a line separator. Carriage
return here does not indicate a new statement, the semicolon does. Following the module
statement, the input and output port modes are declared. For example, the statement input a;
declares signal a as an input port. The modes of the ports are discussed in Section 1.4.2. In
contrast to VHDL, the type of the input and output port signals need not be declared. The order
of writing the inputs and outputs and their declaration is irrelevant. For example, the inputs
and outputs in Listing 1.2 can be written as:
Also, more than one input or output could be entered on the same line by using a comma (,)
to separate each input or output as:
module half_adder (a,b, S, C);

output S, C;
input a, b;
Statements 1 and 2 in Listing 1.2 are signal assignment statements.

In statement 1, the symbol ^ represents an EXCULSIVE-OR operation; this symbol is called
a logical operator (see Section 1.5.1.2). So, statement 1 describes the relationship between S,
a, and b as S = a xor b.
In statement 2, the symbol & represents an AND logic; the symbol is called a logical operator.
So, statement 2 describes the relationship between C, a, and b as C = a and b. Accordingly,
Listing 1.2 simulates a half adder. The double slash (//) is a comment command where a
comment can be entered.
If the comment takes more than one line, a double slash or pair (/◻ ◻ /)can be used. The
module is concluded by the predefined word endmod-ule. Leaving blank lines is allowed in
the module; also, spaces between two words or at the beginning of the line are allowed.

4.2 Operators
HDL has an extensive list of operators. These operators are used ex-tensively in every chapter
of the book. Operators perform a wide variety of functions. These functions can be classified
as:
• Q Logical, such as AND, OR, and XOR
• Q Relational to express the relation between objects.These operators include equality,
inequality, less than, less than or equal, greater than, and greater than or equal.
• Q Arithmetic such as addition, subtraction, multiplication,and division
• Q Shift to move the bits of an object in a certain direction, such as right or left
Logical Operators
These operators perform logical operations, such as AND, OR, NAND, NOR, NOT, and XOR.
The operation can be on two operands or on a single operand. The operand can be single or
multiple bits.
Verilog Logical Operators
Verilog has extensive logical operators. These operators perform logical operations such as
AND, OR, and XOR. Verilog logical operators can be classified into three groups: bitwise,
Boolean logical, and reduction. The bitwise operators operate on the corresponding bits of two
operands. Con-sider the statement: Z= X & Y, where the AND operator (&) “ANDs” the
corresponding bits of X and Y and stores the result in Z. For example, if X is the four-bit signal
1011, and Y is the four-bit signal 1010, then Z = 1010.
Table 1.3 shows bitwise logical operators. For example, the NAND opera-
tion on X and Y is written as: Z = ~(X & Y).

Other types of logical operators include the Boolean logical operators.These operators operate
on two operands, and the result is in Boolean: 0(false) or 1 (true). For example, consider the
statement Z = X && Y where && is the Boolean logical AND operator. If X = 1011 and Y =
0001, then Z = 1. If X = 1010 and Y = 0101, then Z = 0. Table 1.4 shows the Boolean logical
operators.

The third type of logical operator is the reduction operator. Reduction operators operate on a
single operand. The result is in Boolean. For example, in the statement Y = &X, where & is
the reduction AND operator, and assuming X = 1010, then Y = (1 & 0 & 1 & 0) = 0. Table
1.5 shows the reduction logic operators.
Relational Operators
Relational operators are implemented to compare the values of two objects. The result returned
by these operators is in Boolean: false (0) or true (1).
Verilog Relational Operators

Verilog has a set of relational operators similar to VHDL.
Table 1.7 shows Verilog relational operators. As in VHDL, the relational operators return
Boolean values: false (0) or true (1).

For the equality operator (==) and inequality operator (!=), the result can be of type unknown
(x) if any of the operands include “don‟t care,” “un-known (x),” or “high impedance z.” These
types are covered in Section 1.6.
The following are examples of a Verilog relational operator:

if (A == B) ........
If the value of A or B contains one or more “don‟t care” or z bits, the value of the
expression is unknown. Otherwise, if A is equal to B, the value of the expression is
true (1). If A is not equal to B, the value of the expression is false (0).
if (A === B).....
This is a bit-by-bit comparison. A or B can include x or high impedance Z; the result
is true (1) if all bits of A match that of B. Otherwise, the result is false (0).
For the conditional operator “?” the format is: Conditional-expression ? true-
expression : false-expression ;
The conditional expression is evaluated; if true, true-expression is executed If false,

false-expression is executed. If the result of the conditional-expression is “x,” both
false and true are executed, and their results are compared bit by bit; if two
corresponding bits are the same, the common value of these bits is returned. If they are
not equal, an “x” is returned.

Arithmetic Operators
Arithmetic operators can perform a wide variety of operations, such as addition, subtraction,
multiplication, and division.
Verilog Arithmetic Operators

Verilog, in contrast to VHDL, is not extensive type-oriented language.Accordingly, for most
operations, only one type of operation is expected for each operator. An example of an
arithmetic Verilog operator is the addition operator (+); the statement Y = (A + B) calculates
the value of Y as the sum of A and B.
Table 1.9 shows the Verilog arithmetic operators.
Arithmetic Operator Precedence

The precedence of the arithmetic operators in VHDL or Verilog is the same as in C. The
precedence of the major operators is listed below from highest to lowest:

Shift and Rotate Operators

Shift and rotate operators are implemented in many applications, such as in multiplication and
division. A shift left represents multiplication by two, and a shift right represents division by
two.
Verilog Shift Operators

Verilog has the basic shift operators. Shift operators are unary opera-tors; they operate on a
single operand. To understand the function of these operators, assume operand A is the four-
bit vector 1110.
Table 1.11 shows the Verilog shift operators as they apply to operand A.
Verilog Data Types

Verilog supports several data types including nets, registers, vectors, integer, real,
parameters, and arrays.

Nets
Nets are declared by the predefined word wire. Nets have values that change continuously by
the circuits that are driving them. Verilog supports four values for nets, as shown in Table
1.13.
The first statement declares a net by the name sum. The second state-ment declares a net by
the name of S1; its initial value is 1‟b0, which represents 1 bit with value 0.
Register
Register, in contrast to nets, stores values until they are updated. Register, as its name suggests,
represents data-storage elements. Register is declared by the predefined word reg. Verilog
supports four values for register, as shown in Table 1.14.

Vectors
Vectors are multiple bits. A register or a net can be declared as a vector. Vectors are declared
by brackets [ ].
Examples of vectors are:
The first statement declares a net a. It has four bits, and its initial value is 1010 (b stands for
bit). The second statement declares a register total. Its size is eight bits, and its value is decimal
12 (d stands for decimal).
Integers
Integers are declared by the predefined word integer.
An example of integer declaration is:
integer no_bits;
The above statement declares no_bits as an integer.
Real
Real (floating-point) numbers are declared with the predefined word real. Examples of real
values are 2.4, 56.3, and 5e12. The value 5e12 is equal to 5 × 10^12. The following statement
declares the register weight as real:
real weight;
Parameter
Parameter represents a global constant. It is declared by the pre-defined word parameter. The
following is an example of implementing parameters:

Arrays
Verilog, in contrast to VHDL, does not have a predefined word for ar-ray. Registers and
integers can be written as arrays. Consider the following statements:
Brief Comparison of VHDL and Verilog

Data Types
VHDL: Definitely a type-oriented language, and VHDL types are built in or users can create
and define them. User-defined types give the user a tool to write the code effectively; these
types also support flexible coding. VHDL can handle objects with multidimensional array
types.Another data type that VHDL supports is the physical type; the physi-cal type supports
more synthesizable or targeted design code.
Verilog: Compared to VHDL, Verilog data types are very simple and easy to use. All types
are defined by the language.
Ease of Learning
VHDL: For beginners, VHDL may seem hard to learn because of its rigid type
requirements. Advanced users, however, may find these rigid type requirements easier to
handle.
Verilog: Easy to learn, Verilog users just write the module without worrying about what
library or package should be attached. Many of the statements in the language are very
similar to those in C language.

Libraries and Packages

VHDL: Libraries and packages can be easily attached to the standard VHDL package.
Packages can include procedures and functions, and the package can be made available to any
module that needs to use it. Packages are used to target a certain design. For example, if the
system modeled/designed includes arithmetic functions, a package can be used
that includes those functions.
Verilog: Libraries are not as easily implemented as in VHDL, however the basic Verilog
package includes several libraries as integer part of the package.
4.3 Styles (Types) Of Description

Several styles of code writing can be used to describe the system. Selection of the styles
depends on the available information on the system. In the following section, six styles will
be discussed: data flow, behavioral, structural, switch level, mixed type, and mixed language.
• Data Flow Description

Data flow describes how the system‟s signals flow from the inputs to the outputs. Usually, the
description is done by writing the Boolean function of the outputs. The data-flow statements
are concurrent; their execution is controlled by events. The VHDL architecture or Verilog
module data-flow description, as defined here, does not include any of the key words that
identify behavioral, structural, or switch-level descriptions.
• Behavioral Description
A behavioral description models the system as to how the outputs behave with the inputs;
usually, a flowchart is used to show this behavior. In the half adder, the S output can be
described as “1” if the inputs a and b are not equal, otherwise S = “0,” (see Figure 1.2). The
output C can be described as acquiring a value of “1” only if each input (a and b) is “1.” The
HDL behavioral description is the one where the architecture (VHDL) or the module (Verilog)
contains the predefined word process (VHDL) or always or initial (Verilog).

Behavioral description is usually used when the Boolean function or the digital logic of the
system is hard to obtain.
• Structural Description
Structural description models the system as components or gates. This description is identified
by the presence of the keyword component in the architecture (VHDL) or gates construct such
as and, or, and not in the module (Verilog).

• Switch-Level Description
The switch-level description is the lowest level of description. The system is described using
switches or transistors. Some of the Verilog pre-defined words used in the switch level
description are nmos, pmos, cmos,tranif0, tran, and tranif1. VHDL does not have built-in
switch-level primitives, but a construct package can be built to include such primi-
tives.
• Mixed-Type Description
Mixed-type or mixed-style descriptions are those that use more than one type or style of the
above-mentioned descriptions. In fact, most of the descriptions of moderate to large systems
are mixed. Some parts of the system may be described using one type and others using other
types of description.

• Mixed-Language Description
The mixed-language description is a newly added tool to HDL description. The user now can
write a module in one language (VHDL or Verilog) and invoke or import a construct (entity
or module) written in the other language. Listing 1.6 illustrates the mixed-language
description. In this Listing, inside Verilog module Full_Adder1, the VHDL entity HA is
instantiated (imported). The information given in that entity is now visible to the Verilog
module.
Listing 1.6 illustrates the mixed-language description.

4.4 Highlights of Data-Flow Description

Data flow is one type (style) of hardware description. Other types include behavioral,
structural, switch level, mixed type, and mixed language.
Listed below are some facts about data-flow description:
• Q Data-flow description simulates the system to be described by showing how the
signal flows from the system inputs to its outputs. For example, the Boolean function
of the output or the logical structure of the system shows such signal flow.
• Signal-assignment statements are concurrent. At any simulation time, all signal-
assignment statements that have an event are executed concurrently.
4.5 Structure of Data Flow Description
• Signal Declaration and Assignment Statement
Figure 2.1 shows an AND-OR circuit. Signals a, b, c, and d are the inputs, signal y is the
output, and signals s1 and s2 are intermediates. The Boolean function of the output y can be
written as:

Referring to Listing 2.1, the input and output signals are declared in the entity (module) as
ports. In HDL, a signal has to be declared before it can be used (although in Verilog, it is not
necessarily needed if the signal is a single bit). Accordingly, signals s1 and s2 have to be
declared.

In VHDL, s1 and s2 are declared as signals by using the predefined word signal in the
architecture:
signal s1, s2 : bit;
In Verilog, s1 and s2 are declared as signals by using the predefined word wire:
wire s1, s2;
By default, all ports in Verilog are assumed to be wires. The value of the wire is continuously
changing with changes in the device that is deriving it. For example, s1 is the output of the
AND gate in Figure 2.1, and s1 is continuously updated as a or b changes. A signal-assignment
statement is used to assign a value to a signal. The left-hand side of the statement should be
declared as a signal. The right-hand side can be a signal, a variable, or a constant. The operator
for signal assignment is <= in VHDL or the predefined word assign in Verilog. In Listing 2.1,
statements 1, 2, and 3 are signal-assignment statements.
The execution of the signal-assignment statement in HDL is somehow different in

concept from that of software languages such as C. Statements 1–3 need an event to occur on
its right-hand side to start execution. If no event occurred on any statement, this statement
would not be executed. An event is a change in the value of a signal or variable such as a
change from 0 to 1 (from low to high) or from 1 to 0 (from high to low). The statement that
receives an event first will be executed first regardless of the order of its placement in the HDL
code. If more than one statement have an event at the same time, all of these statements will
be executed concurrently (i.e., simultaneously). Accordingly, statement 3, for example, could
have been written before statement 1 in Listing 2.1, and the order of execution would not be
affected.
The signal-assignment statement is executed in two phases: calculation and

assignment. If an event occurs on the right-hand side of a statement, then this side is calculated
at the time of the event; after calculation, the value obtained from the calculation is assigned
to the left-hand side, taking into consideration any timing information given in the statement.

Consider Listing 2.1 and Figure 2.2. At T0, an event has occurred in signal a and signal b
(both signals changed their value from 0 to 1, which is an event). Accordingly, an event
occurred in statement 1; the value of (a and b) is calculated as (1 and 1 = 1).
Because no delay time is specified, the value 1 is assigned immediately to s1, changing s1
from 0 to 1. Changing the value of s1 from 0 to 1 constitutes an event in s1 and in statement
3, which is executed as a result of the event in its right-hand side. The right-hand side of
statement 3 is calculated at T0 as (s1 [1] or s2 [0] = 1). The value of 1 is assigned to y; all at
T0 because no delay time is specified. At T1, there is event on signals a (1 to 0), c (0 to 1),
and d (0 to 1). Statements 1 and 2 will be executed concurrently because an event occurred on
their right-hand side. The right-hand side of statement 1 and 2 is calculated at T1 as (0 and 1
= 0) and (1 and 1 = 1); the value of 0 is assigned to s1, and the value of 1 is assigned to s2 at
T1. Changing the value of s1 and s2 constitutes an event on s1 and s2, which selects statement
3 for execution at T1; statement 3 is executed (calculation, s1 or s2 = 0 or 1 = 1), and
accordingly, 1 is assigned to signal y. At T2, an event occurred on signal c, statement 2 is
executed at T2, and the calculation results in 0 and 1= 0; the value 0 is assigned to s2, changing
its value from 1 to 0 and generat-ing an event in s2. Statement 3 is executed because an event
(changing the value of s2 from 1 to 0) occurred on the right-hand side. The calculation results
in 0 or 0 = 0; the value 0 is assigned to y at T2.
• Constant Declaration and Constant Assignment Statements
A constant in HDL is treated as it is in C language; its value is constant within the segment of
the program where it is visible. A constant in VHDL can be declared using the predefined
word constant. In Verilog, a constant can be declared by its type such as time or integer.
For example, the following statements declare period as a constant of type time:
constant period : time; -- VHDL
time period; // Verilog
To assign a value to a constant, use the assignment operator := in VHDL

or = in Verilog.

For example, to assign a value of 100 nanoseconds to the constant period described
above:
period := 100 ns; -- VHDL
period = 100; // Verilog
In the above Verilog statement, there are no explicit units of time; 100 means 100 simulation
screen time units. If the simulation screen time units are defined as nanoseconds (ns), for
example, then 100 will mean 100 nanoseconds. The declaration and assignment can be
combined in one statement as:
Constant period : time := 100 ns; -- VHDL

time period = 100 //Verilog
• Assigning a Delay Time to the Signal-Assignment Statement
To assign a delay time to a signal-assignment statement, the predefined word after in VHDL
or # in Verilog is used.
For example, the following statement assigns a 10 ns delay time to signal S1:
S1 <= a and b after 10 ns -- VHDL
assign #10 S1 = a & b // Verilog
In Verilog, the delay is in simulation screen unit time. Let us assume that there is a delay of
10 ns between the output of each statement 1–3 and its input in Listing 2.1. This is
equivalent to saying that operation (and) or (or) takes 10 ns to be completed.
Listing 2.2 shows the HDL code for Figure 2.1 with a 10 ns delay for the (and) and (or)
operations.

LISTING 2.2 HDL code of Figure 2.1 with 10 ns delay
Figure 2.3 shows the simulation waveform of Listing 2.2. Table 2.1 shows analysis of the
waveform according to Listing 2.2. At T0, an event occurred on signal a and signal b (both
changed from 0 to 1). This event will invoke execution of statement 1. The right-hand side
(R.H.S) of statement 1 is calculated at T0 as (1 and 1 = 1). However, this value of 1 will not
assigned to s1 at T0; rather, it will be assigned at T0 + 10 ns = T1. The rest of Table 2.1
could be understood by following the same analysis that has been done above at T0.

From Table 2.1, the worst total delay time between the input and the output of Figure 2.1, as
expected, is 20 ns. It is to be noted that if a signal-assignment statement did not specify a delay
time, the assignment to its left-hand side would occur after the default infinitesimally small
delay time of D (delta) seconds. This infinitesimally small time cannot be detected on the
screen, and the delay time will look as if it is zero. In the following several examples, data-
flow descriptions are introduced.
Examples:
• DATA-FLOW DESCRIPTION OF A FULL ADDER

A full adder is a combinational circuit (output depends only on the input) that adds three input
bits (a + b + c) and outputs the result as two bits; one bit for the sum and one bit for the

carryout. Examples of full addition are: 1 + 0 + 1 = 10 (in decimal 1 + 0 + 1 = 2) and 1 + 1 +

1 = 11 (in decimal 1 + 1 + 1 = 3). Table 2.2 shows the truth table of the full adder.

The full adder can be built from several existing logic components such as two half adders
and multiplexers (see Exercise 2.1 at the end of this chapter). Building a full adder from two
half adders is based on the following analysis.
The full adder adds a plus b plus c = carryout sum. If the addition is performed in two steps:
a plus b = C1 S, and c plus S = C2 sum (sum is the sum of the three bits). C1 and C2 cannot
have a value of 1 at the same time. If C1 has value of 1, then C2 has to be 0 and vice versa.
For example, to add 1 plus 1 plus 1, divide the addition in two halves; the first half is 1 plus
1 = 10, and the second half is 0 plus 1 = 1. The carryout will be (C1 or C2); in this example,
it is 1 and the sum = 1. Figure 2.6 shows the logic diagram of the full adder built from two
half adders.

Listing 2.3 shows the HDL code for the full adder as shown in Figure 2.5. Review Section
1.5.1 to know the VHDL and Verilog logical operators. The code assumes no delay time.
The parenthesis in the code, as in C language, gives the highest priority to the expression
within the parenthesis and makes the code more readable.
LISTING 2.3 HDL Code of the Full Adder From Figure 2.5
• FULL SUBTRACTOR
A full subtractor performs the following operation: a - b - c = Borrow Diff. Borrow and Diff
are each one-bit output. The Diff is the difference, and Borrow is the borrow. For example, 0
- 1 - 0 = 11. The subtraction is done as follows: 0 - 1 cannot subtract 1 from 0 because 1 is
greater than 0, so borrow 1 from the higher-order bit. Accordingly, this 1 has a weight of 21,
so its value is 2; subtract 2 - 1 = 1. Now, for bit c, 1 - 0 = 1, so the difference is 1, and the
borrow is 1. Table 2.3 shows the truth table of a full subtractor.

Compare the Diff in Table 2.3 and the Sum in Table 2.2; they are identical, so the Boolean
function of the Diff is the same as the sum in Equation 2.3. For the Borrow, draw the K-map
as shown in Figure 2.8.
• 2x1 MULTIPLEXER WITH ACTIVE LOW ENABLE

A 2x1 multiplexer is a combinational circuit; it has two one-bit inputs, a one-bit select line,
and a one-bit output. Additional control signals may be added, such as enable. The output of
the basic multiplexer depends on the level of the select line. If the select is high (1), the output
is equal to one of the two inputs. If the select is low (0), the output is equal to the other input.
A truth table for a 2x1 multiplexer with active low enable is shown in Table 2.4.

If the enable (Gbar) is high (1), the output is low (0) regardless of the input. When Gbar is low
(0), the output is A if SEL is low (0), or the output is B if SEL is high (1). From Table 2.4, the
Boolean function of the output Y is: Y = (S1 and A and SEL) or (S1 and B and SEL); S1 is
the invert of Gbar Figure 2.9a shows the logic symbol, and Figure 2.9b shows the gate-level
structure of the multiplexer.
Listing 2.4a shows the HDL code. To generate the code, follow Figure 2.9b. Propagation delay
time for all gates is assumed to be 7 ns. Because this is a data-flow description, the order in
which the statements are written in the code is irrelevant. For example, statement st6 could
have been written at the very beginning instead of statement st1. The logical operators in
VHDL and (Verilog) implemented in this Listing are: OR (|), AND (&), and NOT (~).

LISTING 2.4a HDL Code of a 2x1 Multiplexer: VHDL and Verilog
2x1 MULTIPLEXER WITH ACTIVE LOW ENABLE USING VERILOG

CONDITIONAL OPERATOR (?)
The format of this operator can be written as:

Assign Y = Conditional-expression ? true-expression : false-expression

If the conditional expression is true, the value of the true expression is assigned to Y; if the
conditional expression is false, the value of the false expression is assigned to Y.
HDL Code of a 2x1 Multiplexer Using Verilog Conditional (?)

module Mux2x1_conditional(input A,B,SEL,Gbar, output Y );
assign Y = (Gbar) ? 1‟b0 : (SEL & B ) | (~ SEL & A);
endmodule
• A 2x4 DECODER
A decoder is a combinational circuit. A 2x4 decoder has two inputs and four outputs. For
any input, only one output is active; all others are inactive. For active high output decoders,
only one output is high. The output of n-bit input decoder is 2n bits. Table 2.5 shows the
truth table of the 2x4 decoder.

LISTING 2.4 HDL Code of a 2x4 Decoder Without Time Delay
Module 4 Questions
1) What is Verilog?
2) What is the difference between Verilog and VHDL?
3) What are HDL simulators?
4) What is the difference between blocking and non-blocking in Verilog?
5) What do you understand by Verilog full case statements and Verilog parallel case
statements?
6) What are the main differences between Task and Function in Verilog?
7) What are the main differences between Wire and Reg?
8) What is the process to execute blocking and non-blocking assignments?
9) What is a repeat loop in Verilog?
10) Describe data flow description in detail with examples.

Module 5
Verilog Behavioral description: Structure, Variable Assignment Statement, Sequential

Statements, Loop Statements, Verilog Behavioral Description of Multiplexers (2:1, 4:1, 8:1).
(Section 3.1 to 3.4 (only Verilog) of Text 3)
Verilog Structural description: Highlights of Structural description, Organization of

structural description, Structural description of ripple carry adder. (Section 4.1 to 4.2 of Text
3)
5.1 Structure of the HDL Behavioral Description
FIGURE: Execution of signal-assignment statements inside process (VHDL) or inside

always (Verilog).
Referring to the Verilog code in Listing 3.1, always is the Verilog behavioral statement. In contrast to
VHDL, all Verilog statements inside always are treated as concurrent, the same as in the data-flow
description. Also, here any signal that is declared as an output or appears at the left-hand side of a
signal-assignment statement should be declared as a register (reg) if it appears inside always. In Listing
3.1, O1 and O2 are declared outputs, so they should also be declared as reg.
LISTING 3.1 Example of an HDL Behavioral Description

5.2 The VHDL Variable-Assignment Statement
The use of variables inside processes is a common practice in VHDL behavioral description.
Consider the following two signal-assignment statements inside a process, where S1, S2, and
t1 are signals:
In VHDL, a statement can be labeled, and the label should be followed by a colon. In the
above code, Signl, st1, and st2 are labels. VHDL code in this example does not use these
labels for compilation or simulation; they are optional. Labels are used here to refer to a
certain statement by its label. For example, to explain the statement S1 <= t1, it can be
referred to by statement st1.
In the above code, signal S1 appears on both the left-hand side of statement st1 and on the
right-hand side of statement st2. Assume at simulation time T0, t1 = 0 and S1 = 0, and at
simulation time T1, t1 changes from 0 to 1 (see Figure 3.2). This change constitutes an event,
and the process labeled Signl is activated. For statement st1, S1 is calculated as1. S1 does not
acquire this new value of 1 at T1, but rather at T1 + D. For statement st2, S2 at T1 is calculated
using the old value of S1 (0). Alternately, variable-assignment statements can be used instead
of the above signal- assignment statement as follows:

Variable-assignment statements, as in C language, are calculated and assigned immediately

with no delay time between calculation and assignment. The assignment operator is :=. If t1
acquires a new value of 1 at T1,then momentarily temp1 = 1 and temp2 = 0. For statements
st5 and st6, S1 acquires the value of temp1 (1) at T1 + D, and S2 acquires the value of temp2
(0) at T1 + D. Because D is infinitesimally small, S1 and S2 appear on the simulation screen
as if they acquire their new values at T1.

5.3 Sequential Statements
There are several statements associated with behavioral descriptions.These statements have
to appear inside process in VHDL or inside always or initial in Verilog.
• IF Statement
IF is a sequential statement that appears inside process in VHDL or inside always or initial in Verilog.
Verilog IF-Else Formats
The execution of IF statement is controlled by the Boolean expression.If the Boolean

expression is true, then statements 1, 2, and 3 are executed. If the expression is false,
statements a, b, and c are executed.
EXAMPLE 1: BOOLEAN EXPRESSION AND EXECUTION OF IF
In Example 3.1, if clk is high (1), the value of s1 is assigned to the variable temp.
Otherwise, s2 is assigned to the variable temp. The else statement can be eliminated, and in
this case, the IF statement simulates a latch, as shown in Example 3.2.

EXAMPLE 2: EXECUTION OF IF AS A LATCH
If clk is high, the value of s1 is assigned to temp. If clk is not high,temp retains its current
value, thus simulating a latch. Another format for the IF statement is Else-IF.
EXAMPLE 3: EXECUTION OF IF AS ELSE-IF
EXAMPLE 4: IMPLEMENTING ELSE-IF
Verilog
if (signal1 == 1‟b1)
temp = s1;
else if (signal2 == 1‟b1)
temp = s2;
else
temp = s3;
After execution of the above IF statement, temp acquires the values shown in Table 3.1.

EXAMPLE 5: BEHAVIORAL DESCRIPTION OF A LATCH USING VARIABLE AND

SIGNAL ASSIGNMENTS
LISTING 3.4 Verilog Code for Behavioral Description of a D-Latch
module D_latch (d, E, Q, Qb);

input d, E;
output Q, Qb;
reg Q, Qb;
always @ (d, E)
begin
if (E == 1)
begin
Q = d;

Qb = ~ Q;
end
end
endmodule
⚫ The case Statement
The case statement is a sequential control statement. It has the following format:
Verilog Case Format
case (control-expression)
test value1 : begin statements1; end
default : begin default statements end
endcase
If, for example, test value1 is true (i.e., it is equal to the value of the control expression),
statements1 is executed. The case statement must include all possible conditions (values) of the control-
expression. The statement when others (VHDL) or default (Verilog) can be used to guarantee that all
conditions are covered. The case resembles IF except the correct condition in case is determined
directly, not serially as in IF statements. The begin and end are not needed in Verilog if only a single
statement is specified for a certain test value. The case statement can be used to describe data listed
into tables.
EXAMPLE 1: THE CASE STATEMENT
In Example 3.7, the control is sel. If sel = 00, then temp = I1, if sel = 01, then temp = I2, if sel = 10,
then temp = I3, if sel = 11 (others or default), then temp = I4. All four test values have the same priority;
it means that if sel = 10, for example, then the third (VHDL) statement (temp :I3) is executed directly
without checking the first and second expressions (00 and 01).

EXAMPLE 2: BEHAVIORAL DESCRIPTION OF A POSITIVE EDGE-TRIGGERED JK

FLIP-FLOP USING THE CASE STATEMENT
Edge-triggered flip-flops are sequential circuits. Flip-flops are triggered by the edge of the clock, in
contrast to latches where the level of the clock (enable) is the trigger. Positive (negative) edge- triggered
flip-flops sample the input only at the positive (negative) edges of the clock; any change in the input
that does not occur at the edges is not sampled by the output. Figures 3.8a and 3.8b show the logic
symbol and the state diagrams of a positive edge-triggered JK flip-flop, respectively.
Fig: (a) Fig:(b)
FIGURE 3.8 JK flip-flop. a) Logic symbol. b) State diagram.
Table 3.2 shows the excitation table of the JK flip-flop. It conveys the same information as the state
diagram. The state diagram (Figure 3.8b) shows the possible states (two in this case: q can take 0 or
1), state 0 and state 1. The transition between these states has to occur only at the positive edges of the
clock. If the current state is 0 (q = 0), then the next state is 0(1) if JK = 0x(1x), where x is “don‟t care.”
If the current state is 1 (q = 1), then the next state is 1(0) if JK = x0(x1). Table 3.2 shows the same
results as the state diagram. For example, a transition from 0 to 1, according to the excitation table, can
occur if JK = 10 or JK = 11, which is JK = 1x.

Listing 3.7 shows the HDL code for a positive edge-triggered JK flip-flop using the case statement. In
the Listing, rising_edge (VHDL) and posedge (Verilog) are predefined words called attributes. They
represent the positive edge of the clock (clk). If the positive edge is present, the attribute yields to true.
For VHDL, the clk has to be in std_logic to use this attribute. Other attributes are covered in Chapters
4, 6, and 7. Any of the four case statements can be replaced with others (VHDL) or default (Verilog).
For example:
LISTING 3.7 HDL Code for a Positive Edge-Triggered JK Flip-Flop Using the case Statement

5.4 The Loop Statement
Loop is a sequential statement that has to appear inside process inVHDL or inside always or initial in
Verilog. Loop is used to repeat theexecution of statements written inside its body. The number of
repetitionsis controlled by the range of an index parameter. The loop allows the codeto be compressed;
instead of writing a block of code as individual statements, it can be written as one general statement
that, if repeated, reproduces all statements in the block. There are several ways to construct aloop.
Some of those ways are discussed here.
⚫ For-Loop
The HDL general format for a For-Loop is:
EXAMPLE 1: FOR-LOOP: VERILOG
Verilog For-Loop
for (i = 0; i <= 2; i = i + 1)
begin
if (temp[i] == 1‟b1)
begin
result = result + 2**i;
end
end
statement1; statement2; ....
The index is i, the lower value is 0, the upper value is 2, and the stepis 1. All statements between the
for statement and end loop (VHDL) orend (Verilog) are executed until the index i goes out of range.
At the verybeginning of the loop, i takes the value of 0, and the statements if and result are executed
as:

if temp(0) = „1‟ then
result := result + 2 **0;
When the program encounters the end of the loop, it increments i by 1.If i is less than or equal to 2, the
loop is repeated; otherwise, the programexits the loop and executes statement1, statement2, and so on.
In VHDL,index i does not have to be declared, but in Verilog, it has to be declared.If the loop statement
is stated without range, the loop will run indefinitely.
⚫ While-Loop
The general format of the While-Loop is:
while (condition)
Statement1;
Statement2;
............
End
As long as the condition is true, all statements written before the end ofthe loop are executed.
Otherwise, the program exits the loop.
EXAMPLE 1: WHILE-LOOP: VERILOG
Verilog While-Loop
while (i < x)
begin
i = i + 1;
z = i * z;
end
In the above example, the condition is (i < x). As long as i is less thanx, i is incremented, and the
product i ◻ z (i multiplied by z) is calculatedand assigned to z.
⚫ Verilog repeat
In Verilog, the sequential statement repeat causes the execution ofstatements between its begin and
end to be repeated a fixed number oftimes; no condition is allowed in repeat.
VERILOG REPEAT
repeat (32)
begin
#100 i = i + 1;
end

In the above example, i is incremented 32 times with a delay of 100screen time units. This describes
a five-bit binary counter with a clock period of 100 screen time units.
Verilog forever
The statement forever in Verilog repeats the loop endlessly. One common use for forever is to
generate clocks in code-oriented test benches.
The following code describes a clock with a period of 20 screen time units:
initial
begin
Clk = 1‟b0;
forever #20 clk = ~clk;
end
5.5 BEHAVIORAL DESCRIPTION OF A 2x1 MULTIPLEXER WITH TRI-STATE

OUTPUT
Listing 3.5 shows the HDL description of the multiplexer using the IF-Else statement, and Listing 3.6
shows the HDL description with the Else-IF statement.
FIGURE: 2x1 Multiplexer. a) Logic symbol. b) Flow chart.

LISTING 3.5 HDL Description of a 2x1 Multiplexer Using IF-Else
LISTING 3.6 HDL Description of a 2x1 Multiplexer Using Else-IF

5.6 : Highlights of Structural description

5.7 : Organization of Structural Descriptions
Verilog has a large number of built-in gates. For example, the statement:
xor X1 (sum, a, b);
describes a two-input XOR gate. The inputs are a and b, and the output issum. X1 is an optional
identifier for the gate; the identifier can be omitted as:xor (sum, a, b);
Verilog has a complete list of built-in primitive gates. The output ofthe gate sum has to be listed before
the inputs a and b. Accordingly, theVerilog code in Listing 4.1 is a complete structural description of
a halfadder. Figure 4.1 shows a list of gates and their code in Verilog. As in structural VHDL, Verilog
statements are concurrent; the order of appearance ofstatements in the module is irrelevant.
LISTING 4.1 HDL Structural Description

EXAMPLE 1: HDL STRUCTURAL DESCRIPTION OF A HALF ADDER
The logic and symbol diagrams of the half adder have been shown before (see Figure 1.1).
Listing 4.2 shows the HDL structural code for thehalf adder. As mentioned before, VHDL
does not have built-in gates. Tospecify xor2 as an EXCLUSIVE-OR gate, bind (link) the
component xor2with an entity bearing the same name. By having the same name, all
information in the entity is visible to the component. The entity specifies therelationship
between I1, I2, and O1 as EXCLUSIVE-OR; accordingly, theinputs and output of xor2 behave
as EXCLUSIVE-OR. The same is donefor component and2; it is bound to the entity and2.
LISTING 4.2 HDL Code of Half Adder: Verilog
EXAMPLE 2: STRUCTURAL DESCRIPTION OF A FULL ADDER
In this example, a full adder (Listing 4.13) is built from two half adders(Listing 4.12). The full
adder adds (a + b + cin) to generate sum and carry. A half adder is used to add (a + b) to
generate sum1 and carry1. An-other half adder is used to add (sum1 + cin) to generate sum
and carry2.The carry of the summation (a + b + cin) is the logical OR of carry1and carry2.
Figures 4.6a and 4.6b show the logical symbol and diagram ofthis full adder, respectively.


5.7: STRUCTURAL DESCRIPTION OF A THREE-BITRIPPLE-CARRY ADDER
In this example, a three-bit ripple-carry adder is described. Then, inExample 4.7, this adder is
implemented to build a magnitude comparator.The logic diagram of the adder is as shown in
Figure 2.23 of Chapter 2.Listing 4.14 shows the structural description of the three-bit ripple-
carryadder.
LISTING 4.14 HDL Description of a Three-Bit Ripple-Carry Adder: Verilog
Inspection of the code in Listing 4.14 shows that there may be lag timebetween the steady
state of each of the adders and the carryout (cout).This lag time produces transient states before
the values of the sum andcarryout settle. For example, if the inputs to the adder are 101 and
001, andthe previous output of the adder is 1001, some transient states can be 0100and 1010
before the output settles at 0110. The appearance of these transient states is called hazards.
These transient states, however, have shortduration and may not be noticed.

Module 5 Questions
1. Illustrate the Structure of the HDL Behavioural description with necessary diagram and
programs.
2. Write the VHDL variable assignment statement.
3. What are sequential statements?
4. Write the IF statement syntax with expressions.
5. Write the IF Else statement syntax with expressions.
6. Write the Case statement syntax with expressions.
7. Write the Loop statement syntax with expressions.
8. Write the Verilog Behavioral descriptions of Mux (2:1).
9. Write the Structural descriptions of ripple carry adder
10. Write the flow diagram of organization of structural description.

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M5: To achieve Accreditation standards towards International education recognition.
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DIGITAL SYSTEM DESIGN USING VERILOG (IPCC)

Dr S Padmashree, Professor, Dept. of ECE, GSSSIETW, Mysuru.

Dept of ECE, GSSSIETW

M2: To impart Theoretical Knowledge, Practical Knowledge and Entrepreneurship Skills.

M3: Fostering culture of innovation and research for development of society.

M5: To provide industry standard certifications on skills to enhance students knowledge

Program Educational Objective’s

PEO 1: To inculcate students to excel in professional career and/or higher education by

PEO 3: To Produce Technically competent graduates with Ability to analyse, design,

PEO 4: To prepare the students to be able to exhibit professionalism, ethical attitude,

Dept of ECE, GSSSIETW

Engineering Graduates will be able to:

1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering

Program Specific Outcomes

Dept of ECE, GSSSIETW

Semester & Year: III Semester -ODD 2023

At the end of the course, the students will be able to:

SEE for IPCC

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning

Principles of Combinational Logic: Definition of combinational logic, Canonical forms,

Dept. of ECE, GSSSIETW, Mysuru Page 1

Dept. of ECE, GSSSIETW, Mysuru Page 2

Dept. of ECE, GSSSIETW, Mysuru Page 3

EX-OR Gate (Exclusive OR Gate)

EX-NOR Gate (Exclusive NOR Gate)

Dept. of ECE, GSSSIETW, Mysuru Page 4

1.2 Combinational Circuits

1.2.1 Definition of Combinational Logic

Figure 1.1: Combinational Logic Model

Dept. of ECE, GSSSIETW, Mysuru Page 5

Figure 1.2: General logic design sequence

Dept. of ECE, GSSSIETW, Mysuru Page 6

Input Variables Output Variable

The switching equations,

M1 = I2I3I4 + I1I3I4 + I1I2I4 + I1I2I3 + I1I2I3I4,

Dept. of ECE, GSSSIETW, Mysuru Page 7

Here SOP is f(X.Y) = X.Y' + X.Y

9. Canonical Product of Sums: A canonical product of sums is a complete set of

Here POS is F(X,Y) = (X+Y')

Dept. of ECE, GSSSIETW, Mysuru Page 8

1.2.3 Minterms and maxterms

For a three-variable expression, the minterms and maxterms are as follows

1.3 Canonical Forms

To place a SOP equation into canonical form using Boolean algebra,

1. Identify the missing variables in each AND term.

To place a POS equation into canonical form using Boolean algebra,

1. Identify the missing variables in each OR term.

Dept. of ECE, GSSSIETW, Mysuru Page 10

Dept. of ECE, GSSSIETW, Mysuru Page 11

1.4 Generation of Switching Equations from Truth Tables

Input Variables Output Variable

The minterm expression for the output variable, M, is

M = f(a, b, c, d) = a’bcd + ab’cd + abcd =∑(7, 11, 15)

The maxterm expression for the output variable, M, is

M = f(a, b, c, d) = (a+b+c+d) (a+b+c+d’) (a+b+c’+d) (a+b+c’+d’) (a+b’+c+d)

(a+b’+c’+d) (a’+b+c+d) (a’+b+c+d’) (a’+b+c’+d) (a’+b’+c+d)

=π(0, 1, 2, 3, 4, 5, 6, 8, 9, 10, 12, 13, 14)

Input Variables Output Variable

M1 = f(a, b, c) = a’b’c + a’bc’ + a’bc

Dept. of ECE, GSSSIETW, Mysuru Page 13

M2 = f(a, b, c) = a’b’c’ + a’b’c + ab’c’ +ab’c

M3 = f(a, b, c) = a’b’c’ + a’bc’ + ab’c’ + abc’

M4 = f(a, b, c) = a’bc + ab’c + abc’

Writing the same equations using decimal list notation, we get