EPC lab manual-1

Electronic Principles and Circuits Lab
IPCC (BEC303)
3rd SEMESTER, 2023
Prepared by
Bharathi R, Spoorthi Y & Nagashree R N,

Assistant Professor
Dept of ECE
GSSSIETW, Mysuru
VISION
"To foster professional level competence in all areas of Electronics and Communication Engineering and
to benchmark the Department as a centre for nurturing Women Engineers in the Country"
MISSION
M1: To impart value based Technical education and training.
M2: To impart Theoretical Knowledge, Practical Knowledge and Entrepreneurship Skills.
M3: Fostering culture of innovation and research for development of society.
M4: To sensitize the Students regarding Social, Moral and Professional ethics.
M5: To provide industry standard certifications on skills to enhance students knowledge make them
prepared for placements
Program Educational Objective’s
PEO 1: To inculcate students to excel in professional career and/or higher education by acquiring
knowledge in the field of Electronics and Communication.
PEO 2: To make the students capable of managing their profession based on existing as well as new
emerging technologies in the area of Electronics and Communication Engineering.
PEO 3: To Produce Technically competent graduates with Ability to analyse, design, develop, optimise
and implement Electronics and Communication systems.
PEO 4: To prepare the students to be able to exhibit professionalism, ethical attitude, communication
skills, team work in their profession and to adapt to current trends by engaging in life-long learning.
SYLLABUS
EXPERIMENT 1
Design and Test (i) Bridge Rectifier with Capacitor Input Filter
(ii) Zener Voltage Regulator
BRIDGE WAVE RECTIFIER WITH CAPACITOR INPUT FILTER

Aim: To design and test bridge rectifier with filter capacitor and observe output waveform.
Theory: The bridge rectifier circuit is essentially a full-wave rectifier circuit, using four diodes forming the four
arms of an electrical bridge. To one diagonal of the bridge, the ac voltage is applied through a transformer and
the rectified dc voltage is taken from the other diagonal of the bridge.
In the positive cycle of the ac voltage diodes D1 & D2 will be forward biased while D3 & D4 will be
reversed biased .The two diodes D1 & D2 conduct in series with the load. In the next half cycle, when polarity
of ac voltage reverses hence diodes D3 & D4 are in forward biased and diodes D1 & D2 will be reversed
biased. Now diodes D3 & D4 will conduct in series with the load. It is seen that in both cycles of the ac the load
current is flowing in the same direction, hence we get a full wave rectified output.
Circuit Diagram:
Fig: Bride wave rectifier without Filter
Dept. of ECE, GSSSIETW

Fig: Bride wave rectifier with Filter
Expected Waveform:
Fig: Expected Input & output waveforms

Simulation Procedure:
• Open MULTISIM Software.
• Click=> New => Design1
• Click save as in Desk Top rename the Design1 to your circuit name.
• Go to Component tool bar and select the components.
• Draw the above circuits using the components that are available in the tool bar and then save the
circuit.
• Double click AC_POWER set its value above mentioned.
• Click simulate button or press F5 key => RUN
• Then double click connected in the output of the Oscilloscope and measure input and output
waveforms.
• Then Change input Frequency and voltage, again measure and print the output waveforms.
Simulation Waveforms
Fig: Input & output waveforms for BWR without Fig: Input & output waveforms for BWR with
Filter Filter
1. What is Rectification? Why it is necessary?

2. What is a Rectifier? How many types of rectifiers are there?
3. Differences between HWR, FWR, BR.
4. Define efficiency? Write the theoretical efficiencies of half wave and Full wave rectifier & Bridge
Rectifier.
5. What is a Filter? Why it is required?
Exercise
1. For RL=15k, 20k, find ripple factor (γ) for FWR & Bridge Rectifier.
2. Compare ripple factor (γ) between FWR & Bridge Rectifier.
3. Change the capacitor value to 1000µF, Find out the efficiency (η).
4. Build a F.W.R Circuit to rectify a given AC signal of 15V, 50Hz. Measure γ. The γ is to be reduced to
0.01. Improve the Circuit. Find Regulation, efficiencies

ZENER VOLTAGE REGULATOR
Aim: To design voltage regulator using Zener diode and find the load and line regulation.
Theory: Zener diodes are a special kind of diode which permits current to flow in the forward direction. What
makes them different from other diodes is that Zener diodes will also allow current to flow in the reverse
direction when the voltage is above a certain value. This breakdown voltage is known as the Zener voltage. In a
standard diode, the Zener voltage is high, and the diode is permanently damaged if a reverse current above that
value is allowed to pass through it. Zener diodes are designed in a way where the Zener voltage is a much lower
value. There is a controlled breakdown which does not damage the diode when a reverse current above the
Zener voltage passes through a Zener diode.
In the forward bias direction, the Zener diode behaves like an ordinary silicon diode.
In the reverse bias direction, there is practically no reverse current flow until the breakdown voltage is reached.
When this occurs there is a sharp increase in reverse current. Varying amount of reverse current can pass
through the diode without damaging it. The breakdown voltage or zener voltage (V Z) across the diode remains
relatively constant. The maximum reverse current is limited, however, by the wattage rating of the diode
Avalanche Break down:When the diode is in the reverse bias condition, the width of the depletion region is
more. If both p-side and n-side of the diode are lightly doped, depletion region at the junction widens. In reverse
bias, the minority charge carrier current flows through junction. As the applied reverse voltage increases the
minority carriers acquire sufficient energy to collide with the carriers in the covalent bonds inside the depletion
region. As a result, the bond breaks and electron hole pairs are generated. The process becomes cumulative and
leads to the generation of a large number of charge carriers resulting in Avalanche Breakdown.
Zener Break down:If both p-side and n-side of the diode are heavily doped, depletion region at the junction
reduces compared to the width in normal doping. Applying a reverse bias causes a strong electric field get
applied across the device. As the reverse bias is increased, the Electric field becomes strong enough to rupture
covalent bonds and generate large number of charge carriers. Such sudden increase in the number of charge
carriers due to rupture of covalent bonds under the influence of strong electric field is termed as Zener
breakdown
Zener Diode as Voltage Regulator:The function of a regulator is to provide a constant output voltage to a load
connected in parallel with it in spite of the ripples in the supply voltage or the variation in the load current and
the zener diode will continue to regulate the voltage until the diodes current falls below the minimum IZ(min)
value in the reverse breakdown region. It permits current to flow in the forward direction as normal, but will
also allow it to flow in the reverse direction when the voltage is above a certain value - the breakdown voltage
known as the Zener voltage. The Zener diode specially made to have a reverse voltage breakdown at a specific
voltage. Its characteristics are otherwise very similar to common diodes. In breakdown the voltage across the
Zener diode is close to constant over a wide range of currents thus making it useful as a shunt voltage regulator.
The purpose of a voltage regulator is to maintain a constant voltage across a load regardless of variations in the
applied input voltage and variations in the load current. A typical Zener diode shunt regulator is shown in
Figure 3. The resistor is selected so that when the input voltage is at V IN(min) and the load current is at IL(max)
that the current through the Zener diode is at least Iz(min). Then for all other combinations of input voltage and
load current the Zener diode conducts the excess current thus maintaining a constant voltage across the load.
The Zener conducts the least current when the load current is the highest and it conducts the most current when
the load current is the lowest.
If there is no load resistance, shunt regulators can be used to dissipate total power through the series resistance
and the Zener diode. Shunt regulators have an inherent current limiting advantage under load fault conditions
because the series resistor limits excess current.

A Zener diode of break down voltage Vz is reverse connected to an input voltage source Vi across a load
resistance RL and a series resistor RS. The voltage across the zener will remain steady at its break down voltage
VZ for all the values of zener current IZ as long as the current remains in the break down region. Hence a
regulated DC output voltage V0 = VZ is obtained across RL, whenever the input voltage remains within a
minimum and maximum voltage.
Basically there are two types of regulations such as:
a) Line Regulation: In this type of regulation, series resistance and load resistance are fixed, only input voltage
is changing. Output voltage remains the same as long as the input voltage is maintained above a minimum
value.
b) Load Regulation: In this type of regulation, input voltage is fixed and the load resistance is varying. Output
volt remains same, as long as the load resistance is maintained above a minimum value.
Circuit Diagram:
Fig: Zener Diode as Voltage Regulator
Procedure
1. Set up the circuit using Multisim Software.

2. Note down output voltage by varying the input voltage from 0 V to 20 V in steps of 1 V. Plot line
regulation characteristics with Vi along x-axis and VO along y-axis. Calculate percentage line regulation using
the expression ΔVO/ΔVi.
3. Now Keep the input voltage at 10 V and keep varying the load resistor values from 1KΩ to 15KΩ in
steps of 1KΩ. Plot load regulation characteristics with RL along x-axis and VO along y-axis.
4. Measure the full load voltage VFL by setting Resistor to 15KΩ.
5. Remove the Resistor and measure the output voltage to get no-load voltage VNL.
6. Mark VNL and VFL on the load regulation characteristics and calculate load regulation as per the
equation,
Observation: (Line Regulation)

Vi Volts VO Volts
Expected graph (Line Regulation)
Load Regulation:
Vi =10V
RL (KΩ) VO Volts
Expected graph (Load Regulation)

Result: Series Voltage Regulator using Zener diode and power transistor is studied and line and load regulation
characteristics were plotted.
Line Regulation=_______%
Load Regulation=_______%
Viva Questions:
1. What is the difference between p-n Junction diode and zener diode?
Ans: A zener is designed to operate stably in reverse breakdown, which is designed to be at a low voltage,
between 3 volts and 200 volts. The breakdown voltage is specified as a voltage with a tolerance, such as 10
volts ±5%, which means the breakdown voltage or operating voltage will be between 9.5 volts and 10.5 volts. A
signal
diode or rectifier will have a high reverse breakdown, from 50 to 2000 volts, and is NOT designed to operate in
the breakdown region. So exceeding the reverse voltage may result in the device being damaged. In addition,
the breakdown voltage is specified as a minimum only. Forward characteristics are similar to both, although the
zener's forward characteristic is usually not specified, as the zener will never be used in that region. A signal
diode or rectifier has the forward voltage specified as a max voltage at one or more current levels.
2. What is break down voltage?
Ans: The breakdown voltage of a diode is the minimum reverse voltage to make the diode conduct in reverse.
3. What are the applications of Zener diode?
Ans: Zener diodes are widely used as voltage references and as shunt regulators to regulate the voltage across
small circuits.
4. What is cut-in-voltage?
Ans: The forward voltage, at which the current through the junction starts increasing rapidly, is called the knee
voltage or cut-in voltage. It is generally 0.6V for a Silicon diode.
5. What is voltage regulator?
Ans: A voltage regulator is an electronic circuit that provides a stable dc voltage independent of the load
current, temperature and ac line voltage variations.
6. What is the doping concentration in Zener diodes?

7. Can we use Zener diode as a switch?
8. What is PIV of Zener?
9. What will happen if P-N regions are heavily doped in Zener diode?
10. List the other Zener diodes with different breakdown voltages.

11. Is the breakdown region in Zener really destructible?
12. What is a zener diode ?
13. How the name of the Zener came?
14. What is cause of reverse breakdown ?
15. What is zener voltage ?
16. Write the Symbol for the Zener diode.
17. What are the differences between the PN junction diode and Zener diode fabrication?
18. What are the applications of Zener diode?
19. What are the different types of breakdowns in semiconductor junctions?
20. Compare Zener Breakdown and Avalanche breakdown?
21. What is the max value of voltage of Zener breakdown devices?
22. Zener diode is generally used in ________ biased condition. When Zener diode is forward biased, it acts as
a _________.

EXPERIMENT 2
Design and Test (i) Biased Clippers – a)Positive, b) Negative , c) Positive-Negative
(ii) Positive and Negative Clampers with and without Reference.
Aim: To design and test diode clipping (single/double ended) and clamping circuits (positive/negative).
Learning outcome: On completion of this experiment, students will be able to design and test diode clipping
(single/double ended) and clamping circuits (positive/negative).
CLIPPERS
Theory:
Clipper circuits are used to remove the portion of a time varying input signal without distorting the
remaining part of the input waveform. There are two general categories of clippers: Series clipper & Parallel
(shunt) clipper. The Series configuration is defined as one where the diode is in series with the load, whereas
the parallel configuration has the diode in a branch parallel to load.
The circuit is as shown above. During positive half cycle of the input voltage (Vin) till Vin < Vref the diode will
not conduct. But when Vin =Vref, the diode will conduct & Vo=Vd+Vr. Throughout the negative half cycle the
diode is reversed biased and act an open circuit. Therefore Vo =Vin , thus the waveform is as shown below in
fig2
Diode Shunt Clipping above reference voltage.

(Positive peak clipping)
Circuit Diagram:
Design:
Let the output voltage be clipped to say +2.8V i.e., V0 (max) = 2.8V
But V0 (max) = Vd + V ref
Vd = Diode forward voltage drop=0.7V
Vref=V0(max)-Vd=2.8-0.7=2.1V.
The value of resistor R is chosen to be R= Vi (max) – V0 (max) / Id
Choose, Diode forward current, Id = 1.5mA (Typically between 1mA to 10 mA)
Then R= (4 - 2.8) / 1.5mA = 800 Ω ≈ 1K Ω

Tabular Column:
Vref = 2.1V
Vi(p-p) V0+(p-p) Volts V0-(p-p) Volts
Volts
Expected Waveform:
Fig: Output waveform Fig: Transfer characteristics
Diode Shunt Clipping below reference voltage.

(Negative peak clipping)
Circuit Diagram:
Theory:
The circuit is as shown above. During positive half cycle the diode will be reversed biased, hence Vo
=Vin. Thus entire positive half cycle is reproduced as it is, when Vin<Vref, the diode becomes forward biased
& hence Vo= - (Vr+Vd).
Design:
Let the output voltage be clipped to say -2.8V i.e V0(min) = -2.8V
But V0 (min) = - (Vd + V ref )

-Vref =V0(min) + Vd = -2.8 + 0.7= -2.1V.
The value of resistor R is chosen to be R= Vi (max) – V0 (min) / Id
Choose Diode forward current, Id = 1.5mA (Typically between 1mA to 10 mA)
Then R= (-4 + 2.8) / -1.5mA = 800 Ω ≈ 1K Ω
Tabular Column: Vref = - 2.1V

Volts
Expected Waveform:
Fig: output waveform Fig: Transfer characteristics
Diode Series Clipping above reference voltage

(Positive peak clipping)
Circuit Diagram:
Design:
Let the output voltage be clipped to say +2.0V i.e. V0 (max) = V ref = +2.0V
The value of resistor R is chosen to be R= Vi (max) – V0 (max) /Id
Choose Diode forward current, Id = 2mA (Typically between 1mA to 10 mA)
Then R= (4 - 2) / 2mA = 1K Ω

Tabular Column: Vref = 2V
Volts
Expected Waveform:
Fig: Output waveform Fig: Transfer characteristic
DIODE SERIES CLIPPING below reference voltage

(Negative peak clipping)
Circuit Diagram:
Design:
Let the output voltage be clipped to say -2.0V i.e V0(min) = V ref = -2.0V
The value of resistor R is chosen to be R= (Vi (max) + V0 (min) ) / Id
Then R= (4 + 2) / 6mA = 1K Ω

Tabular Column: Vref = -2V
Volts
Expected Waveform:
Fig: Output waveform Fig: Transfer characteristic

NOTE: By changing the polarities of Vref in each of the above circuits, we obtain peak detection circuits
instead of peak clipping.
i.e. Positive peak clipper becomes negative peak detection circuit also
Negative peak clipper becomes positive peak detection circuit.
Clipping at two Independent Levels
Circuit Diagram:
Design:
To obtain a slice of input voltage between 1V and 3.5V
Let Vref1 > Vref2
Since V0 (max) = 3.5V
But V0 (max) = Vd + V ref1
Vref1=V0(max)-Vd = 3.5-0.7=2.8V.

Since V0(min) = 1V
But V0 (min) = Vref2 - V d
Vref2=V0(min)+Vd=1 .0 +0.7=1.7V.
The value of resistor R is chosen to be R= (Vi (max) – V0 (max)) / Id
Then R= (4 – 3.5) / 1mA = 500 Ω ≈ 470Ω.
Expected Waveform:
Double Ended Clipper (Symmetrical square wave generator)

Circuit Diagram:
Design:
To generate a symmetrical square wave of ±3V
i.e. V0 (max) = +3V and V0 (min) = -3V
But V0 (max) = Vd + V ref1
Vref1=V0(max)-Vd=3.0 – 0.7=2.3V.
But V0 (min) = Vd + V ref2
Vref2=V0(min) - Vd=3.0 – 0.7=2.3V.
The value of resistor R is chosen to be R= (Vi (max) – V0 (max) ) / Id
Then R= (4 - 3) / 1mA = 1K Ω.

Expected Waveform:
Procedure: (Same for all the clipper circuits)

1).Rig up the circuit as shown in the circuit diagrams.
2).Apply a sinusoidal signal of 1 KHz and amplitude of 8Vp-p (Peak amplitude should be greater than clipping
level) at input Vi.
3).Observe output signal on the CRO and verify it with the given waveform.
4).Apply Vi and Vo to the X and Y channel of the CRO respectively and transfer characteristics are obtained
using X-Y mode on the CRO.
Result: The clipping circuits are designed and output waveforms are verified.
VIVA QUESTIONS:
1. What is a Clipper?
2. List the types of clippers?
3. List 6 Applications of Clippers.
4. What do you mean by double ended clipper?
5. What is biased clipper?
Exercise:
1. You are given Sine signal of 1 KHz, 2V. Transmit only the +ve half cycle/ Transmit only –ve half cycle.
Now change the Ckt to give output of 1V both at +ve & -ve Cycles.
2. Design and Test suitable Clipper Ckts. To get the following outputs using Sine wave of 5V p-p, 2 KHz
Signal.
a) To transmit up to 1.5V in the +ve half cycle, suppressing the –Ve half
b) To transmit up to 1.5V in the -ve half cycle, suppressing the +Ve half
c) To transmit 1.5V on the top and 3V at the bottom.

CLAMPER CIRCUITS
Aim: To Design and test the Clamping circuits for specific needs Positive Clamping / Negative Clamping.
Learning outcome: On completion of this experiment, students will be able to analyze design clamping circuits
like Negative Clamper and Positive Clamper.
Theory:
A Clamper is a network that shifts a waveform to a different dc level without changing the appearance of the
applied signal.
The circuits which add a dc voltage to the ac input signal are called clamper circuits. The clamper circuits are
also called as DC restorer or DC inserter circuits .Clamper is classified into two types: Negative clamper and
positive clamper.
Negative Clamper
Circuit Diagram:
Design:
To design a Clamper circuit to clamp negative peak of the output voltage at 3V,
We have Vo (max) = Vref + Vd = 3V
Vref = Vo (max) - Vd
To Clamp Positive peak at +3V, Vref = 3 - 0.7 = 2.3V
Given Frequency = 1 KHz, T = 1 / f = 1ms.
Choose RC >> T (so that tilt in the waveform is negligible, ie, C does not discharge)
Let RC = 10T = 10 X 1ms = 10ms
Choose C = 1µF, R = 10ms/1µ = 10KΩ
Tabular Column: Vref = 2.3V
Vi(P-P)Volts Vo+(P-P) Volts Vo-(P-P) Volts

Expected Waveform:
Fig: Input & output waveform
Positive Clamping
Circuit Diagram:
Design:
To design a clamper circuit to clamp positive peak at 3V.
We have Vo (min) = - (Vref + Vd)
Vref = -Vo(min) + Vd
Vref = -3 + 0.7 = -2.3V
Given Frequency = 1 KHz, T = 1ms.
Choose RC >> T (so that C does not discharge during positive half cycle )
Let RC = 10T = 10ms
Let C = 1 µF, R = 10ms/1 µ = 10KΩ
Tabular Column: Vref = -2.3V
Vi(P-P)Volts Vo+(P-P) Volts Vo-(P-P) Volts

Expected Waveform:
Fig: Input & output waveform
Procedure: (Same for both Circuits)

1) Rig up the circuit as shown in the circuit diagram.
2) Input sinusoidal signal of 1 KHz Frequency and amplitude of 8VP-P is applied (Peak amplitude of input
must be greater than clamping level).
3) Display the output on CRO & Compare it with the given waveform.
4) Increase the input further and note that the output peak is clamped to the desired level.
5) For the same ckt, give a square wave input & compare it with the given waveforms.
6) Make Vref = 0V and observe that the corresponding peak is clamped to ±0.7V.
Result: Clamped waveform at desired level is obtained and clamping circuits are studied.
Viva Questions:
1. What is a Clamper?
2. List the types of clampers?
3. List 3 applications of Clamper.
Exercise:
1. Obtain Circuits to get the following. Using Sine wave of 3V Amplitude & 1KHz frequency.
a).Clamp the Signal at 0V
b).Clamp the Signal at 5V
c).Clamp the Signal at -5V

EXPERIMENT- 3
Plot the transfer and drain characteristics of a JFET and calculate its drain resistance,
mutual conductance and amplification factor.
Aim:
 To plot Drain Characteristics and Transfer Characteristics of a Junction Field Effect Transistor (JFET).
 To calculate the drain resistance, trans-conductance and amplification factor.
Learning outcome: On completion of this experiment, students will be able to understand the Characteristic
behavior of JFET
Theory:
A JFET is a semiconductor with 3 terminals, available either in N-channel or P-channel types. The transfer
characteristic for a JFET can be determined experimentally, keeping drain-source voltage, VDS constant and
determining drain current, ID for various values of gate-source voltage, VGS. The curve is plotted between
gate-source voltage, VGS and drain current, ID.The curve drawn between drain current Ip and drain-source
voltage VDS with gate-to source voltage VGS as the parameter is called the drain or output characteristic.
The basic circuit diagram for studying drain and transfer characteristics is shown in the circuit diagram.
1. Drain characteristics are obtained between the drain to source voltage (VDS) and drain current (ID)
taking gate to source voltage (VGS) as the constant.
2. Transfer characteristics are obtained between the gate to source voltage (VGS) and drain current (ID)
taking drain to source voltage (VDS) as the constant
Circuit Diagram:

Fig: Circuit for studying of Characteristics of JFET
Characteristic Graph:
Fig: JFET Transfer (output) Characteristics Fig: JFET Drain (Input) Characteristics
circuit.
• Click on Simulate and select Analyses and Simulation, new window opens, there select DC Sweep
and set the values as shown in Simulation settings.
• Then save and Click simulate button or press F5 key => RUN
Simulation settings & graph:

(i) Transfer characteristics:

(ii) Drain Characteristics :

Calculations from Graph:
1. Drain dynamic resistance:

Construct a Triangle on one of the output characteristic for a particular VGS in the active region and find
and find ΔVDS and ΔID,
Drain dynamic resistance, at constant VGS
2. Transconductance:
Construct a Triangle on one of the Transfer characteristics for a particular VDS and find ΔVGS and ΔID.
Transconductance, at constant VDS.
3. Amplification Factor:
Amplification Factor,
Result: Input and output characteristics are observed for the given JFET. Drain dynamic resistance,
Transconductance and amplification factor are calculated.
Viva Questions:
1. What are the advantages of JFET over BJT?
2. Why input resistance in FET amplifier is more than the BJT amplifier?
3. What is a uni-polar device?
4. What is pinch off voltage?
5. What are various FETs?
6. What is Enhancement mode and Depletion mode?
7. Draw the Small signal Equivalent circuit of JFET?
8. List 5 Applications of JFETs.

EXPERIMENT- 4
Plot the transfer and drain characteristics of n-channel MOSFET and calculate its
parameters, namely; drain resistance, mutual conductance and amplification factor
Aim:
 To plot Drain Characteristics and Transfer Characteristics of a n-channel MOSFET(Metal Oxide
Semiconductor Field Effect Transistor).
 To calculate the drain resistance, mutual conductance and amplification factor.
Learning outcome: On completion of this experiment, students will be able to understand the Characteristic
behavior of a n-channel MOSFET.
Theory:
MOSFETs are tri-terminal, unipolar, voltage-controlled, high input impedance devices which form an integral
part of vast variety of electronic circuits. These devices can be classified into two types viz., depletion-type and
enhancement-type, depending on whether they possess a channel in their default state or no, respectively. Figure
below shows the transfer characteristics of n-channel Enhancement-type MOSFETs. From this, it is evident
that the current through the device will be zero until the VGS exceeds the value of threshold voltage VT. This is
because under this state, the device will be void of channel which will be connecting the drain and the source
terminals.
Under this condition, even an increase in VDS will result in no current flow. As a result this state represents
nothing but the cut-off region of MOSFET’s operation. Next, once VGS crosses VT, the current through the
device increases with an increase in IDS initially (Ohmic region) and then saturates to a value as determined by
the VGS (saturation region of operation) i.e. as VGS increases, even the saturation current flowing through the
device also increases. The drain characteristics of the n channel MOSFET are plotted in between the output
current & the VDS which is known as Drain to source voltage VDS. As we can see in the diagram, for different
Vgs values, we plot the current values. So we can see different plots of drain current in the diagram like lowest
Vgs value, maximum Vgs values, etc. In the above characteristics, the current will stay constant after some
drain voltage. Therefore, minimum voltage for the drain to source is required to work MOSFET. So, when we
increase ‘Vgs’ then the channel width will be increased & which results in more ID (drain current).
Circuit Diagram:

Fig: Circuit for studying of Characteristics of n-channel MOSFET
Characteristic Graph:
Fig: MOSFET Transfer (output) Characteristics Fig: MOSFET Drain (Input) Characteristics

circuit.
• Click on Simulate and select Analyses and Simulation, new window opens, there select DC Sweep
and set the values as shown in Simulation settings.
Simulation settings & graph:

Transfer characteristics

Drain Characteristics:

Calculations from Graph:
1. Drain dynamic resistance:

Construct a Triangle on one of the output characteristic for a particular V GS in the active region and find
and find ΔVDS and ΔID,
Drain dynamic resistance, at constant VGS
2. Transconductance:
Construct a Triangle on one of the Transfer characteristics for a particular VDS and find ΔVGS and ΔID.
Transconductance, at constant VDS.
3. Amplification Factor:
Amplification Factor,
Result: transfer and drain characteristics of n-channel MOSFET are observed. Drain dynamic resistance,
Transconductance and amplification factor are calculated.
Viva Questions:
1. What are the terminals the MOSFET

2. Whether the MOSFET is voltage controlled or current controlled device? Why?
3. List the 5 advantages of the MOSFET over JFET & BJT.
4. Describe the different types of MOSFET.
5. What do you mean by the Depletion mode and Enhancement mode in the MOSFET?
6. What are the regions of a MOSFET?

EXPERIMENT-5
Design and test Emitter Follower
Aim: Design and test Emitter Follower Circuit.
Learning outcome: On completion of this experiment, students will be able to understand the definition of
Emitter follower, its design aspects and will be able to verify its behavior in terms of its waveforms.
Theory: Emitter follower is a case of negative current feedback circuit. This is mostly used as a last stage
amplifier in signal generator circuits. The important features of Emitter Follower are − It has high input
impedance. It has low output impedance. It is not always possible to directly couple the emitter follower,
common collector buffer. When this is the case, it is necessary to add a few additional electronic components:
coupling capacitors and bias resistors to the circuit.
The emitter follower circuit is particularly useful for applications where high input impedance is required.
Offering a high input impedance and low output impedance it is does not load circuits that may only have a
small output capability, or those circuits like oscillators that need a high impedance load to ensure the optimum
stability, etc.
Design:
VCC=12V; IC=10mA; AV=1; VB=0.7V; β=100; RL=600Ω
Choose
And
Choose

F=100Hz
Circuit Diagram:
Fig: Emitter Follower Circuit

Waveforms:
 Open MULTISIM Software.
 Click=> New => Design1
 Click on save as in Desk Top rename the Design1 to your circuit name.
 Go to Component tool bar and select the components.
 Draw the above circuits using the components that are available in the tool bar and then save the circuit.
 Click simulate button or press F5 key => RUN
 Click on Oscillator icon to view waveforms.
VIVA QUESTIONS:
1. What is an emitter follower? What are the applications of emitter follower?
2. What are Cascade and Cascode connections?
3. List the 4 advantages of Emitter Follower amplifier.
4. List the 4 disadvantages of Emitter Follower amplifier.
5. What is the voltage gain of emitter follower amplifier?

EXPERIMENT 6
Design and plot the frequency response of Common Source JFET amplifier
Aim:
To design, setup and plot the frequency response of Common Source JFET amplifier and obtain the
bandwidth.
Learning outcome: On completion of this experiment, students will be able to design and analyze Common
Source JFET amplifier.
Theory:
Common source FET configuration is probably the most widely used of all the FET circuit configurations for
many applications, providing a high level of all round performance.
The common source circuit provides a medium input and output impedance levels. Both current and voltage
gain can be described as medium, but the output is the inverse of the input, i.e. 180° phase change. This
provides a good overall performance and as such it is often thought of as the most widely used configuration
The input signal enters via C1 - this capacitor ensures that the gate is not affected by any DC voltage coming
from the previous stages. The resistor RG holds the gate at ground potential. The resistor RS develops a voltage
across it holding the source above the ground potential. CE acts as a bypass capacitor to provide additional gain
at AC.
The resistor RD develops the output voltage across it, and C2 couples the AC to the next stage whilst blocking
the DC
Circuit Diagram:

Design:
IDSS=12.5mA, V0=-4.4V, gm=3.2mV
Let gain=10
AV=- gm*RD
RD= - AV/ gm= -10/3.2m=3.12KΩ
Choose RD=3.3KΩ
Let RG=2MΩ
ID= IDSS[1-VGS/ VD], VGS=2.5V
ID=12.5[1-2.5/-4.4]=2.3mA
IS= ID=2.3mA
VGS= IS* RS
RS= VGS/ IS=2.5/2.3m=1.08KΩ
Choose RS=1KΩ
• Draw the above circuits using the components that are available in the tool bar and then save the circuit.
• Click on Simulate and select Analyses and Simulation, new window opens, there select DC Sweep and set the
values as shown in Simulation settings.
Simulation settings for Waveform graph:
 Click on RUN.

Simulation settings for frequency response plot:

Expected Graph:
Fig: Frequency response for Common Source JFET amplifier
Frequency response graph:
Result:
Lower Cut-off Frequency, fL =_______
Upper Cut-off Frequency, fU =______
Bandwidth, BW = fU – fL =_______
Viva Questions:
1. What is FET?
2. What is the function of Bypass Capacitor & Coupling Capacitor in an amplifier circuit?
3. What is gain?
4. What is frequency response?
5. What do you mean by Decibel?
6. What do you mean by Bandwidth?
7. Why FET is called voltage controlled device and BJT as current controlled device?
8. What is the ideal input impedance and output impedance of an FET?
9. Why the bandwidth is measured at 3db point?
10. What is semi-log graph?

EXPERIMENT 7
Test the Op-amp Comparator with zero and non-zero reference and obtain the Hysteresis
curve.
Aim: To test the Op-amp Comparator with zero and non-zero reference and obtain the Hysteresis curve.
Learning outcome: On completion of this experiment, students will be able to design and test Comparators
with different references and analyze their Hysteresis curve.
Theory: The Op-amp comparator compares one analogue voltage level with another analogue voltage level,
or some preset reference voltage, VREF and produces an output signal based on this voltage comparison. In other
words, the op-amp voltage comparator compares the magnitudes of two voltage inputs and determines which is
the larger of the two.
We have 3 types:
1. Comparators with Zero Reference
2. Comparators with Nonzero References
3. Comparators with Hysteresis.
Comparators with Zero Reference: The simplest way to build a comparator is to connect an op amp without
feedback resistors, as shown in Fig. Because of the high open-loop voltage gain, a positive input voltage
produces positive saturation, and a negative input voltage produces negative saturation. The comparator of Fig.
a is called a zero-crossing detector because the output voltage ideally switches from low to high or vice versa
whenever the input voltage crosses zero.
Comparators with Nonzero References: In some applications, a threshold voltage different from zero may be
preferred. By biasing either input, we can change the threshold voltage as needed.
From Fig, when Vin is greater than Vref, the differential input voltage is positive and the output voltage is high.
When Vin is less than Vref, the differential input voltage is negative and the output voltage is low.

Comparators with Hysteresis: If the input to a comparator contains a large amount of noise, the output will be
erratic when Vin is near the trip point. One way to reduce the effect of noise is by using a comparator with
positive feedback. The positive feedback produces two separate trip points that prevent a noisy input from
producing false transitions.
A comparator using positive feedback like this is usually called a Schmitt trigger. Here the input voltage is
applied to the inverting input. Because the feedback voltage at the non-inverting input is aiding the input
voltage, the feedback is positive.
Circuit Diagram:
1. Comparators with Zero Reference:

Comparators with Nonzero References:
Positive Vref:

Negative Vref:
Comparators with Hysteresis(Schmitt Trigger):

EXPERIMENT 8
Design and test Precision Half wave and full wave rectifiers using Op-amp
Aim: To design and Precision Half and full wave rectifier.
Learning outcome: On completion of this experiment, students will be able to design and analyze Precision
Half and full wave rectifier.
Theory: A rectifier is a circuit that converts alternating current (AC) to Direct current (DC). An alternating
current always changes its direction over time, but the direct current flows continuously in one direction. In a
typical rectifier circuit, we use diodes to rectify AC to DC. But this rectification method can only be used if the
input voltage to the circuit is greater than the forward voltage of the diode which is typically 0.7V.
To overcome this issue, the Precision Rectifier Circuit was introduced. The precision rectifier is another
rectifier that converts AC to DC, but in a precision rectifier we use an op-amp to compensate for the voltage
drop across the diode, that is why we are not losing the 0.6V or 0.7V voltage drop across the diode, also the
circuit can be constructed to have some gain at the output of the amplifier as well.
Precision HWR working: When the input is greater than zero, D1 is off, and D2 is on, so the output is zero
because the other end of R2 is connected to the virtual ground and there is no current through R2.
On other hand, when the input is less than zero, D1 is on and D2 is off, so the output is like the input with an
amplification of -R2/R1.
Precision FWR working: The first op amp, U1, forms a precision rectifier as before, although the diodes are
reversed. This means that the output at va will be zero for negative inputs and –vi for positive inputs.
The second op amp, U2 forms an inverting summing amplifier with an output voltage given by the equations
below.
Circuit Diagram:
D2

Design:
To produce 2V peak output with input of 0.5V peak voltage and frequency f=1MHz.
I1=500µA (adequate diode current)
=1KΩ (standard value)
=4KΩ (use 3.9KΩ standard value)
=1KΩ || 3.9KΩ
=760Ω (Use 820Ω standard value)
Expected Waveforms:
Fig: Expected Waveforms for Precision Half-wave rectifiers

Simulation Waveforms:
Transfer Characteristic:
Circuit Diagram:
U1
U2

Fig: Full wave Precision Rectifier
Design:
To produce 2V peak output
Input =0.5V, frequency f=1MHz
Let =500µA (Adequate diode current)
=1KΩ (standard value)
= =2KΩ (use 2.2KΩ standard value)
=1KΩ || 2KΩ
=670Ω (use 680Ω standard value)
For output to be 2V when input is 0.5V,

1KΩ
=4KΩ (use 3.9KΩ standard value)
=1KΩ || 1KΩ|| 3.9KΩ
=443Ω (use 470Ω standard value)

Expected Graph:
Fig: Expected Waveforms for Precision Full-wave rectifiers

Simulation Waveforms:
Transfer Characteristic:
Result: Precision Half and full wave rectifier circuits were designed and tested for small values of input voltage
and found to be working well.

Viva Questions:
1. What is Rectification? Why it is necessary?

2. What is a Rectifier? How many types of rectifiers are there?
3. What is precision rectifier? What is advantage of Precision rectifier over normal rectifier?
4. Explain the working of Precision HWR & Precision FWR.
5. What is a ripple factor?

EXPERIMENT 9
Design and test RC Phase shift oscillator
Aim: To design and simulate RC-phase shift Oscillator using Op-Amp.
Learning outcome: On completion of this experiment, students will be able to design and analyze RC-phase
shift Oscillator.
Theory:
An electronic oscillator is an electronic circuit that produces a periodic, oscillating electronic signal, often
a sine wave or a square wave. The most common form of linear oscillator is an electronic amplifier such as
a transistor or operational amplifier connected in a feedback loop with its output fed back into its input through
a frequency selective electronic filter to provide positive feedback. When the power supply to the amplifier is
first switched on, electronic noise in the circuit provides a non-zero signal to get oscillations started. The noise
travels around the loop and is amplified and filtered until very quickly it converges on a sine wave at a single
frequency.
RC phase shift oscillator:

R-C phase shift oscillator using op-amp uses an op-amp in inverting amplifier mode. Thus it introduces the
phase shift of 180° between input and output. The feedback network consists of 3 RC sections each producing
60° phase shift. Such an RC phase shift oscillator using op-amp.
The output of the amplifier is given to the feedback network. The output of the feedback network drives the
amplifier. The total phase shift around a loop is 180° of the amplifier and 180° due to 3 RC sections, thus 360°.
This satisfies the required condition for positive feedback and circuit works as an oscillator.
Design:
Choose C=0.1μF
Let, fo=500Hz
Choose

Circuit Diagram:
Simulation Circuit:
Expected Waveform :

Simulation Waveform:
Waveforms showing all phase-shifts
00(or 3600)
Phase Shift
600 Phase Shift
1200 Phase Shift
1800 Phase Shift
Observation:
Theoretical value f0 in Hz Practical value f0 in Hz

500 Hz
Result: The RC phase-shift Oscillator was designed and studied. The theoretical and practical frequency of
oscillations was found to be almost matching.
Viva Questions:
1. What is an Oscillator?
2. Define Feedback Circuit of Oscillator.
3. Explain the working of RC phase-shift Oscillator.
4. What is the function of Bypass Capacitor & Coupling Capacitor in an amplifier circuit?
5. State Barkaushen Criteria for Oscillators.

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Electronic Principles and Circuits Lab

3rd SEMESTER, 2023

Bharathi R, Spoorthi Y & Nagashree R N,

M2: To impart Theoretical Knowledge, Practical Knowledge and Entrepreneurship Skills.

M3: Fostering culture of innovation and research for development of society.

Program Educational Objective’s

BRIDGE WAVE RECTIFIER WITH CAPACITOR INPUT FILTER

Fig: Bride wave rectifier without Filter

Dept. of ECE, GSSSIETW

Fig: Expected Input & output waveforms

Dept. of ECE, GSSSIETW

1. What is Rectification? Why it is necessary?

Dept. of ECE, GSSSIETW

Dept. of ECE, GSSSIETW

Fig: Zener Diode as Voltage Regulator

Dept. of ECE, GSSSIETW

Observation: (Line Regulation)

Expected graph (Line Regulation)

Expected graph (Load Regulation)

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6. What is the doping concentration in Zener diodes?

Dept. of ECE, GSSSIETW

Dept. of ECE, GSSSIETW

Diode Shunt Clipping above reference voltage.

Dept. of ECE, GSSSIETW

Fig: Output waveform Fig: Transfer characteristics

Diode Shunt Clipping below reference voltage.

Dept. of ECE, GSSSIETW

Tabular Column: Vref = - 2.1V

Fig: output waveform Fig: Transfer characteristics

Diode Series Clipping above reference voltage

Dept. of ECE, GSSSIETW

Fig: Output waveform Fig: Transfer characteristic

DIODE SERIES CLIPPING below reference voltage

Dept. of ECE, GSSSIETW

Fig: Output waveform Fig: Transfer characteristic

Dept. of ECE, GSSSIETW

Fig: Output waveform Fig: Transfer characteristics

Double Ended Clipper (Symmetrical square wave generator)

Dept. of ECE, GSSSIETW

Fig: Output waveform Fig: Transfer characteristics

Procedure: (Same for all the clipper circuits)

Dept. of ECE, GSSSIETW

Dept. of ECE, GSSSIETW

Fig: Input & output waveform

Tabular Column: Vref = -2.3V

Vi(P-P)Volts Vo+(P-P) Volts Vo-(P-P) Volts

Dept. of ECE, GSSSIETW

Fig: Input & output waveform

Procedure: (Same for both Circuits)

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Dept. of ECE, GSSSIETW

Simulation settings & graph:

Dept. of ECE, GSSSIETW

Dept. of ECE, GSSSIETW

1. Drain dynamic resistance:

Dept. of ECE, GSSSIETW

Dept. of ECE, GSSSIETW

Dept. of ECE, GSSSIETW

Simulation settings & graph:

Dept. of ECE, GSSSIETW

Dept. of ECE, GSSSIETW

1. Drain dynamic resistance:

1. What are the terminals the MOSFET