2022 IEEE Microwaves, Antennas, and Propagation Conference (MAPCON)

GaN-based Class-F Power Amplifier for 5G

Applications
Gaurav Bhargava∗ , Pinak Kumar Rath† , and Shubhankar Majumdar‡
Department of Electronics and Communication Engineering, National Institute of Technology Meghalaya
Shillong, India - 793003
Email: ∗ gauravbhargav87@gmail.com, † rathpinak@gmail.com, ‡ shub@nitm.ac.in

Abstract—In this paper, the class F power amplifier is pro-
posed and developed for 5G applications. The design methods
include simulation followed by layout design and fabrication.
Then, 1 tone Harmonic balance analysis of the fabricated
2022 IEEE Microwaves, Antennas, and Propagation Conference (MAPCON) | 978-1-6654-5203-8/22/$31.00 ©2022 IEEE | DOI: 10.1109/MAPCON56011.2022.10047615
performed to analyze the error performance of simulated and
measured scattering parameters [5]. A class-F/ inverse class-
F load circuit design approach has been devised in [6], which

structure of PA is performed to obtain the simulation and
measurement results of PAE 79.251% and 12.194%, Gain of
16.54 dB and 13.03 dB, ACP of - 28.09 dBc and - 22.039 dBc,
and 3rd and 5th order harmonics distortion of -20.5 dBc and
-48.9 dBc and -18.4 dBc and -45.2 dBc respectively. Also, the
study of MAE (in %) performance for Pout, gain, PAE, ACP,
3rd and 5th harmonic distortion having values 0.0064, 0.0023,
0.0072, 0.00605, 0.0021, and 0.0037 respectively is analyzed and
verified.
Index Terms—GaN-HEMT, Power amplifier, Intermodula-
tion distortion
I. I NTRODUCTION
As wireless communication standards evolve, Power am-
plifiers (PA) will be necessary to function efficiently at
higher frequencies like 5G frequency mid-range n78 band
[1]. Non-overlapping mode between drain voltage and drain
current is required to design high-efficiency PAs. These PAs
are mainly categorized into two modes: Switched mode and
harmonic-tuned mode [2], [3] [4].
Harmonic-tuned PAs, such as Class-F, have become the
promising contenders for high operation frequencies, often
above 2 GHz, due to their greater gain/power, improved
linearizability, and lack of intrinsic frequency limits present
in their switch-mode counterparts. Utilizing a harmonic-
tuned technique to enhance efficiency demands accurate
harmonic termination manipulation beyond the third order.
It’s also important to pay close attention to the transistor
parasitics, whose influence on PA design increases with
frequency and power.
A parasitic compensation unit and a harmonic control circuit
(HCC) are often used in a simple Class F PA structure,
which is both complicated and challenging to implement.
This could result in inconsistencies in high-frequency design
features using packaged devices and harmonic regulation
above the third harmonic. This study aims to provide a new
systematical technique for building multi-harmonically tuned
Class-F PAs. Because the circuit at the output side is based
on a high-order, transmission-line (TL) based low-pass filter
architecture, no parasitic compensation or HCC is required.
The GaAs pHEMT device level modeling and optimization is
includes factors such as drain-source capacitance and bond-
ing wire inductance. At 5.8 GHz, a class-F amplifier using
an AlGaN–GaN HEMT was developed using the proposed
technique. The constructed class-F amplifier demonstrated
outstanding efficiency, with a maximum drain efficiency of
79.9%, a maximum power-added efficiency (PAE) of 71.4
percent, and an output power (Pout) of up to 33.4 dBm at
5.86 GHz. Using a packaged gallium nitride high electron
mobility transistor (GaN-HEMT), a Class F amplifier was
designed, manufactured, and tested [7]. With a 16.5 W output
power, the amplifier offers a peak PAE of 85%. A broadband
Radio frequency (RF), PA in” continuous class-F” mode,
which is highly efficient, is constructed [8]. The bandwidth
between 0.55GHz and 1.1GHz is an octave, resulting in a
PA with a DE of 74% at power at the output of 10.5W. This
PA was constructed using a commercially available 10W
GaN HEMT transistor. A logical way of optimum matching
networks is to order n=4 [9]. Iterative approaches are used
in previous solutions. Examples of direct explanations of
the matching network elements are provided, as well as the
insertion of an ideal transformer. When properly synthesized,
this matching network may load the packaged GaN transistor
with the appropriate fundamental and harmonic impedance
up to the fourth order. A highly efficient compact Class-F
PA is accomplished using the suggested technology, with
obtained results of 66 percent PAE and 10 W power at 3
GHz at 3 dB gain compression.
The structure of the work is organized as follows: Section
II describes the design methods with simulation and layout
analysis of the proposed PA structure. Section III includes
the fabrication steps and testing procedure. Section IV dis-
cusses the results obtained, and Section V summarizes the
paper.
II. D ESIGN METHODOLOGY
In this, a Cree CG2H40010F 10 W GaN HEMT device is
utilized to design PA on an FR4 substrate with a dielectric of
4.4, a height of 1.5 mm, and a loss tangent of 0.019. Because
the output matching network (OMN) is directly related to the
package, the parasitic network must be dealt with carelessly

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 2022 IEEE Microwaves, Antennas, and Propagation Conference (MAPCON)

in the actual PA design. Harmonic tuning is achieved up to
the fifth order in this PA design.
• Before doing anything, we must fix the quiescent bias
point needed for our application [10]. The gate voltage
Vgs of the device undergoes sweep from -4.8V to 0 V
and drain voltage Vds having sweep from 0V to 70V to
perform DC bias simulation. For Class AB bias points,
Vds = 28V and Vgs = -2.7 V were chosen towards the
saturation point.
• The Bias network will be created after the FET Curve
Tracer has been completed [11]. It will require bypass
capacitors to avoid transients and blocking purposes,
as well as an RF Choke, because GaN HEMTs have a
unique bias method and work at high frequencies. Be-
cause of the high operating frequency, it uses RF Choke
serving a high-impedance quarter-wave transformer line
[12].
• A stability network of a parallel RC network of a 10-
ohm resistor and 30 pF capacitor was put in the gate
side of the device to make the device and the entire PA
unconditionally stable.
The motive is to provide proper harmonic terminations,
improve efficiency, and perform wave shaping to produce
a non-overlapping voltage and current waveform, i.e., half
sinusoidal current waveform and a square waveform for the
drain voltage.
The Fourier transform can be used to calculate the drain
voltage and drain current, which is given by
∞
!
1 4 X sin ((2n − 1)ωo t)
VD (θ) = VDD + (1)
2 π n=1 2n + 1
The idealized optimum Class F switching conditions can be
written as
Z1 = Ropt (7)
Z2n = 0 (8)
Z2n+1 = ∞ (9)
A. Matching network design
A transmission-line-implemented low-pass filter architec-
ture was implemented to obtain these impedance values
at the corresponding frequencies. In Fig. 1, the proposed
schematic of a high-efficiency transmission line-based Class
F PA OMN is presented, with the optimal load resistance R
matched to the standard load impedance R = Ropt ohms at
the fundamental frequency. TL2 is a series transmission line
with an electrical length of θ that should be able to produce
an inductive reactance which resonates with the device’s
Cds at the third harmonic. TL3 is a shunt transmission,
line whose electrical length is chosen to achieve a quarter-
wave wavelength at the third harmonic on the right-hand side
of TL2. At the device output, both high impedance at the
second harmonic and low impedance at the third harmonic
is produced.

∞
!
1 1 2 X cos(2nωo t)
ID (θ) = IS + sin ωt − (2)
π 2 π n=1 4n2 − 1

Now, the non-overlapping waveforms in the time domain Fig. 1. Schematic of matching network of Class F PA.
correspond to instantaneous power at the drain obtained
from the fundamental current and voltage, which could be
given as

Z 2π
1
Vfo = IS sin2 (θ)dθ (3)
π 0
Z 2π
1
Ifo = 2VDD sin(θ + π)dθ (4)
π π Fig. 2. Schematic of the OMN with the effect of device

VDD IS Also, as TL2 is a short circuit at 2f0 due to the quarter

Pout = (5)
π wave transforming effect of TL1; it can provide a low
From these equations, the impedance that the device impedance at 2f0 . But after adjusting the TL2 and TL3, the
should see at the fundamental frequency can be found as impedance seen at the device output might not match with
the Ropt and is rectified by using an intermediate matching
2 just for the fundamental, as shown in Fig. 2.
8 VDD
Ropt = 2
. (6) The load network viewed by the device multi harmonic
π Popt

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 2022 IEEE Microwaves, Antennas, and Propagation Conference (MAPCON)
current source at the fundamental is shown in Fig. 3(a).
Impedance matching seen between output device impedance
Ropt and load resistance RL is accomplished using a series
transmission line with characteristic impedance Z2 and an
open-circuited capacitive stub TL3 with electrical length of
30 degrees by properly choosing characteristic impedance
Z2 and Z3 of the transmission-line. The electrical length
Fig. 3. Load network at device output for different harmonics(a-c)
of the series transmission line TL2 may be calculated using
this value of Z2 that matches the optimal output device
impedance with the load resistance.
The impedance load network at the fundamental frequency
can be formulated as
RL (Z3 −Z2 tan 30◦ tan θ)+jZ2 Z3 tan θ
 
Znet (wo ) = Z2 Z2 Z3 +j(Z2 tan 30◦ +Z3 tan θ)RL
Fig. 3(b) depicts the load network as seen through
the device output at the second harmonic, adjusting for
the shorting effect of the quarter-wave short-circuited
stub. The transmission line generates a short-circuit for
the second harmonics at the device output. A similar
load network is depicted in Fig. 3(c) due to a three
quarter-wave transforming effect of the stub line TL1 as
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an open circuit and a quarter-wave transforming effect of
the shunt harmonic stub TL3 at third harmonics. The series
transmission line, in combination with the shunt harmonic
stub, forms an open-circuit state for third harmonics at the
device output in this situation.
In order to efficiently achieve the desired open and short
circuit conditions, as well as impedance matching at the
fundamental frequency, depending on the actual physical
length of the device output, the transmission line TL2 is
connected in series to the device output.
The desired electrical length (θ) of the transmission line
TL2 can be defined as
1 1
θ= tan−1 ( ) (11)
3 Z0 3ωo Cds
For the proposed design, the Ropt was found to be
41.54 Ω, and using the device parasitic capacitance and
by taking an optimum impedance for the transmission line
TL2 as 53 Ω, the electric length of the transmission line
TL2, was found to be 63.16 ◦ at 3 GHz. After formulated
design of the OMN,the input matching network is generated
using the smith chart tool with device input impedance of
7.921+j*6.126 ohms matched to the 50 ohm impedance of
term.
B. Simulation and layout
The general schematic of Class-F PA is shown in Fig. 4.
After the full PA schematic was designed, we perform the
simulations to find the RF parameters for characterization of
PA. The small signal simulation like S-parameters and large
signal simulation like harmonic balance (HB) is performed
to find characteristics of PA such as pout, gain and PAE. As
the characteristics of PA did not met the specified goals, i.e.
PAE ≥ 70% and Pout ≥ 40 dBm. So, the PA’s performance
is improved by optimising the network by tuning each micro-
strip line individually with keeping each functionality in
consideration.
Fig. 4. Basic schematic of Class F RF PA
(10)
The layout for the Class-F PA on the FR4 substrate, is
generated using the same ADS simulator in layout editor
mode. The components are placed in the layout one by
one starting from source to the load. First the layout of PA
input matching network was generated. After that OMN is
generated using the same procedure. Now, for the device we
have generated a keepout of dimensions 196.85 mil × 630
mil. This dimension was taken from the CREE CG2H40010F
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 2022 IEEE Microwaves, Antennas, and Propagation Conference (MAPCON)
datasheet [13] and also keeping the soldering space in con-
sideration. After cross checking the entire designed layout,
we proceed for the EM model and symbol generation. After
updating the EM model and symbol, the EM model of layout
is now subjected to simulation.
III. FABRICATION AND TESTING
A. Fabrication
The fabrication of the generated FR4 layout with the help
of a dip trace was performed using the traditional etching.
The dip trace layout was printed on photo paper, and a
cut-out was removed. The specific resolution piece of FR4
substrate was also cut out using particular tools. The cut-
out substrate piece was correctly washed using water and
Isopropyl alcohol. The surface of the substrate sheet was
then dried, and then a tiny amount of nail polish remover
was applied on the surface. The cut-out layout of the photo
paper was then firmly kept on the sheet facing down, keeping
in mind that the generated PA sample would have the mirror
image of the printout. Again, a considerable amount of nail
polish remover was applied on the other side of the photo
paper and rolled in tissue paper to keep it under uniform
pressure for around 15 minutes. After 15 minutes, the sample
was taken out of the stress, and carefully the article was
removed. It is noticed that the PA layout gets imprinted into
the surface of the FR4 substrate. Some surfaces where the
imprinting was not precisely as we wanted were carefully
sized using a permanent marker. Then after drying the
sample well, it was dropped in a mixture of ferric chloride
and water for the copper etching. After 15 minutes, the
etching was successful, and we rinsed the sample with water.
Then the ink was removed from the etched sample using
acetone. The keep-out region for the device was carefully
punched. After this, soldering is performed to place the
required capacitors, resistors, wires, and SMA ports in their
dedicated positions. To avoid any gate current from flowing,
an aluminium plate as a heat sink is used on the back side
of the PA, and the device is rested against the aluminium
plate with physical dimensions of 3.5 cm x 3 cm x 1 cm
and soldered along the gate and drain side along with the
source to the ground plane. After performing PA fabrication
seven times, the final fabricated device under test (DUT) is
selected for testing.
B. Measurement and Testing
The measurement setup consist of RF driver amplifier
(ZX-60-63+) from Mini-circuits [14], EXG N5172B signal
generator (SG), MXA N9020A spectrum analyzer (SA), RF
attenuator (BW-S40W20+) from mini-circuits, multi-meter
and DC power supply. Before performing the measurement,
the fabricated class-F PA is undergone with proper biasing
conditions to turn on the Cree device. At first, the gate
voltage was set to -5 V, and the drain voltage was set to 0 V.
The gate voltage is increased slowly till the desired -2.7V
without altering the drain voltage. Next, the drain voltage
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was slowly increased from 0V to 28V with keeping a few
things in consideration, i.e., no gate current should be there,
and the drain current should not exceed the quiescent current
of 250 mA. After confirmation of proper DUT biasing, the
driver amplifier’s input terminal biased at 5V, 80 mA is
connected to the SG, and the output terminal of the driver
amplifier is connected to the input terminal of DUT, i.e.,class
F PA. Then, the output of class F PA is connected to one
side of the RF attenuator, and the other is connected to the
SA. All the connections are made using the RF connecting
cables. The whole measurement setup for 1-tone analysis of
the proposed PA with a zoomed view of the front and back
sides of DUT is shown in Fig. 5.
Fig. 5. Measurement setup for 1-tone analysis of Class F PA
For performing the 1-tone measurement of PA, the mea-
surement setup mode is chosen and operating frequency is
set at 3 GHz in SA. In SG, amplitude of input power is
set at 13 dBm. After performing the calibration of SA, RF
mode of SG is turned on to provide the input power to the
driver amplifier. A driver amplifier will drive the DUT with
power of 19 dBm. The 1-tone PA measurement results for the
output power, third order harmonics distortion (IM D3 ), and
fifth order harmonics distortion (IM D5 ) can be displayed
in SA. The output power of 28 dBm is obtained at the
input power of 13 dBm. The adjacent channel power (ACP)
analysis of PA with excitation of 16-quadrature amplitude
modulation (QAM) of 20 MHz bandwidth is performed. All
the measured data are saved in .csv file format.
IV. R ESULT AND DISCUSSION
The simulated and measurement results of class-F PA are
discussed and analyzed as shown in Fig. 6. For 1-tone HB
(Harmonic balance) analysis, the simulation results of class-
F PA with PAE 79.251%, drain efficiency of 80.183%, Gain
of 16.54 dB, Pout 41.252 dBm at 26 dBm input power,
ACP of - 28.09 dBc, and 3rd and 5th order harmonics of
-20.5 dBc and -48.9 dBc respectively are obtained. The
obtained measurement results of class F PA includes PAE
 2022 IEEE Microwaves, Antennas, and Propagation Conference (MAPCON)

TABLE I
C OMPARISON OF STATE - OF - THE - ART PA

Frequency Pout Gain PAE DC power ACP IM D3 IM D5

Device Reference
(GHz) (dBm) (dB) (%) consumption(W) (dBc) (dBc) (dBc)
GaN HEMT [15] 2.0 11 13 74 14.5 -17.8 -75
GaN HEMT [16] 2.0 5 19 79 8 -19.2 -18.6
GaN HEMT [17] 2.14 20 12 70 27 -19.1 -60
GaN HEMT [18] 3.5 11 10 72 14.1 -57.1
GaN HEMT [19] 3.5 11 12 78 13.4
GaAs pHEMT [20] 1.1 24 12 86 -17.84 -17.9 -40
GaN HEMT [21] 3.1 40 15 82 1.4 -18.7
GaN HEMT [7] 2 42 14 85 -19.36
GaN HEMT [2] 0.75 40 15 70 4.76 -55
GaN HEMT [22] 1.6 42 10 74.6 6.41 -24 -19.4
GaN HEMT [23] 1.88 40 14.6 70.7 14.6
GaAs pHEMT [24] 2.4 20 10 74 -20.1
GaAs pHEMT [25] 2 19.85 13 70.5 -31
GaN HEMT [26] 2.14 40.2 12.2 70.9 15.5 -65
GaAs pHEMT [27] 1.8 41 12 70 -18.9
GaN HEMT [28] 2.4 40.8 16 70.9 14.5
GaN HEMT This Work 3 28.03 13.03 72.194 6.16 -22.039 -18.4 -45.2

12.194%,drain efficiency of 15.194%, Gain of 13.03 dB,

Pout 28.03 dBm at 15 dBm input power, ACP of - 22.039
dBc and 3rd and 5th order harmonics of -18.4 dBc and -45.2
dBc respectively. From Fig. 6 (A), it can be seen that the
nature of output power is linear up to the point where input
power is 15 dBm. After further increasing the input power,
the nature of output power becomes constant. It is due to the
fact that saturation level of PA is reached. From Fig. 6 (B),
it is observed that the value of simulated gain and measured
gain is constant at input power of 30 dBm and 15 dBm
respectively, then the value of the gain starts decreasing. It
is due to the impact of variation of output power with the
swept input power. It is noted that as the maximum input
intake of driver amplifier is 13 dBm, the value of output
power is low i.e., 28.03 dBm at 15 dBm of input power.

PN Fig. 6. Measurement results of Class F PA (A) Output power vs input

i=1 (Ymeasured − Ysimulated ) power (B) Gain vs output power (C) IM D3 and IM D5 vs output power
M AE = (12) (D) Output spectrum vs frequency
N

TABLE II
Table I compares PA’s performance with some previously MAE(%) COMPARISON FOR DIFFERENT PARAMETERS
designed class F RF power amplifiers. Obtained measure-
ment results of the proposed PA are close to the simulated re- Parameters Measured Simulated MAE (%)
sults. However, some deviation exists between the values of Pout (dBm) 28.03 34.43 0.0064
Gain (dB) 13.03 16.54 0.0023
simulated and measured parameters. This is due to the impact
PAE (%) 72.194 12.194 0.0072
of all the interconnected devices and measuring instruments, ACP (dBc) -22.039 -28.09 0.00605
handmade soldering, and dielectric loss of substrate on the IM D3 -18.4 -20.5 0.0021
performance of DUT. Also, there is an availability of noise IM D5 -45.2 -48.9 0.0037
and thermal effects while performing the measurement of
PA. Table II shows the comparison of MAE (Mean absolute
error) for different parameters. The value of error for gain V. C ONCLUSION
and IM D3 is lower than other parameters. Table 2 data
resembles the best results out of 7 times fabricated and tested The proposed PA structure is implemented on an FR4
PAs. substrate with an operating frequency of 3 GHz. Firstly,

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 2022 IEEE Microwaves, Antennas, and Propagation Conference (MAPCON)
the proposed PA is designed and then simulated to multiple
simulation analysis tests to check and verify the functionality
of the entire design. The simulations were done in ADS
software by Keysight and with the help of the ADS layout
editor, the corresponding layouts were prepared. After that,
the particular design was subjected to the same simulations
and cross-verified under EM- Cosimulation to ensure that the
simulation results and the fabricated PA results would be as
close as possible. Then, the PA was fabricated, and the DUT
was subjected to physical testing to get the readings. The
measured and simulated results are compared to analyze the
characteristics of the proposed PA for wireless applications.
Finally, the MAE performance is analyzed for different
parameters to verify the deviation between the measured
and simulated results. In the future, PA’s linearity can be
improved by designing a pre-distortion-based PA.
ACKNOWLEDGMENT
The authors wish to acknowledge all staff members at the
Center of Excellence Communication Lab, National Insti-
tute of Technology Meghalaya, for providing an Advanced
design system for simulation licensing support. All of the
authors are thankful to Dr. Sandeep Chaturvedi for the
discussions. The authors also thank the DST Indo-Czech
Project (DST/INT/Czech/P-015/2019) for giving financial
assistance.
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