Dell Latitude 7480 Compal CAZ20 LA-E131P Rev 1.0 (A00) Схема

A B C D E
COMPAL CONFIDENTIAL
1 MODEL NAME : CAZ20 1
PCB NO : LA-E131P
BOM P/N : 431A4331L0X
Steamboat 14" AR
Kabylake U
2
2016-11-9 2
REV : 1.0 (A00)

@ : Nopop Component
EMI@ : EMI Component
@EMI@ : EMI Nopop Component
ESD@ : ESDComponent
@ESD@ : ESD Nopop Component
3 RF@ : RF Component 3
@RF@ : RF Nopop Component

CXDP@ : XDP Component
CONN@ : Connector Component
MB PCB
Part Number Description
ESPI@ : ESPI interface Component
DA800188010 PCB 1S1 LA-E131P REV0 MB AR 1
LPC@ : External ESPI Component (SHD)
Layout Dell logo
GT3@ : KBL-U 2+3e Component
4
INFI@ : Infinity SKU Component 4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
COPYRIGHT 2016
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
ALL RIGHT RESERVED TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Cover Sheet
REV:A00 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
PWB: Power CKT : 1107 NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Date:
LA-E131P
Wednesday, November 09, 2016 Sheet 1 of 59
1.0
A B C D E
A B C D E
Steamboat 14 w/ AR Block Diagram Steamboat 12 only support one DIMM

Reverse Type
Memory BUS (DDR4) DDR4-SO-DIMM X2

BANK 0, 1, 2, 3
2133MHz
eDP 14": Lane x 4; 12" :Lane x 2 up to 16GB P20~21
1 EDP CONN 1
P29
USB2.0[8]
LCD Touch
P29
PCIE[5][6][7][8] USB2.0[5]
HDMI 1.4 HDMI INTEL Camera
CONN P23 DDI[1] P29 Trough eDP Cable
USB2.0[1] SLGC55544CVTR USB2.0[1]_PS
AR-SP SW2_DP1 USB POWER SHARE
TBT P24-25 To type C P38 USB3.0 Conn
TypeC USB
P28 KABYLAKE_U MCP PS(Ext Port 1)
DP DeMUX DDI[2] Right
PS8338B USB3.0[1] USB3.0[1] P38
P22
PD Solution
USB2.0/SMBus TPS65982D USB2.0/SMBus SW2_DP2 USB2.0[2] USB3.0 Conn
P26-27 To M2 WiGig card (Ext Port 2)
USB3.0[3]
Left Front P39
USB2.0[3]
2
USB3.0 Conn 2
PCIE[1] PCIE[9]
PAGE 6~19 USB3.0[4] (Ext Port 3) P39
PCIE[4] PCIE[3] Left Rear only 14"
HD Audio I/F
Card reader Intel Jacksonville M.2,3042 Key B
RTS5242 P31 WGI219LM P30 M.2,3030 Key A
WWAN/LTE SATA[2]/PCIE[12][11]
SPI
P32 WLAN+BT/WIGIG
P32
USB2.0[4] W25Q128FVSIQ
SD4.0 Transformer USB2.0[7] P8
ESPI
P31 P30 USB3.0[2]
SW1_DP2 128M 4K sector INT.Speaker
W25Q128FVSIQ P33
RJ45 P30 P8
128M 4K sector HDA Codec Universal Jack
reserve P33
ALC3246 P33
TPM1.2/2.0 Nuvoton
NPCT650VB2YX Dig. MIC
P29
P36
Trough eDP Cable

3 3
KB/TP CONN
W25Q80DVSSIG SHD_IO SMSC KBC P40 LID SWITCH
P41
P34 MEC5105 M.2 2280
8M 4K sector P34-35 SSD Conn P37
reserve FAN CONN USH CONN
P35 P36
CPU&PCH XDP Port

P14
AUTOMATIC POWER
SWITCH(APS) P11
Smart Card TDA8034HN
USH TPM1.2 USB2.0[10]
BCM58102
RFID/NFC SPI
DC/DC Interface
P42
Fingerprint SPI
CONN POWER ON/OFF
4 SW & LED P41
4
USH board P36
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Block diagram
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-E131P
Date: Wednesday, November 09, 2016 Sheet 2 of 59
A B C D E
5 4 3 2 1
POWER STATES AR config

Signal SLP SLP SLP SLP ALWAYS M SUS RUN CLOCKS
USB3.0 SSIC PCIE SATA DESTINATION USB PORT# DESTINATION
S3# S4# S5# A# PLANE PLANE PLANE PLANE
State USB3.0-1 JUSB1-->Right 1 JUSB1-->Right
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH ON ON ON ON ON

USB3.0-2 SSIC M.2 3042(LTE) 2 JUSB2-->Left Front
USB3.0-3 JUSB2-->Left Front 3 JUSB3-->Left Rear (SB14 only)
S3 (Suspend to RAM) / M3 LOW HIGH HIGH HIGH ON ON ON OFF OFF
D
USB3.0-4 JUSB3-->Left Rear (SB14 only) 4 M2 3042(WWAN) D
S4 (Suspend to DISK) / M3 LOW LOW HIGH HIGH ON ON OFF OFF OFF USB3.0-5 PCIE-1 Card Reader (PCIE) 5 Camera
S5 (SOFT OFF) / M3 LOW LOW LOW HIGH ON ON OFF OFF OFF

USB3.0-6 PCIE-2 NA 6 NA
PCIE-3 M.2 3030(WLAN) 7 M.2 3030(BT)
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH LOW ON OFF ON OFF OFF
PCIE-4 M.2 3030(WIGIG) 8 Touch Screen
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW ON OFF OFF OFF OFF PCIE-5 9 NA
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW ON OFF OFF OFF OFF
PCIE-6 10 USH
Alpine Ridge - SP
PCIE-7 SATA-0
PM TABLE PCIE-8 SATA-1
+5V_ALW
PCIE-9 LOM
+3.3V_ALW PCIE-10 NA
+3.3V_ALW_DSW +3.3V_CV2 +5V_RUN
+3.3V_ALW_PCH +1.2V_MEM +3.3V_RUN
PCIE-11 SATA-1*
power
M.2 2280 SSD
C plane +RTC_CELL +2.5V_MEM +0.6V_DDR_VTT PCIE-12 SATA-2 (PCIex2 or SATA) C
+1.8V_PRIM +1.0V_VCCST +1.8V_RUN

12" not support JUSB3
+1.0V_PRIM +VCC_CORE
+1.0V_PRIM_CORE +VCC_GT
+5V_ALW2 +VCC_SA
State
+3.3V_ALW2 +1.0VS_VCCIO
+3.3V_RTC_LDO
+1.0V_MPHYGT
S0 ON ON ON
S3 ON ON OFF
S5 S4/AC ON OFF OFF
S5 S4/AC doesn't exist OFF OFF OFF
B B
A A
AR use 1086PP PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Title
Port assignment
Non AR use 1080PP BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Size Document Number
LA-E131P
Rev
1.0

5 4 3 2 1
5 4 3 2 1
SIO_SLP_SUS# CPU PWR

SIO_SLP_S4#
SIO_SLP_S4# TPS22961 PCH PWR
+1.2V_MEM (UZ26) +VCC_SFR_OC
GT3 PWR
SY8210A
(PU200) Peripheral Device PWR
0.6V_DDR_VTT_ON RUN_ON
TPS22961 SIO_SLP_S0# TYPE-C Power
Barrel Type-C +0.6V_DDR_VTT (UZ19) +1.0V_VCCSTG
ADAPTER ADAPTER GPU PWR
SIO_SLP_S4#
TPS22961
(UZ21) +1.0V_VCCST
D D
SIO_SLP_SUS#
SYX196D 3V3_MAIN_EN
(PU301) +1.0V_PRIM
RUN_ON
CHARGER TPS62134C
ISL88738 +PWR_SRC +5V_ALW (PU401) +1.0VS_VCCIO
ALWON
(PU901) SY8288C
(PU102) TPS62134D SIO_SLP_SUS#
(PU402) +1.0V_PRIM_CORE
+5V_ALW2
RUN_ON 3.3V_TS_EN
EM5209 LP2301
(UZ4) +5V_RUN (QV8) +5V_TSP
BATTERY AUD_PWR_EN
EM5209
(@UZ5) +5V_RUN_AUDIO
USB_PWR_SHR_VBUS_EN
SY8288B +3.3V_RTC_LDO SLGC55544C
(PU100) (UI3) +5V_USB_CHG_PWR
C C
ALWON
USB_PWR_EN1#
+3.3V_ALW2 SY6288
(UI1) +USB_EX2_PWR
USB_PWR_EN2#
+3.3V_ALW SY6288
(UI2) +USB_EX3_PWR
SB14 only
SIO_SLP_SUS# RUN_ON
RT8097A AOZ1336
(PU501) +1.8V_PRIM (UZ8) +1.8V_RUN
SIO_SLP_LAN#
ISL95857 CSD97374C CSD97374C AO6405 TPS62134CRGT TPS62134CRGT
(PU602) (PU604) (PU603) (QV1) (PU1301) (PU1302) +3.3V_LAN
EM5209
(UZ2) AUX_EN_WOWL
IMVP_VR_ON
IMVP_VR_ON
IMVP_VR_ON
+3.3V_WLAN
SIO_SLP_SUS#
RUN_ON
EN_INVPWR
@SIO_SLP_WLAN#
SIO_SLP_SUS#
+3.3V_ALW_PCH
B EM5209 @PCH_ALW_ON B
(UZ3) RUN_ON
+VCC_SA +VCC_GT +VCC_CORE +BL_PWR_SRC +VCC_EDRAM +VCC_EOPIO EM5209
+3.3V_RUN (@UZ5) +3.3V_RUN_AUDIO
GT3 => SB14 only
3.3V_WWAN_EN
EM5209 3.3V_CAM_EN#
(UZ4) +3.3V_WWAN LP2301A
(QZ1) +3.3V_CAM
ENVCC_PCH
G524B1T11U
TYPE-C (UV24) +LCDVDD
+5V_ALW
TPS65982D\
(UT5) +TBTA_Vbus_1(5V~20V)
+PP_HV(5V~20V)
A
+5V_ALW SIO_SLP_S4#
A
AP7361C
AP2204 AP2112K (PU503) +2.5V_MEM
(UT8) (UT7) +3.3V_VDD_PIC for DDR4
+5V_TBT_VBUS
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Power rails
5 4 3 2 1
5 4 3 2 1
1K 2.2K
1K
+3.3V_ALW_PCH 2.2K
+3.3V_RUN
AW44 MEM_SMBCLK 202
MEM_SMBDATA
DMN65D8LDW-7
BB43 200 DIMMA
DMN65D8LDW-7
499
202
KBL-U
+3.3V_ALW_PCH 200 DIMMB
D 499 D
AY44 SML0_SMBCLK 28
SML0_SMBDATA 31 LOM
BB39
AW45 AW42 53
51 XDP
1K
SML1_SMBDATA
SML1_SMBCLK
+3.3V_ALW_PCH
1K
E11 D8
03 03
D7 UPD2_SMBCLK
2.2K
00 +3.3V_ALW
E7 UPD2_SMBDAT 2.2K
00
@2.2K 2.2K
+3.3V_ALW +3.3V_CV2
@2.2K 2.2K
01 B3 USH_SMBCLK M9
C E5 USH_SMBDAT USH C
01 L9
2.2K USH/B
C12 2.2K
02
E10
02 2.2K +3.3V_ALW +3.3V_TBT_FLASH
KBC 2.2K
C3 UPD_SMBCLK B5
04 DMN66D0LDW-7
B4 UPD_SMBDAT PD
A5
04 DMN66D0LDW-7
MEC 5105
F7
05
B6
05
06 A12
06 N10
2.2K
B B
+3.3V_ALW
2.2K
07 M4 EXPANDER_GPU_SMCLK
M7 EXPANDER_GPU_SMDATA Expander IO
07
08 C5
08 C8
09 F6
09 E9 2.2K
Charger
+3.3V_ALW
2.2K
10
100 ohm 7
N2 PBAT_CHARGER_SMBCLK
100 ohm 6
BATTERY
10 M3 PBAT__CHARGER_SMBDAT CONN
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Port assignment
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
UC1A CPU@ SKL-U
2 1 CPU_DP1_CTRL_CLK E55 C47

RC175 2.2K_0402_5% <24> CPU_DP1_N0 F55 DDI1_TXN[0] EDP_TXN[0] C46 EDP_TXN0 <29>
2 1 CPU_DP1_CTRL_DATA <24> CPU_DP1_P0 E58 DDI1_TXP[0] EDP_TXP[0] D46 EDP_TXP0 <29>
RC178 2.2K_0402_5% <24> CPU_DP1_N1 F58 DDI1_TXN[1] EDP_TXN[1] C45 EDP_TXN1 <29>
2 1 CPU_DP2_CTRL_CLK AR(AR)/ <24> CPU_DP1_P1 F53 DDI1_TXP[1] EDP_TXP[1] A45 EDP_TXP1 <29>
<24> CPU_DP1_N2 DDI1_TXN[2] EDP_TXN[2] EDP_TXN2 <29>
D RC176 2.2K_0402_5%
CPU_DP2_CTRL_DATA
HDMI(Non AR) <24> CPU_DP1_P2
G53
DDI1_TXP[2] EDP_TXP[2]
B45
EDP_TXP2 <29>
D
2 1 F56 A47
RC177 2.2K_0402_5% <24> CPU_DP1_N3 G56 DDI1_TXN[3] EDP_TXN[3] B47 EDP_TXN3 <29>
<24> CPU_DP1_P3 DDI1_TXP[3] EDP_TXP[3] EDP_TXP3 <29>
C50 E45
<22> CPU_DP2_N0 D50 DDI2_TXN[0] DDI EDP EDP_AUXN F45 EDP_AUXN <29>
<22> CPU_DP2_P0 C52 DDI2_TXP[0] EDP_AUXP EDP_AUXP <29>
<22> CPU_DP2_N1 D52 DDI2_TXN[1] B52
<22> CPU_DP2_P1 A50 DDI2_TXP[1] EDP_DISP_UTIL
PS8338(AR) <22> CPU_DP2_N2 B50 DDI2_TXN[2] G50 CPU_DP1_AUXN
<22> CPU_DP2_P2 D51 DDI2_TXP[2] DDI1_AUXN F50 CPU_DP1_AUXP CPU_DP1_AUXN <24>
<22> CPU_DP2_N3 C51 DDI2_TXN[3] DDI1_AUXP E48 CPU_DP1_AUXP <24>
<22> CPU_DP2_P3 DDI2_TXP[3] DDI2_AUXN F48 CPU_DP2_AUXN <22>
DDI2_AUXP G46 CPU_DP3_AUXN CPU_DP2_AUXP <22>
DISPLAY SIDEBANDS DDI3_AUXN F46 CPU_DP3_AUXP PAD~D @ T1
CPU_DP1_CTRL_CLK L13 DDI3_AUXP PAD~D @ T2
<24> CPU_DP1_CTRL_CLK CPU_DP1_CTRL_DATA L12 GPP_E18/DDPB_CTRLCLK L9
<24> CPU_DP1_CTRL_DATA GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 L7 CPU_DP1_HPD <24>
CPU_DP2_CTRL_CLK N7 GPP_E14/DDPC_HPD1 L6 CPU_DP2_HPD <22> EDP_HPD 1 2
<22> CPU_DP2_CTRL_CLK CPU_DP2_CTRL_DATA N8 GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 N9 RC1 100K_0402_5%
<22> CPU_DP2_CTRL_DATA GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10
N11 GPP_E17/EDP_HPD EDP_HPD <29>
GPP_E23 N12 GPP_E22/DDPD_CTRLCLK R12
T120@ PAD~D GPP_E23/DDPD_CTRLDATA EDP_BKLTEN PANEL_BKLEN <29>
R11
RC2 2 1 24.9_0402_1% EDP_COMP E52 EDP_BKLTCTL U13 EDP_BIA_PWM <29>
+1.0VS_VCCIO EDP_RCOMP 1 OF 20 EDP_VDDEN ENVDD_PCH <29,34>
KBL-U_BGA1356
COMPENSATION PU FOR eDP
CAD Note:Trace width=20 mils ,Spacing=25mil, SKL-U Ballout Rev0.71 & INTEL symbol Rev1.0
Max length=100 mils.
C C
SKL_ULT
UC1I CPU@
CSI-2
A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D36 CSI2_DN2 CSI2_CLKN2 D29
A38 CSI2_DP2 CSI2_CLKP2 B26
B B38 CSI2_DN3 CSI2_CLKN3 A26 B
CSI2_DP3 CSI2_CLKP3
C31 E13 CSI2_COMP RC3 1 2 100_0402_1%
D31 CSI2_DN4 CSI2_COMP B7
CSI2_DP4 GPP_D4/FLASHTRIG TBT_FORCE_PWR <24>
C33
D33 CSI2_DN5
A31 CSI2_DP5 EMMC
B31 CSI2_DN6 AP2
A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
AT1 EMMC_RCOMP 1 2
EMMC_RCOMP RC4 200_0402_1%
KBL-U_BGA1356 9 OF 20
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT CPU (1/14)
5 4 3 2 1
5 4 3 2 1
For DDR4
<20> DDR_A_DQS#[0..7] <21> DDR_B_DQS#[0..7]
DDR4, Ballout for side by side(Non-Interleave) <20> DDR_A_D[0..63] <21> DDR_B_D[0..63]
<20> DDR_A_DQS[0..7] <21> DDR_B_DQS[0..7]

D D
<20> DDR_A_MA[0..16] SKL-U <21> DDR_B_MA[0..16]
UC1B CPU@ SKL-U UC1C CPU@
AU53 DDR_A_CLK#0
DDR_A_D0 AL71 DDR0_CKN[0] AT53 DDR_A_CLK0 DDR_A_CLK#0 <20> DDR_A_D16 AF65 AN45 DDR_B_CLK#0
DDR_A_D1 AL68 DDR0_DQ[0] DDR0_CKP[0] AU55 DDR_A_CLK#1 DDR_A_CLK0 <20> DDR_A_D17 AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] AN46 DDR_B_CLK#1 DDR_B_CLK#0 <21>
DDR_A_D2 AN68 DDR0_DQ[1] DDR0_CKN[1] AT55 DDR_A_CLK1 DDR_A_CLK#1 <20> DDR_A_D18 AK65 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] AP45 DDR_B_CLK0 DDR_B_CLK#1 <21>
DDR_A_D3 AN69 DDR0_DQ[2] DDR0_CKP[1] DDR_A_CLK1 <20> DDR_A_D19 AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46 DDR_B_CLK1 DDR_B_CLK0 <21>
DDR_A_D4 AL70 DDR0_DQ[3] BA56 DDR_A_CKE0 DDR_A_D20 AF66 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDR_B_CLK1 <21>
DDR_A_D5 AL69 DDR0_DQ[4] DDR0_CKE[0] BB56 DDR_A_CKE1 DDR_A_CKE0 <20> DDR_A_D21 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 DDR_B_CKE0
DDR_A_D6 AN70 DDR0_DQ[5] DDR0_CKE[1] AW56 DDR_A_CKE2 DDR_A_CKE1 <20> DDR_A_D22 AK67 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] AP55 DDR_B_CKE1 DDR_B_CKE0 <21>
DDR_A_D7 AN71 DDR0_DQ[6] DDR0_CKE[2] AY56 DDR_A_CKE3 PAD~D @ T3 DDR_A_D23 AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] AN55 DDR_B_CKE2 DDR_B_CKE1 <21>
DDR_A_D8 AR70 DDR0_DQ[7] DDR0_CKE[3] PAD~D @ T4 DDR_A_D24 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53 DDR_B_CKE3 PAD~D @ T5
DDR_A_D9 AR68 DDR0_DQ[8] AU45 DDR_A_CS#0 DDR_A_D25 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3] PAD~D @ T6
DDR_A_D10 AU71 DDR0_DQ[9] DDR0_CS#[0] AU43 DDR_A_CS#1 DDR_A_CS#0 <20> DDR_A_D26 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42 DDR_B_CS#0
DDR_A_D11 AU68 DDR0_DQ[10] DDR0_CS#[1] AT45 DDR_A_ODT0 DDR_A_CS#1 <20> DDR_A_D27 AH68 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] AY42 DDR_B_CS#1 DDR_B_CS#0 <21>
DDR_A_D12 AR71 DDR0_DQ[11] DDR0_ODT[0] AT43 DDR_A_ODT1 DDR_A_ODT0 <20> DDR_A_D28 AF71 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42 DDR_B_ODT0 DDR_B_CS#1 <21>
DDR_A_D13 AR69 DDR0_DQ[12] DDR0_ODT[1] DDR_A_ODT1 <20> DDR_A_D29 AF69 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] AW42 DDR_B_ODT1 DDR_B_ODT0 <21>
DDR_A_D14 AU70 DDR0_DQ[13] BA51 DDR_A_MA5 DDR_A_D30 AH70 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDR_B_ODT1 <21>
DDR_A_D15 AU69 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BB54 DDR_A_MA9 DDR_A_D31 AH69 DDR1_DQ[14]/DDR0_DQ[30] AY48 DDR_B_MA5
DDR_A_D32 BB65 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BA52 DDR_A_MA6 DDR_A_D48 AT66 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50 DDR_B_MA9
DDR_A_D33 AW65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 DDR_A_MA8 DDR_A_D49 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 DDR_B_MA6
DDR_A_D34 AW63 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AW52 DDR_A_MA7 DDR_A_D50 AP65 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BB48 DDR_B_MA8
DDR_A_D35 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 DDR_A_BG0 DDR_A_D51 AN65 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48 DDR_B_MA7
DDR_A_D36 BA65 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AW54 DDR_A_MA12 DDR_A_BG0 <20> DDR_A_D52 AN66 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52 DDR_B_BG0
DDR_A_D37 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 DDR_A_MA11 DDR_A_D53 AP66 DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50 DDR_B_MA12 DDR_B_BG0 <21>
DDR_A_D38 BA63 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] BA55 DDR_A_ACT# DDR_A_D54 AT65 DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48 DDR_B_MA11
DDR_A_D39 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 DDR_A_BG1 DDR_A_ACT# <20> DDR_A_D55 AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53 DDR_B_ACT#
DDR_A_D40 BA61 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_A_BG1 <20> DDR_A_D56 AT61 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52 DDR_B_BG1 DDR_B_ACT# <21>
DDR_A_D41 AW61 DDR0_DQ[24]/DDR0_DQ[40] AU46 DDR_A_MA13 DDR_A_D57 AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR_B_BG1 <21>
DDR_A_D42 BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 DDR_A_MA15 DDR_A_D58 AP60 DDR1_DQ[25]/DDR0_DQ[57] BA43 DDR_B_MA13
C DDR_A_D43 AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 DDR_A_MA14 DDR_A_D59 AN60 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AY43 DDR_B_MA15 C
DDR_A_D44 BB61 DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AU50 DDR_A_MA16 DDR_A_D60 AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44 DDR_B_MA14
DDR_A_D45 AY61 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AU52 DDR_A_BA0 DDR_A_D61 AP61 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AW44 DDR_B_MA16
DDR_A_D46 BA59 DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AY51 DDR_A_MA2 DDR_A_BA0 <20> DDR_A_D62 AT60 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BB44 DDR_B_BA0
DDR_A_D47 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AT48 DDR_A_BA1 DDR_A_D63 AU60 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AY47 DDR_B_MA2 DDR_B_BA0 <21>
DDR_B_D0 AY39 DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AT50 DDR_A_MA10 DDR_A_BA1 <20> DDR_B_D16 AU40 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] BA44 DDR_B_BA1
DDR_B_D1 AW39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] BB50 DDR_A_MA1 DDR_B_D17 AT40 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW46 DDR_B_MA10 DDR_B_BA1 <21>
DDR_B_D2 AY37 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AY50 DDR_A_MA0 DDR_B_D18 AT37 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46 DDR_B_MA1
DDR_B_D3 AW37 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] BA50 DDR_A_MA3 DDR_B_D19 AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46 DDR_B_MA0
DDR_B_D4 BB39 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] BB52 DDR_A_MA4 DDR_B_D20 AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BB46 DDR_B_MA3
DDR_B_D5 BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDR_B_D21 AP40 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] BA47 DDR_B_MA4
DDR_B_D6 BA37 DDR0_DQ[37]/DDR1_DQ[5] AM70 DDR_A_DQS#0 DDR_B_D22 AP37 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4]
DDR_B_D7 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] AM69 DDR_A_DQS0 DDR_B_D23 AR37 DDR1_DQ[38]/DDR1_DQ[22] AH66 DDR_A_DQS#2
DDR_B_D8 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] AT69 DDR_A_DQS#1 DDR_B_D24 AT33 DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 DDR_A_DQS2
DDR_B_D9 AW35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] AT70 DDR_A_DQS1 DDR_B_D25 AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] AG69 DDR_A_DQS#3
DDR_B_D10 AY33 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] BA64 DDR_A_DQS#4 DDR_B_D26 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] AG70 DDR_A_DQS3
DDR_B_D11 AW33 DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDR_A_DQS4 DDR_B_D27 AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] AR66 DDR_A_DQS#6
DDR_B_D12 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] AY60 DDR_A_DQS#5 DDR_B_D28 AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 DDR_A_DQS6
DDR_B_D13 BA35 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDR_A_DQS5 DDR_B_D29 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 DDR_A_DQS#7
DDR_B_D14 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] BA38 DDR_B_DQS#0 DDR_B_D30 AR30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] AR60 DDR_A_DQS7
DDR_B_D15 BB33 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDR_B_DQS0 DDR_B_D31 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] AT38 DDR_B_DQS#2
DDR_B_D32 AY31 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDR_B_DQS#1 DDR_B_D48 AU27 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] AR38 DDR_B_DQS2
DDR_B_D33 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 DDR_B_DQS1 DDR_B_D49 AT27 DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 DDR_B_DQS#3
DDR_B_D34 AY29 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDR_B_DQS#4 DDR_B_D50 AT25 DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] AR32 DDR_B_DQS3
DDR_B_D35 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] AY30 DDR_B_DQS4 DDR_B_D51 AU25 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] AR25 DDR_B_DQS#6
DDR_B_D36 BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDR_B_DQS#5 DDR_B_D52 AP27 DDR1_DQ[51] DDR1_DQSN[6] AR27 DDR_B_DQS6
DDR_B_D37 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDR_B_DQS5 DDR_B_D53 AN27 DDR1_DQ[52] DDR1_DQSP[6] AR22 DDR_B_DQS#7
DDR_B_D38 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_B_D54 AN25 DDR1_DQ[53] DDR1_DQSN[7] AR21 DDR_B_DQS7
DDR_B_D39 BB29 DDR0_DQ[54]/DDR1_DQ[38] AW50 DDR_A_ALERT# DDR0_PAR,DDR0_ALERT# for DDR4 DDR_B_D55 AP25 DDR1_DQ[54] DDR1_DQSP[7]
DDR_B_D40 AY27 DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# AT52 DDR_A_PARITY DDR_A_ALERT# <20> DDR_B_D56 AT22 DDR1_DQ[55] AN43
DDR1_PAR,DDR1_ALERT# for
DDR_B_ALERT# DDR4
DDR_B_D41 AW27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR DDR_A_PARITY <20> DDR_B_D57 AU22 DDR1_DQ[56] DDR1_ALERT# AP43 DDR_B_PARITY DDR_B_ALERT# <21>
DDR_B_D42 AY25 DDR0_DQ[57]/DDR1_DQ[41] AY67 DDR_B_D58 AU21 DDR1_DQ[57] DDR1_PAR AT13 DDR_DRAMRST# DDR_B_PARITY <21>
B DDR_B_D43 DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA +DDR_VREF_A_DQ +DDR_VREF_CA DDR_B_D59 DDR1_DQ[58] DRAM_RESET# SM_RCOMP0 DDR_DRAMRST# <20> B
AW25 AY68 AT21 AR18
DDR_B_D44 BB27 DDR0_DQ[59]/DDR1_DQ[43] DDR0_VREF_DQ BA67 PAD~D @ T132 DDR_B_D60 AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 SM_RCOMP1
DDR CH - A
DDR_B_D45 DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ +DDR_VREF_B_DQ DDR_B_D61 DDR1_DQ[60] DDR_RCOMP[1] SM_RCOMP2
BA27 AP22 DDR CH - B AU18
DDR_B_D46 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_B_D62 AP21 DDR1_DQ[61] DDR_RCOMP[2]
DDR_B_D47 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL DDR_VTT_CTRL <20> DDR_B_D63 AN21 DDR1_DQ[62]
DDR0_DQ[63]/DDR1_DQ[47] DDR1_DQ[63]
KBL-U_BGA1356 2 OF 20 KBL-U_BGA1356 3 OF 20
DDR4 COMPENSATION SIGNALS

SM_RCOMP0 RC5 1 2 121_0402_1%
SM_RCOMP1 RC6 1 2 80.6_0402_1%
SM_RCOMP2 RC7 1 2 100_0402_1%
CAD Note:
Trace width=12~15 mil, Spacing=20 mils
Max trace length= 500 mil
A A
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1
PCH EDS R0.7 p.235~236
UC1E CPU@
SKL-U
For BR/SB
2
SPI - FLASH
SMBUS, SMLINK
PCH_SPI_CLK AV2 MEM_SMBCLK 6 1
PCH_SPI_D1 AW3 SPI0_CLK R7 MEM_SMBCLK DDR_XDP_WAN_SMBCLK <14,20,21>
CXDP@RC10 1 2 1K_0402_1% PCH_SPI_D0 AV3 SPI0_MISO GPP_C0/SMBCLK R8 MEM_SMBDATA QC2A
<14> PCH_SPI_DO_XDP SPI0_MOSI GPP_C1/SMBDATA
5
CXDP@RC11 1 2 1K_0402_1% PCH_SPI_D2 AW2 R10 PCH_SMB_ALERT# DMN65D8LDW-7_SOT363-6
<14> PCH_SPI_DO2_XDP PCH_SPI_D3 AU4 SPI0_IO2 GPP_C2/SMBALERT#
PCH_SPI_CS#0 AU3 SPI0_IO3 R9 SML0_SMBCLK MEM_SMBDATA 3 4
D PCH_SPI_CS#1 AU2 SPI0_CS0# GPP_C3/SML0CLK W2 SML0_SMBDATA SML0_SMBCLK <30> DDR_XDP_WAN_SMBDAT <14,20,21> D
PCH_SPI_CS#2 AU1 SPI0_CS1# GPP_C4/SML0DATA W1 GPP_C5 SML0_SMBDATA <30> QC2B
<36> PCH_SPI_CS#2 SPI0_CS2# GPP_C5/SML0ALERT# DMN65D8LDW-7_SOT363-6 +3.3V_RUN
W3 SML1_SMBCLK
SPI - TOUCH GPP_C6/SML1CLK V3 SML1_SMBDATA SML1_SMBCLK <34>
M2 GPP_C7/SML1DATA AM7 GPP_B23 SML1_SMBDATA <34> DDR_XDP_WAN_SMBDAT1 2
M3 GPP_D1/SPI1_CLK GPP_B23/SML1ALERT#/PCHHOT# RC318 2.2K_0402_5%
J4 GPP_D2/SPI1_MISO DDR_XDP_WAN_SMBCLK1 2
V1 GPP_D3/SPI1_MOSI RC319 2.2K_0402_5%
V2 GPP_D21/SPI1_IO2 +3.3V_ALW_PCH
M1 GPP_D22/SPI1_IO3
LPC
GPP_D0/SPI1_CS# AY13 ESPI_IO0_R RC3661 2 15_0402_5%
GPP_A1/LAD0/ESPI_IO0 BA13 ESPI_IO1_R ESPI_IO0 <34,35> MEM_SMBCLK
RC3671 2 15_0402_5% 1 2
C LINK GPP_A2/LAD1/ESPI_IO1 BB13 ESPI_IO2_R ESPI_IO1 <34,35>
RC3681 2 15_0402_5% ESPI_IO2 <34,35> RC12 1K_0402_5%
G3 GPP_A3/LAD2/ESPI_IO2 AY12 ESPI_IO3_R RC3691 2 15_0402_5% MEM_SMBDATA 1 2
<32> PCH_CL_CLK1 G2 CL_CLK GPP_A4/LAD3/ESPI_IO3 BA12 ESPI_IO3 <34,35>
RC14 1K_0402_5%
<32> PCH_CL_DATA1 G1 CL_DATA GPP_A5/LFRAME#/ESPI_CS# BA11 ESPI_CS# <34,35> SML1_SMBCLK 1 2
+1.8V? <32> PCH_CL_RST1# CL_RST# GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RESET# <34>
RC15 1K_0402_5%
2 1 10K_0402_5% SML1_SMBDATA 1 2
+3.3V_RUN LPC@ RC13 ESPI_CLK
AW13 AW9 EMI@ RC16 1 2 15_0402_5% RC17 1K_0402_5%
<34> SIO_RCIN# GPP_A0/RCIN# GPP_A9/CLKOUT_LPC0/ESPI_CLK AY9 PCI_CLK_LPC1 ESPI_CLK_5105 <34,35> SML0_SMBCLK
@ RC22 1 2 22_0402_5% 1 2
AY11 GPP_A10/CLKOUT_LPC1 AW11 RC347 499_0402_1%
<34> ESPI_ALERT# GPP_A6/SERIRQ GPP_A8/CLKRUN# CLKRUN# <34> SML0_SMBDATA 1 2
RC21 2 1 8.2K_0402_1% RC348 499_0402_1%
+3.3V_1.8V_ESPI 5 OF 20
KBL-U_BGA1356 CHECK,LPC_CLK FOR DEBUG CARD?
Reserve
+3.3V_LAN
SML0_SMBCLK 1 2
C @ RC19 499_0402_1% C
RF Request SML0_SMBDATA 1 2
SOFTWARE TAA @ RC20 499_0402_1%
PCH_SPI_CLK_1_R PCH_SPI_CLK_0_R ESPI_CLK_5105 1 2 +3.3V_RUN

@RF@ CC316 33P_0402_50V8J
33_0402_5%
33_0402_5%
1
1
@EMI@
@EMI@
RPC1 CLKRUN# 1 2
RC28
RC29
LPC@ RC27 8.2K_0402_5%

PCH_SPI_D1_R1 1 8 PCH_SPI_D1_0_R SML0_SMBCLK 1 2
<36> PCH_SPI_D1_R1 PCH_SPI_D0_R1 2 7 PCH_SPI_D0_0_R
+3.3V_SPI @RF@ CC318 33P_0402_50V8J
2
<36> PCH_SPI_D0_R1 PCH_SPI_CLK_R1 3 6 PCH_SPI_CLK_0_R

33P_0402_50V8J
33P_0402_50V8J
<36> PCH_SPI_CLK_R1 PCH_SPI_D3_R1 4 5 PCH_SPI_D3_0_R SML1_SMBCLK 1 2 +3.3V_ALW_PCH

2 1 PCH_SPI_D2_R1
@EMI@
@EMI@
@RF@ CC319 33P_0402_50V8J

1
@ RC30 1K_0402_5% 33_0804_8P4R_5%

1 PCH_SPI_D3_R1 MEM_SMBCLK
CC7
CC8
2 1 2
@ RC31 1K_0402_5% @RF@ CC320 33P_0402_50V8J PCH_SMB_ALERT# 1 2
2
RC23 2.2K_0402_5%
2 1 PCH_SPI_D3_R1
@ RC316 1K_0402_5% TLS CONFIDENTIALITY
PCH_SPI_D3_R1 @ RC407 1 2 33_0402_5% PCH_SPI_D3_1_R Place close CPU side
03/02:follow Intel MOW_2015WW06 PCH_SPI_CLK_R1@ RC408 1 2 33_0402_5% PCH_SPI_CLK_1_R HIGH ENABLE
PCH_SPI_D0_R1 @ RC409 1 2 33_0402_5% PCH_SPI_D0_1_R LOW(DEFAULT) DISABLE
PCH_SPI_D1_R1 @ RC410 1 2 33_0402_5% PCH_SPI_D1_1_R WEAK INTERNAL 20K PD
+3.3V_ALW_PCH
B B
GPP_C5 1 2
ESPI@RC25 4.7K_0402_5%
E-T_6705K-Y20N-00L
+3.3V_SPI 22
EC interface
21 GND2
CC9 2 1 PCH_SPI_CS#1_R1 20 GND1
HIGH ESPI
1 2 @RC32 0_0402_5% PCH_SPI_CS#1 19 20 LOW(DEFAULT) LPC
1 2 PCH_SPI_D0_R1 18 19 WEAK INTERNAL 20k PD
128Mb Flash ROM 0.1U_0201_10V6K @ RC33 0_0402_5% PCH_SPI_D0 17 18
UC5 1 2 PCH_SPI_D1_R1 16 17
PCH_SPI_CS#0_R1 @ RC37 1 2 0_0402_5% PCH_SPI_CS#0_R2 1 8 @ RC34 0_0402_5% PCH_SPI_D1 15 16
PCH_SPI_D1_0_R 2 /CS VCC 7 PCH_SPI_D3_0_R 1 2 PCH_SPI_CLK_R1 14 15
PCH_SPI_D2_R1 RC39 1 2 33_0402_5% PCH_SPI_D2_0_R 3 IO1 IO3 6 PCH_SPI_CLK_0_R @ RC35 0_0402_5% PCH_SPI_CLK 13 14 +3.3V_ALW_PCH
4 IO2 CLK 5 PCH_SPI_D0_0_R 1 2 PCH_SPI_CS#0_R1 12 13
GND IO0 @ RC36 0_0402_5% PCH_SPI_CS#0 11 12
W25Q128FVSIQ_SO8 1 2 PCH_SPI_D2_R1 10 11
@ RC38 0_0402_5% PCH_SPI_D2 9 10 GPP_B23 1 2
+3.3V_SPI 1 2 PCH_SPI_D3_R1 8 9 RC317 150K_0402_5%
@ RC40 0_0402_5% PCH_SPI_D3 7 8
@ CC10 6 7
+3.3V_SPI
1 2 5 6
128Mb Flash ROM +3.3V_ALW_PCH
4 5
EXI BOOT STALL BYPASS
0.1U_0201_10V6K 1 2 3 4
@ UC6 @ RC41 0_0402_5% 2 3
HIGH ENABLED
PCH_SPI_CS#1_R1 @ RC42 1 2 0_0402_5% PCH_SPI_CS#1_R2 1 8 1 2 LOW(DEFAULT) DIABLED
PCH_SPI_D1_1_R 2 /CS VCC 7 PCH_SPI_D3_1_R 1 WEAK INTERNAL PD
PCH_SPI_D2_R1 @ RC43 1 2 33_0402_5% PCH_SPI_D2_1_R 3 IO1 IO3 6 PCH_SPI_CLK_1_R
IO2 CLK JSPI1
4 5 PCH_SPI_D0_1_R CONN@
GND IO0
A W25Q128FVSIQ_SO8 A
5 4 3 2 1
5 4 3 2 1
For BR/SB
UC1F CPU@ SKL-U
+3.3V_RUN
LPSS ISH
AN8
<31> MEDIACARD_IRQ# ONE_DIMM# GPP_B15/GSPI0_CS# MEM_INTERLEAVED
AP7 P2
D AP8 GPP_B16/GSPI0_CLK GPP_D9 P3 D
3.3V_TS_EN <36> TPM_PIRQ# NRB_BIT GPP_B17/GSPI0_MISO GPP_D10 AR_DET#
2 1 AR7 P4
RC282 100K_0402_5% GPP_B18/GSPI0_MOSI GPP_D11 P1
AM5 GPP_D12
AN7 GPP_B19/GSPI1_CS# M4
SIO_EXT_SCI# <34> SIO_EXT_SCI# GPP_B20/GSPI1_CLK GPP_D5/ISH_I2C0_SDA
2 1 AP5 N3
<29> 3.3V_TS_EN BBS_BIT6 AN5 GPP_B21/GSPI1_MISO GPP_D6/ISH_I2C0_SCL +1.8V_RUN
RC237 10K_0402_5%
2 1 LPSS_UART2_RXD GPP_B22/GSPI1_MOSI N1
@ RC402 49.9K_0402_1% @ RC4052 1 100K_0402_5% GPP_C8 AB1 GPP_D7/ISH_I2C1_SDA N2
2 1 LPSS_UART2_TXD AB2 GPP_C8/UART0_RXD GPP_D8/ISH_I2C1_SCL
<35> SBIOS_TX W4 GPP_C9/UART0_TXD AD11 ISH_I2C2_SDA ISH_I2C2_SDA 1 2
@ RC403 49.9K_0402_1%
AB3 GPP_C10/UART0_RTS# GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD12 ISH_I2C2_SCL ISH_I2C2_SDA <32> WWAN RC363 1K_0402_5%
GPP_C11/UART0_CTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL ISH_I2C2_SCL <32> ISH_I2C2_SCL 1 2
LPSS_UART2_RXD AD1 RC362 1K_0402_5%
LPSS_UART2_TXD AD2 GPP_C20/UART2_RXD U1
9/24: Reserve for embedded location ,refer Intel PDG 0.9
AD3 GPP_C21/UART2_TXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U2 ISH_UART0_RXD <32>
AD4 GPP_C22/UART2_RTS# GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3 ISH_UART0_TXD <32>
GPP_C23/UART2_CTS# GPP_D15/ISH_UART0_RTS# U4 ISH_UART0_RTS# <32> WLAN +3.3V_RUN
+3.3V_ALW_PCH GPP_D16/ISH_UART0_CTS#/SML0BALERT# ISH_UART0_CTS# <32>
U7 AC1
U6 GPP_C16/I2C0_SDA GPP_C12/UART1_RXD/ISH_UART1_RXD AC2 SIO_EXT_WAKE# <34>
GPP_C17/I2C0_SCL GPP_C13/UART1_TXD/ISH_UART1_TXD RTD3_CIO_PWR_EN <24> LCD_CBL_DET#
AC3 1 2
2 1 SIO_EXT_WAKE# U8 GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4 LCD_CBL_DET# <29>
RC287 100K_0402_5%
<40> I2C1_SDA_TP U9 GPP_C18/I2C1_SDA GPP_C15/UART1_CTS#/ISH_UART1_CTS#
RC283 10K_0402_5%
2 1 LPSS_UART2_RXD <40> I2C1_SCK_TP GPP_C19/I2C1_SCL AY8 CLKDET#
AH9 GPP_A18/ISH_GP0 BA8 PAD~D @ T258
RC330 49.9K_0402_1%
2 1 LPSS_UART2_TXD AH10 GPP_F4/I2C2_SDA GPP_A19/ISH_GP1 BB7
RC331 49.9K_0402_1% GPP_F5/I2C2_SCL GPP_A20/ISH_GP2 BA7
AH11 GPP_A21/ISH_GP3 AY7 TPM_TYPE
AH12 GPP_F6/I2C3_SDA GPP_A22/ISH_GP4 AW7 LID_CL#_PCH
GPP_F7/I2C3_SCL GPP_A23/ISH_GP5 AP13 PAD~D @ T268
AF11 GPP_A12/BM_BUSY#/ISH_GP6
C AF12 GPP_F8/I2C4_SDA C
GPP_F9/I2C4_SCL GPP_A GROUP is +1.8V
Reserved TPM_TYPE 1 2
@ RC349 100_0402_1%
+3.3V_RUN
+3.3V_RUN
2 1 NRB_BIT
10K_0402_5%
@ RC186 4.7K_0402_5%
2
@ RC267
+5V_ALW
NO REBOOT STRAP
HIGH No REBOOT CONN@
1
JUART1
LOW(DEFAULT) REBOOT ENABLE ONE_DIMM# 1
LPSS_UART2_TXD 2 1
Weak IPD 2
1
10K_0402_5%
LPSS_UART2_RXD 3
4 3 +3.3V_ALW_PCH +3.3V_ALW_PCH
4
RC268
5
6 GND
2
GND
CVILU_CI1804M1VRA-NH
2
@ RC371 @ RC400
B +3.3V_ALW_PCH B
10K_0402_5% 10K_0402_5%
DIMM Detect
1
2 1 BBS_BIT6
@ RC184 8.2K_0402_5%
HIGH 1 DIMM
LOW 2 DIMM MEM_INTERLEAVED AR_DET#
BOOT BIOS Destination(Bit 6)

HIGH LPC
1
LOW(DEFAULT) SPI
Internal 20k PD 10K_0402_5% 10K_0402_5%
RC372 RC401
2
DIMM TYPE AR_DET#
HIGH Interleave HIGH NON AR
LOW Non-Interleave LOW AR
A A
5 4 3 2 1
5 4 3 2 1
For AR,Steamboat12/14
UC1H CPU@ SKL-U
SSIC / USB3
PCIE/USB3/SATA
H8
USB3_1_RXN G8 USB3_PRX_DTX_N1 <38>
H13 USB3_1_RXP C13 USB3_PRX_DTX_P1 <38>
D <31> PCIE_PRX_DTX_N1 G13 PCIE1_RXN/USB3_5_RXN USB3_1_TXN D13 USB3_PTX_DRX_N1 <38> -----> Ext USB3 Port 1 Charge (Right) D
<31> PCIE_PRX_DTX_P1 B17 PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3_PTX_DRX_P1 <38>
Card Reader RTS5242-----> <31> PCIE_PTX_DRX_N1 A17 PCIE1_TXN/USB3_5_TXN J6
<31> PCIE_PTX_DRX_P1 PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN H6 USB3_PRX_DTX_N2 <32>
G11 USB3_2_RXP/SSIC_1_RXP B13 USB3_PRX_DTX_P2 <32>
F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN A13 USB3_PTX_DRX_N2 <32> -----> M.2 3042(LTE)
D16 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP USB3_PTX_DRX_P2 <32>
C16 PCIE2_TXN/USB3_6_TXN J10
PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN H10 USB3_PRX_DTX_N3 <39>
H16 USB3_3_RXP/SSIC_2_RXP B15 USB3_PRX_DTX_P3 <39>
<32> PCIE_PRX_DTX_N3 G16 PCIE3_RXN USB3_3_TXN/SSIC_2_TXN A15 USB3_PTX_DRX_N3 <39> -----> Ext USB3 Port 2 (Left Front)
M.2 3030(WLAN) ---> <32> PCIE_PRX_DTX_P3 D17 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP USB3_PTX_DRX_P3 <39>
<32> PCIE_PTX_DRX_N3 C17 PCIE3_TXN E10
<32> PCIE_PTX_DRX_P3 PCIE3_TXP USB3_4_RXN F10 USB3_PRX_DTX_N4 <39>
G15 USB3_4_RXP C15 USB3_PRX_DTX_P4 <39> -----> Ext USB3 Port 3 (Left Rear)
<32> PCIE_PRX_DTX_N4 F15 PCIE4_RXN USB3_4_TXN D15 USB3_PTX_DRX_N4 <39>
M.2 3030(WiGig) ---> <32> PCIE_PRX_DTX_P4 B19 PCIE4_RXP USB3_4_TXP USB3_PTX_DRX_P4 <39>
<32> PCIE_PTX_DRX_N4 A19 PCIE4_TXN AB9
<32> PCIE_PTX_DRX_P4 PCIE4_TXP USB2N_1 AB10 USB20_N1 <38>
F16 USB2P_1 USB20_P1 <38> -----> Ext USB Port 1 Charge (Right)
<24> PCIE_PRX_DTX_N5 E16 PCIE5_RXN AD6
<24> PCIE_PRX_DTX_P5 C19 PCIE5_RXP USB2N_2 AD7 USB20_N2 <39>
<24> PCIE_PTX_DRX_N5 D19 PCIE5_TXN USB2P_2 USB20_P2 <39> -----> Ext USB Port 2 (Left Front)
<24> PCIE_PTX_DRX_P5 PCIE5_TXP AH3
G18 USB2N_3 AJ3 USB20_N3 <39>
<24> PCIE_PRX_DTX_N6 F18 PCIE6_RXN USB2P_3 USB20_P3 <39> -----> Ext USB Port 3 Left Rear)
<24> PCIE_PRX_DTX_P6 D20 PCIE6_RXP AD9
<24> PCIE_PTX_DRX_N6 C20 PCIE6_TXN USB2N_4 AD10 USB20_N4 <32>
<24> PCIE_PTX_DRX_P6 PCIE6_TXP USB2P_4 USB20_P4 <32> -----> M2 3042(WWAN)
F20 AJ1
AR(PCIE5~8) ---> <24> PCIE_PRX_DTX_N7 E20 PCIE7_RXN/SATA0_RXN USB2N_5 AJ2 USB20_N5 <29>
<24> PCIE_PRX_DTX_P7 B21 PCIE7_RXP/SATA0_RXP
USB2
USB2P_5 USB20_P5 <29> -----> Camera
C <24> PCIE_PTX_DRX_N7 A21 PCIE7_TXN/SATA0_TXN AF6 C
<24> PCIE_PTX_DRX_P7 PCIE7_TXP/SATA0_TXP USB2N_6 AF7
G21 USB2P_6
<24> PCIE_PRX_DTX_N8 F21 PCIE8_RXN/SATA1A_RXN AH1
<24> PCIE_PRX_DTX_P8 D21 PCIE8_RXP/SATA1A_RXP USB2N_7 AH2 USB20_N7 <32>
<24> PCIE_PTX_DRX_N8 C21 PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P7 <32> -----> M.2 3030(BT)
<24> PCIE_PTX_DRX_P8 PCIE8_TXP/SATA1A_TXP AF8
E22 USB2N_8 AF9 USB20_N8 <29>
<30> PCIE_PRX_DTX_N9 E23 PCIE9_RXN USB2P_8 USB20_P8 <29> -----> LCD Touch
<30> PCIE_PRX_DTX_P9 B23 PCIE9_RXP AG1
10/100/1G LAN ---> <30> PCIE_PTX_DRX_N9 A23 PCIE9_TXN USB2N_9 AG2
<30> PCIE_PTX_DRX_P9 PCIE9_TXP USB2P_9
F25 AH7
E25 PCIE10_RXN USB2N_10 AH8 USB20_N10 <36>
D23 PCIE10_RXP USB2P_10 USB20_P10 <36> -----> USH +3.3V_ALW_PCH
C23 PCIE10_TXN AB6 USBCOMP RC44 1 2 113_0402_1%
PCIE10_TXP USB2_COMP AG3 USB2_ID @ RC337 1 2 0_0402_5%
PCIE_RCOMPN F5 USB2_ID AG4 USB2_VBUSSENSE RC338 1 2 1K_0402_5% RPC3
RC45 1 2 100_0402_1% PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE USB_OC3# 4 5
PCIE_RCOMPP A9 USB_OC0# 3 6
D56 GPP_E9/USB2_OC0# C9 USB_OC0# <38> USB_OC1# 2 7
<14> CPU_XDP_PRDY# D61 PROC_PRDY# GPP_E10/USB2_OC1# D9 USB_OC1# <39> USB_OC2# 1 8
<14> CPU_XDP_PREQ# BB11 PROC_PREQ# GPP_E11/USB2_OC2# B9 USB_OC3# USB_OC2# <39>
Reserve
GPP_A7/PIRQA# GPP_E12/USB2_OC3# 10K_8P4R_5%
E28 J1
<37> PCIE_PRX_DTX_N11 E27 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J2
<37> PCIE_PRX_DTX_P11 D24 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 J3 M3042_DEVSLP <32>
<37> PCIE_PTX_DRX_N11 C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2 M2280_DEVSLP <37>
M2 2280 SSD ---> <37> PCIE_PTX_DRX_P11 E30 PCIE11_TXP/SATA1B_TXP H2 HDD_DET# Reserve
<37> PCIE_PRX_DTX_N12 F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3 M3042_PCIE#_SATA
<37> PCIE_PRX_DTX_P12 A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 G4 M2280_PCIE_SATA# M3042_PCIE#_SATA <34>
NEED DOUBLE CHECK
<37> PCIE_PTX_DRX_N12 B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2 M2280_PCIE_SATA# <37>
B <37> PCIE_PTX_DRX_P12 PCIE12_TXP/SATA2_TXP H1 SATALED# B
GPP_E8/SATALED# SATALED# <37,41>
+3.3V_RUN
RPC4
M2280_PCIE_SATA# 4 5
HDD_DET# 3 6
2 7
SATALED# 1 8
10K_8P4R_5%
M3042_PCIE#_SATA 2 1
RC412 10K_0402_5%
A A
5 4 3 2 1
5 4 3 2 1
For SB/KW UMA w AR CC21

1 2
12P_0402_50V8J
2
1M_0402_1%
3
4
RC46
UC1J CPU@ SKL_ULT
YC1
CLOCK SIGNALS 24MHZ_12PF_X3G024000DC1H
1
2
D42
<31> CLK_PCIE_N0 C42 CLKOUT_PCIE_N0 XTAL24_IN CC22
<31> CLK_PCIE_P0 @RF@ RC373 1 2 0_0402_5% CLKREQ_PCIE#0_R AR10 CLKOUT_PCIE_P0 XTAL24_OUT 1 XTAL24_OUT_R
2 1 2
Cardreader---> <31> CLKREQ_PCIE#0
RC189 2 1 10K_0402_5% GPP_B5/SRCCLKREQ0# @ RC295 0_0402_5%
+3.3V_RUN
B42 For Skylake,YC1 24 MHz (50 Ohm ESR) 12P_0402_50V8J
D <32> CLK_PCIE_N1 A42 CLKOUT_PCIE_N1 F43 CLK_ITPXDP_N 1 2 0_0402_5% For Cannonlake,YC1 38.4 MHz (30 Ohm ESR) D
@ RC297
<32> CLK_PCIE_P1 @RF@ RC374 1 2 0_0402_5% CLKREQ_PCIE#1_R AT7 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N E43 CLK_ITPXDP_P 1 2 0_0402_5% CLK_ITPXDP_N_R <14>
WLAN---> @ RC298 546765_546765_2014WW48_Skylake_MOW_Rev_1_0
<32> CLKREQ_PCIE#1 2 1 10K_0402_5% GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P CLK_ITPXDP_P_R <14>
+3.3V_RUN RC47
D41 BA17 SUSCLK
<32> CLK_PCIE_N2 C41 CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK <32,37>
CC23
<32> CLK_PCIE_P2 @RF@ RC375 1 2 0_0402_5% CLKREQ_PCIE#2_R AT8 CLKOUT_PCIE_P2 E37 XTAL24_IN PCH_RTCX1 1 2
WIGIG---> <32> CLKREQ_PCIE#2
RC50 2 1 10K_0402_5% GPP_B7/SRCCLKREQ2# XTAL24_IN E35 XTAL24_OUT PCH_RTCX2
+3.3V_RUN XTAL24_OUT
D40 15P_0402_50V8J
<37> CLK_PCIE_N3 C40 CLKOUT_PCIE_N3 E42 XCLK_BIASREF 1 2
<37> CLK_PCIE_P3 CLKOUT_PCIE_P3 XCLK_BIASREF +1.0V_CLK5
1
@RF@ RC376 1 2 0_0402_5% CLKREQ_PCIE#3_R AT10 RC52 2.7K_0402_1%
M.2 SDD---> <37> CLKREQ_PCIE#3
RC59 2 1 10K_0402_5% GPP_B8/SRCCLKREQ3# AM18 PCH_RTCX1 1 2 For Skylake, pop RC52,depop RC324 RC54 YC2
+3.3V_RUN RTCX1 PCH_RTCX2
B40 AM20 @ RC324 59_0402_1% For Cannonlake, pop RC324,depop RC52 10M_0402_5% 32.768KHZ_12.5PF_9H03200042
<30> CLK_PCIE_N4 A40 CLKOUT_PCIE_N4 RTCX2 546765_546765_2014WW48_Skylake_MOW_Rev_1_0 ESR MAX=50k ohm
2
<30> CLK_PCIE_P4 1 2 0_0402_5% CLKREQ_PCIE#4_R AU8 CLKOUT_PCIE_P4 AN18 1 2 20K_0402_5%
LAN---> @RF@ RC377 SRTCRST# RC56 +RTC_CELL
1
<30> CLKREQ_PCIE#4 2 1 10K_0402_5% GPP_B9/SRCCLKREQ4# SRTCRST# AM16
+3.3V_RUN RC51 CC26
E40 RTCRST# CC24 1 2 1U_0402_6.3V6K 1 2 PCH_RTCX2_R 1 2
<24> CLK_PCIE_N5 E38 CLKOUT_PCIE_N5 @ RC296 0_0402_5%
<24> CLK_PCIE_P5 @RF@ RC378 1 2 0_0402_5% CLKREQ_PCIE#5_R AU7 CLKOUT_PCIE_P5 PCH_RTCRST# <34>
AR ---> 12P_0402_50V8J
<24> CLKREQ_PCIE#5 2 1 10K_0402_5% GPP_B10/SRCCLKREQ5# PCH_RTCRST# 1 2 20K_0402_5%
+3.3V_RUN RC190 RC57
CC25 1 2 1U_0402_6.3V6K
1 2 +3.3V_ALW_DSW
1 2 8/21 can change to 10K for merge to RP
PCH_PLTRST# @ RC62 1 2 0_0402_5%
PLTRST_LAN# <30> PCH_BATLOW# 1 2
+3.3V_LAN SHORT PADS~D RC72 8.2K_0402_5%
@ RC244 1 2 0_0402_5% @ CMOS1 AC_PRESENT 1 2
PCH_PLTRST#_EC <35>
CMOS1 must take care short & touch risk on layout placement RC243 10K_0402_5%
C 2 1 LAN_WAKE# +3.3V_ALW_PCH +RTC_CELL C
@ RL70 10K_0402_5%
PCH_PLTRST# 1 2
+3.3V_ALW_DSW PLTRST_TPM# <36> INTRUDER# 1 2
@ RC60 0_0402_5%
5
RC69 1M_0402_5%
1 PCH_PLTRST#_AND 1 2
P
2 1 B 4 PCH_PLTRST#_AND @ RC325 0_0402_5% +3.3V_ALW_PCH

2 O PCH_PLTRST#_AND <24,31,32,36,37> MPHYP_PWR_EN 1 2
RC323 10K_0402_5%
A
G
1
UC7 @ RC387 10K_0402_5%
2 1 PCH_PCIE_WAKE# TC7SH08FU_SSOP5~D @ RC65 VRALERT# 1 2
3
RC67 1K_0402_5% 100K_0402_5% @ RC73 10K_0402_5%
1 2
2
+1.0V_VCCST @ RC344 10K_0402_5%
2 1 VCCST_PWRGD +3.3V_ALW
RC71 1K_0402_5%
SIO_SLP_LAN# 1 2
+3.3V_ALW_PCH @ RC68 10K_0402_5%
2 1 ME_SUS_PWR_ACK
@ RC74 10K_0402_5% SUSCLK 1 2
10/6 depop, prevent singal step. @ RC48 1K_0402_5%
2 1 PCH_PWROK
@ RC411 10K_0402_5% UC1K CPU@ SKL-U
SYSTEM POWER MANAGEMENT

AT11 SIO_SLP_S0#
GPP_B12/SLP_S0# AP15 SIO_SLP_S0# <17,36,47>
PCH_PLTRST# AN10 GPD4/SLP_S3# BA16 SIO_SLP_S3# <24,34,35>
SYS_RESET# B5 GPP_B13/PLTRST# GPD5/SLP_S4# AY16 SIO_SLP_S4# <17,34,45,48>
B PCH_RSMRST#_ANDAY17 SYS_RESET# GPD10/SLP_S5# SIO_SLP_S5# <34> B
<14,40> PCH_RSMRST#_AND RSMRST# AN15 JAPS1
H_CPUPWRGD_R@ RC77 1 2 1K_0402_5% H_CPUPWRGD A68 SLP_SUS# AW15 SIO_SLP_SUS# <17,34,42,46,47,48,54> 1
T9 @ PAD~D PROCPWRGD SLP_LAN# SIO_SLP_LAN# <34,42> +3.3V_ALW_PCH 1
RC78 1 2 60.4_0402_1% VCCST_PWRGD_CPU B65 BB17 SIO_SLP_S3# 2
<14,34,35> VCCST_PWRGD VCCST_PWRGD GPD9/SLP_WLAN# AN16 SIO_SLP_WLAN# <34,42> 3 2
GPD6/SLP_A# SIO_SLP_A# <34> +3.3V_ALW SIO_SLP_S5# 3
B6 4
<14,34> SYS_PWROK BA20 SYS_PWROK BA15 SIO_SLP_S4# 5 4
<49> PCH_PWROK BB20 PCH_PWROK GPD3/PWRBTN# AY15 SIO_PWRBTN# <14,34> SIO_SLP_A# 6 5
H_CPUPWRGD VCCST_PWRGD <35> PCH_DPWROK DSW_PWROK GPD1/ACPRESENT AU13 PCH_BATLOW# AC_PRESENT <34> 7 6
GPD0/BATLOW# +3.3V_ALW 7
AR13 8
<34> ME_SUS_PWR_ACK GPP_A13/SUSWARN#/SUSPWRDNACK 8
100P_0402_50V8J
ESD@ CC300
100P_0402_50V8J
ESD@ CC301
AP11 PCH_RTCRST# 9
<34> SUSACK# GPP_A15/SUSACK# AU11 10 9
PME#
GPP_A11/PME# PAD~D @ T115 10
1
BB15 AP16 INTRUDER# 11

<34,35> PCH_PCIE_WAKE# AM15 WAKE# INTRUDER# <35,41> POWER_SW#_MB 12 11
<30,34> LAN_WAKE# AW17 GPD2/LAN_WAKE# AM10 MPHYP_PWR_EN SYS_RESET# 13 12
2
<30> PM_LANPHY_ENABLE AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11 VRALERT# 14 13

<29> 3.3V_CAM_EN# GPD7/RSVD GPP_B2/VRALERT# SIO_SLP_S0# 15 14
connect to VCCMPHYGTAON_1P0 enable pin 16 15
2 1 KBL-U_BGA1356 11 OF 20 17 16
RC311 10K_0402_5% SYS_RESET# 18 17
ESD Request:place near CPU side 19 18
GND
@ESD@ CC302
0.1U_0402_25V6
20
GND
1
CONN@
1 2 +3.3V_RUN ACES_50506-01841-P01
RC215 @ RC290 0_0402_5%
2
10K_0402_5%
POP NO Support Deep sleep

2
RC291 @
DE-POP Support Deep sleep +3.3V_RUN

XDP_DBRESET#
PCH_DPWROK 1 2 PCH_RSMRST#_AND <14> XDP_DBRESET#
5
@ RC215 0_0402_5% ESD Request:place near CPU side

1
A +3.3V_RUN 1 A
P
B
1
1
0.01UF_0402_25V7K
100K_0402_1%
4 SYS_RESET#_R 1 2 SYS_RESET#
1 O
@ CC266
RC75 2 1 ME_RESET# 2 RC224 1K_0402_5%

A
G
RC220
10K_0402_5% @ RC225 8.2K_0402_5% @ UC12

2 1 74AHC1G09GW_TSSOP5
3
2 @ RC227 8.2K_0402_5%
2

Title
if pop UC12, RC291 also need pop(74AHC1G09GW is OD output)PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
5 4 3 2 1
5 4 3 2 1
+1.0V_VCCSTG
PCH_JTAG_TDI 1 2
RC81 51_0402_5%
PCH_JTAG_TDO 1 2
RC82 100_0402_5%
PCH_JTAG_TMS 1 2
UC1D CPU@ SKL-U RC130 51_0402_5%
CPU_XDP_TCLK 1 2 XDP_JTAGX
H_CATERR# D63 @ RC328 0_0402_5%
A54 CATERR#
D <34> PECI_EC 1 2 H_PROCHOT#_R C65 PECI D
<34,49,52> H_PROCHOT# PROCHOT# JTAG
RC84 499_0402_1% H_THERMTRIP# C63
<20,21,35> H_THERMTRIP# A65 THERMTRIP# B61 CPU_XDP_TCLK
SKTOCC# PROC_TCK D60 CPU_XDP_TDI CPU_XDP_TCLK <14>
CPU MISC PROC_TDI CPU_XDP_TDI <14>
C55 A61 CPU_XDP_TDO
<14> XDP_OBS0_R D55 BPM#[0] PROC_TDO C60 CPU_XDP_TMS CPU_XDP_TDO <14>
<14> XDP_OBS1_R XDP_OBS2_R B54 BPM#[1] PROC_TMS B59 CPU_XDP_TRST# CPU_XDP_TMS <14>
T10 @ PAD~D BPM#[2] PROC_TRST# CPU_XDP_TRST# <14>
C56 1 2
BPM#[3] B56 PCH_JTAG_TCK @ RC86 51_0402_5%
+1.0V_VCCST A6 PCH_JTAG_TCK D59 PCH_JTAG_TDI PCH_JTAG_TCK <14>
<34> SIO_EXT_SMI# A7 GPP_E3/CPU_GP0 PCH_JTAG_TDI A56 PCH_JTAG_TDO PCH_JTAG_TDI <14>
2 1 H_CATERR# <29> TOUCH_SCREEN_PD# TOUCHPAD_INTR# BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDO C59 PCH_JTAG_TMS PCH_JTAG_TDO <14>
<34,40> TOUCHPAD_INTR# AY5 GPP_B3/CPU_GP2 PCH_JTAG_TMS C61 CPU_XDP_TRST# PCH_JTAG_TMS <14>
@ RC79 49.9_0402_1%
2 1 H_THERMTRIP# <29> TOUCH_SCREEN_DET# GPP_B4/CPU_GP3 PCH_TRST# A59 XDP_JTAGX 1 2
CPU_POPIRCOMP AT16 JTAGX +1.0V_VCCSTG
RC80 1K_0402_5% @ RC87 1K_0402_5%
PCH_POPIRCOMP AU16 PROC_POPIRCOMP
+1.0V_VCCSTG EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
EOPIO_RCOMP H65 OPCE_RCOMP
2 1 H_PROCHOT# OPC_RCOMP
1
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
RC83 1K_0402_5%
RC88
RC89
RC90
RC91
Service Mode Switch:

+3.3V_RUN Add a switch to ME_FWP signal to unlock the ME region and
2
allow the entire region of the SPI flash to be updated using FPT.
2 1 TOUCHPAD_INTR# +3.3V_ALW_PCH
RC414 10K_0402_5%
2 1 CAM_MIC_CBL_DET# ME_FW_EC 1 2 ME_FWP
RC413 10K_0402_5% @ RC221 0_0402_5%
2
@ PT,ST pop RC222 and SW1; MP pop RC221
RC222
C 2 1 CONTACTLESS_DET# 1K_0402_5% C
RC278 10K_0402_5%
2 1 TOUCH_SCREEN_PD# TOUCH_SCREEN_PD# don't move to RPC,
1
@RC272 10K_0402_5% @ SW1
2 1 AUD_PWR_EN 1
<34> ME_FW_EC A
RC279 10K_0402_5% 2
2 1 IR_CAM_DET# ME_FWP 3 B
RC345 100K_0402_5% 4 C
2 1 HOST_SD_WP# 5 G1
RC292 10K_0402_5% G2
SS3-CMFTQR9_3P
+3.3V_ALW_PCH ME_FWP PCH has internal 20K PD.
2 1 SIO_EXT_SMI# (suspend power rail)
RC346 10K_0402_5% FLASH DESCRIPTOR SECURITY OVERRIDE
UC1G CPU@ SKL-U
2 1 KB_DET#
RC288 10K_0402_5%
LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short
AUDIO
HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short
RC92 1 2 33_0402_5% HDA_SYNC BA22
<33> HDA_SYNC_R 1 2 HDA_BIT_CLK AY22 HDA_SYNC/I2S0_SFRM
EMI@ RC93 33_0402_5%
<33> HDA_BIT_CLK_R 1 2 HDA_SDOUT BB22 HDA_BLK/I2S0_SCLK
RC94 33_0402_5% SDIO/SDXC
<33> HDA_SDOUT_R ME_FWP RC223 1 2 BA21 HDA_SDO/I2S0_TXD
1K_0402_5%
<33> HDA_SDIN0 AY21 HDA_SDI0/I2S0_RXD AB11
1 2 33_0402_5% HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13 CAM_MIC_CBL_DET# <29>
RC95
<33> HDA_RST#_R J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12 TBT_CIO_PLUG_EVENT#
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12 TBT_CIO_PLUG_EVENT# <24>
AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11 CONTACTLESS_DET#
HDA_BIT_CLK_R I2S1_TXD GPP_G4/SD_DATA3 W10 CONTACTLESS_DET# <36>
AK7 GPP_G5/SD_CD# W8 AUD_PWR_EN HOST_SD_WP# <31>
GPP_F1/I2S2_SFRM GPP_G6/SD_CLK AUD_PWR_EN <33>
RF@ CC27
47P_0402_50V8J
AK6 W7
GPP_F0/I2S2_SCLK GPP_G7/SD_WP
1
AK9
B AK10 GPP_F2/I2S2_TXD BA9 B
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
2
GPP_A16/SD_1P8_SEL
IR_CAM_DET# H5 AB7 SD_RCOMP RC96 1 2 200_0402_1%
<29> IR_CAM_DET# TBT_PWR_EN D7 GPP_D19/DMIC_CLK0 SD_RCOMP
T269@ PAD~D GPP_D20/DMIC_DATA0
Close to RC93
KB_DET# D8 AF13
<40> KB_DET# C8 GPP_D17/DMIC_CLK1 GPP_F23
GPP_D18/DMIC_DATA1
AW5
<33> SPKR GPP_B14/SPKR
PCH_JTAG_TDO PCH_JTAG_TDI XDP_JTAGX H_THERMTRIP# H_PROCHOT#
@ESD@ CC303
@ESD@ CC304
@ESD@ CC305
@ESD@ CC312
@ESD@ CC310
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
RF Request. Place near CPU side (Intel MOW)
1
2
2
HDA_RST# HDA_SDIN0 HDA_SDOUT
+3.3V_ALW_PCH +3.3V_ALW_PCH
1 HDA_SDOUT
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2 1 SPKR 2 1 1 1
@ RC183 8.2K_0402_5% @ RC187 4.7K_0402_5% ESD request,Place near CPU side.
RF@ CC331
RF@ CC332
RF@ CC333
2 2 2
A TOP SWAP STRAP Flash Descriptor Security override A
HIGH ENABLE HIGH DISABLE

LOW(DEFAULT) DISABLE LOW(DEFAULT) ENABLE
Internal 20k PD
5 4 3 2 1
5 4 3 2 1
<14> CFG[0..19]
D D
CFG[2][5][6][7] for SKYLAKE-H CPU CFG strap pin

UC1S CPU@ SKL-U
UC1T SKL-U
RESERVED SIGNALS-1
2 1 CFG0 SPARE
@ RC113 10K_0402_1% CFG0 E68 BB68 1/5 2014WW52 MOW reserve to support
2 1 CFG1 B67 CFG[0] RSVD_TP_BB68 BB69 PAD~D @ T12 Cannonlake-U PCH compatibility AW69 F6
CFG2 D65 CFG[1] RSVD_TP_BB69 PAD~D @ T13 AW68 RSVD_AW69 RSVD_F6 E3
@ RC112 10K_0402_1% close UC1.U11/U12 and <400mil
2 1 CFG3 D67 CFG[2] AK13 AU56 RSVD_AW68 RSVD_E3 C11
@ RC110 10K_0402_1% CFG4 E70 CFG[3] RSVD_TP_AK13 AK12 +1.8V_PRIM +VCC_1P8 AW48 RSVD_AU56 RSVD_C11 B11
CFG5 C68 CFG[4] RSVD_TP_AK12 PAD~D @ T15 C7 RSVD_AW48 RSVD_B11 A11
CFG6 D68 CFG[5] BB2 1 2 U12 RSVD_C7 RSVD_A11 D12
Stall reset sequence CFG7 C67 CFG[6] RSVD_BB2 BA3 @ RC313 0_0402_5% U11 RSVD_U12 RSVD_D12 C12
CFG[7] RSVD_BA3 RSVD_U11 RSVD_C12
1U_0402_6.3V6K
CFG8 F71 H11 F52
HIGH(DEFAULT) No stall(Normal Operation) CFG9 G69 CFG[8] 1 RSVD_H11 RSVD_F52
LOW stall CFG[9]
CC222
CFG10 F70 AU5
CFG11 G68 CFG[10] TP5 AT5 PAD~D @ T128
CFG12 H70 CFG[11] TP6 PAD~D @ T129 2 20 OF 20
KBL-U_BGA1356
CFG13 G71 CFG[12] @
CFG14 H69 CFG[13] D5
CFG15 G70 CFG[14] RSVD_D5 D4
CFG[15] RSVD_D4 B2
CFG16 E63 RSVD_B2 C2
CFG17 F63 CFG[16] RSVD_C2
CFG[17] B3
CFG18 E66 RSVD_B3 A3
CFG19 F66 CFG[18] RSVD_A3
C 2 1 CFG4 CFG[19] AW1 C
RC109 1K_0402_5% 2 1 CFG_RCOMP E60 RSVD_AW1
RC114 49.9_0402_1% CFG_RCOMP E1
2 1 ITP_PMODE E8 RSVD_E1 E2
+1.0V_PRIM_XDP ITP_PMODE RSVD_E2
RC115 1.5K_0402_5%
AY2 BA4
AY1 RSVD_AY2 RSVD_BA4 BB4
<14> ITP_PMODE RSVD_AY1 RSVD_BB4
eDP enable D1 A4
D3 RSVD_D1 RSVD_A4 C4
HIGH(DEFAULT) Disabled RSVD_D3 RSVD_C4
LOW Enabled K46 BB5
K45 RSVD_K46 TP4 PAD~D @ T130
RSVD_K45 A69
AL25 RSVD_A69 B69
AL27 RSVD_AL25 RSVD_B69
RSVD_AL27 AY3
C71 RSVD_AY3
B70 RSVD_C71 D71
RSVD_B70 RSVD_D71 C70
F60 RSVD_C70
RSVD_F60 C54
A52 RSVD_C54 D54
RSVD_A52 RSVD_D54
BA70 AY4
T16 @ PAD~D RSVD_TP_BA70 TP1 PAD~D @ T126
BA68 BB3
T17 @ PAD~D RSVD_TP_BA68 TP2 PAD~D @ T127
J71 AY71
J68
F65
RSVD_J71
RSVD_J68
VSS_AY71
ZVM#
AR56
AW71
LPM_ZVM_N <54> ZVM# for SKYLAKE-U 2+3e
G65 VSS_F65 RSVD_TP_AW71 AW70 PAD~D @ T113
PAD~D @ T114
B
F61
E61
VSS_G65
RSVD_F61
RSVD_TP_AW70
MSM#
AP56
C64 1 MSM_N
2 <54>
MSM# for SKYLAKE-U 2+3e B
RSVD_E61 PROC_SELECT# +1.0V_VCCST

@ RC120 100K_0402_5%
For Skylake , RC120 depop

KBL-U_BGA1356 19 OF 20 For Cannonlake, RC120 pop
546765_546765_2014WW48_Skylake_MOW_Rev_1_0
A A
5 4 3 2 1
5 4 3 2 1
+1.0V_PRIM +1.0V_PRIM_XDP
1 2 +1.0V_PRIM_XDP CXDP@
@ RC216 0_0603_1% CPU XDP XDP_PRSNT_PIN1 1
RC121
2 CFG3
0_0402_5% +1.0V_PRIM_XDP
<13> CFG[0..19]
1 2 +3.3V_RUN
@ RC122 0_0402_5%
+1.0V_PRIM_XDP JXDP1 CONN@ CC30
1 2 2 1
<10> CPU_XDP_PREQ#
CPU_XDP_PREQ# 3 1 2 4 CFG17 UC8
5 3 4 6
0.1U_0201_10V6K
0.1U_0201_10V6K
CPU_XDP_PRDY# CFG16 0.1U_0201_10V6K
<10> CPU_XDP_PRDY# 5 6 8
@ CC28
@ CC29
1 1 7 14
CFG0 9 7 8 10 CFG8 VCC
CFG1 11 9 10 12 CFG9 TDO_XDP 2 3 CPU_XDP_TDO <12>
13 11 12 14 1A 1B
D 2 2 CFG2 15 13 14 16 CFG10 D
CFG3 17 15 16 18 CFG11 1
19 17 18 20 1OE
CXDP@ RC239 1 2 0_0402_5% XDP_OBS0 21 19 20 22 CFG19 TDI_XDP 5 6 CPU_XDP_TDI <12>
<12> XDP_OBS0_R XDP_OBS1 23 21 22 24 2A 2B
CXDP@ RC240 1 2 0_0402_5% CFG18
<12> XDP_OBS1_R 25 23 24 26
Place near CFG4 27 25 26 28 CFG12 4
JXDP1 CFG5 29 27 28 30 CFG13 2OE
31 29 30 32 XDP_TMS 9 8
RC5 need to close to JCPU1 31 32 34 3A 3B CPU_XDP_TMS <12>
CFG6 33 CFG14
@ RC123 1 2 1K_0402_5% CFG7 35 33 34 36 CFG15
<11,34,35> VCCST_PWRGD 37 35 36 38 10
<11,40> PCH_RSMRST#_AND CXDP@ RC1241 2 H_VCCST_PWRGD_XDP 39 37 38 40 3OE
41 39 40 42 CLK_ITPXDP_P_R <11> TRST#_XDP 12 11
1K_0402_5% CPU_XDP_TRST# <12>
FIVR_EN <11,34> SIO_PWRBTN# 41 42 44 CLK_ITPXDP_N_R <11> 4A 4B
@ RC2171 2 0_0402_5% 43
CFG0 @ RC1261 2 1K_0402_5% FIVR_EN_R 45 43 44 46 ITP_PMODE
RESET_OUT#_R 45 46 48 XDP_DBRESET# ITP_PMODE <13>
CXDP@ RC1281 2 0_0402_5% 47 XDP_DBRESET# <11> 13 7
<8> PCH_SPI_DO_XDP 49 47 48 50 <34> RUNPWROK 4OE GND
@ RC1291 2 0_0402_5%
<11,34> SYS_PWROK 51 49 50 52 TDO_XDP 15
<8,20,21> DDR_XDP_WAN_SMBDAT 53 51 52 54 TRST#_XDP GND PAD
<8,20,21> DDR_XDP_WAN_SMBCLK 55 53 54 56 TDI_XDP
<12> PCH_JTAG_TCK CPU_XDP_TCLK 57 55 56 58 XDP_TMS
<12> CPU_XDP_TCLK 57 58 60 74CBTLV3126BQ_DHVQFN14_2P5X3
59
61 59 60 PCH_SPI_DO2_XDP <8>
61
62 63
GND GND
E-T_6601K-Y61N-04L
+1.0V_VCCSTG
+1.0VS_VCCIO +3.3V_ALW_PCH
CPU_XDP_TMS 1 2
1.5K_0402_5%
FIVR_EN_R
CXDP@ RC133
2 1 RC131 51_0402_5%
2
C RC132 150_0402_5% +3.3V_ALW_DSW CPU_XDP_TDI 1 2 C
+1.0V_VCCST RC134 51_0402_5%
1.5K_0402_5%
CPU_XDP_TDO 1 2
@ RC241
2 1 FIVR_EN RC135 100_0402_5%
@ RC218 150_0402_5%
1
2 1 FIVR_EN CPU_XDP_TRST# 1 2
@ RC219 10K_0402_5% PCH_SPI_DO_XDP @ RC136 51_0402_5%
Place near JXDP1.48
1
CPU_XDP_TCLK 1 2
RESET_OUT#_R XDP_DBRESET# SIO_PWRBTN# RC139 51_0402_5%
0.1U_0402_25V6
0.1U_0402_25V6
CXDP@ CC32
0.1U_0402_25V6
1
@ CC33
CC269
@
1
+3.3V_RUN Place near JXDP1.41
2
XDP_TMS 1 2
2
@ RC228
PCH_JTAG_TMS <12>
0_0402_5%
2
2 1 XDP_DBRESET# TDI_XDP 1 2
@ RC229
PCH_JTAG_TDI <12>
RC137 3K_0402_5% 0_0402_5%
+1.0V_PRIM_XDP TDO_XDP 1 2
@ RC230 PCH_JTAG_TDO <12>
0_0402_5%
2 1 CPU_XDP_PREQ# Place near JXDP1.47

@ RC138 51_0402_5%
TDO_XDP H_VCCST_PWRGD_XDP CPU_XDP_TRST#

B B
@ESD@ CC306
@ESD@ CC307
@ESD@ CC308
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1
1
2
2
ESD request,Place near JXDP1 side. ESD request,Place near UC8 side.
A A
5 4 3 2 1
5 4 3 2 1
+VCC_CORE: 0.3~1.35V +VCC_CORE +VCC_CORE

PSC(Primary side cap) : Place as close to the package as possible
UC1L CPU@ SKL-U BSC(Backside cap) : Place on secondary side, underneath the package
CPU POWER 1 OF 4
A30 G32
A34 VCC_A30 VCC_G32 G33
Component placement order:
A39 VCC_A34 VCC_G33 G35 Package edge > 0402 caps > 0805 caps > Bulk caps >Power source
A44 VCC_A39 VCC_G35 G37
AK33 VCC_A44 VCC_G37 G38
AK35 VCC_AK33 VCC_G38 G40
AK37 VCC_AK35 VCC_G40 G42
AK38 VCC_AK37 VCC_G42 J30
D AK40 VCC_AK38 VCC_J30 J33 D
AL33 VCC_AK40 VCC_J33 J37
AL37 VCC_AL33 VCC_J37 J40
AL40 VCC_AL37 VCC_J40 K33 +VCC_CORE
AM32 VCC_AL40 VCC_K33 K35
AM33 VCC_AM32 VCC_K35 K37
100_0402_1%
VCC_AM33 VCC_K37
2
AM35 K38
RC140
G30 VCC_AM38 VCC_K42 K43
VCC_G30 VCC_K43
1
+VCC_CORE_G0 K32 E32 VCCSENSE
T122@ PAD~D RSVD_K32 VCC_SENSE VCCSENSE <49>
E33 VSSSENSE
+VCC_CORE_G1 AK32 VSS_SENSE VSSSENSE <49>
T123@ PAD~D RSVD_AK32
100_0402_1%
B63 H_CPU_SVIDALRT#
AB62 VIDALERT# A63 VIDSCLK
+VCC_EDRAM VCCOPC_AB62 VIDSCK VIDSCLK <49>
RC141
P62 D64 VIDSOUT
V62 VCCOPC_P62 VIDSOUT
VCCOPC_V62 G20
2
1 2 +1.8V_PRIM_R H63 VCCSTG_G20
+1.8V_PRIM VCC_OPC_1P8_H63
@ RC232 0_0603_5%
G61
VCC_OPC_1P8_G61
AC63
<54> VCC_EDRAM_SENSE AE63 VCCOPC_SENSE
<54> VSS_EDRAM_SENSE VSSOPC_SENSE +1.0V_VCCSTG_R 1 2
+1.0V_VCCSTG
AE62 @ RC143 0_0603_5%
+VCC_EOPIO VCCEOPIO
AG62
VCCEOPIO
AL63
<54> VCCEOPIO_SENSE AJ62 VCCEOPIO_SENSE
<54> VSSEOPIO_SENSE VSSEOPIO_SENSE
C C
12 OF 20
RF Request
KBL-U_BGA1356
VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e VIDSCLK

@RF@ CC321
1 2
33P_0402_50V8J
(w/ on package cache)
Place close CPU side
+VCC_EDRAM +VCC_EOPIO
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1
GT3@ CC180
GT3@ CC183
GT3@ CC289
GT3@ CC290
GT3@ CC291
GT3@ CC292
GT3@ CC293
GT3@ CC184
GT3@ CC187
2 2 2 2 2 2 2 2 2
B B
+1.0V_VCCST
SVID ALERT
56_0402_1%
2
RC152
CAD Note: Place the PU resistors close to CPU

RC204 close to CPU 300 - 1500mils
1
2 1 H_CPU_SVIDALRT#
<49> VIDALERT_N
220_0402_5% RC153
+1.0V_VCCST
SVID DATA
2
100_0402_1%
CAD Note: Place the PU resistors close to CPU

RC157
RC208close to CPU 300 - 1500mils

1
A VIDSOUT A
<49> VIDSOUT
5 4 3 2 1
5 4 3 2 1
+VCCGT: 0.3~1.35V
+VCCGTX : 0.3~1.35V
+VCC_GT +VCC_GT
UC1M CPU@ SKL-U
D CPU POWER 2 OF 4 D
N70
A48 VCCGT N71
A53 VCCGT VCCGT R63
A58 VCCGT VCCGT R64
A62 VCCGT VCCGT R65
A66 VCCGT VCCGT R66
AA63 VCCGT VCCGT R67
AA70 VCCGT VCCGT T62
AA71 VCCGT VCCGT U65
AC64 VCCGT VCCGT U68
AC65 VCCGT VCCGT U71
AC66 VCCGT VCCGT W63
J43 VCCGT VCCGT W69
J45 VCCGT VCCGT W70
J46 VCCGT VCCGT W71
J48 VCCGT VCCGT Y62
J50 VCCGT VCCGT +VCC_GT
J52 VCCGT
J53 VCCGT AK42
J55 VCCGT VCCGTX_AK42 AK43
C J60 VCCGT VCCGTX_AK46 AK48 C
K48 VCCGT VCCGTX_AK48 AK50
L62 VCCGT VCCGTX_AK70 AL43
L63 VCCGT VCCGTX_AL43 AL46
VCCGTX for SKYLAKE-U 2+3e
L68 VCCGT VCCGTX_AL60 AM48
+VCC_GT L69 VCCGT VCCGTX_AM48 AM50
L70 VCCGT VCCGTX_AM50 AM52
L71 VCCGT VCCGTX_AM52 AM53
M62 VCCGT VCCGTX_AM53 AM56
100_0402_1%
VCCGT VCCGTX_AM56
2
N63 AM58
RC161
N64 VCCGT VCCGTX_AM58 AU58

N66 VCCGT VCCGTX_AU58 AU63
N67 VCCGT VCCGTX_AU63 BB57
N69 VCCGT VCCGTX_BB57 BB66
1
VCCGT VCCGTX_BB66
VCC_GT_SENSE J70 AK62
<49> VCC_GT_SENSE VSS_GT_SENSE J69 VCCGT_SENSE VCCGTX_SENSE AL61
<49> VSS_GT_SENSE VSSGT_SENSE VSSGTX_SENSE
1
100_0402_1%
B B
RC163
2
A A
5 4 3 2 1
5 4 3 2 1
+1.2V_MEM +VCC_SFR_OC
+VCCPLL_OC source 1 2
@ RZ119 0_0402_5%
+1.2V_MEM_CPUCLK +1.2V_MEM
UZ26
@ RC231 1 2 0_0402_5% VDDQ: 8.45A 1
+1.2V_MEM 2 1 2 VIN1
CZ102 1U_0402_6.3V6K VIN2
7 6 1 2
D PSC VIN thermal VOUT CZ103 0.1U_0201_10V6K D
3
+5V_ALW VBIAS
VCCSTG_EN
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1 2 4 5
@ RZ120 0_0402_5% ON GND
1 1 1 1
CC176
CC177
CC178
CC179
+3.3V_ALW TPS22961DNYR_WSON8
+1.0VS_VCCIO @ CZ104
2 2 2 2 UC1N CPU@ SKL-U 1 2
CPU POWER 3 OF 4
5
0.1U_0402_10V7K
AU23 AK28 1
P
AU28 VDDQ_AU23 VCCIO AK30 <11,34,42,46,47,48,54> SIO_SLP_SUS# B 4
PSC AU35 VDDQ_AU28 VCCIO AL30 2 O
VDDQ_AU35 VCCIO <11,17,34,45,48> SIO_SLP_S4# A
G
AU42 AL42
BB23 VDDQ_AU42 VCCIO AM28 @ UZ34
3
VDDQ_BB23 VCCIO
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M BB32 AM30

1 1 1 TC7SH08FU_SSOP5~D
VDDQ_BB32 VCCIO
CC294
CC295
CC296 BB41 AM42 +VCC_SA

+1.2V_MEM_CPUCLK BB47 VDDQ_BB41 VCCIO
BB51 VDDQ_BB47 AK23
2 2 2 VDDQ_BB51 VCCSA AK25
PSC VCCSA G23
AM40 VCCSA G25
VDDQC VCCSA G27
VCCSA +1.0VS_VCCIO
10U_0402_6.3V6M
A18 G28
VCCST VCCSA J22
1 VCCSA
CC297
A22 J23
VCCSTG_A22 VCCSA J27
100_0402_1%
VCCSA
2
AL23 K23
2 VCCPLL_OC VCCSA K25
RC165
+1.0V_VCCST K20 VCCSA K27
K21 VCCPLL_K20 VCCSA K28 +1.0VS_VCCIO
C PSC VCCPLL_K21 VCCSA K30 C
1
VCCSA
AM23 VCCIO_SENSE
VCCIO_SENSE AM22 VSSIO_SENSE VCCIO_SENSE <47> PSC
+1.0V_VCCSTG VSSIO_SENSE VSSIO_SENSE <47>
1U_0402_6.3V6K
1
H21
BSC VSSSA_SENSE
CC195
H20
VCCSA_SENSE
1
100_0402_1%
100_0402_1%
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2 1 1 1 1
RC166
RC167
CC252
CC253
CC250
CC251
+VCC_SFR_OC
1U_0402_6.3V6K
1 1 2
+VCC_SA 2 2 2 2
CC199
RC168 100_0402_1%
2
+1.0V_VCCST
2@ PSC
1U_0402_6.3V6K
1U_0402_6.3V6K
2.2P_0402_50V8C
1 1
1 VSA_SEN- <49>
CC288
RF@ CC322
VSA_SEN+ <49>
CC202
S0 S0Ix S3
2 2
2
SIO_SLP_S0# HIGH LOW LOW
SIO_SLP_S3# HIGH HIGH LOW

RF Request
AND HIGH LOW LOW
B B
+1.0V_VCCST source +1.0V_VCCSTG source

+1.0V_VCCSTG +1.0V_VCCST
1 2
@ RZ151 0_0603_5%
pop option with UZ19
1
+1.0V_PRIM @
PJP2
UZ19 PAD-OPEN1x1m
+1.0V_PRIM @ PJP1 2 1 1
UZ21 2 1 CZ105 1U_0402_6.3V6K 2 VIN1
+1.0V_VCCST VIN2
2 1 1
2
CZ100 1U_0402_6.3V6K 2 VIN1 +5V_ALW 7 6 +1.0V_VCCSTG_C1 2
VIN2 PAD-OPEN1x1m VIN thermal VOUT CZ106 0.1U_0201_10V6K
+5V_ALW 7 6 +1.0V_VCCST_C 1 2 3
VIN thermal VOUT CZ101 0.1U_0201_10V6K VBIAS
3 +3.3V_ALW 4 5
VBIAS ON GND
4 5
<11,17,34,45,48> SIO_SLP_S4# ON GND TPS22961DNYR_WSON8
4.4mohm/6A
5
TPS22961DNYR_WSON8
1 TR=12.5us@Vin=1.05V
P
<11,36,47> SIO_SLP_S0# B 4 VCCSTG_EN
4.4mohm/6A 2 O
TR=12.5us@Vin=1.05V <34,35,42,47,54> RUN_ON
UZ35 A G
TC7SH08FU_SSOP5~D
3
A A
@ RZ320 1 2 0_0402_5%
5 4 3 2 1
5 4 3 2 1
close UC1.AL1 and <120mil +1.0V_MPHYGT

+1.0V_PRIM
+1.0V_MPHYAON +1.0V_PRIM
+1.0VO_DSW +1.0V_PRIM_CORE
close UC1.K17 and <120mil close UC1.AB19 and <400mil
PCH PWR close UC1.Y16 and <400mil +1.0V_SRAM
+3.3V_PGPPB 1 2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 close UC1.AG15 and <120mil @ RC309 0_0603_5%
+3.3V_PGPPC +3.3V_PGPPE
@ CC205
@ CC206
+1.0V_APLLEBB
CC203
CC204
1U_0402_6.3V6K
1
@ CC265
+1.0V_MPHYAON UC1O CPU@ SKL-U close UC1.T16 and <400mil
Imax : 2.57A 2 2 2 2
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 2
CPU POWER 4 OF 4
@ CC207
@ CC208
1 2 @ RC310 0_0603_5%
D @ RC299 0_0603_5% AB19 Must be +1.8V 2 D
AB20 VCCPRIM_1P0 AK15
VCCPRIM_1P0 VCCPGPPA +3.3V_1.8V_PGPPA 2 2
+1.0V_CLK6 P18 AG15
VCCPRIM_1P0 VCCPGPPB Y16
close UC1.AF18 and <400mil VCCPGPPC
1 2 AF18 Y15 +3.3V_1.8V_PGPPG
VCCPRIM_CORE VCCPGPPD +3.3V_PGPPD
@ RC300 0_0402_5% AF19 T16
V20 VCCPRIM_CORE VCCPGPPE AF16
VCCPRIM_CORE VCCPGPPF +1.8V_PGPPF close UC1.AD15 and <400mil
+3.3V_ALW_PCH
1U_0402_6.3V6K
+1.0V_DTS V21 AD15 1
VCCPRIM_CORE VCCPGPPG +3.3V_1.8V_PGPPG
CC326
1 2 AL1 V19
@ RC301 0_0402_5% DCPDSW_1P0 VCCPRIM_3P3_V19
+1.8V_PRIM 2
1U_0402_6.3V6K
K17 T1 1
VCCMPHYAON_1P0 VCCPRIM_1P0_T1 +1.0V_DTS
@ CC209
+1.0V_CLK1 L1
VCCMPHYAON_1P0 AA1
VCCATS_1P8 close UC1.AA1 and <400mil
1 2 +1.0V_MPHYGT N15
VCCMPHYGT_1P0_N15 +RTC_CELL 2
1U_0402_6.3V6K
@ RC302 0_0402_5% N16 AK17 1
VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3 +3.3V_ALW_PCH
close UC1.N15 and CC210 <400mil, CC211 <120mil N17
VCCMPHYGT_1P0_N17
CC212
+1.0V_CLK3 P15 AK19
VCCMPHYGT_1P0_P15 VCCRTC_AK19
1U_0201_6.3V6K
P16 BB14 close UC1.AK19 and <120mil close UC1.V19 and <120mil
VCCMPHYGT_1P0_P16 VCCRTC_BB14 2
47U_0805_6.3V6M
1U_0402_6.3V6K
0.1U_0201_10V6K
1 2 1 1 1 1
@ CC210
@ RC303 0_0402_5% K15 BB10 +DCPRTC
+1.0V_AMPHYPLL VCCAMPHYPLL_1P0 DCPRTC
CC211
CC270
CC213
L15 close UC1.BB10 and <120mil
VCCAMPHYPLL_1P0
0.1U_0201_10V6K
A14 1
2 2 VCCCLK1 +1.0V_CLK1 2 2
V15
+1.0V_APLL VCCAPLL_1P0
CC214
K19
+1.8V_PRIM VCCCLK2 +1.0V_CLK2
+1.8V_PGPPF AB17
+1.0V_PRIM VCCPRIM_1P0_AB17 2
Y18 L21
VCCPRIM_1P0_Y18 VCCCLK3 +1.0V_CLK3
1 2
@ RC304 0_0402_5% AD17 N20
+3.3V_ALW_DSW VCCDSW_3P3_AD17 VCCCLK4 +1.0V_CLK4
AD18 RF Request
+3.3V_1.8V_PGPPG AJ17 VCCDSW_3P3_AD18 L19 +1.0V_CLK6
VCCDSW_3P3_AJ17 VCCCLK5 +1.0V_CLK5
C @ RC234 1 2 0_0402_5% AJ19 A10 +1.0V_APLL +3.3V_VCCHDA +1.0V_APLLEBB C
+3.3V_VCCHDA VCCHDA VCCCLK6
close UC1.A10 and <120mil
+1.0V_SRAM
1U_0402_6.3V6K
AJ16 AN11 CORE_VID0 <47> 1
+3.3V_ALW_PCH +3.3V_SPI VCCSPI GPP_B0/CORE_VID0
@ CC216
AN13 CORE_VID1 <47>
AF20 GPP_B1/CORE_VID1
close UC1.AF20 and <400mil VCCSRAM_1P0
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
1 2 AF21 1 1 1
+3.3V_ALW_PCH VCCSRAM_1P0 2
1U_0402_6.3V6K
@ RC235 0_0402_5% T19

1 VCCSRAM_1P0 Take care!!! Note1 on Page 19
@ CC217
RF@ CC323
RF@ CC324
RF@ CC325
T20
+3.3V_1.8V_PGPPA +1.0V_PRIM VCCSRAM_1P0
AJ21 2 2 2
LPC@ RC211 1 2 0_0402_5% 2 +1.0V_APLLEBB VCCPRIM_3P3_AJ21
AK20
+3.3V_1.8V_ESPI VCCPRIM_1P0_AK20
+1.8V_PRIM N18
@ PJP4 VCCAPLLEBB
1U_0402_6.3V6K
1 2 1 2 1 close UC1.N18 and <120mil

@ESPI@ RC212 0_0402_5% KBL-U_BGA1356 15 OF 20
CC218
PAD-OPEN1x1m
+3.3V_ALW_PCH +3.3V_PGPPB
2
1 2 Must be +1.8V for eSPI I/F
@ RC305 0_0402_5%
+3.3V_PGPPC
1 2
@ RC306 0_0402_5% +1.0V_MPHYGT +1.0V_AMPHYPLL +1.0V_PRIM +1.0V_CLK2 +1.0V_PRIM +1.0V_CLK5 +3.3V_ALW_PCH
close UC1.K15, UC1.L15 and <100mil close UC1.AK17 and <120mil
+3.3V_PGPPD
@ RC1691 2 0_0603_5% 1 2 1 2
1 2 close UC1.K15 and <120mil @ RC170 0_0402_5% @ RC171 0_0402_5%
47U_0805_6.3V6M
47U_0805_6.3V6M
0.1U_0201_10V6K
1U_0402_6.3V6K
0.1U_0201_10V6K
1U_0402_6.3V6K
@ RC307 0_0402_5% close UC1.L19 and <100mil
B
1 1 1 1 1 1 B
@ CC220
@ CC221
CC223
+3.3V_PGPPE
@ CC281
@ CC264
CC224
2 2
close UC1.K19 and <100mil 2 2 2 2
1 2
@ RC308 0_0402_5%
8/28 schematic review
+1.0V_PRIM +1.0V_MPHYGT
+3.3V_ALW_PCH +1.0V_PRIM
+1.0V_APLL
+1.0V_PRIM +1.0V_CLK4
+1.0V_MPHYGT source 1
@ PJP3
2
+3.3V_VCCHDA PAD-OPEN1x3m
LC1 1 2 BLM15GA750SN1D_2P LC2 1 2 BLM15GA750SN1D_2P 1 2

0.1U_0201_10V6K
0.1U_0201_10V6K
@ RC173 0_0402_5%
47U_0805_6.3V6M
47U_0805_6.3V6M
1U_0402_6.3V6K
1 1 1 1 close UC1.N20 and <100mil 1

@ CC215
CC313
@ CC225
CC314
@ CC226
561280_561280_KBL_UY_PDG_Rev0p9 :MPHY has defeature

2 2 2 2 2
close UC1.AJ19 and <400mil close UC1.V15 and <100mil
+3.3V_ALW +3.3V_ALW_DSW
A 1 2 A
@ RC214 0_0402_5%
@ CC279
@ CC280
22U_0603_6.3V6M
22U_0603_6.3V6M
1 1
2 2
5 4 3 2 1
5 4 3 2 1
Note1: VCCPRIM_CORE Implementation with PCH CORE_VID Recommendation

CPU@ CPU@
UC1P SKL-U UC1Q SKL-U CPU@ R1: PR408,PR411 ; R2: PR417,PR418 ; R3,PR419,PR420 ; R4: PR423 ; R5: PR424
UC1R SKL-U
GND 1 OF 3 GND 2 OF 3
GND 3 OF 3
A5 AL65 AT63 BA49 F8 L18
A67 VSS VSS AL66 AT68 VSS VSS BA53 G10 VSS VSS L2
A70 VSS VSS AM13 AT71 VSS VSS BA57 G22 VSS VSS L20
AA2 VSS VSS AM21 AU10 VSS VSS BA6 G43 VSS VSS L4
AA4 VSS VSS AM25 AU15 VSS VSS BA62 G45 VSS VSS L8
D AA65 VSS VSS AM27 AU20 VSS VSS BA66 G48 VSS VSS N10 D
AA68 VSS VSS AM43 AU32 VSS VSS BA71 G5 VSS VSS N13
AB15 VSS VSS AM45 AU38 VSS VSS BB18 G52 VSS VSS N19
AB16 VSS VSS AM46 AV1 VSS VSS BB26 G55 VSS VSS N21
AD13 VSS VSS AM68 AV71 VSS VSS BB43 G63 VSS VSS P17
AD16 VSS VSS AM71 AW10 VSS VSS BB55 G66 VSS VSS P19
AD19 VSS VSS AM8 AW12 VSS VSS BB6 H15 VSS VSS P20
AD20 VSS VSS AN20 AW14 VSS VSS BB60 H18 VSS VSS P21
AD21 VSS VSS AN23 AW16 VSS VSS BB64 H71 VSS VSS R13
AD62 VSS VSS AN28 AW18 VSS VSS BB67 J11 VSS VSS R6
AD8 VSS VSS AN30 AW21 VSS VSS BB70 J13 VSS VSS T15
AE64 VSS VSS AN32 AW23 VSS VSS C1 J25 VSS VSS T17
AE67 VSS VSS AN37 AW30 VSS VSS D10 J35 VSS VSS T21
AE68 VSS VSS AN38 AW32 VSS VSS D11 J38 VSS VSS T4
AE69 VSS VSS AN40 AW34 VSS VSS D14 J42 VSS VSS U10
AF1 VSS VSS AN42 AW36 VSS VSS D18 J8 VSS VSS U63
AF10 VSS VSS AN58 AW38 VSS VSS D22 K16 VSS VSS U64
AF15 VSS VSS AN63 AW41 VSS VSS D25 K18 VSS VSS U66
AF17 VSS VSS AP10 AW43 VSS VSS D26 K22 VSS VSS U67
AF63 VSS VSS AP23 AW49 VSS VSS D39 K64 VSS VSS V16
AG16 VSS VSS AP28 AW51 VSS VSS D44 K65 VSS VSS V17
AG17 VSS VSS AP32 AW53 VSS VSS D45 K66 VSS VSS V18
AG18 VSS VSS AP35 AW55 VSS VSS D47 K67 VSS VSS W13
C AG21 VSS VSS AP58 AW60 VSS VSS D58 K71 VSS VSS Y17 C
AG71 VSS VSS AP63 AW62 VSS VSS D6 L11 VSS VSS Y19
AH13 VSS VSS AP68 AW64 VSS VSS D62 L16 VSS VSS Y20
AH6 VSS VSS AP70 AW66 VSS VSS D66 L17 VSS VSS Y21
AH63 VSS VSS AR11 AW8 VSS VSS D69 VSS VSS
AH64 VSS VSS AR15 AY66 VSS VSS E11
AH67 VSS VSS AR16 B10 VSS VSS E15
AJ15 VSS VSS AR20 B14 VSS VSS E18
AJ18 VSS VSS AR23 B18 VSS VSS E21 KBL-U_BGA1356 18 OF 20
AK11 VSS VSS AR42 B34 VSS VSS E53
AK27 VSS VSS AR5 B58 VSS VSS F1
AK8 VSS VSS AR55 BA1 VSS VSS F23
AL2 VSS VSS AR58 BA10 VSS VSS F27
AL35 VSS VSS AT2 BA2 VSS VSS F33
AL52 VSS VSS AT4 F68 VSS VSS F40
AL58 VSS VSS AT56 VSS VSS BA41
B AL64 VSS VSS AT58 VSS B
VSS VSS
KBL-U_BGA1356 16 OF 20 KBL-U_BGA1356 17 OF 20
A A
5 4 3 2 1
5 4 3 2 1
For DDR4
<7> DDR_A_DQS#[0..7]
JDIMM1 REV Type H=9.2
+1.2V_MEM +1.2V_MEM
JDIMM1
<7> DDR_A_D[0..63]
1 2
<7> DDR_A_DQS[0..7] DDR_A_D1 VSS1 VSS2 DDR_A_D4
3 4
5 DQ5 DQ4 6
<7> DDR_A_MA[0..16] DDR_A_D0 VSS3 VSS4 DDR_A_D5
7 8
9 DQ1 DQ0 10
DDR_A_DQS#0 11 VSS5 VSS6 12
DDR_A_DQS0 13 DQS0_c DM0_n/DBI0_n 14
15 DQS0_t VSS7 16 DDR_A_D3
Layout Note: DDR_A_D6 17 VSS8 DQ6 18
DQ7 VSS9
D
Place near JDIMM1 DDR_A_D2
19
21 VSS10 DQ2
20
22
DDR_A_D7 +1.2V_MEM
D
23 DQ3 VSS11 24 DDR_A_D9
DDR_A_D13 25 VSS12 DQ12 26
DQ13 VSS13
1
DDR_A_D8
470_0402_1%
27 28
DDR_A_D12 29 VSS14 DQ8 30
DQ9 VSS15 DDR_A_DQS#1
RD11
31 32
+1.2V_MEM 33 VSS16 DQS1_c 34 DDR_A_DQS1
35 DM1_n/DBI_n DQS1_t 36
2
DDR_A_D15 37 VSS17 VSS18 38 DDR_A_D10
39 DQ15 DQ14 40
DDR_A_D14 41 VSS19 VSS20 42 DDR_A_D11 1 2 DDR_DRAMRST#
DQ10 DQ11 <21> DDR_DRAMRST#_R DDR_DRAMRST# <7>
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
330U_D3_2.5VY_R6M
43 44 @ RD12 0_0402_5%
47 DQ21 DQ20 48
VSS23 VSS24
@ CD17
DDR_A_D37 49 50 DDR_A_D36
DQ17 DQ16
1
1
CD1
CD2
CD3
CD4
CD5
CD6
CD7
CD8
+ 51 52
2
2
DDR_A_D38 59 VSS28 DQ22 60
61 DQ23 VSS29 62 DDR_A_D33 +1.2V_MEM
DDR_A_D34 63 VSS30 DQ18 64
65 DQ19 VSS31 66 DDR_A_D40
1K_0402_1%
VSS32 DQ28
1
DDR_A_D44 67 68
69 DQ29 VSS33 70 DDR_A_D41
DDR_A_D45 VSS34 DQ24
RD15
71 72
+1.2V_MEM +2.5V_MEM 73 DQ25 VSS35 74 DDR_A_DQS#5
75 VSS36 DQS3_c 76 DDR_A_DQS5 +DDR_VREF_A_CA +DDR_VREF_CA
2
77 DM3_n/DBI3_n DQS3_t 78
DQ30 DQ31
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_10V6M
10U_0603_10V6M
81 82 1 2
DDR_A_D46 83 VSS39 VSS40 84 DDR_A_D43 RD17 2_0402_1%
1 1 1 1 DQ26 DQ27
1
0.022U_0402_16V7K
85 86
VSS41 VSS42
CD9
CD10
CD11
CD12
CD13
CD14
CD15
CD16
CD18
CD19
CD20
CD21
1K_0402_1%
87 88
CB5/NC CB4/NC
1
89 90
2
VSS43 VSS44
1
2 2 2 2
RD16
CD31
91 92
93 CB1/NC CB0/NC 94
95 VSS45 VSS46 96
2
97 DQS8_c DM8_n/DBI_n/NC 98
2
99 DQS8_t VSS47 100
VSS48 CB6/NC
1
24.9_0402_1%
101 102
CB2/NC VSS49
RD18
103 104
C VSS50 CB7/NC C
105 106
107 CB3/NC VSS51 108 DDR_DRAMRST#_R
DDR_A_CKE0 109 VSS52 RESET_n 110 DDR_A_CKE1
<7> DDR_A_CKE0 DDR_A_CKE1 <7> 1
2
111 CKE0 CKE1 112
DDR_A_BG1 113 VDD1 VDD2 114 DDR_A_ACT# CD29 @
<7> DDR_A_BG1 DDR_A_BG0 BG1 ACT_n DDR_A_ALERT# DDR_A_ACT# <7>
115 116 0.1U_0402_25V6
<7> DDR_A_BG0 BG0 ALERT_n DDR_A_ALERT# <7> 2
117 118
DDR_A_MA12 119 VDD3 VDD4 120 DDR_A_MA11
DDR_A_MA9 121 A12 A11 122 DDR_A_MA7
123 A9 A7 124
DDR_A_MA8 125 VDD5 VDD6 126 DDR_A_MA5
Layout Note: DDR_A_MA6 127 A8 A5 128 DDR_A_MA4
A6 A4
Place near DDR_A_MA3
129
131 VDD7 VDD8
130
132 DDR_A_MA2 JDIMM1_EVENT# 1 2
JDIMM1.258 DDR_A_MA1 133 A3
A1
A2
EVENT_n/NF
134 JDIMM1_EVENT# @ RD14 1K_0402_5%
H_THERMTRIP# <12,21,35>
135 136
DDR_A_CLK0 137 VDD9 VDD10 138 DDR_A_CLK1
<7> DDR_A_CLK0 DDR_A_CLK#0 CK0_t CK1_t/NF DDR_A_CLK#1 DDR_A_CLK1 <7>
139 140
<7> DDR_A_CLK#0 CK0_c CK1_c/NF DDR_A_CLK#1 <7>
141 142
DDR_A_PARITY 143 VDD11 VDD12 144 DDR_A_MA0
<7> DDR_A_PARITY PARITY A0
+DDR_VREF_A_CA DDR_A_BA1 145 146 DDR_A_MA10

<7> DDR_A_BA1 BA1 A10/AP
+0.6V_DDR_VTT 147 148
DDR_A_CS#0 149 VDD13 VDD14 150 DDR_A_BA0
<7> DDR_A_CS#0 DDR_A_MA14 CS0_n BA0 DDR_A_MA16 DDR_A_BA0 <7>
151 152
<7> DDR_A_MA14 WE_n/A14 RAS_n/A16
153 154
VDD15 VDD16
0.1U_0402_10V6K
DDR_A_ODT0 155 156 DDR_A_MA15

<7> DDR_A_ODT0 ODT0 CAS_n/A15
10U_0603_10V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
2.2U_0402_6.3V6M
DDR_A_CS#1 157 158 DDR_A_MA13

1 1 <7> DDR_A_CS#1 CS1_n A13 +DDR_VREF_A_CA
@ CD26
1 1 159 160
VDD17 VDD18
1
CD22
CD23
CD24
CD25
DDR_A_ODT1 161 162 T50 @ PAD~D

<7> DDR_A_ODT1 ODT1 C0/CS2_n/NC +DDR_VREF_A_CA
163 164
2 2 PAD~D @ T51 165 VDD19 VREFCA 166 DIMM1_SA2
2
2 2 167 C1, CS3_n,NC SA2 168

171 DQ37 DQ36 172
175 DQ33 DQ32 176
DDR_A_D27 183 VSS60 DQ39 184
B B
185 DQ38 VSS61 186 DDR_A_D24
DDR_A_D29 187 VSS62 DQ35 188
189 DQ34 VSS63 190 DDR_A_D20
DDR_A_D21 191 VSS64 DQ45 192
193 DQ44 VSS65 194 DDR_A_D16
DDR_A_D17 195 VSS66 DQ41 196
197 DQ40 VSS67 198 DDR_A_DQS#2
DIMM Select +3.3V_RUN +3.3V_RUN +3.3V_RUN
+3.3V_RUN DDR_A_D19
199
201
203
VSS68
DM5_n/DBI5_n
VSS69
DQS5_c
DQS5_t
VSS70
200
202
204
DDR_A_DQS2
DDR_A_D18 +1.2V_MEM
DQ46 DQ47
1
205 206
@ RD4 @ RD6 @ RD8 DDR_A_D22 207 VSS71 VSS72 208 DDR_A_D23 UD1
1
0_0402_5% 0_0402_5% 0_0402_5% @ 209 DQ42 DQ43 210 1 5 1 2

RD10 DDR_A_D48 211 VSS73 VSS74 212 DDR_A_D53 NC VCC @ CD32 0.1U_0201_10V6K
213 DQ52 DQ53 214 2
0_0603_5%
2
DDR_A_D49 VSS75 VSS76 DDR_A_D52 <7> DDR_VTT_CTRL A

215 216 4
DIMM1_SA0 DQ49 DQ48 Y 0.6V_DDR_VTT_ON <45>
217 218 3
2
DIMM1_SA1 +3.3V_RUN_DIMM1 DDR_A_DQS#6 219 VSS77 VSS78 220 GND 1 2

DIMM1_SA2 DQS6_c DM6_n/DBI6_n +3.3V_RUN
0.1U_0201_10V6K
DDR_A_DQS6 221 222 74AUP1G07SE-7_SOT353_5P RD19 100K_0402_5%

SA0 SA1 SA2 DQS6_t VSS79
2.2U_0402_6.3V6M
223 224 DDR_A_D54

1 1 VSS80 DQ54
1
CD28
@ @ @ DDR_A_D50 225 226 CHECK

* DIMM1 0 0 0 DQ55 VSS81
CD27
RD5 RD7 RD9 227 228 DDR_A_D55

DDR_A_D51 229 VSS82 DQ50 230
DIMM2 1 0 0 0_0402_5% 0_0402_5% 0_0402_5%
2 2 231 DQ51 VSS83 232 DDR_A_D61
DDR_A_D56 233 VSS84 DQ60 234
DIMM3 0 1 0
2
235 DQ61 VSS85 236 DDR_A_D60

DDR_A_D57 237 VSS86 DQ57 238
DIMM4 1 1 0 239 DQ56 VSS87 240 DDR_A_DQS#7
241 VSS88 DQS7_c 242 DDR_A_DQS7
247 DQ62 DQ63 248
251 DQ58 DQ59 252
253 VSS93 VSS94 254
<8,14,21> DDR_XDP_WAN_SMBCLK +3.3V_RUN_DIMM1 SCL SDA DIMM1_SA0 DDR_XDP_WAN_SMBDAT <8,14,21>
255 256
257 VDDSPD SA0 258
+2.5V_MEM VPP1 VTT DIMM1_SA1 +0.6V_DDR_VTT
259 260
261 VPP2 SA1 262
GND1 GND2
A A
LCN_DAN05-Q0406-0103
CONN@
LINK SP07001D200 DONE
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DDR4
5 4 3 2 1
5 4 3 2 1
For DDR4
<7> DDR_B_DQS#[0..7] JDIMM2 REV Type H=5.2
+1.2V_MEM +1.2V_MEM
<7> DDR_B_D[0..63]
JDIMM2
<7> DDR_B_DQS[0..7]
1 2
DDR_B_D1 3 VSS1 VSS2 4 DDR_B_D5
<7> DDR_B_MA[0..16] DQ5 DQ4
5 6
9 DQ1 DQ0 10
DDR_B_DQS#0 11 VSS5 VSS6 12
DDR_B_DQS0 13 DQS0_c DM0_n/DBI0_n 14
15 DQS0_t VSS7 16 DDR_B_D2
DDR_B_D7 17 VSS8 DQ6 18
19 DQ7 VSS9 20 DDR_B_D3
Layout Note: DDR_B_D6 21 VSS10 DQ2 22
DQ3 VSS11
D
Place near JDIMM2 DDR_B_D13
23
25 VSS12 DQ12
24
26
DDR_B_D9
D
27 DQ13 VSS13 28 DDR_B_D8
DDR_B_D12 29 VSS14 DQ8 30
31 DQ9 VSS15 32 DDR_B_DQS#1
33 VSS16 DQS1_c 34 DDR_B_DQS1
35 DM1_n/DBI_n DQS1_t 36
+1.2V_MEM 39 DQ15 DQ14 40
43 DQ10 DQ11 44
DQ21 DQ20
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
330U_D3_2.5VY_R6M
47 48
51 DQ17 DQ16 52
VSS25 VSS26
@ CD49
DDR_B_DQS#4 53 54
DQS2_c DM2_n/DBI2_n
1
1
CD33
CD34
CD35
CD36
CD37
CD38
CD39
CD40
+ DDR_B_DQS4 55 56
57 DQS2_t VSS27 58 DDR_B_D34
DDR_B_D39 59 VSS28 DQ22 60
2
2
61 DQ23 VSS29 62 DDR_B_D35
DDR_B_D38 63 VSS30 DQ18 64
65 DQ19 VSS31 66 DDR_B_D40
DDR_B_D42 67 VSS32 DQ28 68
69 DQ29 VSS33 70 DDR_B_D41
DDR_B_D43 71 VSS34 DQ24 72
+1.2V_MEM +2.5V_MEM 75 VSS36 DQS3_c 76 DDR_B_DQS5
81 DQ30 DQ31 82
VSS39 VSS40
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_10V6M
10U_0603_10V6M
DDR_B_D45 83 84 DDR_B_D47
85 DQ26 DQ27 86
1 1 1 1
1
87 VSS41 VSS42 88
CB5/NC CB4/NC
CD41
CD42
CD43
CD44
CD45
CD46
CD47
CD48
CD50
CD51
CD52
CD53
89 90
91 VSS43 VSS44 92 JDIMM2_EVENT# 1 2
2
2 2 2 2 CB1/NC CB0/NC H_THERMTRIP# <12,20,35>

93 94 @ RD27 1K_0402_5%
95 VSS45 VSS46 96
97 DQS8_c DM8_n/DBI_n/NC 98
99 DQS8_t VSS47 100
101 VSS48 CB6/NC 102
103 CB2/NC VSS49 104
105 VSS50 CB7/NC 106
107 CB3/NC VSS51 108 DDR_DRAMRST#_R
C DDR_B_CKE0 VSS52 RESET_n DDR_B_CKE1 DDR_DRAMRST#_R <20> C
109 110
<7> DDR_B_CKE0 CKE0 CKE1 DDR_B_CKE1 <7>
111 112
DDR_B_BG1 113 VDD1 VDD2 114 DDR_B_ACT#
<7> DDR_B_BG1 BG1 ACT_n DDR_B_ACT# <7> 1
DDR_B_BG0 115 116 DDR_B_ALERT#
<7> DDR_B_BG0 BG0 ALERT_n DDR_B_ALERT# <7>
117 118 @ CD61
DDR_B_MA12 119 VDD3 VDD4 120 DDR_B_MA11 0.1U_0402_25V6
DDR_B_MA9 121 A12 A11 122 DDR_B_MA7 2
123 A9 A7 124
DDR_B_MA8 125 VDD5 VDD6 126 DDR_B_MA5
DDR_B_MA6 127 A8 A5 128 DDR_B_MA4
129 A6 A4 130
DDR_B_MA3 131 VDD7 VDD8 132 DDR_B_MA2
DDR_B_MA1 133 A3 A2 134 JDIMM2_EVENT#
135 A1 EVENT_n/NF 136
DDR_B_CLK0 137 VDD9 VDD10 138 DDR_B_CLK1
<7> DDR_B_CLK0 DDR_B_CLK#0 CK0_t CK1_t/NF DDR_B_CLK#1 DDR_B_CLK1 <7>
139 140
<7> DDR_B_CLK#0 CK0_c CK1_c/NF DDR_B_CLK#1 <7>
141 142
DDR_B_PARITY 143 VDD11 VDD12 144 DDR_B_MA0
<7> DDR_B_PARITY PARITY A0
Layout Note:
Place near <7> DDR_B_BA1
DDR_B_BA1 145
147 BA1 A10/AP
146
148
DDR_B_MA10
JDIMM2.258 <7> DDR_B_CS#0

DDR_B_CS#0 149 VDD13
CS0_n
VDD14
BA0
150 DDR_B_BA0
DDR_B_BA0 <7>
DDR_B_MA14 151 152 DDR_B_MA16
<7> DDR_B_MA14 WE_n/A14 RAS_n/A16
153 154
DDR_B_ODT0 155 VDD15 VDD16 156 DDR_B_MA15
<7> DDR_B_ODT0 DDR_B_CS#1 ODT0 CAS_n/A15 DDR_B_MA13
157 158
<7> DDR_B_CS#1 CS1_n A13 +DDR_VREF_B_CA
159 160
DDR_B_ODT1 161 VDD17 VDD18 162 T54 @ PAD~D
<7> DDR_B_ODT1 ODT1 C0/CS2_n/NC +DDR_VREF_B_CA
+0.6V_DDR_VTT 163 164
PAD~D @ T55 165 VDD19 VREFCA 166 DIMM2_SA2 +1.2V_MEM
+DDR_VREF_B_CA 167 C1, CS3_n,NC SA2 168
VSS53 VSS54
1
DDR_B_D21 DDR_B_D16
1K_0402_1%
169 170
171 DQ37 DQ36 172
DDR_B_D20 VSS55 VSS56 DDR_B_D17
10U_0603_10V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
173 174
RD28
175 DQ33 DQ32 176
1 1 VSS57 VSS58
1
+DDR_VREF_B_CA +DDR_VREF_B_DQ
CD54
CD55
CD56
0.1U_0402_10V6K
2.2U_0402_6.3V6M
DDR_B_DQS#2 177 178
2
DQS4_c DM4_n/DBI4_n
@ CD58
DDR_B_DQS2 179 180

1 1 DQS4_t VSS59
CD57
181 182 DDR_B_D18

2
2 2 DDR_B_D23 183 VSS60 DQ39 184 1 2

185 DQ38 VSS61 186 DDR_B_D19 RD30 2_0402_1%
2 2 VSS62 DQ35
0.022U_0402_16V7K
B
DDR_B_D22 187 188 B
DQ34 VSS63 DDR_B_D28
1K_0402_1%
189 190
VSS64 DQ45
1
DDR_B_D24 191 192
1
DQ44 VSS65 DDR_B_D29
RD29
CD62
193 194
DDR_B_D25 195 VSS66 DQ41 196
2
199 VSS68 DQS5_c 200 DDR_B_DQS3
2
DDR_B_D26 VSS69 VSS70 DDR_B_D31
24.9_0402_1%
203 204
DQ46 DQ47
1
205 206
+3.3V_RUN DDR_B_D27 VSS71 VSS72 DDR_B_D30
RD31
207 208
209 DQ42 DQ43 210
DIMM Select +3.3V_RUN +3.3V_RUN +3.3V_RUN DDR_B_D52 211 VSS73 VSS74 212 DDR_B_D53
1
@ 213 DQ52 DQ53 214
2
RD26 DDR_B_D49 215 VSS75 VSS76 216 DDR_B_D48
DQ49 DQ48
1
@ 0_0603_5% 217 218

@ RD20 RD22 @ RD24 DDR_B_DQS#6 219 VSS77 VSS78 220
0_0402_5% 0_0402_5% DDR_B_DQS6 221 DQS6_c DM6_n/DBI6_n 222
0_0402_5%
2
+3.3V_RUN_DIMM2 223 DQS6_t VSS79 224 DDR_B_D50

DDR_B_D55 225 VSS80 DQ54 226
2
227 DQ55 VSS81 228 DDR_B_D51

VSS82 DQ50
2.2U_0402_6.3V6M
DIMM2_SA0
0.1U_0201_10V6K
DDR_B_D54 229 230

1 DQ51 VSS83
1
DIMM2_SA1 231 232 DDR_B_D61

DIMM2_SA2 DDR_B_D56 VSS84 DQ60
CD59
CD60
233 234
SA0 SA1 SA2 235 DQ61 VSS85 236 DDR_B_D60
2
VSS86 DQ57
1
@ @ 2 DDR_B_D57 237 238

DIMM1 0 0 0 RD21 @ RD23 RD25 239 DQ56 VSS87 240 DDR_B_DQS#7
0_0402_5% 241 VSS88 DQS7_c 242 DDR_B_DQS7
DIMM2 1 0 0 0_0402_5% 0_0402_5%
* DIMM3 0 1 0
2
247 DQ62 DQ63 248

DIMM4 1 1 0 251 DQ58 DQ59 252
253 VSS93 VSS94 254
<8,14,20> DDR_XDP_WAN_SMBCLK +3.3V_RUN_DIMM2 SCL SDA DIMM2_SA0 DDR_XDP_WAN_SMBDAT <8,14,20>
255 256
257 VDDSPD SA0 258
+2.5V_MEM VPP1 VTT DIMM2_SA1 +0.6V_DDR_VTT
259 260
261 VPP2 SA1 262
GND1 GND2
A LCN_DAN05-Q0406-0103 A
CONN@
LINK SP07001D200 DONE
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DDR4
5 4 3 2 1
5 4 3 2 1
For Steamboat12/14 &Kirkwood
+3.3V_RUN
2 1 SW2_DP1_AUXN CV62 CV61 close to pin30 &57 +3.3V_RUN

D RV70 100K_0402_5% CV66,CV69,CV70 close to pin5,21,51 D
2 1 SW2_DP2_AUXN
Priority : AR -> WIGI
0.01UF_0402_25V7K
0.01UF_0402_25V7K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
RV71 100K_0402_5%
2 1 SW2_PS8338_CFG0
1 1 1
CV83
CV84
CV85
RV85 4.7K_0402_5% UV7
CV81
CV82
2 1 SW2_PS8338_SW
RV89 4.7K_0402_5% 5
2
2 1 SW2_PS8338_P0 2 2 2 21 VDD33 50
RV95 4.7K_0402_5% 30 VDD33 OUT1_D0p 49 SW2_DP2_P0 <32>
51 VDD33 OUT1_D0n SW2_DP2_N0 <32>
57 VDD33 47
VDD33 OUT1_D1p 46 SW2_DP2_P1 <32>
OUT1_D1n SW2_DP2_N1 <32>
CV86 1 2 0.1U_0201_10V6K CPU_DP2_P0_C 6 45 WIGI
2 1 SW2_DP1_CADET <6> CPU_DP2_P0 1 2 0.1U_0201_10V6K CPU_DP2_N0_C 7 IN_D0p OUT1_D2p 44 SW2_DP2_P2 <32>
CV87
<6> CPU_DP2_N0 IN_D0n OUT1_D2n SW2_DP2_N2 <32>
RV73 1M_0402_5%
2 1 SW2_DP2_CADET CV88 1 2 0.1U_0201_10V6K CPU_DP2_P1_C 9 42
<6> CPU_DP2_P1 1 2 0.1U_0201_10V6K CPU_DP2_N1_C 10 IN_D1p OUT1_D3p 41 SW2_DP2_P3 <32>
RV74 1M_0402_5% CV89
2 1 SW2_DP1_AUXP <6> CPU_DP2_N1 IN_D1n OUT1_D3n SW2_DP2_N3 <32>
RV76 100K_0402_5% CV90 1 2 0.1U_0201_10V6K CPU_DP2_P2_C12
2 1 SW2_DP2_AUXP <6> CPU_DP2_P2 1 2 0.1U_0201_10V6K CPU_DP2_N2_C 13 IN_D2p 40
CV91
<6> CPU_DP2_N2 IN_D2n OUT2_D0p 39 SW2_DP1_P0 <24>
RV77 100K_0402_5%
CV92 1 2 0.1U_0201_10V6K CPU_DP2_P3_C15 OUT2_D0n SW2_DP1_N0 <24>
<6> CPU_DP2_P3 1 2 0.1U_0201_10V6K CPU_DP2_N3_C 16 IN_D3p 37
CV93
<6> CPU_DP2_N3 IN_D3n OUT2_D1p 36 SW2_DP1_P1 <24>
OUT2_D1n SW2_DP1_N1 <24>
35
+3.3V_RUN 4 OUT2_D2p 34 SW2_DP1_P2 <24> AR
3 IN_CA_DET OUT2_D2n SW2_DP1_N2 <24>
<6> CPU_DP2_HPD 2 IN_HPD 32
SW2_PS8338_P1 1 I2C_CTL_EN OUT2_D3p 31 SW2_DP1_P3 <24>
SW2_PS8338_P0 60 Pl1/SCL_CTL OUT2_D3n SW2_DP1_N3 <24>
C Pl0/SDA_CTL C
2
2
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
@ @ @ @ @ for support TMDS signal need contact SCL/SDA to P22,23 26

22 OUT1_AUXp_SCL 27 SW2_DP2_AUXP <32>
<6> CPU_DP2_CTRL_CLK SW2_DP2_AUXN <32>
RV79
RV81
RV83
RV91
RV87
RV93
23 IN_DDC_SCL OUT1_AUXn_SDA
<6> CPU_DP2_CTRL_DATA 1 2 0.1U_0201_10V6K CPU_DP2_AUXP_C 24 IN_DDC_SDA 28
CV94
<6> CPU_DP2_AUXP 1 2 0.1U_0201_10V6K CPU_DP2_AUXN_C 25 IN_AUXp OUT2_AUXp_SCL 29 SW2_DP1_AUXP <24>
CV95
1
SW2_PS8338_P1 <6> CPU_DP2_AUXN IN_AUXn OUT2_AUXn_SDA SW2_DP1_AUXN <24>

SW2_PS8338_CFG0 59 43 SW2_DP2_CADET
SW2_PS8338_PEQ 58 CFG0 OUT1_CA_DET 48
SW2_PS8338_PC10 56 CFG1 OUT1_HPD SW2_DP2_HPD <32>
SW2_PS8338_PC10 SW2_PS8338_PC11 55 PC10 33 SW2_DP1_CADET
SW2_PS8338_PC20 54 PC11 OUT2_CA_DET 38
SW2_PS8338_PC11 SW2_PS8338_PC21 53 PC20 OUT2_HPD SW2_DP1_HPD <24>
PC21 18 SW2_PS8338_SW
SW2_PS8338_PC20 11 SW 8 SW2_PS8338_PEQ
19 GND PEQ 14
SW2_PS8338_PC21 52 GND PD 17
GND CEXT
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
61 20
PAD(GND) REXT
1
2.2U_0402_6.3V6M
1
4.99K_0402_1%
RV80
RV82
RV84
RV90
RV88
RV94
PS8338BQFN60GTR-A0_QFN60_5X9
1
RV97
CV96
@ @ @ @ @
2
2
2
B Port switching control or priority configuration. Internal pull down ~150KΩ, B
3.3V I/O
For Control Switching Mode (CFG0 = L):
SW = L: Port1 is selected (default)
SW = H: Port2 is selected
For Automatic Switching Mode (CFG0 = H):
SW = L: Port1 has higher priority when both ports are plugged
SW = H: Port2 has higher priority when both ports are plugged (default)
vender sugguest MUX use LLEQ PEQ=M and PI0=H !!
Programmable input equalization levels, Internal pull down at ~150Kohm,3.3V I/O

PEQ =
L: default,LEQ, compensate channel loss up to 11.5dB @HBR2
H: HEQ, compensate channel loss up to 14.5dB @HBR2
M:LLEQ, compensate channel loss up to 8.5dB @HBR2
PI0:Automatic EQ disable, Internal pull down ~150K ohm, 3.3V I/O

PI0 = L: Automatic EQ enable(default)
H: Automatic EQ disable
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DP SW2 PS8338
5 4 3 2 1
5 4 3 +5V_RUN 2 1
For passive level shifter from AR
0.1U_0201_10V6K
1
1
CV39
+VHDMI_VCC
2
IN
AP2330W-7_SC59-3
UV2
0.1U_0201_10V6K
10U_0603_10V6M
EMI@ LV31 12NH_LQG15HN12NJ02D_5% 1
CV41
1 2
GND
OUT
HDMI_L_TX_P2 @
HCM1012GH900BP_4P
CV40
D D
2
2
1 2 HDMI_TX_P2 2 3 EMI@ 2
<24> AR_DP1_P0
3
CV31 0.1U_0402_25V6 2 3 RV26
<24> AR_DP1_N0
1 2 HDMI_TX_N2 1
4 1
4
300_0402_5% HDMI connector
CV32 0.1U_0402_25V6
1
@EMI@ HDMI_L_TX_N2
LV3
2 1 ACON_HMRBL-A41L0F
EMI@ LV32
12NH_LQG15HN12NJ02D_5%
EMI@ LV33
12NH_LQG15HN12NJ02D_5% HDMI_HPD 19
1 2 18 HPD
HDMI_L_TX_P1 17 +5V
HCM1012GH900BP_4P +3.3V_RUN HDMI_CTRL_DATA 16 DDC/CEC GND 23
SDA GND
2
1 2 HDMI_TX_P1 2 3 EMI@ HDMI_CTRL_CLK 15 22
<24> AR_DP1_P1 2 3 SCL GND
CV33 0.1U_0402_25V6 RV29 14 21
2 1 HDMI_CEC 13 Reserved GND 20
300_0402_5% CEC GND
1 2 HDMI_TX_N1 1 4 10K_0402_5% @ RV19 HDMI_L_CLKN 12
<24> AR_DP1_N1 1 4 CK-
CV34 0.1U_0402_25V6 11
1
@EMI@ LV6 HDMI_L_TX_N1 HDMI_L_CLKP 10 CK_Shield
1 2 HDMI_L_TX_N0 9 CK+
EMI@ LV34 12NH_LQG15HN12NJ02D_5% 8 D0-
EMI@ LV35 12NH_LQG15HN12NJ02D_5% HDMI_L_TX_P0 7 D0_Shield
1 2 HDMI_L_TX_N1 6 D0+
HDMI_L_TX_P0 5 D1-
HCM1012GH900BP_4P HDMI_L_TX_P1 4 D1_Shield
D1+
2
1 2 HDMI_TX_P0 2 3 EMI@ HDMI_L_TX_N2 3
<24> AR_DP1_P2 2 3 D2-
CV35 0.1U_0402_25V6 RV32 2
HDMI_L_TX_P2 1 D2_Shield
300_0402_5% D2+
1 2 HDMI_TX_N0 1 4
<24> AR_DP1_N2 1 4
CV36 0.1U_0402_25V6
1
@EMI@ LV9 HDMI_L_TX_N0 JHDMI1 CONN@
1 2
EMI@ LV36 12NH_LQG15HN12NJ02D_5%
EMI@ LV37 12NH_LQG15HN12NJ02D_5% LINK DC231604012 (temp) DONE
1 2
HDMI_L_CLKP
C HCM1012GH900BP_4P HDMI_TX_P2 RV10 1 2 470_0402_1% HDMI_OB

C
2
2 1 HDMI_CLKP 2 3 EMI@ HDMI_TX_N2 RV11 1 2 470_0402_1%
<24> AR_DP1_P3 0.1U_0402_25V6 2 3 HDMI_TX_P1
CV37 RV35 RV12 1 2 470_0402_1%
300_0402_5% HDMI_TX_N1 RV13 1 2 470_0402_1%
2 1 HDMI_CLKN 1 4 HDMI_TX_P0 RV14 1 2 470_0402_1%
<24> AR_DP1_N3 0.1U_0402_25V6 1 4 HDMI_TX_N0 1 2
CV38 RV15 470_0402_1%
1
@EMI@ LV12 HDMI_L_CLKN HDMI_CLKP RV16 1 2 470_0402_1%
HDMI_CLKN RV17 1 2 470_0402_1%
1 2
EMI@ LV38 12NH_LQG15HN12NJ02D_5%
1
D
RV18 1 2 10K_0402_5% 2 QV4
+3.3V_RUN
G L2N7002WT1G_SC-70-3
S
3
+3.3V_RUN
1M_0402_5%
2
RV20
2
G
1
3 1 HDMI_HPD 1 2
B <24> AR_DP1_HPD RV21 20K_0402_5%
B
S
QV5
L2N7002WT1G_SC-70-3
+3.3V_RUN
QV3A +VHDMI_VCC
2
DMN65D8LDW-7_SOT363-6
1 6 HDMI_CTRL_CLK 1 2
<24> AR_DP1_CTRL_CLK
RV22 2.2K_0402_5%
5
4 3 HDMI_CTRL_DATA 1 2
<24> AR_DP1_CTRL_DATA
RV23 2.2K_0402_5%
QV3B
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT HDMI CONN
5 4 3 2 1
5 4 3 2 1
+3.3V_TBT_LC
For Steamboat 12/14
+3.3V_TBT_FLASH_R +3.3V_TBT_FLASH_R
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
+3.3V_TBT_FLASH_R +3.3V_TBT_LC +3.3V_TBTA_FLASH
2
+3.3V_ALW_PCH
RT5
RT6
RT7
RT8
0_0402_5% 1 2 @ RT9
0.1U_0201_10V6K
1
2.2K_0402_5%
2.2K_0402_5%
2
2
TBT_JTAG_TDI
3.3K_0402_5%
3.3K_0402_5%
1
TBT_JTAG_TMS
CT1
0_0402_5% 2 1 @ RT10
TBT_JTAG_TCK TBT_CIO_PLUG_EVENT# RT391 1 2 10K_0402_5%
TBT_JTAG_TDO For backdrive issue
RT1
RT2
RT3
RT4
2
1
1
Rework Debug Pin1 +3.3V_TBT_LC, Pin6 GND
UT2
D 8 1 TBT_ROM_CS# D
TBT_ROM_HOLD# 7 VCC CS# 2 TBT_ROM_DO
TBT_ROM_CLK 6 HOLD#(IO3) DO(IO1) 3 TBT_ROM_WP# +3.3V_TBT
TBT_ROM_DI 5 CLK WP#(IO2) 4
DI(IO0) GND
W25Q80DVSSIG_SO8 TBT_RESET_N_EC @ RT11 1 2 10K_0402_5%
UT1A
CT2 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_P8 Y23 V23 PCIE_PRX_C_DTX_P8 CT6 1 2 0.22U_0201_6.3V6K
<10> PCIE_PTX_DRX_P8 PCIE_RX0_P PCIE_TX0_P PCIE_PRX_DTX_P8 <10>
CT3 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_N8 Y22 V22 PCIE_PRX_C_DTX_N8 CT7 1 2 0.22U_0201_6.3V6K AR_DP1_CTRL_DATA RT12 1 2 2.2K_0402_5%
<10> PCIE_PTX_DRX_N8 PCIE_RX0_N PCIE_TX0_N PCIE_PRX_DTX_N8 <10> AR_DP1_CTRL_CLK RT13 1 2 2.2K_0402_5%
CT4 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_P7 T23 P23 PCIE_PRX_C_DTX_P7 CT8 1 2 0.22U_0201_6.3V6K DPSNK0_DDC_CLK @ RT14 1 2 2.2K_0402_5%
2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_N7 P22 PCIE_PRX_C_DTX_N7 DPSNK0_DDC_DATA
PCIe GEN3
CT5 1 T22 CT9 1 2 0.22U_0201_6.3V6K @ RT15 1 2 2.2K_0402_5%
<10> PCIE_PTX_DRX_N7 PCIE_RX1_N PCIE_TX1_N PCIE_PRX_DTX_N7 <10> DPSNK1_DDC_CLK @ RT336 1 2 2.2K_0402_5%
CT123 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_P6 M23 K23 PCIE_PRX_C_DTX_P6 CT127 1 2 0.22U_0201_6.3V6K SNK0_CONFIG1 @ RT337 1 2 2.2K_0402_5%
<10> PCIE_PTX_DRX_P6 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_N6 M22 PCIE_RX2_P PCIE_TX2_P K22 PCIE_PRX_C_DTX_N6 1 2 0.22U_0201_6.3V6K PCIE_PRX_DTX_P6 <10>
CT124 CT128
<10> PCIE_PTX_DRX_N6 PCIE_RX2_N PCIE_TX2_N PCIE_PRX_DTX_N6 <10>
SNK0_DDC_data/clk – connect to 2k PU only if
CT125 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_P5 H23 F23 PCIE_PRX_C_DTX_P5 CT129 1 2 0.22U_0201_6.3V6K SRC0 is connected and support HDMI (a.i HDMI
CT126 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_N5 H22 F22 PCIE_PRX_C_DTX_N5 CT130 1 2 0.22U_0201_6.3V6K or DP++ connector). Otherwise can be 100k PD.
<10> PCIE_PTX_DRX_N5 PCIE_RX3_N PCIE_TX3_N PCIE_PRX_DTX_N5 <10>
PCH_PLTRST#_AND
SNK1_DDC_data – connect to 100k PD. If SRC0
V19 L4
<11> CLK_PCIE_P5 T19 PCIE_REFCLK_100_IN_P PERST_N PCH_PLTRST#_AND <11,31,32,36,37> support HDMI, connect as SNK0_CFG1 to GPU
<11> CLK_PCIE_N5
AC5 PCIE_REFCLK_100_IN_N N16 TBT_PCIE_RBIAS 1 2 and/or appropriate AUX/DDC demux control
<11> CLKREQ_PCIE#5 PCIE_CLKREQ_N PCIE_RBIAS RT34 3.01K_0402_1% SNK1_DDC_clk – connect to 100k PD.
CT10 1 2 0.1U_0201_10V6K CPU_DP1_P0_C AB7 R2 AR_DP1_P0
<6> CPU_DP1_P0 CPU_DP1_N0_C DPSNK0_ML0_P DPSRC_ML0_P AR_DP1_N0 AR_DP1_P0 <23> AR_DP1_P0 AR_DP1_N0
CT11 1 2 0.1U_0201_10V6K AC7 R1 1 2
<6> CPU_DP1_N0 DPSNK0_ML0_N DPSRC_ML0_N AR_DP1_N0 <23> @ CT201 1P_0201_50V8C
CT12 1 2 0.1U_0201_10V6K CPU_DP1_P1_C AB9 N2 AR_DP1_P1 AR_DP1_P1 1 2 AR_DP1_N1
<6> CPU_DP1_P1 CPU_DP1_N1_C DPSNK0_ML1_P DPSRC_ML1_P AR_DP1_N1 AR_DP1_P1 <23> +3.3V_TBT_SX
CT13 1 2 0.1U_0201_10V6K AC9 N1 @ CT202 1P_0201_50V8C
<6> CPU_DP1_N1 DPSNK0_ML1_N DPSRC_ML1_N AR_DP1_N1 <23>
SOURCE PORT 0
AR_DP1_P2 1 2 AR_DP1_N2
CPU
SINK PORT 0
CT14 1 2 0.1U_0201_10V6K CPU_DP1_P2_C AB11 L2 AR_DP1_P2 @ CT203 1P_0201_50V8C
<6> CPU_DP1_P2 CPU_DP1_N2_C DPSNK0_ML2_P DPSRC_ML2_P AR_DP1_N2 AR_DP1_P2 <23> AR_DP1_P3 AR_DP1_N3 TBTA_I2C_INT
CT15 1 2 0.1U_0201_10V6K AC11 L1 1 2 RT16 1 2 10K_0402_5%
<6> CPU_DP1_N2 DPSNK0_ML2_N DPSRC_ML2_N AR_DP1_N2 <23> TBTB_I2C_INT
@ CT204 1P_0201_50V8C RT17 1 2 10K_0402_5%
CT16 1 2 0.1U_0201_10V6K CPU_DP1_P3_C AB13 J2 AR_DP1_P3
<6> CPU_DP1_P3 CPU_DP1_N3_C DPSNK0_ML3_P DPSRC_ML3_P AR_DP1_N3 AR_DP1_P3 <23> TBT_I2C_SDA
CT17 1 2 0.1U_0201_10V6K AC13 J1 RT18 1 2 2.2K_0402_5%
<6> CPU_DP1_N3 DPSNK0_ML3_N DPSRC_ML3_N AR_DP1_N3 <23> Close UT1 TBT_I2C_SCL RT19 1 2 2.2K_0402_5%
<6> CPU_DP1_AUXP CT18 1
CT19 1
2 0.1U_0201_10V6K
2 0.1U_0201_10V6K
CPU_DP1_AUXP_C
CPU_DP1_AUXN_C
Y11
W11 DPSNK0_AUX_P DPSRC_AUX_P
W19
Y19
Intel Review request
C <6> CPU_DP1_AUXN DPSNK0_AUX_N DPSRC_AUX_N 20160324 TDOCK_BATLOW# RT20 1 2 10K_0402_5% C
AA2 G1 AR_DP1_HPD
<6> CPU_DP1_HPD DPSNK0_HPD DPSRC_HPD AR_DP1_HPD <23> TBT_SRC_CFG1 RT338 1 2 10K_0402_5%
1 2 DPSNK0_DDC_CLK Y5 N6 TBT_DP_RBIAS 1 2
<6> CPU_DP1_CTRL_CLK @ RT341 DPSNK0_DDC_DATA DPSNK0_DDC_CLK DPSRC_RBIAS TBT_CIO_PLUG_EVENT# @ RT371 1
1 2 0_0402_5% R4 RT35 14K_0402_1% 2 10K_0402_5%
<6> CPU_DP1_CTRL_DATA @ RT342 0_0402_5% DPSNK0_DDC_DATA U1 TBT_I2C_SDA RTD3_CIO_PWR_EN @ RT372 1 2 10K_0402_5% Intel review request
GPIO_0 TBT_I2C_SDA <26>
<22> SW2_DP1_P0
CT177 1
CT176 1
2 0.1U_0201_10V6K
2 0.1U_0201_10V6K
SW2_DP1_P0_C
SW2_DP1_N0_C
AB15
AC15 DPSNK1_ML0_P GPIO_1
U2
V1
TBT_I2C_SCL
TBT_ROM_WP# TBT_I2C_SCL <26> TBTA_LSRX RT21 1 2 1M_0402_5%
20160324
LC GPIO
<22> SW2_DP1_N0 DPSNK1_ML0_N GPIO_2 V2 TBT_TMU_CLK_OUT TBTA_LSTX 1 2
RT22 1M_0402_5%
CT172 1 2 0.1U_0201_10V6K SW2_DP1_P1_C AB17 GPIO_3 W1 PCIE_WAKE# TBTA_HPD RT23 1 2 100K_0402_5%
<22> SW2_DP1_P1 SW2_DP1_N1_C DPSNK1_ML1_P GPIO_4 TBT_CIO_PLUG_EVENT# PCIE_WAKE# <32,35,37> CPU_DP1_HPD
CT171 1 2 0.1U_0201_10V6K AC17 W2 RT24 1 2 100K_0402_5%
<22> SW2_DP1_N1 DPSNK1_ML1_N GPIO_5 AR_DP1_CTRL_DATA TBT_CIO_PLUG_EVENT# <12> RTD3_CIO_PWR_EN
Y1 RT25 1 2 100K_0402_5%
PS8338 CT174 1 2 0.1U_0201_10V6K SW2_DP1_P2_C AB19 GPIO_6 Y2 AR_DP1_CTRL_CLK AR_DP1_CTRL_DATA <23> RTD3_USB_PWR_EN RT26 1 2 100K_0402_5%
<22> SW2_DP1_P2
SINK PORT 1
CT168 1 2 0.1U_0201_10V6K SW2_DP1_N2_C AC19 DPSNK1_ML2_P GPIO_7 AA1 TBT_SRC_CFG1 AR_DP1_CTRL_CLK <23> TBT_FORCE_PWR RT27 1 2 10K_0402_5%
<22> SW2_DP1_N2 DPSNK1_ML2_N GPIO_8 TBTA_I2C_INT TBT_TMU_CLK_OUT
J4 RT28 1 2 100K_0402_5%
SW2_DP1_P3_C POC_GPIO_0 TBTB_I2C_INT TBTA_I2C_INT <26> SW2_DP1_HPD
CT173 1 2 0.1U_0201_10V6K AB21 E2 @ RT29 1 2 100K_0402_5%
POC GPIO
<22> SW2_DP1_P3 SW2_DP1_N3_C DPSNK1_ML3_P POC_GPIO_1 RTD3_USB_PWR_EN
CT170 1 2 0.1U_0201_10V6K AC21 D4
<22> SW2_DP1_N3 DPSNK1_ML3_N POC_GPIO_2 TBT_FORCE_PWR
H4
CT169 1 2 0.1U_0201_10V6K SW2_DP1_AUXP_C Y12 POC_GPIO_3 F2 TDOCK_BATLOW# TBT_FORCE_PWR <6> TBT_SRC_CFG1 @ RT30 1 2 1M_0402_5%
<22> SW2_DP1_AUXP SW2_DP1_AUXN_C DPSNK1_AUX_P POC_GPIO_4 SIO_SLP_S3# TBTB_LSTX
<22> SW2_DP1_AUXN CT175 1 2 0.1U_0201_10V6K W12 D2 RT31 1 2 100K_0402_5%
DPSNK1_AUX_N POC_GPIO_5 F1 RTD3_CIO_PWR_EN_R 1 SIO_SLP_S3#
2 <11,34,35> TBTB_LSRX RT32 1 2 100K_0402_5%
SW2_DP1_HPD Y6 POC_GPIO_6 @ RT392 0_0402_5% RTD3_CIO_PWR_EN <9> TBTB_HPD RT33 1 2 100K_0402_5%
<22> SW2_DP1_HPD DPSNK1_HPD E1 TEST_EN 1 2
DPSNK1_DDC_CLK Y8 TEST_EN RT36 100_0402_5%
Misc
SNK0_CONFIG1 N4 DPSNK1_DDC_CLK AB5 TEST_PWRGD 1 2

DPSNK1_DDC_DATA TEST_PWR_GOOD RT37 100_0402_5%
2 1 DPSNK_RBIAS Y18 F4 TBT_RESET_N_EC
DPSNK_RBIAS RESET_N TBT_RESET_N_EC <26,34> AR_DP1_CTRL_DATA
RT38 14K_0402_1% @ RT124 1 2 100K_0402_5%
TBT_JTAG_TDI Y4 D22 XTAL_25_IN AR_DP1_CTRL_CLK @ RT125 1 2 100K_0402_5%
TBT_JTAG_TMS V4 TDI XTAL_25_IN D23 XTAL_25_OUT 1 2 XTAL_25_OUT_R DPSNK0_DDC_CLK @ RT126 1 2 100K_0402_5%
TBT_JTAG_TCK T4 TMS XTAL_25_OUT @ RT40 0_0402_5% DPSNK0_DDC_DATA @ RT127 1 2 100K_0402_5%
TBT_JTAG_TDO W4 TCK AB3 TBT_ROM_DI DPSNK1_DDC_CLK RT128 1 2
TDO MISC EE_DI TBT_ROM_DO
YT1
SNK0_CONFIG1
100K_0402_5%
AC4 3 1 RT129 1 2 100K_0402_5%
1 2 TBT_RBIAS H6 EE_DO AC3 TBT_ROM_CS# OUT IN
RT39 4.75K_0402_1% TBT_RSENSE J6 RBIAS EE_CS_N AB4 TBT_ROM_CLK 4 2
RSENSE EE_CLK GND GND
27P_0402_50V8J
27P_0402_50V8J
1
1
A15 B7 25MHZ 10PF 7V25000034
<28> TBTA_RX2P PA_RX1_P PB_RX1_P
CT20
CT21
B15 A7
<28> TBTA_RX2N PA_RX1_N PB_RX1_N
B B
2
A17 A9
<28> TBTA_TX2P B17 PA_TX1_P PB_TX1_P B9
<28> TBTA_TX2N PA_TX1_N PB_TX1_N
A19 A11
<28> TBTA_TX1P B19 PA_TX0_P PB_TX0_P B11
<28> TBTA_TX1N PA_TX0_N PB_TX0_N
TBT PORTS
B21 A13
<28> TBTA_RX1P PA_RX0_P PB_RX0_P
A21 B13
Port A
PORT B
<28> TBTA_RX1N PA_RX0_N PB_RX0_N

Type C Y15 Y16
<26> TBTA_AUXP PA_DPSRC_AUX_P PB_DPSRC_AUX_P
W15 W16
<26> TBTA_AUXN PA_DPSRC_AUX_N PB_DPSRC_AUX_N
E20 E19
<26> TBTA_USB20_P PA_USB2_D_P PB_USB2_D_P
D20 D19
<26> TBTA_USB20_N PA_USB2_D_N PB_USB2_D_N
TBTA_LSTX A5 B4 TBTB_LSTX
<26> TBTA_LSTX PA_LSTX PB_LSTX
POC
TBTA_LSRX TBTB_LSRX
POC
A4 B5
<26> TBTA_LSRX TBTA_HPD PA_LSRX PB_LSRX TBTB_HPD
M4 G2
<26> TBTA_HPD PA_DPSRC_HPD PB_DPSRC_HPD
2 1 TBTA_USB2_RBIAS H19 F19 TBTB_USB2_RBIAS 1 2
RT41 499_0402_1% PA_USB2_RBIAS PB_USB2_RBIAS RT42 499_0402_1%
AC23 D6
AB23 THERMDA MONDC_SVR
THERMDA A23
V18 ATEST_P B23
PCIE_ATEST ATEST_N
AC1 DEBUG E18
TEST_EDM USB2_ATEST
L15 W13
N15 FUSE_VQPS_64 MONDC_DPSNK_0
FUSE_VQPS_128 W18
C23 MONDC_DPSNK_1
C22 MONDC_CIO_0 AB2
MONDC_CIO_1 MONDC_DPSRC
ALPINE-RIDGE_BGA337
A A
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
TBT-AR-SP(1/2) DP, PCIE
Size Document Number Rev
5 4 3 2 1
A B C D E
For Steamboat 12/14 &kirkwood,For AR
+0.9V_TBT_DP +0.9V_TBT_USB
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
+3.3V_ALW
PJP6
+3.3V_VDD_PIC @ +3.3V_TBT_SX +3.3V_TBT
1 1 1 1 1 1 1 1 1 1 2 1 2
CT25
CT26
CT27
CT28
CT29
CT30
CT31
CT32
CT33
1 @ RT48 0_0603_5% VCC3P3_SVR:3.3V @ 0.6A max 1
PAD-OPEN1x1m +3.3V_TBT_LC 1 2
@ RT49 0_0603_5%
2 2 2 2 2 2 2 2 2 +3.3V_TBT_S0
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
CT44
CT45
CT46
CT47
1 1 1 1 1 1 1
CT41
CT42
CT43
2 2 2 2 2 2 2
<BOM Structure>
R13
+0.9V_TBT_PCIE +0.9V_TBT_CIO +0.9V_TBT_DP
R6
H9
F8
UT1B
L8 A2 VCC0P9_SVR:0.9V @ 1.8A max
VCC3P3_LC
VCC3P3_SX
VCC3P3A
VCC3P3_S0
L11 VCC0P9_DP VCC3P3_SVR A3
VCC0P9_DP VCC3P3_SVR Minimum of 4vias must be used
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
L12 B3
M8 VCC0P9_DP VCC3P3_SVR +0.9V_TBT_SVR
T11 VCC0P9_DP
1 1 1 1 1 1 1 VCC0P9_DP
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
CT34
CT35
CT36
CT37
CT38
CT39
CT40
T12 L9
L6 VCC0P9_DP VCC0P9_SVR M9
M6 VCC0P9_ANA_DPSRC VCC0P9_SVR E12
VCC0P9_ANA_DPSRC VCC0P9_SVR_ANA 1 1 1 1 1 1 1
2 2 2 2 2 2 2
CT48
CT49
CT50
CT51
CT52
CT53
CT54
V11 E13
V12 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F11
+0.9V_TBT_PCIE V13 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F12
VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F13 2 2 2 2 2 2 2
M13 VCC0P9_SVR_ANA F15
M15 VCC0P9_PCIE VCC0P9_SVR_ANA J9
M16 VCC0P9_PCIE VCC0P9_SVR_SENSE
L19 VCC0P9_PCIE
N19 VCC0P9_ANA_PCIE_1 C1 +TBT_SVR_IND LT1 1 2 0.6UH_MND-04ABIR60M-XGL_20%
VCC0P9_ANA_PCIE_1 SVR_IND
47U_0603_6.3V6M
47U_0603_6.3V6M
47U_0603_6.3V6M
L18 C2
VCC0P9_ANA_PCIE_2 SVR_IND
CT55
CT56
CT57
M18 D1 1 1 1
+0.9V_TBT_USB N18 VCC0P9_ANA_PCIE_2 SVR_IND Share Same GND plane
VCC
VCC0P9_ANA_PCIE_2 with SVR_VSS of AR
R15 A1
R16 VCC0P9_USB SVR_VSS B1 2 2 2
+0.9V_TBT_CIO VCC0P9_USB SVR_VSS B2 Intel review request
SVR_VSS
R8 Change 10U*4 to 47U*3
2 TBT Power circuit R9
R11
VCC0P9_CIO
VCC0P9_CIO
VCC0P9_CIO
SVR_VSS:Minimum of 4 vias must be used. +0.9V_TBT_LVR_OUT
20160324 2
1U_0201_6.3V6M
1U_0201_6.3V6M
R12 F18
VCC0P9_CIO VCC0P9_LVR
10U_0402_6.3V6M
10U_0402_6.3V6M
H18
+3.3V_RUN +3.3V_TBT +VCC3V3_ANA_PCIE L16 VCC0P9_LVR J11
VCC3P3_ANA_PCIE VCC0P9_LVR 1 1 1 1
1U_0201_6.3V6M
1U_0201_6.3V6M
CT59
CT60
CT61
CT62
+VCC3V3_ANA_USB2 J16 H11
VCC3P3_ANA_USB2 VCC0P9_LVR_SENSE
@ PJP5 1 1 A6 V5
VSS_ANA VSS_ANA 2 2 2 2
CT63
CT64
2 1 A8 V6
2 1 A10 VSS_ANA VSS_ANA V8
JUMP_43X79 A12 VSS_ANA VSS_ANA V9
2 2 A14 VSS_ANA VSS_ANA V15
A16 VSS_ANA VSS_ANA V16
A18 VSS_ANA VSS_ANA V20
A20 VSS_ANA VSS_ANA W5
A22 VSS_ANA VSS_ANA W6
B6 VSS_ANA VSS_ANA W8
B16 VSS_ANA VSS_ANA Y9
B22 VSS_ANA VSS_ANA AA22
D8 VSS_ANA VSS_ANA AA23
D9 VSS_ANA VSS_ANA AB6
GND
E8 VSS_ANA VSS_ANA AB20
E9 VSS_ANA VSS_ANA AB22
E11 VSS_ANA VSS_ANA AC6
3 3
F9 VSS_ANA VSS_ANA AC16
G22 VSS_ANA VSS_ANA AC22
G23 VSS_ANA VSS_ANA D5
+3.3V_TBT_S0 change pn to SHI0000N600 +3.3V_TBT H1 VSS_ANA VSS E4
H2 VSS_ANA VSS E5
1 2 H12 VSS_ANA VSS E6
LT2 1UH_LQM18NN1R0K00D_10% H13 VSS_ANA VSS F5
VSS_ANA VSS
47U_0805_6.3V6M
47U_0805_6.3V6M
1U_0402_6.3V6K
H15 F6
VSS_ANA VSS
CT67
1 1 H16 H5
VSS_ANA VSS
1
CT68
CT69
H20 H8
J5 VSS_ANA VSS J8
J18 VSS_ANA VSS J12
2
2 2 J19 VSS_ANA VSS J13

J20 VSS_ANA VSS J15
J22 VSS_ANA VSS L13
J23 VSS_ANA VSS M11
K1 VSS_ANA VSS M12
K2 VSS_ANA VSS N8
L5 VSS_ANA VSS N9
L20 VSS_ANA VSS N11
L22 VSS_ANA VSS N12
L23 VSS_ANA VSS N13
M1 VSS_ANA VSS T6
M2 VSS_ANA VSS T8
M5 VSS_ANA VSS T9
M19 VSS_ANA VSS T13
M20 VSS_ANA VSS T15
N5 VSS_ANA VSS T16
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
N20 VSS_ANA VSS T18

N22 VSS_ANA VSS AB1
N23 VSS_ANA VSS AC2
VSS_ANA VSS
P1
P2
R5
R18
R19
R20
R22
R23
T1
T2
T5
T20
U22
U23
4 4
PROPRIETARY NOTE:
TBT-AR-SP(2/2) PWR,VSS
A B C D E
5 4 3 2 1
+3.3V_TBTA_FLASH +3.3V_TBTA_FLASH
+3.3V_VDD_PIC
For AR port1
2
.1U_0402_16V7K
2
2
3.3K_0402_5%
3.3K_0402_5%
3.3K_0402_5%
3.3K_0402_5%
CT70
1
1 6 UPD1_SMBCLK_Q
<34> UPD1_SMBCLK
RT50
RT51
RT52
RT53
@ QT1A
2 DMN66D0LDW-7_SOT363-6
1
1
@ RT58 1 2 0_0402_5%
UT6
5
8 1 TBTA_ROM_CS#_PD_R
TBTA_ROM_HOLD#_PD 7 VCC CS# 2 TBTA_ROM_DO_PD_R
TBTA_ROM_CLK_PD_R 6 HOLD#(IO3) DO(IO1) 3 TBTA_ROM_WP#_PD 4 3 UPD1_SMBDAT_Q
TBTA_ROM_DI_PD_R CLK WP#(IO2) <34> UPD1_SMBDAT
5 4
DI(IO0) GND @ QT1B
W25Q80DVSSIG_SO8 DMN66D0LDW-7_SOT363-6
@ RT59 1 2 0_0402_5%
D D
TBTA_ROM_CLK_PD_R @ RT54 1 2 0_0402_5% TBTA_ROM_CLK_PD
TBTA_ROM_DI_PD_R @ RT55 1 2 0_0402_5% TBTA_ROM_DI_PD
TBTA_ROM_DO_PD_R @ RT56 1 2 0_0402_5% TBTA_ROM_DO_PD @ RT60 1 2 0_0402_5% UPD1_SMBUS_ALERT#
TBTA_ROM_CS#_PD_R TBTA_ROM_CS#_PD <34> UPD1_ALERT#
@ RT57 1 2 0_0402_5%
+3.3V_TBTA_FLASH
JDB1
1
1 2 TBTA_ROM_CLK_PD_R
2 3 TBTA_ROM_DI_PD_R
3 4 TBTA_ROM_DO_PD_R
7 4 5 TBTA_ROM_CS#_PD_R
8 GND 5 6
GND 6
ACES_50506-00641-P01
CONN@
+5V_ALW
@ +TBTA_Vbus_1
PJP8
TI is 1x47uf+1x0.1uf
1 2
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
PAD-OPEN1x2m
1 1 1 1
CT75
CT76
CT77
CT78
DIV = R2/(R1+R2) 2 2 2 2
Factory Device Description
DIV_min DIV_max Configuration
UFP only
5V @0.9A Sink capability with "Ask for Max/" for +TBTA_LDO_BMC
0.00 0.08 0 anything from 0.9 -3.0A +VCC1V8D_TBTA_LDO RT64 @ 1 2 0_0402_5%
TBT Alternate Modes not supported +VCC1V8A_TBTA_LDO
C DisplayPort Alternate Modes not supported C
RT65 @ 1 2 0_0402_5%
TI VID supported
+3.3V_VDD_PIC +3.3V_VDD_PIC_PDA
HV_GATE1_A
HV_GATE2_A
2.2U_0402_16V6K
2.2U_0402_16V6K
2.2U_0402_16V6K
PJP7
1 1 1 @
UFP only TI is 3x1uf 1 2
5V @0.9A Sink capability with "Ask for Max/" for +5V_ALW_PDA
CT71
CT72
CT73
0.10 0.18 1 anything from 0.9 -3.0A PAD-OPEN1x1m
1U_0402_16V6K
TBT Alternate Modes not supported 1
2 2 2
CT74
1 2
DisplayPort Alternate Modes -Sink, C and D pin configuration @ RT63 0_0402_5%
TI VID supported
H10
C11
D11
A11
B11
B10
A10
2
H1
B1
K1
A2
E1
A6
A7
A8
B7
B9
A9
UFP only UT5
0.20 0.28 2 5V @3.0A Source capability F1
VIN_3V3
PP_5V0
PP_5V0
PP_5V0
PP_5V0
HV_GATE1
HV_GATE2
LDO_1V8A
PP_CABLE
SENSEP
VDDIO
LDO_1V8D
LDO_BMC
GND
GND
GND
GND
SENSEN
TBT Alternate Modes not supported I2C_ADDR
DisplayPort Alternate Modes not supported D1
TI VID supported <24> TBT_I2C_SDA I2C_SDA1 +TBTA_Vbus_1
D2
+3.3V_TBTA_FLASH <24> TBT_I2C_SCL I2C_SCL1
+3.3V_TBTA_FLASH C1
<24> TBTA_I2C_INT I2C_IRQ1_N
UFP only TI has 1x1uf
0.30 0.38 3 5V @3.0A Source capability +3.3V_ALW
TBT Alternate Modes not supported 3.3K_0402_5% 2 1 RT66 @ UPD1_SMBDAT_Q A5 +3.3V_PDA_VOUT +3.3V_TBTA_FLASH
2
DisplayPort Alternate Modes -Sink, C and D pin configuration 3.3K_0402_5% 2 1 RT67 @ UPD1_SMBCLK_Q B5 I2C_SDA2 H11
TI VID supported I2C_SCL2 VBUS
1
UPD1_SMBUS_ALERT# B6
CT82
10K_0402_5% 2 1 RT68 @ J10
1U_0603_25V6K
10K_0402_1% I2C_IRQ2_N VBUS J11
1U_0402_16V6K
10U_0603_6.3V6M
VBUS 1 1
PD1_GPIO0
CT83
DRP RT76 @ RT69 2 1 0_0402_5% B2 K11
2
5V @0.9-3.0A Sink capability EN_PD_HV_1_R GPIO0 VBUS
CT84
@ RT70 1 2 0_0402_5% C2
<53> EN_PD_HV_1
1
0.40 0.48 5V @3.0A Source capability PD1_GPIO8 RT71 2 1 1M_0402_5% PD1_GPIO2 D10 GPIO1
4 TBT Alternate Modes not supported @ RT72 1 2 0_0402_5% AC1_DISC#_R G11 GPIO2 2 2
DisplayPort Alternate Modes not supported <52,53> AC1_DISC# GPIO3
1
@ RT73 1 2 0_0402_5% TBTA_HPD_R C10

TI VID supported <24> TBTA_HPD PD1_GPIO5 GPIO4
Accepts data and power role swaps, but does not RT377 @ RT74 2 1 0_0402_5% E10 H2
@ RT75 2 1 0_0402_5% PD1_GPIO6 G10 GPIO5 VOUT_3V3
initiate. 43K_0402_1%
@ RT339 2 1 0_0402_5% PD1_GPIO7 D7 GPIO6
PD1_GPIO8 H6 GPIO7
2
DRP GPIO8 G1
5V @0.9-3.0A Sink capability TBTA_ROM_CLK_PD A3 LDO_3V3
GPIO8: USB_TYPEC_FAULT# SPI_CLK
5V @3.0A Source capability TBTA_ROM_DI_PD B4
0.50 0.58 5 TBT Alternate Modes not supported TBTA_ROM_DO_PD A4 SPI_MOSI
DisplayPort Alternate Modes - Source, C, D, and E TBTA_ROM_CS#_PD B3 SPI_MISO K6
pin configurations. SPI_SS_N C_USB_TP TBTA_TOP_P <28>
L6
TI VID supported C_USB_TN TBTA_TOP_N <28>
Accepts power role swaps but will not initiate. L5
UART_MOSI <24> TBTA_USB20_P USB_RP_P
Accepts data role swap to UFP and can initiate. 2 1 K5
100K_0402_5% RT81 UART_MOSI <24> TBTA_USB20_N USB_RP_N
DRP 2 1 UART_MISO 1 2 E2 K7
UART_MISO UART_TX C_USB_BP TBTA_BOT_P <28>
B 5V @0.9-3.0A Sink capability 1M_0402_5% @ RT82 @ RT83 0_0402_5% F2 L7 B
5V @3.0A Source capability UART_RX C_USB_BN TBTA_BOT_N <28>
0.60 0.68 6 TBT Alternate Modes not supported 0_0402_5% 2 1 @ RT84 F4
DisplayPort Alternate Modes - Source, C, D, and E @ T219 PAD~D SWD_DATA
TI ref ckt: 100k @ T220 PAD~D 0_0402_5% 2 1 @ RT85 G4 TI has 2x220pf
pin configurations. Intel ref ckt: 1M SWD_CLK TBTA_CC1 <28>
L9
TI VID supported C_CC1
Accepts power role swaps but will not initiate. L10
C_CC2 WHEN CONNECT BUSPOWERZ TO GND,
220P_0402_50V8J
220P_0402_50V8J
Accepts data role swap to DFP and can initiate. TBTA_CC2 <28>
RT86 2 1 1M_0402_5% TBTA_MRESET E11 CONNECT ALSO RPD_Gn to C_CCn
MRESET 1 1
0.70 1.00 7 Infinite boot retry from Flash to Host I/F cycles.
CT85
CT86
K9 1 2
TBTA_LSTX 1 2 TBTA_LSTX_R L4 RPD_G1 K10 @ RT104 1 2 0_0402_5%
<24> TBTA_LSTX TBTA_LSRX @ RT87 1 2 0_0402_5% TBTA_LSRX_R K4 TBT_LSTX/R2P RPD_G2 @ RT105 0_0402_5% +3.3V_TBTA_FLASH 2 2
<24> TBTA_LSRX @ RT88 0_0402_5% TBT_LSRX/P2R
TBTA_LSTX 1 2 TBTA_DEBUG3 L3 E4 TBTA_DBG_CTL1 RT106 1 2 10K_0402_5%

TBTA_LSRX @ RT89 1 2 0_0402_5% TBTA_DEBUG4 K3 DIG_AUD_P/DEBUG3 DEBUG_CTL1 D5 TBTA_DBG_CTL2 RT107 1 2 10K_0402_5%
@ RT90 0_0402_5% DIG_AUD_N/DEBUG4 DEBUG_CTL2
UPD1_SMBCLK_Q 1 2 TBTA_DEBUG1 L2
UPD1_SMBDAT_Q @ RT92 1 2 0_0402_5% TBTA_DEBUG2 K2 DEBUG1
@ RT93 0_0402_5% DEBUG2
K8 TBTA_SBU1_R 1 2
TBTA_AUXP_C C_SBU1 TBTA_SBU1 <28>
CT80 1 2 0.1U_0201_10V6K J1 @ RT108 0_0402_5%
<24> TBTA_AUXP TBTA_AUXN_C AUX_P TBTA_SBU2_R
CT81 1 2 0.1U_0201_10V6K J2 L8 1 2
<24> TBTA_AUXN AUX_N C_SBU2 @ RT109
TBTA_SBU2 <28>
0_0402_5%
+3.3V_TBTA_FLASH
F10
BUSPOWER_N F11 TBTA_RESET_N_EC_R @ RT110 1 2 0_0402_5%
+3.3V_TBTA_FLASH RESET_N TBT_RESET_N_EC <24,34>
HRESET
2 1 TBTA_AUXN_C TBTA_ROSC G2
100K_0402_5% RT95 R_OSC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1
15K_0402_1%
SS
2
2 1 TBTA_AUXP_C @
0_0402_5%
RT100
100K_0402_5% RT96 TPS65982_BGA96
A1
D6
E5
E6
E7
F5
G5
H4
H5
B8
D8
E8
F6
F7
F8
G6
G7
G8
H7
H8
L1
L11
RT98
2
1
+VCC1V8D_TBTA_LDO 1 2
@ RT97 0_0402_5%
100K_0402_5%
1
0_0402_5%
1
1
RT101
@ RT103
@ CT87
A RT99 A
0_0402_5% 0.22U_0402_16V7K
2 2
2
2
Need Link TPS65982D

[Type C]PD Controller TI
LA-E131P 1.0

5 4 3 2 1
5 4 3 2 1
+5V_ALW
DT1 +5V_PD_VDD
2 1 +3.3V_VDD_PIC
+5V_TBT_VBUS UT7
1N4148WS-7-F_SOD323-2 1 5
DT2 VCC VOUT
D 2 1 2 D
100K_0402_5%
GND
1
@
0.1U_0201_10V6K
1U_0402_10V6K
1N4148WS-7-F_SOD323-2 3 4
RT393
1 1 EN ADJ/NC
2.2U_0603_25V6K
0.1U_0402_25V6K
1
1
CT88
CT89
@
CT91
CT92
1 2 AP2112K-3.3TRG1_SOT23-5
2
2 2 RT111 100K_0402_5%
2
1
CT90
1U_0402_10V6K
2
+TBTA_VBUS_1
UT8
place near UT7
1
VCC
1U_0603_50V6K
DT3 1
1 2+5V_TBTA_VBUS_D3
VOUT
CT94
2
1N4148WS-7-F_SOD323-2 GND
AP2204R-5.0TRG1_SOT89-3 2
1U_0402_10V6K
1
CT93
C C
B B
A A
[Type C]PD Power
LA-E131P 1.0

5 4 3 2 1
5 4 3 2 1
For AR Config
D D
Check ,FROM PWR PAGE

+TBTA_VBUS +TBTA_VBUS
RF Request
JUSBC1 +TBTA_VBUS
A1 B12
GND_A1 GND_B12 +TBTA_VBUS
1 2 TBTA_TX1P_C A2 B11 TBTA_RX1P
<24> TBTA_TX1P SSTXp1 SSRXp1 TBTA_RX1P <24>
CT95 1 2 0.22U_0201_6.3V6K TBTA_TX1N_C A3 B10 TBTA_RX1N
<24> TBTA_TX1N SSTXn1 SSRXn1 TBTA_RX1N <24>
CT96 0.22U_0201_6.3V6K
2 1 A4 B9 1 2
CT99 0.47U_0201_25V VBUS_A4 VBUS_B9 CT100 0.47U_0201_25V
2
TBTA_CC1 A5 B8 TBTA_SBU2
<26> TBTA_CC1 CC1 SBU2 TBTA_SBU2 <26>
ESD@ DT4
TBTA_TOP_P_R TBTA_BOT_N_R
12P_0402_50V8J
RF@ CT189
82P_0402_50V8J
RF@ CT190
1 2 A6 B7 1 2 1 1 L30ESD24VC3-2_SOT23-3
<26> TBTA_TOP_P @EMI@ RT120 TBTA_TOP_N_R Dp1 Dn2 TBTA_BOT_P_R @EMI@ RT122
TBTA_BOT_N <26>
<26> TBTA_TOP_N 1 2 0_0402_5% A7 B6 1 2 0_0402_5%
Bottom
C Dn1 Dp2 TBTA_BOT_P <26> C
@EMI@ RT121 0_0402_5% @EMI@ RT123 0_0402_5%
TOP
TBTA_SBU1 A8 B5 TBTA_CC2
<26> TBTA_SBU1 SBU1 CC2 TBTA_CC2 <26> 2 2
2 1 A9 B4 1 2
0.47U_0201_25V CT101 VBUS_A9 VBUS_B4 CT102 0.47U_0201_25V
1
TBTA_RX2N A10 B3 TBTA_TX2N_C 2 1
<24> TBTA_RX2N TBTA_RX2P A11 SSRXn2 SSTXn2 B2 TBTA_TX2P_C 0.22U_0201_6.3V6K 2 1 CT98 TBTA_TX2N <24>
<24> TBTA_RX2P SSRXp2 SSTXp2 TBTA_TX2P <24>
0.22U_0201_6.3V6K CT97
A12 B1
GND_A12 GND_B1
1 2
3 GND1 GND2 4
GND3 GND4
JAE_DX07B024XJ1R1300~D
CONN@
Premium 12/14/15 UMA:Check SBU1/SBU2 connect to PD or PS8740B

Link DC23300MEBL Done
ESD@ DT5 ESD@ DT13
TBTA_TX1P_C 1 2 TBTA_RX1P 1 2
ESD8011MUT5G_X3DFN2-2 ESD8011MUT5G_X3DFN2-2
B ESD@ DT6 ESD@ DT14 B
TBTA_TX1N_C 1 2 TBTA_RX1N 1 2
ESD@ DT7 ESD@ DT15
TBTA_CC1 1 2 TBTA_SBU2 1 2
ESD@ DT8 ESD@ DT16

TBTA_SBU1 1 2 TBTA_CC2 1 2
ESD@ DT9 ESD@ DT17

TBTA_RX2N 1 2 TBTA_TX2P_C 1 2
ESD@ DT10 ESD@ DT18
TBTA_RX2P 1 2 TBTA_TX2N_C 1 2
ESD@ DT11 ESD@ DT19
TBTA_TOP_P_R 1 2 TBTA_BOT_P_R 1 2
ESD@ DT12 ESD@ DT20
TBTA_TOP_N_R 1 2 TBTA_BOT_N_R 1 2
A A
PROPRIETARY NOTE: Compal Electronics, Inc.

TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT USB 3.0 CONN TYPE C
5 4 3 2 1
5 4 3 2 1
LINK 50398-04041-001 DONE

JEDP1
For 4LANE EDP &5V_TSP,Steamboat14
1
Due to SB12/14 Mic. receive path is different between Touch and
1 2 Non-Touch Panel, so add TOUCH_SCREEN_DET# pin for different verb
2 3 DMIC0 <33> table
3 4
4 5 DMIC_CLK0 <33> +5V_TSP
5 +3.3V_RUN
6 TOUCH_PANEL_PD#:
6 USB20_N5_R +3.3V_CAM CONN@ JTS1 EXC24CQ900U_4P
100P_0402_50V8J
@EMI@ CA5
100P_0402_50V8J
@EMI@ CA6
7 Close lid >> TP_EN = 0 >> Disable touch events
7 8 USB20_P5_R 1 Open lid >> TP_EN = 1 >> Enable touch events 4 3
8 1 USB20_N8 <10>
1
9 2 USB20_N8_R
9 CAM_MIC_CBL_DET# <12> 2 USB20_P8_R
10 3
10 11 Pin10: LOOP_BACK 3 4 1 2
USB20_P8 <10>
2
11 12 4 5 TOUCH_SCREEN_DET#
12 +BL_PWR_SRC 5 TOUCH_SCREEN_DET# <12> LV27 EMI@
13 6
13 6 TOUCH_SCREEN_PD# <12>
AZC199-02SPR7G_SOT23-3
14 7
14 GND
@ESD@
15 8
D
15 16 EMI@ LV1 1 2 BIA_PWM GND D
3
16 17 DISP_ON BLM15PX221SN1D_2P
17 EMI Request ACES_50209-0060N-P01
18
18 +3.3V_RUN
1
19
19
DV4
20
Link E-T_4260K-Q06N-23L DONE
1
20
10K_0402_5%
21
21 EDP_HPD <6>
2
22 +LCDVDD
RV8
22 23
23 24 EDP_HPD 1 2
24 25 LCD_TST <34>
@ RV7 100K_0402_5% RF Request
25 26
+LCDVDD ESD depop location
1
26 27 Reserve for EA +5V_TSP TOUCH_SCREEN_DET#
27 28
28 29 EDP_AUXN_C CV1 2 1 0.1U_0402_25V6
29 30 EDP_AUXP_C 2 1 EDP_AUXN <6>
CV2 0.1U_0402_25V6
30 EDP_TXP0_C EDP_AUXP <6>
31 CV3 2 1 0.1U_0402_25V6
31 32 EDP_TXN0_C 2 1 EDP_TXP0 <6>
CV4 0.1U_0402_25V6
32 33 EDP_TXP1_C 2 1 EDP_TXN0 <6>
CV5 0.1U_0402_25V6
33 34 EDP_TXN1_C 2 1 EDP_TXP1 <6>
CV6 0.1U_0402_25V6
34 EDP_TXP2_C EDP_TXN1 <6>
12P_0402_50V8J
RF@ CV18
82P_0402_50V8J
RF@ CV19
35 CV7 2 1 0.1U_0402_25V6 1 1
41 35 36 EDP_TXN2_C 2 1 EDP_TXP2 <6>
CV8 0.1U_0402_25V6
42 G1 36 37 EDP_TXP3_C EDP_TXN2 <6>
CV9 2 1 0.1U_0402_25V6 CONN@ JIR1 RF Request
43 G2 37 38 EDP_TXN3_C 2 1 EDP_TXP3 <6> 1
CV10 0.1U_0402_25V6
G3 38 EDP_TXN3 <6> 2 2 1 IR_CAM_DET# <12> +PWR_SRC
44 39 2
45 G4 39 40 2 3
G5 40 LCD_CBL_DET# <9> 3 4
ACES_50398-04041-001 7 4 5
CONN@ 8 GND 5 6
GND 6 +PWR_SRC
E-T_4251K-F06N-40L
+BL_PWR_SRC +LCDVDD +3.3V_CAM +5V_TSP
100P_0402_50V8J
RF@ CZ3
+3.3V_RUN 1
0.1U_0603_50V7K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1 1 1 1
1
USB20_N5_R 2
@
@ @ @ @
USB20_P5_R
CV11
CV12
CZ1
CZ2
CA7
2
2 2 2 2
C C
@ESD@
@ESD@
ESD8011MUT5G_X3DFN2-2
ESD8011MUT5G_X3DFN2-2
Close to JEDP1.17~19 Close to JEDP1.30~31 Close to JEDP1.11 Close to JEDP1.1 Close to JEDP1.10
1
DV7
DV8
DV1 DV2
3 EDP_BIA_PWM 3
EDP_BIA_PWM <6> PANEL_BKLEN <6>
BIA_PWM 1 DISP_ON 1
2
2 BIA_PWM_EC 2
BIA_PWM_EC <34> PANEL_BKEN_EC <34>
1
4.7K_0402_5%
4.7K_0402_5%
1
BAT54CW_SOT323-3 BAT54CW_SOT323-3
RV1
RV2
ESD depop location

For Touchscreen
2
+5V_RUN +5V_TSP +5V_RUN

QV8
47K_0402_5%
LP2301ALT1G_SOT23-3
2
RF Request 1 3
RV6
S
+LCDVDD +3.3V_CAM +BL_PWR_SRC
G
1
2
L2N7002WT1G_SC-70-3
1
D
RF@ CV20
RF@ CV21
RF@ CV22
RF@ CV23
RF@ CV24
RF@ CV25
12P_0402_50V8J
82P_0402_50V8J
12P_0402_50V8J
82P_0402_50V8J
12P_0402_50V8J
82P_0402_50V8J
1 1 1 1 1 1
QV7
B 2 B
<9> 3.3V_TS_EN
G
S
3
2 2 2 2 2 2
LCDVDD POWER +LCDVDD +EDP_VDD

+3.3V_ALW
@
CV16 @ PJP12 UV24
2 1 1 2 1
VOUT 5
WebCAM Backlight POWER +BL_PWR_SRC

10U_0603_10V6M
PAD-OPEN1x1m 2
VIN
GND
0.01UF_0402_25V7K
4
EN
@
+PWR_SRC QV1
CV17
3
+3.3V_CAM +3.3V_RUN 6 /OC
D
4 5 G524B1T11U_SOT23-5
S
2
QZ1 2 DV3
LP2301ALT1G_SOT23-3 1
1000P_0402_50V7K
0.1U_0603_50V7K
2
G
270K_0402_5%
<34> LCD_VCC_TEST_EN
2
1 3 AO6405_TSOP6 1 EN_LCDPWR
D
CV13
3
2
1
RV4
CV15
3
<6,34> ENVDD_PCH
2
100K_0402_5%
G
2
RV3
1
BAT54CW_SOT323-3
<11> 3.3V_CAM_EN# BL_PWR_SRC_ON
1
A A
QV2
L2N7002WT1G_SC-70-3
0.01U_0402_50V7K
1
1 2 1 3
D
S
CV14
RV5 47K_0402_5%
LZ1 EMI@
1 2 USB20_P5_R 2
G
<10> USB20_P5
2
4 3 USB20_N5_R
<10> USB20_N5 <34> EN_INVPWR
EXC24CQ900U_4P
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT eDP CONN & Touch screen
5 4 3 2 1
5 4 3 2 1
Layout Notice : Place bead as

+3.3V_LAN UL1 close UL4 as possible
2 1 TP_LAN_JTAG_TMS CLKREQ_PCIE#4 48 13 LAN_MDIP0 RL71 1 2 2.2_0603_5% LAN_MDIP0_L
<11> CLKREQ_PCIE#4 CLK_REQ_N MDI_PLUS0 LAN_MDIN0 LAN_MDIN0_L
@ RL1 10K_0402_5% 36 14 RL72 1 2 2.2_0603_5%
TP_LAN_JTAG_TCK <11> PLTRST_LAN# PE_RST_N MDI_MINUS0
2 1
@ RL2 10K_0402_5% 44 17 LAN_MDIP1 RL73 1 2 2.2_0603_5% LAN_MDIP1_L
CLKREQ_PCIE#4 <11> CLK_PCIE_P4 PE_CLKP MDI_PLUS1 LAN_MDIN1 LAN_MDIN1_L
2 1 45 18 RL74 1 2 2.2_0603_5%
<11> CLK_PCIE_N4 PE_CLKN MDI_MINUS1
PCIE
@ RL4 4.7K_0402_5% 1 2 PCIE_PRX_C_DTX_P9
MDI
<10> PCIE_PRX_DTX_P9 LAN_MDIP2 LAN_MDIP2_L
CL1 0.1U_0402_25V6 38 20 RL75 1 2 2.2_0603_5%
1 2 PCIE_PRX_C_DTX_N9 39 PETp MDI_PLUS2 21 LAN_MDIN2 RL76 1 2 2.2_0603_5% LAN_MDIN2_L
<10> PCIE_PRX_DTX_N9 PETn MDI_MINUS2
CL2 0.1U_0402_25V6
+3.3V_LAN 1 2 PCIE_PTX_C_DRX_P9 41 23 LAN_MDIP3 RL77 1 2 2.2_0603_5% LAN_MDIP3_L
<10> PCIE_PTX_DRX_P9 PERp MDI_PLUS3 LAN_MDIN3 LAN_MDIN3_L
CL5 0.1U_0402_25V6 42 24 RL78 1 2 2.2_0603_5%
1 2 PCIE_PTX_C_DRX_N9 PERn MDI_MINUS3
<10> PCIE_PTX_DRX_N9
CL6 0.1U_0402_25V6
2
VCT_LAN_R1
10K_0402_5%
28 6 1 2
<8> SML0_SMBCLK SMB_CLK SVR_EN_N
SMBUS
31 0_0402_5% @ RL3 RF Request
D <8> SML0_SMBDATA SMB_DATA +RSVD_VCC3P3_1 D
1 4.7K_0402_5% 1 2 RL6
RL5 @
RSVD_VCC3P3_1 +3.3V_LAN +3.3V_LAN_OUT
2 5
1
1 2 <11,34> LAN_WAKE# LAN_DISABLE#_R 3 LANWAKE_N VDD3P3_IN
<11> PM_LANPHY_ENABLE LAN_DISABLE_N +3.3V_LAN_OUT
@ RL7 0_0402_5% SMBus Device Address 0xC8 4 1 2
VDD3P3_4 +3.3V_LAN
0_0603_5% @ RL8
10K_0402_5%
0.1U_0201_10V6K
22U_0805_6.3V6M
15 1
VDD3P3_15
1
@ RL9
LOM_ACTLED_YEL# 26 19
LOM_SPD100LED_ORG# LED0 VDD3P3_19
CL7
CL28
@RF@ CL29
@RF@ CL30
27 29 Place CL28 close to UL1.5
LED1 VDD3P3_29 +0.9V_LAN
LED
LOM_SPD10LED_GRN#
12P_0402_50V8J
82P_0402_50V8J
25 1 1
2
LED2 2
2 47 +3.3V_LAN
VDD0P9_47 46
@ T88 PAD~D TP_LAN_JTAG_TDI 32 VDD0P9_46 37 2 2
@ T89 PAD~D TP_LAN_JTAG_TDO 34 JTAG_TDI VDD0P9_37
JTAG_TDO
JTAG
+0.9V_LAN TP_LAN_JTAG_TMS 33 43
TP_LAN_JTAG_TCK 35 JTAG_TMS VDD0P9_43
JTAG_TCK 11
VDD0P9_11
470P_0402_50V7K
XTALO_R
0.1U_0201_10V6K
1 2 XTALO 9 40 1
XTAL_OUT VDD0P9_40
1
22U_0603_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
@ RL34 0_0402_5% XTALI 10 22
1
XTAL_IN VDD0P9_22
CL18
CL19
1 1 1 1 16
VDD0P9_16
1
CL9
CL10
CL11
CL8
8 +0.9V_LAN
RJ45 LOM circuit
2
VDD0P9_8 2
CL12
RL11 LAN_TEST_EN 30
1M_0402_5% TEST_EN
2
2 2 2 2 YL1 RES_BIAS 12 7 +REGCTL_PNP10 1 2

+3.3V_LAN:20mils
2
3 1 RBIAS CTRL0P9 4.7UH +-20% MPB201210T-4R7M-NA2 LL1
OUT IN
0.1U_0201_10V6K
10U_0603_10V6M
49 Idc_min=500mA
27P_0402_50V8J
VSS_EPAD
1
1K_0402_5%
3.01K_0402_1%
4 2 DCR=100mohm 1 @ JLOM1 CONN@
27P_0402_50V8J
GND GND
1
CL3
CL4
WGI219LM-QREF- A0_QFN48_6X6~D
CL14
1
RL12
RL13
Note: 25MHZ_18PF_7V25000034 LAN_ACTLED_YEL# 1 2 LAN_ACTLED_YEL_R# 10
CL13
RL14 150_0402_5% Yellow LED-

+1.0V_LAN will work at 0.95V to 1.15V
2
change to SA000081G1L ,(S IC WGI219LM SLKJ2 A0 QFN 48P PHY A31 !) 2 9
2
2
Yellow LED+
RJ45_MDIN3 8
PR4-
RJ45_MDIP3 7
Place CL3, CL4 and LL1 close to UL1 PR4+
RJ45_MDIN1 6
PR2-
RJ45_MDIN2 5
PR3-
C RJ45_MDIP2 C
4
PR3+ 17
RJ45_MDIP1 3 GND
PR2+ 16
RJ45_MDIN0 2 GND
PR1- 15
RJ45_MDIP0 1 GND
PR1+ 14
LED_10_GRN# 1 2 LED_10_GRN_R# 11 GND
RL19 150_0402_5% Green LED-
LED_100_ORG# 1 2 LED_100_ORG_R# 13
RL20 150_0402_5% Orange LED-
12
Green-Orange LED+
SANTA_130470-19
Link DC231603220 (temp) DONE

TL1
LAN_MDIP0_L 1 1:1 24 RJ45_MDIP0

TD1+ TX1+
When LAN & WLAN are exist at the same time, WLAN will disable
LAN_MDIN0_L 2
TD1- 23 RJ45_MDIN0
TX1-
+3.3V_LAN
3 22 Z2805
@
CL15 TDCT1 TXCT1
1 2
4 21 Z2807
TDCT2 TXCT2
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K LAN_MDIP1_L 5 20 RJ45_MDIP1

TD2+ 1:1 TX2+
5
LOM_SPD100LED_ORG# 1
P
B
CL16
CL17
4
LOM_SPD10LED_GRN# 2 O LOM_CABLE_DETECT# <34>
2
A
G
UL2 LAN_MDIN1_L 6 19 RJ45_MDIN1

TC7SH08FU_SSOP5~D TD2- TX2-
B B
3
LAN_MDIP2_L 7 1:1 18 RJ45_MDIP2

QL1A TD3+ TX3+
LOM_ACTLED_YEL# 1 6 LAN_ACTLED_YEL#
LAN_MDIN2_L 8
TD3- 17 RJ45_MDIN2
+3.3V_LAN TX3-
2
SYS_LED_MASK# 9 16 Z2806
SYS_LED_MASK# <34,41> TDCT3 TXCT3
1
RL29
1M_0402_5% 10 15 Z2808
TDCT4 TXCT4
0.1U_0201_10V6K
0.1U_0201_10V6K
QL1B LAN_MDIP3_L 11 1:1 14 RJ45_MDIP3

TD4+ TX4+
1 75_0402_1%
1 75_0402_1%
1 75_0402_1%
1 75_0402_1%
2
LOM_SPD100LED_ORG#
4 3 LED_100_ORG#
1
+3.3V_LAN
CL20
CL21
LAN_MDIN3_L 12 13 RJ45_MDIN3
5
TD4- TX4-
1
SYS_LED_MASK#
RL30
1M_0402_5% MHPC_NS692417
QL2A
2
RL15 2
RL16 2
RL17 2
RL18 2
LOM_SPD10LED_GRN# 1 6 LED_10_GRN#
GND 1 2 +GND_CHASSIS
2
EMI@ CL22 10P_1808_3KV8J
For WLAN can't recognize during enable

SYS_LED_MASK# CHASSIS use 40mil trace if necessary
Unobtrusive mode(BITS152312) 0601:EMI ask to change 150pF

QL2B
4 3
A A
5
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT LAN Clarkvillie & RJ45
5 4 3 2 1
A B C D E
For PCIE Interface
1 1
+3.3V_RUN +3.3V_MMI_IN
PJP14
1 2
RF Request +3.3V_MMI_AUX +3.3V_MMI_IN
+3.3V_MMI_AUX +3.3V_MMI_IN PAD-OPEN1x2m
+3.3V_MMI_IN +3.3V_MMI_AUX
4.7U_0402_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
10U_0402_6.3V6M
1 2
support D3 Hot(if D3 cold PIN11,PIN27 need Add MOS on/off 3V3AUX)
1 1 1 1
CR4
0_0603_5% R274 @
CR3
CR1
CR2
@RF@ CR27
@RF@ CR28
@RF@ CR25
@RF@ CR26
2 2 2 2
12P_0402_50V8J
82P_0402_50V8J
12P_0402_50V8J
82P_0402_50V8J
1 1 1 1
+3.3V_MMI_AUX
2 2 2 2
2 1 MEDIACARD_IRQ# 7/18 Vender suggest.

RR19 10K_0402_5%
27
11
UR1
3V3aux
3V3_IN
1 12
<11,24,32,36,37> PCH_PLTRST#_AND PERST# CARD_3V3 +DV33_18 +3.3V_RUN_CARD
2 18 1 2
<11> CLKREQ_PCIE#0 CLK_REQ# DV33_18 CR22 1U_0402_6.3V6K
5
<11> CLK_PCIE_P0 REFCLKP SD/MMCDAT1/RCLK-_R
6 15 SD/MMCDAT1/RCLK- 1 2
<11> CLK_PCIE_N0 REFCLKN SP1 SD/MMCDAT0/RCLK+_R
16 SD/MMCDAT0/RCLK+ @ RR9 1 2 0_0402_5%
CR11 1 2 0.1U_0402_25V6 PCIE_PTX_C_DRX_P1 3 RTS5242 SP2 17 SD/MMCCLK @ RR10 1 2 0_0402_5% SD/MMCCLK_R
<10> PCIE_PTX_DRX_P1 PCIE_PTX_C_DRX_N1 HSIP SP3 SD/MMCCMD_R
@EMI@ CR21
CR12 1 2 0.1U_0402_25V6 4 19 SD/MMCCMD @EMI@ RR5 1 2 0_0402_5%
<10> PCIE_PTX_DRX_N1 HSIN SP4
5P_0402_50V8C
CR13 1 2 0.1U_0402_25V6 PCIE_PRX_C_DTX_P1 7 20 SD/MMCDAT3 @ RR6 1 2 0_0402_5% SD/MMCDAT3_R
<10> PCIE_PRX_DTX_P1 CR14 1 2 0.1U_0402_25V6 PCIE_PRX_C_DTX_N1 8 HSOP SP5 21 SD/MMCDAT2 @ RR7 1 2 0_0402_5% SD/MMCDAT2_R
<10> PCIE_PRX_DTX_N1 HSON SP6
1
29 SDWP @ RR8 0_0402_5%
SP7
32
2
2 <9> MEDIACARD_IRQ# WAKE# 2
31
SD/MMCCD# 30 MS_INS#
+1.2V_LDO SD_CD#
7/18 Vender suggest
CR13 close to UR2.10 22 SD_UHS2_D1P EMI depop location
SD_LN1_P 23 SD_UHS2_D1N
CR9 CR10 close to UR2.14 SD_LN1_M
10
14 AV12 26 SD_UHS2_D0P
DV12S SD_LN0_P 25 SD_UHS2_D0N
SD_LN0_M
4.7U_0603_6.3V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
+1.8V_RUN_CARD 13
SD_VDD2 24 +SDREG2 CR15 1 2
1 1
E-PAD
SDREG2
CR5
+RREF 9 28 1U_0402_6.3V6K
CR6
CR7
RREF GPIO SD_GPIO 2 1 +3.3V_MMI_AUX
10K_0402_5% RR3
2
2 2 RTS5242-GR_QFN32_4X4
33
1
6.2K_0402_1%
RR4
2
3 3
QR1
L2N7002WT1G_SC-70-3 JSD1 CONN@
HOST_SD_WP# SDWP_Q SDWP STATUS 4
SDWP_Q +3.3V_RUN_CARD VDD1
SDWP 1 3 15
S
+1.8V_RUN_CARD SD/MMCCMD_R VDD2
3
High Low Low Write Enable SD/MMCCLK_R 5 CMD
CLK
G
2
SD/MMCCD# 9
Low Low High Write Protect(FW LOCK) 16 CD
<12> HOST_SD_WP# SWIO
SD/MMCDAT0/RCLK+_R 7
SD/MMCDAT1/RCLK-_R 8 DAT0/RCLK+
SD/MMCDAT2_R 1 DAT1/RCLK-
SD/MMCDAT3_R 2 DAT2
CD/DAT3
+3.3V_RUN_CARD +1.8V_RUN_CARD
SD_UHS2_D0P 18
SD_UHS2_D0N 19 D0+
SD_UHS2_D1P 22 D0-
SD_UHS2_D1N 21 D1+
0.1U_0201_10V6K
0.1U_0201_10V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
D1-
2 2
2
10
CR20
CR17
CR19
6 GND1 11
CR18
17 VSS1 GND2 12
1
1 1 20 VSS2 GND3 13
23 VSS3 GND4 14
VSS4 GND5
T-SOL_158-1240902600
CR38,CR39 near JSD1.4 CR40,CR41 near JSD1.14
LINK SP071603151 (temp) DONE

4 4
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Card Reader RTS5242
A B C D E
5 4 3 2 1
+3.3V_WWAN for AR Steamboat

NGFF slot B Key B
2 1 WWAN_PWR_EN +3.3V_WWAN
NGFF slot A Key A
RZ43 47K_0402_5%
100P_0402_50V8J
JNGFF2 CONN@
RF@ CZ198
1 2
<34> SLOT2_CONFIG_3 1 2
3 4 +3.3V_WLAN
3 4
1
5 6 WWAN_PWR_EN
USB20_P4_L 7 5 6 8 WWAN_RADIO_DIS#_R JNGFF1 CONN@
USB20_N4_L 9 7 8 10 1 2
2
11 9 10 USB20_P7_L 3 1 2 4
11 USB20_N7_L 5 3 4 6
7 5 6
D 7 D
12
13 12 14 16
<34> SLOT2_CONFIG_0 13 14 16
15 16 17 18
<34> WWAN_WAKE# 15 16 HW_GPS_DISABLE#_R SW2_DP2_N3_C 17 18 SW2_DP2_AUXN_C
2 1 17 18 1 2 19 20 2 1
17 18 <22> SW2_DP2_N3 19 20 SW2_DP2_AUXN <22>
@RF@ RZ326 0_0402_5% 19 20 CV145 1 2 0.1U_0402_25V6 SW2_DP2_P3_C 21 22 SW2_DP2_AUXP_C
0.1U_0402_25V6 2 1CV150
USB3_PRX_L_DTX_N2 19 20 UIM_RESET <22> SW2_DP2_P3 21 22 SW2_DP2_AUXP <22>
21 22 CV146 0.1U_0402_25V6 23 24 0.1U_0402_25V6 CV149
USB3_PRX_L_DTX_P2 23 21 22 24 UIM_CLK 1 2 SW2_DP2_N2_C 25 23 24 26 SW2_DP2_N1_C 2 1
23 24 UIM_DATA <22> SW2_DP2_N2 25 26 SW2_DP2_N1 <22>
25 26 CV148 1 2 0.1U_0402_25V6 SW2_DP2_P2_C 27 28 SW2_DP2_P1_C 0.1U_0402_25V6 2 1CV152
USB3_PTX_L_DRX_N2 25 26 <22> SW2_DP2_P2 27 28 SW2_DP2_P1 <22>
Drop HCA function in DVT1.0 27 28 CV147 0.1U_0402_25V6 29 30 0.1U_0402_25V6 CV153
USB3_PTX_L_DRX_P2 27 28 +SIM_PWR 29 30 SW2_DP2_N0_C
29 30 31 32 2 1
29 30 ISH_I2C2_SCL_R M3042_DEVSLP <10> <22> SW2_DP2_HPD 31 32 SW2_DP2_P0_C 0.1U_0402_25V6 SW2_DP2_N0 <22>
31 32 2 1 33 34 2 1CV156
31 32 ISH_I2C2_SDA_R ISH_I2C2_SCL <9> PCIE_PTX_C_DRX_P3 33 34 SW2_DP2_P0 <22>
33 34 @ RZ76 2 1
0_0402_5% CZ12 1 2 0.1U_0402_25V6 35 36 0.1U_0402_25V6 CV157
33 34 ISH_I2C2_SDA <9> <10> PCIE_PTX_DRX_P3 PCIE_PTX_C_DRX_N3 35 36
35 36 @ RZ77 0_0402_5% CZ13 1 2 0.1U_0402_25V6 37 38
35 36 <10> PCIE_PTX_DRX_N3 37 38 PCH_CL_RST1# <8>
37 38 9/24: Reserve for embedded location ,refer Intel PDG 0.9 39 40
39 37 38 40 WLAN 41 39 40 42
PCH_CL_DATA1
PCH_CL_CLK1 <8>
<8>
41 39 40 42 PCH_PLTRST#_AND <10> PCIE_PRX_DTX_P3 43 41 42 44 W LAN_COEX3
43 41 42 44 <10> PCIE_PRX_DTX_N3 45 43 44 46 W LAN_COEX2
45 43 44 46 PCIE_WAKE# 47 45 46 48 W LAN_COEX1
45 46 <11> CLK_PCIE_P1 47 48 W IGIG_32KHZ
47 48 @ RZ131 2 1 0_0402_5% 49 50 @ RZ56 1 2 0_0402_5%
47 48 PORT80_DET# <34> <11> CLK_PCIE_N1 49 50 PCH_PLTRST#_AND SUSCLK <11,37>
49 50 @ RZ132 2 1 0_0402_5% 51 52
49 50 WWAN_COEX3 HOST_DEBUG_TX WLAN_COEX3
<34,35> 51 52 BT_RADIO_DIS#_R PCH_PLTRST#_AND <11,24,31,36,37>
51 52 @RF@ RZ128 1 2 0_0201_5% 53 54
51 52 WWAN_COEX2 <11> CLKREQ_PCIE#1 53 54
53 54 @RF@ RZ129 1 2 0_0201_5% WLAN_COEX2 PCIE_WAKE# 55 56 W LAN_WIGIG60GHZ_DIS#_R
55 53 54 56 WWAN_COEX1 @RF@ RZ130 1 2 0_0201_5% WLAN_COEX1 <24,35,37> PCIE_WAKE# 57 55 56 58 ISH_UART0_RXD_R 2 1
55 56 SIM_DET PCIE_PTX_C_DRX_P4 57 58 ISH_UART0_TXD_R @ RZ78 2 ISH_UART0_RXD <9>
57 58 CZ14 1 2 0.1U_0402_25V6 59 60 1 0_0402_5%
57 58 <10> PCIE_PTX_DRX_P4 PCIE_PTX_C_DRX_N4 59 60 ISH_UART0_CTS#_R @ RZ79 2 ISH_UART0_TXD <9>
PAD~D @ T225 59 60 CZ15 1 2 0.1U_0402_25V6 61 62 1 0_0402_5%
59 60 <10> PCIE_PTX_DRX_N4 61 62 ISH_UART0_RTS#_R @ RZ80 2 ISH_UART0_CTS# <9>
61 62 63 64 1 0_0402_5%
<34> SLOT2_CONFIG_1
63 61 62 64 WIGI 65 63 64 66 PCH_PLTRST#_AND @ RZ81 0_0402_5%
ISH_UART0_RTS# <9>
65 63 64 66 <10> PCIE_PRX_DTX_P4 67 65 66 68
65 66 <10> PCIE_PRX_DTX_N4 67 68 PCIE_WAKE# CLKREQ_PCIE#2 <11>
67 69 70
<34> SLOT2_CONFIG_2 67 69 70
71 72
<11> CLK_PCIE_P2 71 72
73 74
<11> CLK_PCIE_N2 73 74
69 68 75
GND GND 75 9/24: Reserve for embedded location ,refer Intel PDG 0.9
RF Request BELLW_80149-3221 76 77
GND GND
8
0
1
4
9
-
3
2
2
1
L
I
N
K
D
O
N
E
+3.3V_WWAN +3.3V_WWAN
LCN_DAN05-67306-0100
.047U_0402_16V7K
.047U_0402_16V7K
33P_0402_50V8J
33P_0402_50V8J
S
P
0
7
0
0
1
9
F
0
0
L
I
N
K
D
O
N
E
C C
22U_0603_6.3V6M
47P_0402_50V8J
100P_0402_50V8J
2200P_0402_50V7K
RF@
1
RF@ CZ24
100U_B2_6.3VM_R35M
RF@CZ26
1
RF@ CZ25
CZ17
CZ18
CZ19
CZ20
CZ21
+
2
CZ23
2
1 2 WWAN_RADIO_DIS#_R
<34> WWAN_RADIO_DIS#
+3.3V_WLAN
DZ5
RB751S40T1G_SOD523-2 1 2 WLAN_WIGIG60GHZ_DIS#_R
<34> WLAN_WIGIG60GHZ_DIS#
DZ1
RB751S40T1G_SOD523-2
4.7U_0603_6.3V6K
HW_GPS_DISABLE#_R
0.01UF_0402_25V7K
0.1U_0201_10V6K
10U_0603_10V6M
0.01UF_0402_25V7K
0.1U_0201_10V6K
1 2
<34> HW_GPS_DISABLE#
DZ6 1 1 1
1
CZ28
CZ30
CZ27
CZ29
CZ31
CZ32
1 2
@RF@ RI27 0_0402_5%
2
2 2 2
LI16 RF@ 1 2 BT_RADIO_DIS#_R
USB3_PRX_L_DTX_P2 <34> BT_RADIO_DIS#
1 2
<10> USB3_PRX_DTX_P2 DZ2
4 3 USB3_PRX_L_DTX_N2
<10> USB3_PRX_DTX_N2
RF Request
HCM2012GA900AE_4P Place near JNGFF1.72/JNGFF1.74 Place near JNGFF1.2/JNGFF1.4
1 2
@RF@ RI28 0_0402_5% RF Request
1 2
1 2 @RF@ RI49 0_0402_5%
@RF@ RI29 0_0402_5% 1 2
@RF@ RI47 0_0402_5%
LI17 RF@
2 1 USB3_PTX_C_DRX_P2 1 2 USB3_PTX_L_DRX_P2
<10> USB3_PTX_DRX_P2
CI30 0.1U_0402_25V6
USB3_PTX_C_DRX_N2 USB3_PTX_L_DRX_N2 HCM2012GA900AE_4P

RF Request
2 1 4 3
<10> USB3_PTX_DRX_N2 USB20_P7_L
B CI29 0.1U_0402_25V6 4 3 +3.3V_WLAN B
<10> USB20_P7
HCM2012GA900AE_4P LI8 RF@
1 2 USB20_P4_L
<10> USB20_P4 USB20_N7_L
1 2 1 2
<10> USB20_N7
@RF@ RI30 0_0402_5%
USB20_N4_L LI9 RF@
15P_0402_50V8J
15P_0402_50V8J
15P_0402_50V8J
15P_0402_50V8J
4 3
<10> USB20_N4
RF@ CZ33
RF@ CZ34
RF@ CZ35
RF@ CZ36
HCM2012GA900AE_4P
SIM Card Push-Push
1
1 2
@RF@ RI50 0_0402_5%
2
1 2
@RF@ RI48 0_0402_5%
JSIM1 CONN@
C8 3
UIM_DATA C7 RFU1 GND1 4
C6 IO GND2 5
C5 VPP GND3 6
C4 GND GND4 7
UIM_CLK C3 RFU2 GND5 8
UIM_RESET C2 CLK GND6 9
C1 RST GND7
+SIM_PWR VCC
4.7U_0402_6.3V6M
STATE # CONFIG_0 CONFIG_1 CONFIG_2 CONFIG_3 Module Type

1
1
DLSW
CZ37
SIM_DET 2
DTSW 0 GND GND GND GND SSD-SATA
2
S
P
0
7
0
0
1
7
I
0
0
L
I
N
K
D
O
N
E
JAE_SF51S006V4DR1000Q 1 GND HIGH GND GND SSD-PCIE(2 lane) Power Rating TBD
8 HIGH GND GND GND WWAN Primary Power Aux Power
PWR Voltage
Rail Tolerance
+SIM_PWR 14 HIGH GND HIGH HIGH HCA-PCIE(1 lane) Peak Normal Normal
UIM_CLK 15 HIGH HIGH HIGH HIGH NA +3.3V

@RF@ RZ335
1
15K_0402_5%
47P_0402_50V8J
@RF@ CZ38
A A
1
+SIM_PWR
UIM_DATA UIM_RESET
2
33P_0402_50V8J
33P_0402_50V8J
@RF@ CZ39
@RF@ CZ40
1
RF@RZ334
51_0402_5%
0.1U_0402_25V6
RF@ CZ41
1
1
2
2
2
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT NGFF Card
RF Request NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
5 4 3 2 1
5 4 3 2 1
SPKR_R
100P_0402_50V8J
10K_0402_5%
1W x 1ch, 4ohm (Transducer spec is 8Ohm/0.5Watt per unit, there are two transducer units in one speaker box.)
1
BEEP_R
@ CA72
@ RA51
+5V_RUN_AUDIO
100P_0402_50V8J
10K_0402_5%
place close to pin41 place close to pin46 LA13
1
+5V_RUN_PVDD_L
@ CA62
@ RA45
1 2
HCB2012VF-601T20_2P
Internal Speakers Header
2
ACES_50271-0040N-001
0.1U_0201_10V6K
10U_0603_10V6M
0.1U_0201_10V6K
10U_0603_10V6M
0.1U_0201_10V6K
10U_0603_10V6M
1 1 1 1 600 Ohm/2A 1 1
2
CA45
CA47
CA60
6
GND2
CA46
CA48
CA59
5
40 mils trace keep 20 mil spacing
2
GND1
INT_SPK_L+ EMI@ LA6 1 2 BLM15PX330SN1D_2P INT_SPKR_L+ 4 2 2 2 2 2 2
INT_SPK_L- EMI@ LA7 1 2 BLM15PX330SN1D_2P INT_SPKR_L- 3 4
INT_SPK_R+ EMI@ LA8 1 2 BLM15PX330SN1D_2P INT_SPKR_R+ 2 3
INT_SPK_R- EMI@ LA9 1 2 BLM15PX330SN1D_2P INT_SPKR_R- 1 2
1 +3.3V_RUN_AUDIO
JSPK1 CONN@
L03ESDL5V0CC3-2_SOT23-3
D D
3
+5V_RUN_AUDIO
@ESD@
@ESD@
2 1 +3.3V_RUN_AUDIO_IO LA5
LA12 BLM15PX600SN1D_2P +VDDA_AVDD1 place close to pin26 1 2
@EMI@ CA22
@EMI@ CA23
@EMI@ CA19
@EMI@ CA24
0.1U_0201_10V6K
10U_0603_10V6M
BLM15PX600SN1D_2P
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
10U_0603_10V6M
0.1U_0201_10V6K
Link SP02000TS00 DONE 1 RF Request
1
1
CA55
CA56
2 1 1
1
DA6
DA7
CA8
LA14 BLM15PX600SN1D_2P +5V_RUN_AUDIO
CA9
2
2
2
0.1U_0201_10V6K
10U_0603_10V6M
1
2
2
1
1
CA10
CA61
place close to pin9
+1.8V_RUN
2
2 +3.3V_RUN_AUDIO_DVDD
+1.8V_RUN_AUDIO
12P_0402_50V8J
RF@ CA63
68P_0402_50V8J
RF@ CA64
place close to pin40 1 2 1 1
Close to UA1 @ RA3 0_0603_5%
10U_0603_10V6M
0.1U_0201_10V6K
place close to pin1 1
1
2 2
CA58
CA57
2
2
41
46
26
40
36
1
9
UA1
Close to UA1 pin6
PVDD1
PVDD2
AVDD1
AVDD2
DVDD-IO
DVDD
CPVDD
HDA_BIT_CLK_R DMIC_CLK0 11
I2C_SDA
@EMI@ RA17
12 31 +LINE1-VREFO-L RA57 1 2 4.7K_0402_5% AUD_HP_OUT_L

I2C_SCL LINE1-VREFO-L
82P_0402_50V8J
RF@ CA54
30 +LINE1-VREFO-R RA58 1 2 4.7K_0402_5% AUD_HP_OUT_R AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width
1
1
LINE1-VREFO-R
33_0402_5%
10 29 +MIC2-VREFO
<12> HDA_SYNC_R HDA_BIT_CLK_R SYNC MIC2-VREFO
6 28 1 2 RF Request
<12> HDA_BIT_CLK_R HDA_SDOUT_R BIT-CLK VREF
Place RA9 close to codec 5 35 CA35 2.2U_0402_6.3V6M
2 <12> HDA_SDOUT_R SDATA-OUT CBN +1.8V_RUN_AUDIO +1.8V_RUN
1 2 HDA_SDIN0_R 8 37 2 1
<12> HDA_SDIN0 RA9 33_0402_5% SDATA-IN CBP CA29 1U_0603_10V6K
Place CA29 close to Codec
2
100K_0402_5%1 2 RA52 4 20 @ RA53 1 2 0_0402_5%

+5V_ALW
EAPD/DC DET 5VSTB
10P_0402_50V8J
@EMI@ CA33
2 @ RA54 1 2 0_0402_5%
<29> DMIC0 DMIC_CLK0 1 GPIO0/DMIC-DATA12 +RTC_CELL
place close to UA1 pin3 2 DMIC_CLK_CODEC 3 34 1 2 1 2 RING2
<29> DMIC_CLK0 GPIO1/DMIC-CLK CPVEE
1
EMI@ RA14 22_0402_5% 47 CA49 1U_0603_10V6K RA5 2.2K_0402_5%

PDB
RF@ CA69
+3.3V_RUN_AUDIO 10K_0402_5% 2 1 RA18 PD# 48 +MIC2-VREFO 1 2 SLEEVE
SPDIFO/GPIO2/DMIC-DATA-34/DMIC-CLK-In/MIC-GPI
33P_0402_50V8J
2 1 SLEEVE/RING2 please keep 40 mils trace width RA6 2.2K_0402_5%
2
C C
12P_0402_50V8J
RF@ CA65
68P_0402_50V8J
RF@ CA66
100K_0402_5% 2 1 RA44 27 1 1 1
1U_0603_10V6K 2 1 CA31 10U_0603_10V6M 2 1 CA51 39 LDO1-CAP 17 RING2 AUD_PC_BEEP 2 1 SPKR_R 1 2
LDO2-CAP MIC2-L/RING2 BEEP_R SPKR <12>
10U_0603_10V6M 2 1 CA52 7 18 SLEEVE CA27 2 1 0.1U_0402_25V6 RA12 1 2 1K_0402_5%
LDO3-CAP MIC2-R/SLEEVE BEEP <34>
10U_0603_10V6M CA53 19 1 2 CA28 0.1U_0402_25V6 RA13 1K_0402_5%
MIC-CAP 24 10U_0603_10V6M CA25 2 2 2
INT_SPK_L+ 42 LINE2-L 23
INT_SPK_L- 43 SPK-L+ LINE2-R 22 LINE1_L 1 2 HP_OUT_L
INT_SPK_R- 44 SPK-L- LINE1-L 21 LINE1_R 10U_0603_10V6M 1 2 CA43 HP_OUT_R AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width
+3.3V_RUN_AUDIO INT_SPK_R+ 45 SPK-R- LINE1-R 16 AUD_PC_BEEP
10U_0603_10V6M CA44
SPK-R+ PCBEEP 32 HP_OUT_L 1 2 AUD_HP_OUT_L
AUD_SENSE_A 13 HP-OUT-L 33 HP_OUT_R 16.2_0402_1% 1 2 RA7 AUD_HP_OUT_R
AUD_SENSE_B 14 HP/LINE1 JD1 HP-OUT-R 16.2_0402_1% RA8
MIC2/LINE2 JD2
1
+3.3V_RUN_AUDIO 15 25
SPDIFO/FRONT JD3/GPIO3 AVSS1 38
100K_0402_5% AVSS2 49
Place closely to Pin 13. RA61 THERMAL PAD
100K_0402_1% 200K_0402_1%
1
AUD_SENSE_B ALC3246-CG_MQFN48_6X6 RF Request

RA59
+3.3V_RUN_AUDIO
2
AUD_SENSE_A
0.1U_0402_25V6
1
@ CA41
RA60
12P_0402_50V8J
RF@ CA67
68P_0402_50V8J
RF@ CA68
1 1
2
Add for solve

AUD_HP_NB_SENSE
pop noise and
detect issue 2 2
CLASS-D POWER DOWN CONTROL CIRCUIT

Add this Filter to avoid other HP-Out-Right Nokia-MIC
components/chips be influenced
HP-Out-Left iPhone-MIC
B B
1 2
@ RA48 0_0402_5%
place at AGND and DGND plane
680P_0402_50V7K
@ESD@ CA13
1 2 @ DA8 1 2 1
@ RA35
<34> AUD_NB_MUTE#
0_0402_5% Global Headset
RB751S40T1G_SOD523-2 PD#
1
@ RA36
2
1
@ PJP19
2 <12> HDA_RST#_R
1 2 2 Universal Jack
0_0402_5% @ RA50 0_0402_5%
HDA_Link is 3.3V,no need level shift circuit
PAD-OPEN1x1m JHP1 CONN@
1 2 7
@ RA37 0_0402_5% RE313@one control line if DVDD is 3.3V RING2 ESD@ LA10 1 2 BLM15PX330SN1D_2P RING2_R 4 GND
DE2@two control lines1 AUD_HP_OUT_L @EMI@ RA55 1 2 0_0402_5% AUD_HP_OUT_L1 1 #4 G/M
#1 L/R Normal
Open
5
Only BR15U UMA use LA2,LA3,because 6L #5
AUD_HP_NB_SENSE 6
#6 AGND
AUD_HP_OUT_R @EMI@RA56 1 2 0_0402_5% AUD_HP_OUT_R1 2
SLEEVE ESD@ LA11 1 2 BLM15PX330SN1D_2P SLEEVE_R 3 #2 R/L
@ PJP17 #3 M/G
Power sequence +5V_RUN_AUDIO(501us) > +3.3V_RUN_AUDIO(1204 us) > +1.5V_RUN 1 2 SINGA_2SJ3095-085111F
680P_0402_50V7K
+5V_RUN +5V_RUN_AUDIO
ESD@
EMI@
EMI@
ESD@
ESD@ ESD@ ESD@
3
+5V_RUN_AUDIO PAD-OPEN1x2m DA1 DA2 DA3
2.5A Link DC23000DG10 DONE
330P_0402_50V8J
330P_0402_50V8J
680P_0402_50V7K
AZ5123-02S.R7G_SOT23-3
AZ5123-02S.R7G_SOT23-3
680P_0402_50V7K
@ESD@ CA12
2 1 1 1 1
Reserve for support D3 cold
1
CA1
CA2
CA3
CA4
@ PJP18
@ PJP15 1 2
+3.3V_RUN +3.3V_RUN_AUDIO 1 2 2 2 2
PAD-OPEN1x1m
+5V_RUN PAD-OPEN1x1m
500mA
@ UZ5
2
1
1 14 +5V_RUN_AUDIO_UZ5 1 2
2 VIN1 VOUT1 13 @ CZ125 0.1U_0201_10V6K
A VIN1 VOUT1 A
3 12 1 2
<12> AUD_PWR_EN ON1 CT1 220P_0402_50V7K
@ CZ126
4 11
+5V_ALW VBIAS GND
5 10 1 2
ON2 CT2 @ CZ127 1000P_0402_50V7K
+3.3V_RUN
6 9 @ PJP16
7 VIN2 VOUT2 8 +3.3V_RUN_AUDIO_UZ5 1 2
VIN2 VOUT2 +3.3V_RUN_AUDIO
15
EM5209VF_SON14_2X3
GPAD PAD-OPEN1x1m
1 2
@ CZ128 0.1U_0201_10V6K Security Classification Compal Secret Data
Title
Issued Date 2016/01/01 Deciphered Date 2017/01/01
Codec ALC3246
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-E131P
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
+RTC_CELL
@ RE32
1 2
0_0402_5%
+RTC_CELL_VBAT eSPI
LPC
GPIO223
NA
SHD_IO0
GPIO224
NA
SHD_IO1
GPIO227
*PRIM_PWRGD
SHD_IO2
GPIO016
NA
SHD_IO3
GPIO056
NA
SHD_CLK
GPIO055
PCH_RSMRST#
SHD_CS#
For SB
0.1U_0201_10V6K
* For Version B IC UPD1_SMBDAT 1 2
1
CE11
RE302 2.2K_0402_5%
GPIO204 GPIO011 GPIO100 GPIO021 GPIO067 UPD1_SMBCLK 1 2
+3.3V_ALW_UE1
eSPI NA NA NA SIO_RCIN# NA RE303 2.2K_0402_5%
2
0.1U_0201_10V6K
1U_0402_6.3V6K
0.1U_0201_10V6K
@ PJP22 LPC RSMRST# SIO_EXT_SMI# SIO_EXT_SCI# LPCPD# CLKRUN# UPD1_ALERT# 1 2
+3.3V_ALW 1 2 1 1 RE91 100K_0402_5%
1
UPD2_ALERT#
CE13
CE14
CE23
1 2
10U_0603_6.3V6M
PAD-OPEN1x1m RE92 100K_0402_5%
1
For EVT/DVT1.0 Only,SA00009GL10, S IC MEC5105K-TMP2-TN WFBGA 169P EC
2
2 2
CE16
After DVT1.1,SA00009GL00, S IC MEC5105K-D1-TN WFBGA 169P EC PBAT_CHARGER_SMBDAT 1 2
2
UE1 RE37 2.2K_0402_5%
F2 TYPEC_ID PBAT_CHARGER_SMBCLK 1 2
GPIO033/RC_ID0 PANEL_ID TYPEC_ID <35>
A2 J10 RE43 2.2K_0402_5%
+3.3V_ALW_UE1 VBAT GPIO034/RC_ID1/SPI0_CLK BOARD_ID PANEL_ID <35>
J13
D GPIO036/RC_ID2/SPI0_MISO UPD2_SMBDAT BOARD_ID <35> EXPANDER_GPU_SMDAT D
B7 E7 1 2
2 1 VTR_ANALOG GPIO003/SMB00_DATA/SPI0_CS# D7 UPD2_SMBCLK RE524 2.2K_0402_5%
+3.3V_ALW_UE1 GPIO004/SMB00_CLK/SPI0_MOSI
0.1U_0201_10V6K
0.1U_0201_10V6K
100_0402_1% RE314 K2 EXPANDER_GPU_SMCLK 1 2

VREF_ADC
22U_0603_6.3V6M
0.1U_0201_10V6K
1 1 1 1 G3 RE525 2.2K_0402_5%
GPIO057/VCC_PWRGD RUNPWROK <14>
CE19
CE20
@ CE17
+3.3V_EC_PLL F1 H5 HW_GPS_DISABLE#
VTR_PLL GPIO060/KBRST/48MHZ_OUT HW_GPS_DISABLE# <32>
CE18
G11 RPE12
GPIO104/UART0_TX HOST_DEBUG_TX <32,35>
H1 G12 1 8
2 2 2 2 VTR_REG GPIO105/UART0_RX ME_FW_EC <12>
B13 2 7
GPIO127/A20M/UART0_CTS# UPD1_ALERT# ME_SUS_PWR_ACK <11> UPD2_SMBCLK
G8 F10 3 6
M9 VTR1 GPIO225/UART0_RTS# UPD1_ALERT# <26> UPD2_SMBDAT 4 5
+VSS_PLL +3.3V_ALW_UE1 VTR2 PCIE_WAKE#_R
close to pin G8/M9 +1.8V_3.3V_ALW_VTR3 N5 N13
VTR3 GPIO025/TIN0/nEM_INT/UART_CLK N12 PCIE_WAKE#_R <35> 2.2K_0804_8P4R_5%
GPIO026/TIN1 SIO_SLP_S4# <11,17,45,48>
F8 M11
+3.3V_ALW_UE1 <35> PCH_DPWROK_EC RUN_ON_EC GPIO020 GPIO027/TIN2 SIO_SLP_A# <11>
RF Request E8 H9
<35> RUN_ON_EC GPIO045 GPIO030/TIN3 SIO_SLP_LAN# <11,42>
0.1U_0201_10V6K
1 M12 RPE9
+3.3V_ALW <9> SIO_EXT_WAKE# BT_RADIO_DIS# GPIO120 SLOT2_CONFIG_0
C2 L9 1 8
<32> BT_RADIO_DIS# GPIO166 GPIO017/GPTP-IN5 BEEP <33> SLOT2_CONFIG_1
CE15
F9 M10 2 7
<43,52> PBAT_PRES# GPIO175 GPIO151/ICT4 SLOT2_CONFIG_1 <32> SLOT2_CONFIG_2
1 2 N4 N9 3 6
2<11,17,42,46,47,48,54> SIO_SLP_SUS# PCH_ALW_ON GPIO230 GPIO152/GPTP-OUT3 SLOT2_CONFIG_0 <32> SLOT2_CONFIG_3
RE349 43K_0402_1% M8 4 5
<42> PCH_ALW_ON GPIO231
K8 C11
<11> AC_PRESENT GPIO233 GPIO156/LED0 BREATH_LED# <41>
D10 100K_0804_8P4R_5%
GPIO157/LED1 BAT1_LED# <41>
E11 D11 RPE11
<8> SML1_SMBDATA GPIO007/SMB03_DATA/PS2_CLK0B GPIO153/LED2 BAT2_LED# <41> USB_PWR_SHR_VBUS_EN
Close to pin H1 D8 E1 1 8
<8> SML1_SMBCLK GPIO010/SMB03_CLK/PS2_DAT0B GPIO226/LED3 LCD_VCC_TEST_EN <29>
12P_0402_50V8J
RF@ CE59
68P_0402_50V8J
RF@ CE60
WWAN_WAKE# M13 USB_PWR_SHR_LFT_EN# 2 7

1 1 <32> WWAN_WAKE# GPIO110/PS2_CLK2
K12 E5 USB_PWR_EN1# 3 6
<11> SUSACK# GPIO111/PS2_DAT2 GPIO005/SMB01_DATA/GPTP-OUT4 USH_SMBDAT <36> USB_PWR_EN2#
<32> WLAN_WIGIG60GHZ_DIS# L13 B3 4 5
GPIO112/PS2_CLK1A GPIO006/SMB01_CLK/GPTP-OUT7 EXPANDER_GPU_SMDAT USH_SMBCLK <36>
K11 M7
2 2 <11,14> SIO_PWRBTN# VCCST_PWRGD_EC K10 GPIO113/PS2_DAT1A GPIO012/SMB07_DATA/TOUT3 EXPANDER_GPU_SMCLK EXPANDER_GPU_SMDAT <35>
1 2 M4 100K_0804_8P4R_5%
<11,14,35> VCCST_PWRGD RE308 @ 0_0402_5% N11 GPIO114/PS2_CLK0A/nEC_SCI GPIO013/SMB07_CLK/TOUT2 M3 PBAT_CHARGER_SMBDAT EXPANDER_GPU_SMCLK <35>
<35> LID_CL#_NB GPIO115/PS2_DAT0A GPIO130/SMB10_DATA/TOUT1 PBAT_CHARGER_SMBCLK PBAT_CHARGER_SMBDAT <43,52>
E10 N2
<40> CLK_TP_SIO_I2C_DAT GPIO154/SMB02_DATA/PS2_CLK1B GPIO131/SMB10_CLK/TOUT0 PBAT_CHARGER_SMBCLK <43,52>
C12 N10 SLOT2_CONFIG_2 <32>
<40> DAT_TP_SIO_I2C_CLK GPIO155/SMB02_CLK/PS2_DAT1B GPIO132/SMB06_DATA AC_DIS
A12 1 2
change to PS2 JTAG_TDI E9 GPIO140/SMB06_CLK/ICT5 B6 RTCRST_ON_GPIO141 SYS_LED_MASK# <30,41> @ RE83 100K_0402_5%
<35> JTAG_TDI JTAG_TDO F6 GPIO145/SMB09_DATA/JTAG_TDI GPIO141/SMB05_DATA/SPI1_CLK/UART0_DCD# F7 HW_GPS_DISABLE# 1 2
<35> JTAG_TDO JTAG_CLK C8 GPIO146/SMB09_CLK/JTAG_TDO GPIO142/SMB05_CLK/SPI1_MOSI/UART0_DSR# B4 UPD1_SMBDAT RE12 100K_0402_5%
<35> JTAG_CLK JTAG_TMS GPIO147/SMB08_DATA/JTAG_CLK GPIO143/SMB04_DATA/SPI1_MISO/UART0_DTR# UPD1_SMBCLK UPD1_SMBDAT <26>
C5 C3
<35> JTAG_TMS JTAG_RST# GPIO150/SMB08_CLK/JTAG_TMS GPIO144/SMB04_CLK/SPI1_CS#/UART0_RI# UPD1_SMBCLK <26>
G13
@ PJP20 JTAG_RST# J4 I_BATT_R RE64 1 2 300_0402_5% W LAN_WIGIG60GHZ_DIS# 1 2
GPIO200/ADC00 I_SYS_R I_BATT <52>
1 2 E3 J5 RE312 1 2 300_0402_5% RE8 100K_0402_5%
+1.8V_PRIM +1.8V_3.3V_ALW_VTR3 <35> FAN1_TACH LCD_TST D1 GPIO050/FAN_TACH0/GTACH0 GPIO201/ADC01 J6
I_SYS <49,52> W WAN_WAKE# 1 2
1 <29> LCD_TST GPIO051/FAN_TACH1/GTACH1 GPIO202/ADC02
PAD-OPEN1x1m WWAN_RADIO_DIS# M2 G2 @ RE318 1 2 0_0402_5% RE38 10K_0402_5%
<32> WWAN_RADIO_DIS# GPIO052/FAN_TACH2/LRESET# GPIO203/ADC03 PCH_RSMRST#_GPIO204 TOUCHPAD_INTR# <12,40> SYS_LED_MASK#
CE22 L10 H2 1 2
C <35> FAN1_PWM GPIO053/PWM0/GPWM0 GPIO204/ADC04 USB_PWR_SHR_VBUS_EN C
0.1U_0201_10V6K L11 J2 RE21 10K_0402_5%
2 <43> PS_ID SHD_CS# GPIO054/PWM1/GPWM1 GPIO205/ADC05 USB_PWR_SHR_LFT_EN# USB_PWR_SHR_VBUS_EN <38>
M5 J3 THERMATRIP1# 1 2
CE21 SHD_CLK J8 GPIO055/PWM2/SHD_CS#/(RSMRST#) GPIO206/ADC06 K3 USB_PWR_EN1# USB_PWR_SHR_LFT_EN# <38> RE301 10K_0402_5%
1 GPIO056/PWM3/SHD_CLK GPIO207/ADC07 USB_PWR_EN1# <39>
@ PJP21 0.1U_0201_10V6K N1 D3 PORT80_DET# 1 2
<29>
BIA_PWM_EC TBT_RESET_N_EC_R L8 GPIO001/PWM4 GPIO210/ADC08 AUX_EN_WOWL <42>
1 2 1 2 D2 RE512 100K_0402_5%
+3.3V_ALW <24,26> TBT_RESET_N_EC GPIO002/PWM5 GPIO211/ADC09 LOM_CABLE_DETECT# <30> LOM_CABLE_DETECT#
Close to pin N5 @ RE506 0_0402_5% N6 E2 1 2
PAD-OPEN1x1m 2 <43,52,53> ACAV_IN_NB J9 GPIO014/PWM6/GPTP-IN6 GPIO212/ADC10 G5 USB_PWR_EN2# BC_INT#_ECE1117 <40> @ RE505 100K_0402_5%
<29> PANEL_BKEN_EC VGA_ID GPIO015/PWM7 GPIO213/ADC11 UPD2_ALERT# USB_PWR_EN2# <39> PCIE_WAKE#_R
H11 F5 1 2
D9 GPIO035/PWM8/CTOUT1 GPIO214/ADC12 K4 LPC@ RE35 10K_0402_5%
<11,42> SIO_SLP_WLAN# AC_DIS GPIO133/PWM9 GPIO215/ADC13 PORT80_DET# <32> SHD_CLK RE374 1
<52> AC_DIS
H12 L1 2 24.9_0402_1% SHD_CLK_R1 GPIO126 1 2
GPIO134/PWM10/UART1_RTS# GPIO216/ADC14 PCH_PCIE_WAKE# <11,35>
G10 L3 RE5 10K_0402_5%
<36> BCM5882_ALERT# GPIO135/UART1_CTS# GPIO217/ADC15 LAN_WAKE# <11,30>
MSCLK H10
<35> MSCLK GPIO170/TFDP_CLK/UART1_TX CV2_ON_R SHD_IO0 <35> BC_DAT_ECE1117
MSDATA G9 H8 RE539 1 2 100_0402_5% 1 2
<35> MSDATA GPIO171/TFDP_DATA/UART1_RX GPIO222/SER_IRQ SHD_IO0 CV2_ON
SHD_IO0_R1 <36> SHD_IO0_R2
J7 LPC@ RE366 1 2 24.9_0402_1% LPC@ RE367 1 2 45.3_0402_1% RE365 100K_0402_5%
RPE10 A4 GPIO223/SHD_IO0 L6 SHD_IO1 LPC@ RE368 1 2 24.9_0402_1% SHD_IO1_R1 LPC@ RE369 1 2 45.3_0402_1% SHD_IO1_R2 W WAN_RADIO_DIS# 1 2
8 1 CV2_ON_R <33> AUD_NB_MUTE# EN_INVPWR B2 GPIO022/GPTP-IN0 GPIO224/GPTP-IN4/SHD_IO1 L7 SHD_IO2 LPC@ RE370 1 2 24.9_0402_1% SHD_IO2_R1 LPC@ RE371 1 2 45.3_0402_1% SHD_IO2_R2 RE10 100K_0402_5%
IMVP_VR_ON_EC <29> EN_INVPWR PRIM_PWRGD_GPIO024 GPIO023/GPTP-IN1 GPIO227/SHD_IO2 SHD_IO3 SHD_IO3_R1 SHD_IO3_R2 BT_RADIO_DIS#
7 2 C1 M6 LPC@ RE372 1 2 24.9_0402_1% LPC@ RE373 1 2 45.3_0402_1% 1 2
6 3 PCH_ALW_ON IMVP_VR_ON_EC N7 GPIO024/nRESETI GPIO016/GPTP-IN7/SHD_IO3/ICT3 Place near UE1 Place near UE9 RE11 100K_0402_5%
5 4 RUN_ON_EC <35> IMVP_VR_ON_EC K9 GPIO031/GPTP-OUT1 D6
<11,24,35> SIO_SLP_S3# GPIO032/GPTP-OUT0 BGPO0 EC_FPM_EN <36> +3.3V_ALW
N8 C7
<11> SIO_SLP_S5# GPI0040/GPTP-OUT2 GPIO164/VCI_OVRD_IN ACAV_IN <35,52>
100K_0804_8P4R_5% A5 RE59 close to UE2 at least 250mils
VCI_OUT ALWON <44> +PECI_VREF SHD_IO2_R1
F13 D5 POWER_SW_IN# <35>
1 2
+1.0V_VCCST
1 2
E13 GPIO121/PVT_IO0 GPIO163/VCI_IN0# B5 VCI_IN1# @ RE59 0_0402_5% LPC@ RE376 1K_0402_5%
<43,53> AC_DISC# C13 GPIO124/GPTP-OUT6/PVT_CS# GPIO162/VCI_IN1# D4 VCI_IN2# SHD_IO3_R1 1 2
<36> USH_DET# GPIO125/GPTP-OUT5/PVT_CLK GPIO161/VCI_IN2# POA_WAKE#
GPIO126 E12 E4 POA_WAKE# <36> LPC@ RE377 1K_0402_5%
GPIO126/PVT_IO3 GPIO000/VCI_IN3# SHD_CS# 1 2
+3.3V_ALW RTCRST_ON_GPIO122
0.1U_0201_10V6K
F11 LPC@ RE98 4.7K_0402_5%
F12 GPIO122/BCM0_DAT/PVT_IO1 C6
GPIO123/BCM0_CLK/PVT_IO2 GPIO165/32KHZ_IN/CTOUT0 3.3V_WWAN_EN <42>
1
+3.3V_ALW
CE25
D12
<40> BC_DAT_ECE1117 GPIO046/BCM1_DAT 32KHZ_OUT
D13 F3 @ CE54 1 2 10P_0402_50V8J LPC@ UE9
USH_DET# <40> BC_CLK_ECE1117 GPIO047/BCM1_CLK GPIO221/GPTP-IN3/32KHZ_OUT SHD_CS#
1 2 8 1
2
@ RE526 10K_0402_5% F4 SHD_IO3_R2 7 VCC CS# 2 SHD_IO1_R2
BCM5882_ALERT# <32> SLOT2_CONFIG_3 GPIO041/SYS_SHDN# +PECI_VREF SHD_CLK_R1 HOLD#(IO3) DO(IO1) SHD_IO2_R2
1 2 RE57 2 1 1K_0402_5% B1 J11 6 3
+3.3V_ALW2 SIO_EXT_SMI#_EC SYSPWR_PRES GPIO044/VREF_VTT PECI_EC_R SHD_IO0_R2 CLK WP#(IO2)
RE532 4.7K_0402_5% K7 K13 RE60 1 2 43_0402_5% 5 4
PECI_EC <12>
1
SIO_RCIN#_EC N3 GPIO011/nSMI GPIO042/PECI_DAT/SB-TSI_DAT J12 M3042_PCIE#_SATA DI(IO0) GND

GPIO021/LPCPD# GPIO043/SB-TSI_CLK M3042_PCIE#_SATA <10>
100K_0402_5%
K6 A8 REM_DIODE1_N CE24 1 2 2200P_0402_50V7K REM_DIODE1_N W25Q80DVSSIG_SO8

<8> ESPI_RESET# GPIO061/LPCPD#/ESPI_RESET# DN1_DP1A REM_DIODE1_N <35>
RE58
H7 A7 REM_DIODE1_P REM_DIODE1_P
<8> ESPI_ALERT# GPIO063/SER_IRQ/ESPI_ALERT# DP1_DN1A REM_DIODE2_N REM_DIODE2_N REM_DIODE1_P <35>
K1 A10 CE26 1 2 2200P_0402_50V7K
<35> PCH_PLTRST#_5105 GPIO064/LRESET# DN2_DP2A REM_DIODE2_P REM_DIODE2_P REM_DIODE2_N <35> I_BATT_R
G7 A9 CE3 1 2 2200P_0402_50V7K
REM_DIODE2_P <35>
2
<8,35> ESPI_CLK_5105 H6 GPIO065/PCI_CLK/ESPI_CLK DP2_DN2A B9

<8,35> ESPI_CS# K5 GPIO066/LFRAME#/ESPI_CS# DN3_DP3A B8 I_SYS_R CE4 1 2 2200P_0402_50V7K
<8,35> ESPI_IO0 GPIO070/LAD0/ESPI_IO0 DP3_DN3A REM_DIODE4_N REM_DIODE4_N
B L4 A11 CE27 1 2 2200P_0402_50V7K B
<8,35> ESPI_IO1 GPIO071/LAD1/ESPI_IO1 DN4_DP4A REM_DIODE4_P REM_DIODE4_P REM_DIODE4_N <35>
+3.3V_ALW G6 B10
<8,35> ESPI_IO2 GPIO072/LAD2/ESPI_IO2 DP4_DN4A +VR_CAP REM_DIODE4_P <35>
L5 C10
100K_0402_5%
<8,35> ESPI_IO3 CLKRUN#_EC GPIO073/LAD3/ESPI_IO3 VIN VSET_5105

L2 C9 VSET_5105 <35>
GPIO067/CLKRUN# VSET
2
SIO_EXT_SCI#_EC M1 B11
I_ADP <52>
RE63
SYS_PWROK G4 GPIO100/nEC_SCI VCP H3 THERMATRIP2# PCH_RSMRST# 1 2
VSS_ANALOG
<11,14> SYS_PWROK GPIO106/PWROK GPIO103/THERMTRIP2# THERMATRIP2# <35>
L12 B12 THERMATRIP1# RE342 10K_0402_5%
<6,29> ENVDD_PCH GPIO107/nSMI THERMTRIP1# H_PROCHOT#_R1 SYS_PWROK
H13 1 2 1 2
VSS_ADC
VSS_PLL
GPIO160/PWM11/PROCHOT# H_PROCHOT# <12,49,52>
VR_CAP
MEC_XTAL1 A1 RE288 100_0402_5% RE56 10K_0402_5%
1
MEC_XTAL2_R A3 XTAL1 I_SYS_R 1 2

VSS1
VSS2
VSS3
XTAL2
@
For EMI request RE313 10K_0402_5%
JTAG_RST# LCD_TST 1 2
MEC5105_WFBGA169_11X11 ESPI_CLK_5105 RE20 100K_0402_5%
A6
A13
E6
H4
1+VR_CAP J1
C4
G1
EN_INVPWR 1 2
1U_0402_6.3V6K
1
RE55 100K_0402_5%
33_0402_5%
1
1U_0402_6.3V6K
TBT_RESET_N_EC_R 1 2
@EMI@
1
1
@SHORT PADS~D
JTAG1 CONN@
100_0402_1%
RE95 100K_0402_5%
+VSS_PLL
RE350
1
@ RE65
PORT80_DET# 1 2
CE30
@ RE513 100K_0402_5%
2
2
2
33P_0402_50V8J
CE31
2
+RTC_CELL
2
@EMI@
1
2
VCI_IN1#
CE57
For MEC5105 Rev.A:Pop RE361,Depop RE360,RE362 1 2
For MEC5105 Rev.B:Depop RE361,Pop RE360,RE362 RE507 100K_0402_5%
2
For WDT issue fix options&assessment:Pop RE361, Depop RE362 +3.3V_RUN VCI_IN2# 1 2
SHD_IO2 @ RE360 1 2 0_0402_5% RE508 100K_0402_5%
1.8V_PRIM_PWRGD <48> POA_WAKE# 1 2
2
+3.3V_ALW
10K_0402_5% DMN65D8LDW-7_SOT363-6
RE324 100K_0402_5%
PRIM_PWRGD_GPIO024 @ RE361 1 2 49.9K_0402_1%
RE67
RE362 1 2 100K_0402_5% +3.3V_ALW +3.3V_ALW

100K_0402_5%
1
2
GPIO055 use for SHD_CS# (LPC) or PCH_RSMRST#(eSPI) RUNPWROK

GPIO024 use for SHD_IO2 (LPC) or PRIM_PWRGD(eSPI)
RE68
MEC_XTAL2_R VGA_ID 1 2
PCH_RSMRST#_GPIO204 LPC@ RE363 1 2 0_0402_5% RE84 100K_0402_5%
PCH_RSMRST# <40>
3
RE94 VGA_ID 1 2
1
QE2B
1 2 @ RE85 100K_0402_5%
PCH_RTCRST# <11>
1
@ SHD_CS# 1 2 75_0402_5%
1
RE290 @ESPI@ RE364 0_0402_5% RUN_ON# 5 D
A 32 KHz Clock 0_0402_5% RTCRST_ON_GPIO141 1 2 RTCRST_ON 2 QE12 A
@ RE514 0_0402_5% G L2N7002WT1G_SC-70-3

4
1
RTCRST_ON_GPIO122 1 2 S
2
3
6
@ RE515 0_0402_5% RE93

YE1 VGA_ID0
QE2A
MEC_XTAL1 1 2 MEC_XTAL2 8/28 schematic review 100K_0201_5%

2
Discrete 0
<17,35,42,47,54> RUN_ON
2
10P_0402_50V8J
10P_0402_50V8J
32.768KHZ_9PF_X1A000141000200
UMA 1
1
1
CE28
CE29
2
LPC@ RE337 1 2 0_0402_5% CLKRUN#_EC Compal Electronics, Inc.

<8> CLKRUN# Title
LPC@ RE338 1 2 0_0402_5% SIO_EXT_SMI#_EC
<12> SIO_EXT_SMI# SIO_RCIN#_EC
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT EC MEC5105
LPC@ RE339 1 2 0_0402_5%
<8> SIO_RCIN# LPC@ RE341 1 2 0_0402_5% SIO_EXT_SCI#_EC Size Document Number Rev
<9> SIO_EXT_SCI# NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
5 4 3 2 1
5 4 3 2 1
+1.8V_3.3V_ALW_VTR3
+3.3V_ALW
For SB
2
UE6
RE340
1 5 10K_0402_5%
NC VCC
2
<11> PCH_PLTRST#_EC
1
A 4
3 Y PCH_PLTRST#_5105 <34>
GND
74AUP1G07GW_TSSOP5 +RTC_CELL
PCIE_WAKE# <24,32,37>
1
100K_0402_5%
RE31
@ CE10
1 2 1 2 1 2
<34> PCIE_WAKE#_R PCH_PCIE_WAKE# <11,34>
@ RE275 0_0402_5% 0_0402_5% @ RE274
1U_0402_6.3V6K
2
1 2 Stuff RE275 and no stuff RE274 keep E5 design
<34> POWER_SW_IN# POWER_SW#_MB <11,41>
RE33 1K_0402_5% Stuff RE274 and no stuff RE275 to save two GPIOs on EC(PCH_PCIE_WAKE# should be output with OD)
ESPI LPC
2.2U_0402_6.3V6M
1
PAGE
D D
CE12
2 1
2
0_0402_5% @ RE304
CONN@ JESPI
+3.3V_RUN
8 RC25_10K RC8_15ohm +3.3V_ALW
+3.3V_ALW
@ CE53
1 2
RC13/RC27_8.2K
+3.3V_ALW
100K_0402_5%
1 UE4
1 2
1
RE25
0.1U_0402_25V6K
2 3
5
ESPI_IO0 <8,34> 1 5
3 4 IMVP_VR_ON_EC 1 NC VCC
ESPI_IO1 <8,34>
P
4 5 <34> IMVP_VR_ON_EC B IMVP_VR_ON
ESPI_IO2 <8,34> 4 2
5 6 RE26 SIO_SLP_S3# 2 O A 4
ESPI_IO3 <8,34> <11,24,34,35> SIO_SLP_S3#
2
6 7 A Y VCCST_PWRGD <11,14,34>
G
LID_CL#_NB 2 1 UE3 3
7 8 20_0402_5% PCH_PLTRST#_EC ESPI_CS# <8,34> <34> LID_CL#_NB LID_CL# <41> GND
.047U_0402_16V7K
LPC@ RE3751 TC7SH08FU_SSOP5~D
3
8 9
9 10
18 RC212_0ohm RC211_0ohm 10_0402_5% 74AUP1G07GW_TSSOP5
1
10 ESPI_CLK_5105 <8,34>
CE8
2
IMVP_VR_ON <49,54>
GND1
GND2
11
12
0603 0603 0_0402_5%
1 2
@ RE280
ACES_50506-01041-P01
RUN_ON_EC 2 1
<34> RUN_ON_EC RUN_ON <17,34,42,47,54>
0_0402_5% @ RE292
RE337,RE338 RF Request +3.3V_ALW

@ CE52
RE339,RE340, +3.3V_ALW 1 2
31 0.1U_0402_25V6K
5
68P_0402_50V8J
RE341
1
1
P
B
RF@ CE61
4
2 O
A
G
2 UE5
LPC 80Port Debug LPC ESPI
0_ohm TC7SH08FU_SSOP5~D
3
1 +3.3V_RUN +3.3V_RUN
2 +3.3V_RUN +3.3V_RUN
+3.3V_ALW +3.3V_ALW
RE2 / RE3
+3.3V_ALW
3 LPC_LAD0 ESPI_IO0
2
C
4 LPC_LAD1 ESPI_IO1 32 0_ohm RE343
130K_0402_5%
RE79
4.3K_0402_5%
RE300
130K_0402_5%
C
5 LPC_LAD2 ESPI_IO2
1
BOARD_ID PANEL_ID
<34> TYPEC_ID <34> BOARD_ID <34> PANEL_ID
1
6 LPC_LAD3 ESPI_IO3
CE62 CE40 CE47
4700P_0402_25V7K 4700P_0402_25V7K 4700P_0402_25V7K
2
7 LPC_FRAME# ESPI_CS#
8 PCH_PLTRST# NA RE343 CE62 REV RE79 CE40 REV RE300 CE47 PANEL SIZE
240K 4700p Single Port ACE w/o AR 240K 4700p X00 240K 4700p 12"
9 GND GND
WDT option 130K 4700p Single Port ACE w/AR 130K 4700p X01 130K 4700p 14"
* *
10 LPC_CLOCK ESPI_CLK MEC5105 rev.B Pop RE361, QE13, CE503, RE530, UE7, CE5,CE6, RE348 62K 4700p Dual Port ACE w/o AR 62K 4700p X02 33K 4700p 15"
Depop RE362, RE536, RE537 33K 4700p Dual Port ACE w/AR 33K 4700p X03 4.3K 4700p 17"
8.2K 4700p Dual Port ACE (w/AR +w/o AR) 8.2K 4700p X04
Pop RE362, RE536
MEC5105 rev.C 4.3K 4700p * 4.3K 4700p A00
Depop RE361, QE13, CE503, RE530, UE7, CE5,CE6, RE348, RE537
2K 4700p 2K 4700p
+3.3V_ALW 1K 4700p 1K 4700p PANEL_ID rise time is measured from 5%~68%.
@
UE7
5 1
1
VDD RESET PCH_DPWROK <11> PD_ACE_DET# rise time is measured from 5%~68%. BOARD_ID rise time is measured from 5%~68%.
@ CE6 3 4
MR CT
2
0.1U_0402_25V6K @ 2 VSET_5105
GND VSET_5105 <34>
1
2 RE348 @
0.1U_0402_25V6
10K_0402_5% RT9826-30GB CE5
1
1.58K_0402_1%
3300P_0402_50V7-K
2
1
1
CE38
RE77
1 2 RE536 1 2 0_0402_5%
<34> PCH_DPWROK_EC
2
@ RE34 0_0402_5% +3.3V_ALW
2
2
@RE537
GPIO223 is OD. When EC fetches
8
7
6
5
10K_8P4R_5%
10K_0402_5%
CT: 3300 pF ~ 10ms delay
49.9_0402_1%
the code, set GPIO223 to Low.
RE71
@ RE530 1M_0402_5%
RPE7
2 1
Rest=1.58K , Tp=96 degree???
<34,35,52> ACAV_IN SHD_IO0 <34>
Reset Threshold Level 3.0V
1
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
100K_0402_5%
1U_0402_6.3V6K
@ RE75
CONN@
1
2
3
4
@ CE503
RE72
RE73
RE74
B JDEG1 B
1
1 +EC_DEBUG_VCC
1 2 JTAG_TDI Link 50271-0040N-001 DONE
JTAG_TDI <34>
2
2 3 JTAG_TMS JFAN1
JTAG_TMS <34>
2
3 4 JTAG_CLK 1
4 5 JTAG_TDO JTAG_CLK <34> 1 2 FAN1_PWM
RE86
11 5 6 JTAG_TDO <34> 2 3 FAN1_TACH FAN1_PWM <34>
MSCLK 10K_0402_5%
G1 6 3 FAN1_TACH <34>
5
12 7 MSDATA 1 2 +3.3V_RUN 4
G2 7 HOST_DEBUG_TX 4 +5V_RUN
8
To prevent backdrive to PCH_DPWROK_EC 8 DEBUG_TX
10U_0603_6.3V6M
4 3 6 1 9 5
<34,35,52> ACAV_IN when AC is plugged before +3.3V_ALW ramps up. 9 GND1
1
10 6
10 GND2
1
FAN1_PWM
@ DE1
1 2 1 2
@ QE13B @ QE13A
<9> SBIOS_TX
CE32
ACES 50506-01041-P01 RE306 RE48 10K_0402_5% ACES_50271-0040N-001
DMN65D8LDW-7_SOT363-6 DMN65D8LDW-7_SOT363-6 0_0402_5% 1 2 FAN1_TACH CONN@
2
@ RE51 10K_0402_5%
HOST_DEBUG_TX <32,34>
2
MSDATA <34>
1 2 MSCLK <34>
In DC mode, ACAV_IN is LOW. This circuit doesn't affect PCH_DPWROK. @ RE30 0_0402_5%
In AC mode, 1. ACAV_IN is high. GPIO223 is tri-state. QE13B is ON. QE13A can prevent backdrive to PCH_DPWROK.
2. EC fetches code and the drives GPIO223 to LOW to turn off QE13B. When QE13B is off, un-plug/plug AC will not affect DSW_DPWROK.
3. When WDT occurs, GPIO223 is tri-state (EC reset). ACAV_IN charges CE503. When AC is removed, ACAV_IN goes LOW immediately. Thermal diode mapping
QE13B still kepps on according to RC discharging rate. PCH_DPWROK is LOW because ACAV_IN is LOW.
5105 Channel Location
Place under CPU
Place CE35 close to the QE3 as possible
DP1/DN1 CPU (QE3)
REM_DIODE1_P <34>
100P_0402_50V8J
Control Byte DP2/DN2 WiGig (QE5)
1
C
@ CE35
2
0 1 0 0 A2 A1 A0 R/W DN2a/DP2a DDR (QE7) B
1
E QE3
3
R/W = 0 = Write LMBT3904WT1G SC70-3
R/W = 1 = Read DP3/DN3 NA REM_DIODE1_N <34>
+3.3V_ALW
DP2/DN2 for WiGig on QE5, place QE5 close
DP4/DN4 CPU VR (QE6) to WiGig and CE37 close to QE5
SMBus address 0x40 1
1
1U_0402_6.3V6K
0.1U_0402_25V6K
CE1
CE2
DP4/DN4 for Skin on

2
2
CHECK RE69 QE6, place QE6 close to DN2a/DP2a for DDR on QE7, place QE7 close
+3.3V_ALW Vcore VR choke. to DDR and CE46 close to QE7
0.1U_0402_25V6
1 2
+1.0VS_VCCIO +3.3V_ALW THERMATRIP2# <34>
REM_DIODE4_P <34> REM_DIODE2_P <34>
LMBT3904WT1G SC70-3
UE2 SIO_SLP_S3# <11,24,34,35> 8.2K_0402_5%
1
+3.3V_ALW
CE36
100P_0402_50V8J
LMBT3904WT1G SC70-3
@ QE11
1
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
100P_0402_50V8J
100P_0402_50V8J
@ CE37
QE7
18
E
C
G
VSTBY33
1
@ RE13
@ RE15
@ RE17
@ CE46
2 2
C C B
2
1
2
10K_0402_5%
QE4
@CE39
A 19 1 3 1 2 2 2 B A
2
<34> EXPANDER_GPU_SMCLK 20 SCL RE70 2.2K_0402_5% B B C E QE5
D
<34> EXPANDER_GPU_SMDAT
3
SDL +1.0V_VCCST
RE6
16 E E QE6 LMBT3904WT1G SC70-3

VBUS2_ECOK <43,53>
2
3
1 GP7 15 L2N7002WT1G_SC-70-3 LMBT3904WT1G SC70-3
2 A2 GP6 14 DCIN2_EN <43>
SATA_LED_EN <41> REM_DIODE2_N <34>
2
3 A1 GP5 13 1 2
A0 GP4 VBUS1_ECOK <53> <12,20,21> H_THERMTRIP# REM_DIODE4_N <34>
WRST# 12 @ RE90 0_0402_5%
4 GP3 11 DCIN1_EN <53>
WRST#
WRST# GP2
1
1
1U_0402_6.3V6K
10K_0402_5%
10K_0402_5%
10K_0402_5%
10
EXPANDER_ALERT# GP1
RE14
RE16
RE18
7 9
T267@ PAD~D INT GP0 USH_PWR_STATE# <36>
CE500
2
5
6 NC
2
8 NC 17
NC VSS 21
EPAD DELL CONFIDENTIAL/PROPRIETARY
MCP23008T-E-ML_QFN20_4X4
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT MEC5105 support
Link Microchip MCP23008 SA0000ADQ00 OK (9/6) BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
1.0
5 4 3 2 1
5 4 3 2 1
For NUVOTON TPM RF Request RF Request

+3.3V_ALW +3.3V_M_TPM
place CZ50, CZ75 as close as UZ12.8
12P_0402_50V8J
RF@ CZ57
68P_0402_50V8J
RF@ CZ58
12P_0402_50V8J
RF@ CZ59
68P_0402_50V8J
RF@ CZ60
@ RZ89 1 2 0_0402_5% +UZ12_TPM
D +3.3V_RUN 1 1 1 1 D
4.7U_0402_6.3V6M
0.1U_0201_10V6K
1 1 2 2 2 2
CZ75
CZ50
2 2
+3.3V_ALW_PCH +3.3V_M_TPM
PJP391
1 2
PAD-OPEN1x1m
+3.3V_ALW
+3.3V_M_TPM +3.3V_ALW
1 2 USH_SMBCLK
RZ8 4.7K_0402_5%
1 2 TPM_PIRQ# 1 2 USH_SMBDAT
0.1U_0201_10V6K
10U_0603_10V6M
RZ69 10K_0402_5% RZ9 4.7K_0402_5%
1 1 place CZ51,CZ52 as close as UZ12.1
+3.3V_RUN 1 2 USH_PWR_STATE#
CZ51
CZ52
RZ10 100K_0402_5%
1
2 2
@ RZ362
10K_0402_5%
UZ12
USH CONN
1 +3.3V_M_TPM
2
1 2 29 VSB
C <11,17,47> SIO_SLP_S0# @ RZ112 30 GPIO0/SDA/XOR_OUT 8 +UZ12_TPM C
0_0402_5%
1 2 TPM_LPM# 3 GPIO1/SCL VDD 14 JUSH1 CONN@
@ RZ363 0_0402_5% 6 GPIO2/GPX VHIO 22 @ RZ85 1 2 0_0402_5% +PWR_SRC_R 1
GPIO3/BADD VHIO +PWR_SRC 1
0.1U_0201_10V6K
0.1U_0201_10V6K
10U_0603_10V6M
2
RZ58 1 2 33_0402_5% PCH_SPI_D1_2_R 24 2 3 2
<8> PCH_SPI_D1_R1 LAD0/MISO NC 1 1 1 <34> CV2_ON 3
RZ59 1 2 33_0402_5% PCH_SPI_D0_2_R 21 7 4
<8> PCH_SPI_D0_R1 LAD1/MOSI NC <34> POA_WAKE# 4
CZ53
CZ54
CZ55
18 10 5
<9> TPM_PIRQ# 15 LAD2/SPI_IRQ# NC 11 <34> EC_FPM_EN 6 5
LAD3 NC 25 2 2 2 7 6
EMI@ RZ60 1 2 33_0402_5% PCH_SPI_CLK_2_R 19 NC 26 8 7
<8> PCH_SPI_CLK_R1 @ RZ61 1 2 0_0402_5% PCH_SPI_CS#2_R 20 LCKL/SCLK NC 31 <10> USB20_N10 9 8
<8> PCH_SPI_CS#2 17 LFRAME#/SCS# NC <10> USB20_P10 10 9
<11> PLTRST_TPM# 27 LRESET#/SPI_RST#/SRESET# 9 11 10
TPM_GPIO4 13 SERIRQ GND 16 <34> USH_SMBCLK 12 11
T283@ PAD~D CLKRUN#/GPIO4/SINT# GND <34> USH_SMBDAT 12
28 23 CZ53,CZ55 as close as UZ12.14 13
LPCPD# GND <34> BCM5882_ALERT# 13
1
10K_0402_5%
32 CZ54 as close as UZ12.22 14

GND 14
RZ62
4 33 15
5 PP PGND 12 16 15
TEST Reserved +3.3V_ALW 16
17
NPCT650VB2YX_QFN32_5X5 18 17
+5V_ALW
2
19 18
+3.3V_RUN 19
20
+5V_RUN USH_RST#_R 20
@ RZ114 1 2 0_0402_5% 21
<11,24,31,32,37> PCH_PLTRST#_AND 22 21
<35> USH_PWR_STATE# 23 22
<12> CONTACTLESS_DET# 24 23
25 24
@ RZ87 1 2 0_0402_5% USH_DET#_R 26 25
<34> USH_DET# 26
@ DZ7 27
2 1 28 GND1
PCH_SPI_CLK_2_R GND2
B RB751S40T1G_SOD523-2 B
CVILU_CF5026FD0RK-05-NH
33_0402_5%
2
@EMI@
RZ63
Update to LTCX007Q600 (DVT1.0)

1
0.1U_0402_25V6
PCH_PLTRST#_AND Close to JUSH1

1
@EMI@
+5V_ALW +5V_RUN +3.3V_RUN +3.3V_ALW

+3.3V_M_TPM
CZ56
.047U_0402_16V7K
ESD@ CZ61
2
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1 1 1 1
@
2
3
CZ64
CZ66
CZ67
CZ68
PCH_SPI_CS#2_R 1 2 2
G LP2301ALT1G_SOT23-3
@ RZ113 100_0402_5% @ QZ9 For ESD solution 2 2 2 2
D
1
TPM_LPM#
1
RF Request
@ RZ111 +5V_ALW +5V_RUN +3.3V_RUN +3.3V_ALW
RZ113 RZ111 POP 10K_0402_5% RF Request
RF@ CZ69
RF@ CZ71
RF@ CZ72
RF@ CZ73
68P_0402_50V8J
68P_0402_50V8J
68P_0402_50V8J
68P_0402_50V8J
1K 1K MMBT3906
2
USH_SMBCLK 1 2 1 1 1 1
100 10K LP2301A @RF@CZ62 68P_0402_50V8J
USH_SMBDAT 1 2
A @RF@CZ63 68P_0402_50V8J 2 2 2 2 A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT USH & TPM
5 4 3 2 1
5 4 3 2 1
For Brekenridge 12/14/15 UMA/Steamboat
RF Request
+3.3V_HDD_M2 +3.3V_HDD_M2
D D
0.1U_0201_10V6K
0.1U_0201_10V6K
68P_0402_50V8J
@RF@CN60
22U_0603_6.3V6M
22U_0603_6.3V6M
@
1 1
1
CN61
CN62
1
CN63
CN64
2
2
2 2
2
2280 SSD
NGFF slot C Key M

Place near HDD CONN
+3.3V_HDD_M2 2.8A
JNGFF3 CONN@
@ PJP31
1 2 1 2
GND 3.3VAUX +3.3V_RUN
3 4
5 GND 3.3VAUX 6 PAD-OPEN1x3m
7 PERn3 N/C 8
9 PERp3 N/C 10 NVME_LED# 1 2
11 GND DAS/DSS# 12 SATALED# <10,41>
+3.3V_HDD_M2 @ RN100 0_0402_5%
13 PETp3 3.3VAUX 14
15 PETn3 3.3VAUX 16
1 2 M2280_DEVSLP 17 GND 3.3VAUX 18
@ RN37 10K_0402_5% 19 PERn2 3.3VAUX 20
if signal is PCIE GEN3/SATA GEN3 maybe change C value PERp2 N/C
or no need for DG0.9 SATA EXPRESS HDD 21 22
C 23 GND N/C 24 C
25 PETp2 N/C 26
27 PETn2 N/C 28
29 GND N/C 30
<10> PCIE_PRX_DTX_N11 31 PERn1 N/C 32
<10> PCIE_PRX_DTX_P11 33 PERp1 N/C 34
CN69 2 1 0.22U_0402_10V6K PCIE_PTX_C_DRX_N11 35 GND N/C 36
<10> PCIE_PTX_DRX_N11 PCIE_PTX_C_DRX_P11 PETn1 N/C
CN70 2 1 0.22U_0402_10V6K 37 38
<10> PCIE_PTX_DRX_P11 39 PETp1 DEVSLP 40 M2280_DEVSLP <10>
41 GND N/C 42
<10> PCIE_PRX_DTX_P12 43 PERn0/SATA-B+ N/C 44
<10> PCIE_PRX_DTX_N12 45 PERp0/SATA-B- N/C 46
CN71 2 1 0.22U_0402_10V6K PCIE_PTX_C_DRX_N12 47 GND N/C 48
<10> PCIE_PTX_DRX_N12 PCIE_PTX_C_DRX_P12 PETn0/SATA-A- N/C
CN72 2 1 0.22U_0402_10V6K 49 50
<10> PCIE_PTX_DRX_P12 51 PETp0/SATA-A+ PERST# 52 PCH_PLTRST#_AND <11,24,31,32,36>
53 GND CLKREQ# 54 PCIE_WAKE# CLKREQ_PCIE#3 <11>
<11> CLK_PCIE_N3 55 REFCLKN PEWake# 56 PCIE_WAKE# <24,32,35>
<11> CLK_PCIE_P3 57 REFCLKP N/C 58
GND N/C
67 68 SUSCLK_R 1 2
69 N/C SUSCLK(32kHz) (O)(0/3.3V) 70 @ RN99
SUSCLK <11,32>
0_0402_5%
<10> M2280_PCIE_SATA# 71 PEDET (OC-PCIe/GND-SATA) 3.3VAUX 72
73 GND 3.3VAUX 74
75 GND 3.3VAUX
GND
77 76
GND GND
B LOTES_APCI0170-P001A B
Link DC04000LI00 DONE
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT M2 2280 Socket
5 4 3 2 1
5 4 3 2 1
+5V_USB_CHG_PWR
DI4 ESD@ JUSB1 CONN@

USB3_PRX_DTX_N1 1 1 10 9 USB3_PRX_DTX_N1 1
<10> USB3_PRX_DTX_N1 VBUS
150U_B2_6.3VM_R35M
USB20_N1_R 2
D-
100U_1206_6.3V6M
0.1U_0201_10V6K
D USB3_PRX_DTX_P1 2 2 9 8 USB3_PRX_DTX_P1 USB20_P1_R 3 D
<10> USB3_PRX_DTX_P1 @ 4 D+
1 1 1 GND
CI17
2 1 USB3_PTX_C_DRX_N1 4 4 7 7 USB3_PTX_C_DRX_N1 USB3_PRX_DTX_N1 5
<10> USB3_PTX_DRX_N1 SSRX-
CI32
CI14
CI13 0.1U_0402_25V6 + USB3_PRX_DTX_P1 6 10
SSRX+ GND
2
2 1 USB3_PTX_C_DRX_P1 5 5 6 6 USB3_PTX_C_DRX_P1 7 11
<10> USB3_PTX_DRX_P1 2 2 GND GND
ESD@ DI5
CI16 0.1U_0402_25V6 USB3_PTX_C_DRX_N1 8 12
2
3 3 2 USB3_PTX_C_DRX_P1 9 SSTX- GND 13
SSTX+ GND
1
8 ACON_TCRA2-9U1U93
1
L05ESDL5V0NA-4_SLP2510P8-10-9
LINK DC231604011 DONE
RF Request
+5V_USB_CHG_PWR
LI7 EMI@
SW_USB20_N1 1 2 USB20_N1_R
SW_USB20_P1 4 3 USB20_P1_R
12P_0402_50V8J
RF@ CI43
68P_0402_50V8J
RF@ CI44
1 1
EXC24CQ900U_4P
C C
+5V_ALW
+5V_USB_CHG_PWR 2 2
UI3
1 12
VIN VOUT
2
<10> USB20_N1 3 DM_OUT
<10> USB20_P1 DP_OUT 10 SW_USB20_P1
13 DP_IN 11 SW_USB20_N1
<10> USB_OC0# FAULT# DM_IN
ILIM_SEL 4
ILIM_SEL
5 15
<34> USB_PWR_SHR_VBUS_EN EN ILIM_L 16 2 1
RI14
ILIM_HI 22.1K_0402_1%
6
<34> USB_PWR_SHR_LFT_EN# 7 CTL1 9
8 CTL2 NC 14
CTL3 GND 17
Thermal Pad
+5V_ALW SLGC55544CVTR_TQFN16_3X3
RI13 2 1 ILIM_SEL SA000097E10 Link Done

10K_0402_5%
B +5V_ALW B
47U_0603_6.3V6M
47U_0603_6.3V6M
10U_0402_6.3V6M
0.1U_0201_10V6K
1 1 1 1
@ CI34
@ CI33
@ CI31
CI19
2 2 2 2
Place near UI3.1
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT JUSB1+PS
5 4 3 2 1
5 4 3 2 1
For Breckenridge 14&15/Steamboat 14

DI1 ESD@
USB3_PRX_DTX_N3 1 1 10 9 USB3_PRX_DTX_N3 RF Request +USB_EX2_PWR
<10> USB3_PRX_DTX_N3
USB3_PRX_DTX_P3 2 2 9 8 USB3_PRX_DTX_P3 +USB_EX2_PWR JUSB2 CONN@
<10> USB3_PRX_DTX_P3 1
2 1 USB3_PTX_C_DRX_N3 4 4 USB3_PTX_C_DRX_N3 USB20_N2_R VBUS
<10> USB3_PTX_DRX_N3 7 7 2
D-
CI5 0.1U_0402_25V6 USB20_P2_R 3
D+
0.1U_0201_10V6K
2 1 USB3_PTX_C_DRX_P3 5 5 6 6 USB3_PTX_C_DRX_P3 4
<10> USB3_PTX_DRX_P3 GND
100U_1206_6.3V6M
CI4 0.1U_0402_25V6 1 USB3_PRX_DTX_N3 5
SSRX-
CI3
3 3 USB3_PRX_DTX_P3 6 10
SSRX+ GND
CI1
7 11
GND GND
2
12P_0402_50V8J
RF@ CI45
68P_0402_50V8J
RF@ CI46
8 1 1 USB3_PTX_C_DRX_N3 8 12
2
2 SSTX- GND
ESD@ DI2
USB3_PTX_C_DRX_P3 9 13
2
L05ESDL5V0NA-4_SLP2510P8-10-9 SSTX+ GND
D D
C-K_26230A-8K1A-02
2 2
1
1
EXC24CQ900U_4P
USB20_P2 4 3 USB20_P2_R
<10> USB20_P2
USB20_N2 1 2 USB20_N2_R
<10> USB20_N2
LI3 EMI@
Link DC231604112(Temp) DONE
DFB request:
main SM070003Z00 (INPAQ_MCM1012B900F06BP_4P)
Footprint use 2nd source SM070004400 (PANAS_EXC24CQ900U_4P) +USB_EX2_PWR
Pitch change from 0.5mm to 0.55mm
+5V_ALW
UI1
1
5 OUT
IN 2
GND
10U_0603_10V6M
0.1U_0201_10V6K
4
<34> USB_PWR_EN1# EN
1 3 USB_OC1# <10>
OCB
@ CI6
CI7
SY6288D20AAC_SOT23-5
2
2
C C
RF Request 12" not support

+USB_EX3_PWR
DI6 ESD@ +USB_EX3_PWR
2 1 USB3_PTX_C_DRX_P4 1 1 10 9 USB3_PTX_C_DRX_P4
<10> USB3_PTX_DRX_P4
CI28 0.1U_0402_25V6 JUSB3 CONN@
2 1 USB3_PTX_C_DRX_N4 2 2 9 8 USB3_PTX_C_DRX_N4 1
<10> USB3_PTX_DRX_N4 USB20_N3_R VBUS
CI27 0.1U_0402_25V6 2
USB3_PRX_DTX_P4 4 4 USB3_PRX_DTX_P4 USB20_P3_R D-
7 7 3
<10> USB3_PRX_DTX_P4 D+
100U_1206_6.3V6M
0.1U_0201_10V6K
4
GND
12P_0402_50V8J
RF@ CI47
68P_0402_50V8J
RF@ CI48
USB3_PRX_DTX_N4 5 5 6 6 USB3_PRX_DTX_N4 USB3_PRX_DTX_N4 5
<10> USB3_PRX_DTX_N4 1 1 1 SSRX-
CI10
USB3_PRX_DTX_P4 6 10
SSRX+ GND
CI8
3 3 7 11
GND GND
USB3_PTX_C_DRX_N4 8 12
2
SSTX- GND
2
8 2 2 2 USB3_PTX_C_DRX_P4 9 13
SSTX+ GND
ESD@ DI3
2
L05ESDL5V0NA-4_SLP2510P8-10-9 C-K_26230A-8K1A-02
1
1
B B
Link DC231604112(Temp) DONE

EXC24CQ900U_4P
USB20_P3 4 3 USB20_P3_R
<10> USB20_P3
USB20_N3 1 2 USB20_N3_R
<10> USB20_N3
LI4 EMI@ +USB_EX3_PWR
+5V_ALW
UI2
1
5 OUT
IN 2
GND
10U_0603_10V6M
0.1U_0201_10V6K
4
<34> USB_PWR_EN2# EN
@ CI11
1 3
OCB USB_OC2# <10>
CI12
SY6288D20AAC_SOT23-5
2
2
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT JUSB2&JUSB3
5 4 3 2 1
5 4 3 2 1
RF Request
+3.3V_TP
Touch Pad +3.3V_RUN +3.3V_TP

1
+3.3V_TP @ PJP35 RF@CZ83
1 2 68P_0402_50V8J
2
PAD-OPEN1x1m
4.7K_0402_5%
4.7K_0402_5%
1
1
RZ18
RZ19
D D
PS2
2
2 1 DAT_TP_SIO_R CVILU_CF5020FD0RK-05-NH
<34> DAT_TP_SIO_I2C_CLK
@ RZ22 0_0402_5%
2 1 CLK_TP_SIO_R
<34> CLK_TP_SIO_I2C_DAT 22
@ RZ23 0_0402_5%
21 GND
GND
10P_0402_50V8J
10P_0402_50V8J
Keyboard
1
CZ80
CZ81
1 2 I2C1_SDA_TP_R KB_DET# 20
@ RZ346 0_0402_5% <12> KB_DET# 19 20
2
1 2 I2C1_SCK_TP_R 18 19
@ RZ347 0_0402_5% 17 18
16 17
+5V_RUN 16
15
+3.3V_ALW BC_INT#_ECE1117 15 +3.3V_TP +3.3V_ALW +5V_RUN
I2C From EC 14
<34> BC_INT#_ECE1117 BC_DAT_ECE1117 13 14
<34> BC_DAT_ECE1117 12 13
BC_CLK_ECE1117 11 12
<34> BC_CLK_ECE1117 11
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
10 1 1 1
10
@
9
+3.3V_TP 9
CZ90
CZ91
CZ92
DAT_TP_SIO_R 8
+3.3V_TP +3.3V_TP CLK_TP_SIO_R 7 8
6 7 2 2 2
5 6
<12,34> TOUCHPAD_INTR# 5
10K_0402_5%
10K_0402_5%
4
4
1
@ @ I2C1_SDA_TP_R 3
3
1
2.2K_0402_5%
2.2K_0402_5%
RZ116
RZ117
I2C1_SCK_TP_R 2
2
RZ20
RZ21
1
C Reserve for future use 1 Place close to JKBTP1 C
JKBTP1 CONN@
2
2
2
1 2 I2C1_SDA_TP_R
<9> I2C1_SDA_TP @ RZ26 0_0402_5% CHECK PIN DEFINE
1 2 I2C1_SCK_TP_R
<9> I2C1_SCK_TP @ RZ29 0_0402_5%
I2C From CPU Update to LTCX007Q500 (DVT1.0)
@ EDP Cable nonTS_HD-HD Cam

@ LED Cable
Plan is for I2C to be driven by the EC for Win7 and Pre-OS (will utilize Intel I2C drivers for Win7) Part Number Description
For Win8.1 and 10 the EC will control TP over I2C Pre-OS and then the PCH will drive I2C when in Windows Part Number Description
Route PS2 from EC to the touch pad also for contingency plan if I2C has issues DC02C00DX00 H-CONN SET 1S1 MB-LCD-CAM HD NTS
DC02002LY00 H-CONN SET 1S1 MB-LED/B
@ EDP Cable nonTS_FHD-HD Cam
@ FP FFC
DC02C00DW00 H-CONN SET 1S1 MB-LCD-CAM FHD NTS
NBX00023800 FFC 12P F P=0.5 PAD=0.3 66MM FP-USH 1S1
@ EDP Cable nonTS_FHD-IR
@ TP FFC
DC02C00DY00 H-CONN SET 1S1 MB-LCD-CAM FHD IR NTS
NBX00023900 FFC 20P F P=0.5 PAD=0.3 118MM MB-TP 1S1
B @ EDP Cable TS_FHD-HD Cam B
@ USH Board FFC
DC02C00E300 H-CONN SET 1S1 MB-LCD-CAM FHD TS
NBX00023A00 FFC 26P F P=0.5 PAD=0.3 50MM MB-USH 1S1
RSMRST circuit @ EDP Cable infinity nonTS_FHD-3mm RGB

Part Number Description @ RTC BATT
DC02C00DZ00 H-CONN SET 1S1 MB-LCD-CAM FHD INF NTS Part Number Description
+3.3V_ALW GC02001DS00 BATT CR2032 3V 225MAH PA 5 W/C 30MM

@ EDP Cable infinity TS_FHD-3mm RGB
@ CZ82
1 2 Part Number Description @ FAN
DC02C00E400 H-CONN SET 1S1 MB-LCD-CAM FHD INF TS Part Number Description
0.1U_0201_10V6K
DC28A000800 FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA
5
@ EDP Cable infinity TS_QHD-3mm RGB

1
P
<34> PCH_RSMRST# B Part Number Description

4 @ Speak
O PCH_RSMRST#_AND <11,14>
2
<44> ALW_PWRGD_3V_5V A DC02C00E500 H-CONN SET 1S1 MB-LCD-CAM QHD INF TS Part Number Description
G
UZ6 PK230003Q0L SPK PACK ZJX 2.0W 4 OHM FG

3
TC7SH08FU_SSOP5~D
A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Keyboard
5 4 3 2 1
5 4 3 2 1
HDD LED MUX Battery LED

means EC can switch battery white led and HDD LED by hot key “Fn+H”
<35> SATA_LED_EN
BATT_WHITE#
5
D 4 3 BAT2_LED#_R 1 2 BATT_WHITE# D
<10,37> SATALED# <34,41> BAT2_LED#
RZ361 150_0402_5%
@ QZ2B
3
R1=10K/R2=10K 1 2 BATT_YELLOW#
Change back to SB000002T00 4/25 <34> BAT1_LED#
2 RZ28 330_0402_5%
+3.3V_ALW DDTA144VCA-7-F_SOT23-3
@ QZ3
1
2
LID SWITCH <34,41> BAT2_LED#
1
@ QZ2A
6 BAT2_LED#_R
1
@ RZ25
2
150_0402_5%
+3.3V_ALW DMN65D8LDW-7_SOT363-6
Infi@
1
UZ1
GND
2 3
VDD VOUT LID_CL# <35,41>
APX8131AI-TRG_SOT23-3
Place CZ94 near UZ1.
LED P/N change to SC50000FL00 from SC50000BA00

0.1U_0201_10V6K
1
Breath LED
@ CZ94
2
+5V_ALW
QZ7B LED3
DMN65D8LDW-7_SOT363-6 LTW-C193DC-C_WHITE
C
Hall sensor: SA00009EM00 <34> BREATH_LED#
4 3 BREATH_LED#_Q 1 2 BREATH_WHITE_LED_SNIFF# 1 2
C
RZ32 330_0402_5%
(MAX hight is 1.45mm) Place LED3 close to SW3
5
+3.3V_ALW
MASK_BASE_LEDS#
@ CZ93
1 2
0.1U_0201_10V6K
5
1
P
<30,34> SYS_LED_MASK# B MASK_BASE_LEDS#

4
2 O
<35,41> LID_CL# A
G
UZ10
TC7SH08FU_SSOP5~D
3
POWER & INSTANT ON SWITCH

LED board CONN
2 SW3 1
<11,35> POWER_SW#_MB +5V_ALW
JLED1 CONN@
1
BATT_YELLOW# 2 1
4 3 BATT_WHITE# 3 2
4 3
SKRBAAE010_4P 5 4
<35,41> LID_CL# 5
6
+3.3V_ALW 6
7
8 GND
B B
GND
ACES_50209-0060N-P01
LED Circuit Control Table

Fiducial Mark
@ FD1
1 SYS_LED_MASK# LID_CL# CLIP1 CONN@ CLIP2 CONN@ CLIP3 CONN@ CLIP4 CONN@
1 1 1 1
FIDUCIAL MARK~D P1 P1 P1 P1
@ FD2
Mask All LEDs (Unobtrusive mode) 0 X EMIST_SUL-12A2M EMIST_SUL-12A2M EMIST_SUL-12A2M EMIST_SUL-12A2M
1
Mask Base MB LEDs (Lid Closed) 1 0
FIDUCIAL MARK~D
Do not Mask LEDs (Lid Opened) 1 1
@ FD3
1 CLIP5 CONN@ CLIP6 CONN@ CLIP7 CONN@ CLIP8 CONN@
1 1 1 1
FIDUCIAL MARK~D P1 P1 P1 P1
For JAE JSIM1 boss hole
@ FD4
CPU NGFF EMIST_SUL-12A2M EMIST_SUL-12A2M EMIST_SUL-12A2M EMIST_SUL-12A2M
1 @ H1 @ H2 @ H3 @ H4 @ H5 @ H6 @ H7 @ H8 @ H9 @ H10 @ H12 @ H14 @ H15 @ H17 @ H18 @ H19 @ H21 @ H22 @ H23 @ H24 @ H25 @ H26 @ H27 @ H28
H_3P3 H_3P3 H_3P3 H_3P3 H_1P0N H_1P0N H_3P2 H_3P2 H_2P3 H_2P3 H_2P3 H_2P3 H_2P3 H_3P7 H_3P7 H_2P3 H_2P3 H_2P3 H_2P5 H_4P7X3P7
H_4P7X3P7
H_2P5 H_2P5NH_5P0X4P0
FIDUCIAL MARK~D
CLIP9 CONN@ CLIP10 CONN@ CLIP11 CONN@ CLIP12 CONN@

1
1 1 1 1
P1 P1 P1 P1
EMIST_SUL-12A2M EMIST_SUL-12A2M EMIST_SUL-12A2M EMIST_SUL-12A2M
A @ H29 @ H30 @ H31 @ H34 A

H_3P5X2P5N H_3P7 H_3P7 H_3P5x2P5
1
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT PAD, LED
5 4 3 2 1
5 4 3 2 1
+3.3V_WLAN/+3.3V_LAN source +1.8V_RUN source

2A
@ PJP36
1 2 +3.3V_WLAN
+3.3V_ALW
PAD-OPEN1x2m @ PJP42 0.013A
UZ2 1 2 +1.8V_RUN
1 14 +3.3V_WLAN_UZ2 1 2 +1.8V_PRIM UZ8
1 2 2 VIN1 VOUT1 13 CZ122 0.1U_0201_10V6K PAD-OPEN1x1m
<11,34> SIO_SLP_WLAN# VIN1 VOUT1 1 7
@ RZ71 0_0402_5%
1 2 3 12 1 2 2 VIN VOUT 8 +1.8V_RUN_UZ8 1 2
<34> AUX_EN_WOWL ON1 CT1 VIN VOUT
@ RZ70 0_0402_5% CZ109 470P_0402_50V7K CZ120 0.1U_0201_10V6K
D D
+5V_ALW 4 11 1 2 3 6 1 2
VBIAS GND <17,34,35,42,47,54> RUN_ON @ RZ345 ON CT
0_0402_5% CZ121 470P_0402_50V7K
5 10 1 2
<11,34> SIO_SLP_LAN# ON2 CT2 4
CZ110 470P_0402_50V7K +5V_ALW
6 9 VBIAS 5
7 VIN2 VOUT2 8 +3.3V_LAN_UZ2 1 2 GND 9
VIN2 VOUT2 GND
1
CZ111 0.1U_0201_10V6K @
15 CZ197
1 2 AUX_EN_WOWL GPAD @ PJP37 470P_0402_50V7K AOZ1336_DFN8_2X2
2
RZ38 100K_0402_5% EM5209VF_SON14_2X3 1 2 +3.3V_LAN
PAD-OPEN1x1m
1A
Reserve R/C for Audio power sequence, +5V->+3.3V->+1.8V
+3.3V_ALW_PCH/+3.3V_RUN source
@ PJP38 0.63A
1 2 +3.3V_ALW_PCH
PAD-OPEN1x1m
+3.3V_ALW
UZ3
C 1 14 +3.3V_ALW_PCH_UZ3 1 2 C
2 VIN1 VOUT1 13 CZ112 0.1U_0201_10V6K
VIN1 VOUT1
@ RZ65 1 2 0_0402_5% 3 12 1 2
<34> PCH_ALW_ON ON1 CT1
@ RZ64 1 2 0_0402_5% CZ113 470P_0402_50V7K
<11,17,34,46,47,48,54> SIO_SLP_SUS#
+5V_ALW 4 11
VBIAS GND
RUN_ON 5 10 1 2
ON2 CT2 CZ114 1000P_0402_50V7K
6 9
7 VIN2 VOUT2 8 +3.3V_RUN_UZ3 1 2
VIN2 VOUT2 CZ115 0.1U_0201_10V6K
15
GPAD
EM5209VF_SON14_2X3 @ PJP39
1 2 +3.3V_RUN
PAD-OPEN1x3m
3.435A
+5V_RUN/+3.3V_WWAN source
B B
@
PJP40 2A
1 2 +5V_RUN
+5V_ALW
UZ4 PAD-OPEN1x2m
1 14 +5V_RUN_UZ4 1 2
2 VIN1 VOUT1 13 CZ116 0.1U_0201_10V6K
VIN1 VOUT1
3 12 1 2
<17,34,35,42,47,54> RUN_ON ON1 CT1 CZ117 470P_0402_50V7K
4 11
VBIAS GND
3.3V_WWAN_EN 5 10 1 2
<34> 3.3V_WWAN_EN ON2 CT2 CZ118 470P_0402_50V7K
6 9 +3.3V_WWAN_UZ4
+3.3V_ALW VIN2 VOUT2
7 8 1 2
1 2 3.3V_WWAN_EN VIN2 VOUT2 CZ119 0.1U_0201_10V6K
RZ40 100K_0402_5% 15
GPAD PJP41
@
EM5209VF_SON14_2X3 1 2
+3.3V_WWAN
PAD-OPEN1x3m 2.5A
+3.3V_WWAN_UZ4
A 1 A
RF@ CZ124
2200P_0402_50V7K
2
RF Request Compal Electronics, Inc.
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Power control
5 4 3 2 1
5 4 3 2 1
+COINCELL
COIN RTC Battery
2200P_0402_50V7K
1
PR2
1
PC2
1K_0402_5%
+3.3V_RTC_LDO
+Z4012 2
2
@ JRTC1
1 3
+COINCELL 2 1 G 4
2 G
D D
ACES_50271-0020N-001
2
+RTC_CELL
1
EMC@ PD1 EMC@ PD2
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
EMC@ PL1 PD3
1
FBMJ4516HS720NT_2P
+3.3V_ALW BAS40CW SOT-323 1
3
1 2 PC3
Primary Battery Connector 1U_0603_25V6K
EMC@ PL2
1
FBMJ4516HS720NT_2P 2
PBATT+_C 1 2 +PBATT
@PBATT1 PR1
1
1 2 100K_0402_5%
2
2 3 PRP1
3 PBAT_SMBCLK_C
2200P_0402_50V7K
4 8 1
4 5 PBAT_SMBDAT_C 7 2
5 PBAT_PRES#_C PBAT_CHARGER_SMBDAT <34,52>
6 6 3
PBAT_CHARGER_SMBCLK <34,52> PBAT_PRES# <34,52>
1
6
EMC@ PC1
7 5 4
7 8
8 9 100_0804_8P4R_5%
2
9 10
10 11
GND 12
GND
DEREN_40-42251-01001RHF +3.3V_ALW
@ PR3
2
GND 1 2
0_0402_5%
PR4
2.2K_0402_5%
C EMC@ PL3 PR5 C
1
BLM15AG102SN1D_2P 33_0402_5%
NB_PSID 2 1 1 3 1 2 PS_ID
S
PS_ID <34>
PQ2
2
FDV301N-G_SOT23-3 +5V_ALW
G
2
PR6
100K_0402_1%
3
PD4 EMC@
1
PESD5V0U2BT_SOT23-3 C
2 PQ3 PR7
B MMST3904-7-F_SOT323~D 10K_0402_1%
E
1
3
2
2
PR8
15K_0402_1%
1
PD5
SS5P10-M3/86A TO-277A
+3.3V_VDD_DCIN +DC_IN
2
DC_IN+ Source 1 PU2
3 2
+DC_IN VIN
1U_0603_50V6K
3 1
VOUT
S1 S2 +SDC_IN
PC11
1
GND
PQ9 +DC_IN_SS PQ4 2
1
AON7409_DFN8-5 AON7409_DFN8-5 AP2204RA-3.3TRG1_SOT89-3
EMC@ PL4 1 1 +SDC_IN PC10
FBMJ4516HS720NT_2P 2 2 2.2U_0402_10V6M
2
1
1 2 3 5 5 3
0.022U_0603_50V7K
PR10
PC4
PR11
1
499K +-1% 0402
300K +-5% 0402
1
4
4
1
3
B S B
499K +-1% 0402
0.022U_0603_50V7K
PQ5
PC7 can't over 1000P
2
2
G
2 AO3409 P-CHANNEL SOT-23
2 PR12
2
PC6
1000P_0603_50V7K
2
1
1
100K_0402_5%
+3.3V_VDD_DCIN
10U_0805_25V6K
0.1U_0603_25V7K
@ PJPDC1 D
4.7K_0805_5%
1
1
7 PR15
1
GND
EMC@ PC5
PC7
PC8
6 100K_0402_5%
2
GND
PR14
5 -DCIN_JACK
PR13
5 4
PR16
2
2
1
1
4 3 +DCIN_JACK
49.9K +-1% 0402

@EMC@
3 2 PR17
@
2 1 100K_0402_5%
6
1
1
CVILU_CI0805M1HRC-NH @ PR19
2
2
PQ1A
0_0402_5%
2 1 2
DMN65D8LW-7_SOT323-3
PR18
PC9 @ PR20
+3.3V_VDD_DCIN
1
2 1 49.9K +-1% 0402 D 0_0402_5%

2
1
PQ7
2 1 2
0.1U_0402_10V7K
G
S
3
@ PR21 PU1
5
0_0402_5% MC74VHC1G08DFT2G SC70 5P AND

1
3
<34,52,53> ACAV_IN_NB 1 2 1 D VBUS2_ECOK <35,53>
P
B
PQ6
4 1 2 2 @ PR25
O 1
PQ1B
1 2 2 G 0_0402_5%
A
G
@ PR23 S 5 1 2
AC_DISC# <34,53>
3
@ PR22 0_0402_5%
3
0_0402_5% PR24
4
100K_0402_5%
2
PQ8
@ PR26 DMN65D8LW-7_SOT323-3
0_0402_5%
S
1 2 3 1
<35> DCIN2_EN
G
1 2
A A
1
1
100K_0402_5%
PR28
@ PR29 PR27
0_0402_5% 100K_0402_5%
2
2
2
+3.3V_VDD_DCIN
+3.3V_ALW Compal Electronics, Inc.
Title
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D +DCIN
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1.0
LA-E131P
5 4 3 2 1
A B C D E
@ PR119
0_0402_5%
PGOOD_3V 1 2
@ PR120 ALW_PWRGD_3V_5V <40>

0_0402_5%
1 PGOOD_5V 1 2 1
PR102
499K_0402_1%
+PWR_SRC ENLDO_3V5V 1 2
@ PR100 +PWR_SRC
PJP100 0_0603_5% PC102
1
499K_0402_1%
1 2 3V_VIN BST_3V 1 2 1 2
PR103
PAD-OPEN 1x2m~D 0.1U_0603_25V7K
1
100P_0402_50V8J
100P_0402_50V8J
RF@ PC100
RF@ PC103
PU100
2
10U_0603_25V6M
10U_0805_25V6K
BS
IN
IN
IN
IN
1
1
LX_3V 6
PC105
PC104
20 PL100
LX LX 1.5UH +-20% 9A 7X7X3 MOLDING, A.7
2
2
7 19 LX_3V 1 2
GND LX +3.3V_ALWP
RF@ PR106
8 SY8288BRAC_QFN20_3X3 18 @ PR104
GND GND
4.7_1206_5%
0_0402_5%
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
9 17 1 2
PG LDO +3.3V_ALW2
1
PC106
PC107
PC108
PC109
PC129
PC110
10 16 @ PR105
NC NC 0_0402_5%
3VALWP
OUT
2
EN2
EN1
21 1 2
NC
+3.3V_RTC_LDO
FF
GND
TDC 5.9 A
1 3V_SN 2
PR107
Peak Current 8.4 A
11
12
13
14
15
680P_0603_50V7K
100K_0402_5%
RF@ PC112
2 2
+3.3V_ALW
1 2 3.3V LDO 150mA~300mA OCP Current 10.1A
1
ENLDO_3V5V
PC111 Vout is 3.234V~3.366V
4.7U_0603_6.3V6K
2
PGOOD_3V
PJP102
PC113 PR108 +3.3V_ALWP 1 2 +3.3V_ALW
1000P_0402_50V7K 1K_0402_5% 1 2
3V5V_EN 3V_FB 1 2 1 2 JUMP_43X118
+PWR_SRC PJP103
@ PR111 +5V_ALWP 1 2 +5V_ALW
PJP101 0_0603_5% PC114 1 2
1 2 5V_VIN BST_5V 1 2 1 2 JUMP_43X118
PAD-OPEN 1x2m~D 0.1U_0603_25V7K

2200P_0402_50V7K
1
10U_0805_25V6K
10U_0805_25V6K
@EMC@ PC115
@EMC@ PC116
0.1U_0402_25V6
PU102
1
BS
IN
IN
IN
IN
PC117
PC118
LX_5V 6 20 PL101
2
LX LX 1.5UH +-20% 9A 7X7X3 MOLDING, A.7

7 19 LX_5V 1 2 +5V_ALWP
3 GND
SY8288CRAC_QFN20_3X3 LX 3
@EMC@ PR112
8 18
GND GND
1
4.7_1206_5%
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
PC119
1
9 17 1 2
PC120
PC121
PC122
PC123
PC130
PC124
PG VCC
10 16
2
NC NC 4.7U_0603_6.3V6K
OUT
LDO
5V_SN2
EN2
EN1
21
FF
GND
680P_0603_50V7K
11
12
13
14
15
@EMC@ PC125
PR113
1
100K_0402_5%
1 2 +5V_ALW2
+3.3V_ALW
ENLDO_3V5V
5V LDO 150mA~300mA
2
3V5V_EN
PGOOD_5V
PC126
4.7U_0603_6.3V6K
@ PR114
0_0402_5%
5VALWP
2
1 2
<34> ALWON
TDC 5.5 A
Peak Current 7.9 A
2 1
3V5V_EN OCP Current 9.5 A
1M_0402_1%
4.7U_0402_6.3V6M
1
1
PR116
PC128
@ PD100 PC127 PR117

RB520SM-30T2R_EMD2-2 1000P_0402_50V7K 1K_0402_5%
5V_FB 1 2 1 2
2
2
4 4
EN1 and EN2 dont't floating
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +5V_ALW/3.3V_ALW
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
A B C D E
5 4 3 2 1
D D
+PWR_SRC
PJP202
1 2 +1.2V_DDR_B+
100P_0402_50V8J
RF@
100P_0402_50V8J
RF@
10U_0805_25V6K
10U_0805_25V6K
PU200
PAD-OPEN 1x2m~D RF@ RF@
1
1
PC200
PC201
+3.3V_ALW 10 19 PR202 PC204

IN OT 4.7_1206_5% 680P_0603_50V7K
PC202
PC203
13 18 @ PR203 PC205 1 2 1 2
2
BYP PG
1U_0402_6.3V6K
14 12
0_0603_5%
1 2
0.1U_0603_16V7K
1 2
+1.2V_DDRP
VCC BS
1
PC206
C PL201 C
1
2.2U_0402_6.3V6M
4 11 LX_DDR 1 2
VTTGND LX
PC207
1UH +-20% 11A 7X7X3 MOLDING, A.2
2
330P_0402_50V7K
2 9 16
PGND FB
1
102K_0402_1%
RF@
RF@
1
PC208
PR204
15 8 +1.2V_DDRP PC209
+3.3V_ALW SGND VDDQSNS
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
R1
100P_0402_50V8J
100P_0402_50V8J
7 1 2
2
VLDOIN
1
PC210
PC211
PC212
PC213
PC214
PC216
PC217
2
2
@ ILMT_DDR 17 6
PR205 ILMT VTT +0.6VSP
2
The current limit is 0_0402_5% 1 5
S5 VTTSNS
set to 8A, 12A or 16A
1
100K_0402_1%
2 3
1
when this pin is pull S3 VTTREF
22U_0603_6.3V6M
PR206
R2
1
1U_0402_10V6K
PC218
low, floating or pull ILMT_DDR
PC219
SY8210AQVC_QFN19_4X3
EN_1.2V
high
+1.2V_DDR OCP set 8A
2
2
@
EN_0.6V
PR207
0_0402_5%
1
@ PR208
0_0402_5%
1 2
B <11,17,34,48> SIO_SLP_S4# B
0.1U_0402_10V7K
1M_0402_5%
1
1
PC221
PR209
+1.2V_DDRP +1.2V_MEM +0.6VSP +0.6V_DDR_VTT

2
@
PJP200 PJP201
2
JUMP_43X118 JUMP_43X39
1 2 1 2
@ PR210 1 2 1 2
0_0402_5%
<20> 0.6V_DDR_VTT_ON
1 2
0.1U_0402_10V7K
1M_0402_5%
1
@ PC222
+1.2V_DDR 0.6Volt +/- 5%

PR212
TDC 6.5A TDC 0.007A

2
Mode S3 S5 VOUT VTT Peak Current 9.4A Peak Current 0.01A

Normal H H on on
2
Stadby L H on off OCP Current 11.2A OCP Current 2A (fix)

Shutdown L L off off
Note: S3 - sleep ; S5 - power off
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.2V_MEN/+0.6V_DDR_VTT
5 4 3 2 1
5 4 3 2 1
D D
@ PR312
0_0402_5%
1 2
SIO_SLP_SUS# <11,17,34,42,47,48,54>
EN_+1VALWP
1
1M_0402_1%
PR302 PJP302
+1VALWP 1 2 +1.0V_PRIM
2
1 2
JUMP_43X118
RF@ RF@
PR303 PC302
4.7_1206_5% 680P_0603_50V7K
2 SNB_+1VALWP 1
+PWR_SRC PJP301 PU301
1 2
1 2 +1VALW P_B+ 8 1 PC304 @ PR304

IN EN
10U_0603_25V6M
10U_0603_25V6M
PC301
PC303
0.1U_0603_25V7K 0_0603_5%
100P_0402_50V8J
100P_0402_50V8J
PAD-OPEN 1x2m~D 6 BST_+1VALWP 1 2BST_+1VALWP_C

1 2 PL301
BS
1
1
PC305
PC306
0.68UH +-20% 7.9A 5X5X3 MOLDING, A.3
C 9
GND LX
10 SW_+1VALWP 1 2 +1VALWP C
RF@
RF@
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
330P_0402_50V7K
1
1
4 FB_+1VALWP
FB
21.5K_0402_1%
PC307
PC308
PC309
PC310
PC311
1
ILMT_+1VALWP 3 7
+3.3V_ALW
2
ILMT BYP
PR306
4.7U_0603_6.3V6K
+3.3V_ALW 2 5
4.7U_0603_6.3V6K
PG LDO
1
1K_0402_5%
PC312
1
PC313
PR308
SYX196DQNC_QFN10_3X3
2
1
2
2
@ PR307
2
0_0402_5%
2
ILMT_+1VALWP
1
1
PR311
31.6K_0402_1%
@ PR310
0_0402_5%
2
+1.0V_PRIM
2
TDC 4.9A
Peak Current 7.1 A
OCP Current 8.6A
B TYP MAX B
Choke DCR 11.0mohm , 12.0mohm
The current limit is set to 6A, 9A or 12A when this pin

is pull low, floating or pull high
A A
Title
+1VALWP
1.0
LA-E131P
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
LPM LOGIC VID1 LOGIC VID0 LOGIC OUTPUT VOLTAGE
1
@ PR425
0_0402_5% PR404 @ 0 X X 0(LPM)
<11,17,36,47> SIO_SLP_S0# 1 2 0_0402_5%
PJP401
TPS62134C 1 0 0 0.80
2
JUMP_43X79 1 0 1 0.95
@ PR402 1 2
0_0402_5% +1VS_VCCIOP 1 2 +1.0VS_VCCIO 1 1 0 1.00
1 2
<17,34,35,42,54> RUN_ON
1 1 1 1.05
EN_1VS_VCCIO
0.1U_0402_25V6
1
1
@ PC402
PR403
D 1M_0402_1% D
2
2
13
14
15
16
17
PU401
Vin=3~17V
+1.0VS_VCCIO
TP
LPM
EN
PGND
PGND
PJP403
TDC 1.9 A
+5V_ALW 1 2 VIN_1VS_VCCIO 12
PVIN VOS
1
+1VS_VCCIOP Peak Current 2.7 A
OCP Current 3.3 A
10U_0603_10V6M
10U_0603_10V6M
PL402
PAD-OPEN1x1m 1UH_1277AS-H-1R0N-P2_3.3A_30%
TYP MAX
1
+3.3V_ALW LX_1VS_VCCIO
+1VS_VCCIOP
PC403
PC404
11 2 1 2
PVIN SW
Choke DCR 48.0mohm
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2
2
TPS62134CRGT_QFN16_3X3
1
PC406
PC407
PC422
10 3
AVIN SW
2
2200P_0402_50V7K
SNUB_1VS_VCCIO
0.1U_0402_25V6
1
1
VID0_VCCIO 9 4
PC408
@EMC@ PC409
VID0 PG PR405
1
AGND
4.7_0603_5%
VID1
FBS
@ PR413 PR414 @EMC@
SS
2
10K_0402_1% 10K_0402_1%
2
5
VID0_VCCIO
1
PC401 +1VS_VCCIOP
SS_1VS_VCCIO
VID1_VCCIO
VID1_VCCIO
0_0402_5%
470P_0402_50V7K
1
1
PR421
470P_0402_50V7K
PR415 @ PR416
10K_0402_1% 10K_0402_1% @ PR422
2
1
1
0_0402_5%
0_0402_5%
C C
2
@ PR427
PC410
1 2
VCCIO_SENSE <17>
2
@ PR412
0_0402_5%
2
1 2
VSSIO_SENSE <17>
"R" for SILERGY

+3.3V_ALW
1
@ PR426 @ PR410
0_0402_5% 0_0402_5%
1 2
<11,17,36,47> SIO_SLP_S0#
2
PJP402
@ PR406 JUMP_43X79
EN_1.0V_PRIM_COREP
0_0402_5% 1 2
<11,17,34,42,46,48,54> SIO_SLP_SUS# 1 2 +1.0V_PRIM_COREP 1 2 +1.0V_PRIM_CORE
0.1U_0402_25V6
1
1
@ PC411
PR407
1M_0402_1%
2
2
13
14
15
16
17
PU402
B Vin=3~17V B
TP
LPM
EN
PGND
PGND
PJP404
+5V_ALW 1 2 VIN_1V_PRIM 12
PVIN VOS
1
+1.0V_PRIM_COREP
+3.3V_ALW
10U_0603_10V6M
10U_0603_10V6M
PL404
1
LX_1V_PRIM
+1.0V_PRIM_COREP
PC412
PC413
11 2 1 2
PVIN SW
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2
TPS62134DRGT_QFN16_3X3
1
PC424
PC415
PC416
10 3
AVIN SW
Rup
LPM LOGIC VID1 LOGIC VID0 LOGIC OUTPUT VOLTAGE
2
2200P_0402_50V7K
0.1U_0402_25V6
1
9 4
PC417
0 X X 0.7(LPM)
@EMC@ PC418
VID0 PG
1SNUB_1V_PRIM
PR409
PR417 PR418 TPS62134D 1 0 0 0.85
2
AGND
VID0_PRIM_CORE
10K_0402_1% 10K_0402_1% 4.7_0603_5%

VID1
FBS
@EMC@
1 0 1 0.90
SS
2
VID0_PRIM_CORE
1 1 0 0.95
8
VID1_PRIM_CORE
PC419 1 1 1 1.00
1
VID1_PRIM_CORE
470P_0402_50V7K
2
@ PR408
@ PR419 @ PR420 0_0402_5%
SS_1V_PRIM
10K_0402_1% 10K_0402_1% 1 2
<18> CORE_VID0
2
@ PR411 @ PR423
+1.0V_PRIM_CORE
0_0402_5% 0_0402_5% TDC 1.8 A
1 2 1 2
<18> CORE_VID1 Peak Current 2.6 A
OCP Current 3.1 A
470P_0402_50V7K
1M_0402_1%
1
1
PR428
A A
TYP MAX
PC420
@ PR424
100K_0402_1%
Choke DCR 48.0mohm
2
@
2
"R" for SILERGY
Title
+1VS_VCCIOP/+1.0V_PRIM_COREP
1.0
LA-E131P
5 4 3 2 1
5 4 3 2 1
PC502
22U_0603_6.3V6M PJP502
1 2 1 2
+1.8VALWP +1.8V_PRIM
PJP501 PAD-OPEN1x1m
1 2 VIN_1.8VALW
+3.3V_ALW Imax= 2A, Ipeak= 3A
PAD-OPEN1x1m
FB=0.6V
D D
PR517
PU501
100K_0402_5% PL501
2 1 1UH_1277AS-H-1R0N-P2_3.3A_30%
+3.3V_ALW 4 3 LX_1.8VALW 1 2
IN LX +1.8VALWP
1
5 2
68P_0402_50V8J
<34> 1.8V_PRIM_PWRGD PG GND
1SNUB_1.8VALW
22U_0603_6.3V6M
22U_0603_6.3V6M
@EMC@ PR502
1
PC503
6 1
1
FB EN
PC501
PC504
4.7_0603_5%
PR501
2
@ PR504 RT8097ALGE_SOT23-6
2
0_0402_5% 20K_0402_1%
1 2 EN_1.8VALW
<11,17,34,42,46,47,54> SIO_SLP_SUS# Rup
2
@EMC@ PC506
1
680P_0402_50V7K
2
1
PR505 @ PC505
1M_0402_1% 0.1U_0402_16V7K
2
FB_1.8VALW
1
PR506
Rdown +1.8V_PRIM
10K_0402_1% TDC 0.7 A
Note: Peak Current 1.0 A
2
When design Vin=5V, please stuff snubber OCP Current 1.2 A
to prevent Vin damage
Vout=0.6V* (1+Rup/Rdown)
C C
B B
+2.5V_MEN
TDC 0.3A by power budget
AP7361 U-DFN3030-8 Pd limit=1.7W
Peak loading=1.1A.
Pd=(3.3-2.5)*1.1=0.88W < 1.7W
OCP is 1.1~1.5A
PU503
PJP505
AP7361C-FGE-7_U-DFN3030-8_3X3 PJP506
1 2 +2.5V_VIN 9
+3.3V_ALW GND 1 2.5VSP 1 2
OUT
+2.5V_MEM
1
8
PAD-OPEN1x1m PC514 IN 2 PAD-OPEN1x1m
1
4.7U_0603_6.3V6K 7 NC PR515
2
NC 3 21.5K_0402_1% PC515
@ PR513 6 ADJ/NC 0.01UF_0402_25V7K
2
NC
1
0_0402_5% 4
EN_2.5V GND PC516
1 2 5
<11,17,34,45> SIO_SLP_S4# EN 22U_0603_6.3V6M
2
1
@
PR514 PC513
PR516
2
1M_0402_1% .1U_0402_16V7K 10.2K_0402_1%

A A
2
Title
+1.8VALWP/+1.5VSP
1.0
LA-E131P
5 4 3 2 1
5 4 3 2 1
+1.0V_VCCST VCC_SA (U23E) VCC_SA (U22)

TDC 5.0A TDC 4.0A
Peak Current 5.1A Peak Current 4.5A
@ PR602
0_0402_5%
OCP current 6.1A OCP current 5.4A
0.1U_0402_25V6
Choke DCR 13 m ohm Choke DCR 13 m ohm
1
45.3_0402_1%
100_0402_1%
75_0402_1%
1 2
PC602
+5V_ALW
PR605
PR601
PR604
@ PR603
Local sense put on HW site
2
0_0402_5% PJP603
@ 1 2 CPU_B+
0.22U_0603_25V7K
2
2
1 2
1U_0603_10V6K
D PR618 1 2 49.9_0402_1% VCCSA_B+ CPU_B+ D
<15> VIDSCLK
1
PC603
PC604
PAD-OPEN1x1m
<15> VIDALERT_N @ PR625 1 2 0_0402_5%
2
<15> VIDSOUT PR626 1 2 10_0402_1%
VCCSA_B+
VIDSCLK_B
PR678
VIDALERT_N_B
<12,34,52> H_PROCHOT#
100_0402_1%
VIDSOUT_B
1 2 1 2
PC605 PR612 1 2
47P_0402_50V8J~D 1.91K_0402_1%
470K_0402_5%_B25/50 4700K 1 2 @ PR608
PR610 +3.3V_RUN 78.7K_0402_1%
10U_0805_25V6K
10U_0805_25V6K
PH601
10K_0402_1% @ PR614 1 2
1 2 1 2 PR613 0_0402_5%
1
1 2
PC608
PC612
90.9K +-1% 0402 <11> PCH_PWROK PR611
1 2 1 2 48.7K_0402_1%
PR631 PC613 @ PR616
2
27.4K_0402_1% 330P_0402_50V7K 0_0402_5%
1 2 1 2
<35,54> IMVP_VR_ON
PC614 PR617
2200P_0402_50V7K 4.3K_0402_1%
1 2 1 2
40
39
38
37
36
35
34
33
32
31
PU602 PR619
@ PC616 2.2_0603_5%
VR_ENABLE
VR_READY
SCLK
SDA
VCC
VIN
VR_HOT#
ALERT#
PROG1
PROG2
33P_0402_50V8J @ PR620 1 2
1 2 @ PC617 @ PR621 0_0402_5%
1200P_0402_50V7K 316_0402_1% 1 2 1 30 PWM_VSA PU614 AON7934_DFN3X3A-8-10
<34,52> I_SYS PSYS PWM_C
1
1 2 1 2 2 29 FCCM_VSA ISL95808HRZ-TS2378_DFN8_2X2 PQ501
<16> VCC_GT_SENSE IMON_B FCCM_C
@ PR622 3 28
D1
D1
D1
G1
@ PC618 1.91K_0402_1% 4 NTC_B ISUMN_C 27 1 8 PL614
1 2 1 2 5 COMP_B ISUMP_C 26 PC611 UGATE PHASE 0.47UH_MMD05CZR47M_12A_20%
0.082U_0402_16V7K
6 FB_B RTN_C 25 FB_VSA 1 2 2 7 10 9 SA_SW 4 1

PC620
0.22U_0603_16V7K
RTN_B FB_C BOOT FCCM D1 D2/S1
+VCC_SA
1
COMP_VSA
PR627 @EMC@
330P_0402_50V7K 7 24
PC621 PR623 8 ISUMP_B COMP_C 23 IMON_VSA PWM_SA 3 6 3 2
C
PC619 680P_0402_50V7K 2K_0402_1% 9 ISUMN_B IMON_C 22 PWM VCC C
4.7_1206_5%
G2
S2
S2
S2
2
ISEN1_B PWM_A PWM_IA <50>
1
1 2 @ 1 2 1 2 10 21 4 5
0_0402_5%
ISEN2_B FCCM_A FCCM_IA <50> GND LGATE
@ PR606
TP
ISUMN_A
ISUMP_A
PWM1_B
PWM2_B
COMP_A
8
FCCM_B
IMON_A
0.01UF_0402_25V7K 41
NTC_A
RTN_A
AGND
FB_A
<16> VSS_GT_SENSE
0_0402_5%
2
2
1
@ PR679
PR624
PWM_VSA
+5V_ALW
SA_SNUB
11
12
13
14
15
16
17
18
19
20
S IC ISL95857AHRTZ-T TQFN 40P PWM 3.65K_0603_1%
1
1U_0402_10V6K
<50> ISUMP_GT
2
IMON_IA
FB_IA
<50> FCCM_GT
NTC_IA
ISUMP_VSA 2
FCCM_VSA
COMP_IA
PC685
4.42K_0402_1%
<50> PWM1_GT
ISUMN_VSA
2
<50> PWM2_GT
PR628
@ PR658 PC625
680P_0603_50V7K
20M_0402_5% 330P_0402_50V7K
1
1 2
@EMC@ PC622
0.033U_0402_16V7K
0.047U_0402_25V7K
@ @ PR629
1
100K +-1% 0402
2
1
1
1 2
PC624
PC626
2.49K_0402_1%
33P_0402_50V8J
PH603
PR630
10K_0402_5%_B25/50 4250K
1
PC628
PR632 PC627 470K_0402_5%_B25/50 4700K
11K_0402_1%
2200P_0402_50V7K
2
2
1
2200P_0402_50V7K
PR633
@ @ 1K_0402_1% 1 2 1 2 PR636
1 2 1 2 ISUMP_VSA
PH602
649_0402_1%
4700P_0402_25V7K
2
2
PR647 PR635 1 2
383_0402_1%
1
@ PR638 27.4K_0402_1% 10K_0402_1%
2.61K_0402_1%
2
2
1 2
PC630
PR640
PC631
20M_0402_5%
374_0402_1% PC632
2
@ PR654
1 2 PC629 PR639 1000P_0402_50V7K
PR642
<50> ISUMN_GT 2200P_0402_50V7K 3.09K_0402_1% 1 2 1 2
2
@U23E PC635 1 2 1 2 @
2
0.022U_0402_16V7K PR641
3300P_0402_25V7K
0.033U_0402_16V7K
1
2
1 2 ISEN1_GT PC636 1K_0402_1%
1K_0402_1%
11K_0402_1%
33P_0402_50V8J
PR643
1
1
1 2
PR644
PC633
PC637
@U23E PC638
1
B 0.022U_0402_16V7K @ PC639 PR645 PR646 PC640 B
1
1 2 ISEN2_GT 2200P_0402_50V7K 316_0402_1% 1 2 1 2 PH604
@U22PR634 1 2 1 2 10K_0402_5%_B25/50 4250K
2
0_0402_5% 316_0402_1% 2200P_0402_50V7K
1 2
330P_0402_50V7K
2
1 2 PR649
.1U_0402_16V7K
+5V_ALW
1
1
1 2 @ PR648 1 2
133K_0402_1%
1
ISUMN_VSA
PC641
1.5K_0402_1% PC642
<50> ISEN1_GT
PR651
PC643
@U22PR615 0.033U_0402_16V7K 1.62K_0402_1% PC644
680P_0402_50V7K 2K_0402_1%
680P_0402_50V7K 2K_0402_1%
2
1
1 2
PR652
0_0402_5% .1U_0402_16V7K
<50> ISEN2_GT
2
1 2
.1U_0402_16V7K
2
1
@
PR650
PC645 @
2
1 2
PC646
0.047U_0402_25V7K
2
1 2 VSA_SEN- <17>
PC647
PC601
2
1
@ PC649
0.01UF_0402_25V7K
0.082U_0402_16V7K
1 2
PR656
11K_0402_1%
<15> VCCSENSE
2
1 2
PC650
@ PC652
PR657
1
@ PC651 @ 330P_0402_50V7K
PH605
1 2 4.42K_0402_1% 1 2
1 2 1 2
0.082U_0402_16V7K
330P_0402_50V7K
PC653
1
@ PR653 10K_0402_5%_B25/50 4250K VSA_SEN+ <17>

2 1 ISUMN_IA <50>
2
PC654 @ 20M_0402_5%
A A
1 2
ISUMP_IA <50>
0.01UF_0402_25V7K
<15> VSSSENSE
Local sense put on HW site DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_VCORE_ISL95857
5 4 3 2 1
5 4 3 2 1
U23E
VCC_core (U22) VCC_core (U23E) PR628 @U23E PR651 @U23E PC626 @U23E PR621 @U23E PR608 @U23E PR648 @U23E PR622 @U23E
TDC 21A TDC 22A
Peak Current 32A Peak Current 29A
OCP current 38.4A OCP current 34.8A
Choke DCR 0.9 +-7%m ohm Choke DCR 0.9 +-7%m ohm 4.99K +-1% 0402 78.7K +-1% 0402 0.022U_0402_16V7K 1K +-1% 0402 100K +-1% 0402 1.5K +-1% 0402 2.55K_0402_1%
PR640 @U23E PR638 @U23E PR629 @U23E PC624 @U23E PC616 @U23E PC617 @U23E PC639 @U23E
D D
383 +-1% 0402 470 +-1% 0402 86.6K +-1% 0402 0.1U 25V 0402 68P 50V J 0402 220P 50V 0402 2200P 50V 0402
+PWR_SRC
PJP601
1 2
CPU_B+ PAD-OPEN 4x4m
U22
@EMC@ PL602
1 2 PR628 @U22 PR651 @U22 PC626 @U22 PR621 @U22 PR608 @U22 PR648 @U22 PR622 @U22
9A Z80 10M 1812_2P

100P_0402_50V8J
100P_0402_50V8J
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
100U_D_20VM_R55M
RF@
RF@
1
1
+
PC682
PC657
PC658
PC606
PC656
4.42K +-1% 0402 133K +-1% 0402 0.047U_0402_25V7K 316 +-1% 0402 78.7K +-1% 0402 1.5K +-1% 0402 1.91K +-1% 0402
PC659
PC660
2
@ 2 PR640 @U22 PR638 @U22 PR629 @U22 PC624 @U22 PC616 @U22 PC617 @U22 PC639 @U22
383 +-1% 0402 374 +-1% 0402 100K +-1% 0402 .033U 16V 0402 33P 50V J 0402 1200P 50V 0402 1500P 50V K 0402
PL610
PU610 0.15UH_MMD06CZER15MG_37A_20%
9
<49> PWM_IA
PC655 8 PGND2 GPU_B+
1 2 7 PWM 4 CORE_SW 4 1
0.22U_0603_16V7K
BOOT VSW
PGND1
3 +VCC_CORE
1 2 6 2 3 2
C BOOT_R VDD VCC_GT (U22) C
RF@
PR660 5 1
+5V_ALW
VIN SKIP#
1
2.2_0603_5% @ PJP602 TDC 18A
4.7_1206_5%
1
1 2
1U_0402_10V6K
10U_0805_25V6K
10U_0805_25V6K
PR661 GPU_B+ CPU_B+ Peak Current 31A
1
PC661
CSD97396Q4M_SON8_3P5X4P5
10P_0402_50V8J
3.65K_0603_1%
5.11K_0402_1%
OCP current 37.2A

PR663
PAD-OPEN 1x2m~D
1
1
PR662
PC664
PC665
PC686
PC680
Choke DCR 0.9 +-7%m ohm
2
1000P_0402_50V7K
2
2
1
0_0402_5%
CORE_SNUB
2
2
<49>
<49>
ISUMP_IA
@U23E
@U23E
ISUMN_IA
@ PR659
2
VCC_GT (U23E)
TDC 38A
2
Peak Current 57A

680P_0603_50V7K
OCP current 68.4A

1
RF@ PC662
Choke DCR 0.9 +-7%m ohm

<49>
FCCM_IA
@U23E PL613
@U23E PU613 0.15UH_MMD06CZER15MG_37A_20%
9
@U23E PC663 8 PGND2
<49> PWM2_GT PWM GT_SW2
1 2 7 4 4 1
BOOT VSW +VCC_GT
PR669 @EMC@
0.22U_0603_16V7K 3
1 2 6 PGND1 2 3 2
PR665 5 BOOT_R VDD 1
4.7_1206_5%
+5V_ALW
GT2P
VIN SKIP#
1
2.2_0603_5% GT2N
1U_0402_10V6K
1
1
@U23E PC669
GPU_B+ @U23E
CSD97396Q4M_SON8_3P5X4P5 @U23E PR667 @U23E PR668 @U23E PR666
10P_0402_50V8J
1
5.11K_0402_1%
3.65K_0603_1% 100K_0603_1% 10_0402_1%
2
1
1 2 1 2
@U23E PR681
PC687
@U23E PC681
2
1
1000P_0402_50V7K
2
<49> ISEN2_GT
2
@U23E
@ PR664
GT_SNUB2
2
0_0402_5% PR670 @
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
B B
GT1N 1 2
2
100K_0402_1%
1
1
PC683
PC684
PC672
PC673
2
<49,50>
<49,50>
ISUMP_GT
ISUMN_GT
<49,50>
FCCM_GT
680P_0603_50V7K
@ @
1
@EMC@ PC670
2
PL612
PU612 0.15UH_MMD06CZER15MG_37A_20%
9
PC671 8 PGND2
<49> PWM1_GT PWM GT_SW1
1 2 7 4 4 1
BOOT VSW
+VCC_GT
PR676 @EMC@
0.22U_0603_16V7K 3
1 2 6 PGND1 2 3 2
PR672 5 BOOT_R VDD 1
4.7_1206_5%
GT1P
VIN SKIP#
1
2.2_0603_5% GT1N
+5V_ALW
1
1U_0402_10V6K
CSD97396Q4M_SON8_3P5X4P5 PR674 @U23E PR675 PR673

10P_0402_50V8J
1
5.11K_0402_1%
PC677
3.65K_0603_1% 100K_0603_1% 10_0402_1%

1
PC688
PR680
PC679 1 2 1 2
2
1
0_0402_5%
1000P_0402_50V7K
2
2
@ PR671
<49> ISEN1_GT
2
GT_SNUB1
2
@ PR677
GT2N 2 1
2
100K_0402_1%
A A
<49,50>
FCCM_GT
680P_0603_50V7K
<49,50>
<49,50>
ISUMP_GT
ISUMN_GT
1
@EMC@ PC678
2
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_VCORE
5 4 3 2 1
4
3
2
1
+VCC_CORE
+VCC_SA
A
A
2 1 2 1 2 1
2
1
+
2 1 2 1
330U_D3_2VM_R6M
PC1127 PC1099 PC1083 PC1076
PC1153 PC1057 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 22U_0603_6.3V6M 2 1 2 1 2 1 2 1
2
1
+
2 1 2 1
330U_D3_2VM_R6M
PC1062 PC1095 PC1030 PC1081 PC1078
PC1147 PC1058 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 22U_0603_6.3V6M 2 1 2 1 2 1 2 1 2 1
2 1 2 1
@ PC1170 PC1094 PC1031 PC1080 PC1077
PC1148 PC1059 22U_0603_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
22U_0603_6.3V6M
+330u_D2*2 pcs
1U_0201_6.3V6M 2 1 2 1 2 1 2 1 2 1
2 1 2 1
@ PC1171 PC1096 PC1032 PC1082 PC1079
1U_0201_6.3V6M 22U_0603_6.3V6M 2 1 2 1 2 1 2 1 2 1
2 1 2 1
@ PC1172 PC1090 PC1033 PC1067 PC1001
VCC_CORE Place on CPU

1U_0201_6.3V6M 22U_0603_6.3V6M 2 1 2 1 2 1 2 1 2 1
2 1 2 1
@ PC1173 PC1093 PC1034 PC1072 PC1002
1U_0201_6.3V6M 22U_0603_6.3V6M 2 1 2 1 2 1 2 1 2 1
2 1 2 1
@ PC1174 PC1091 PC1035 PC1069 PC1003
1U_0201_6.3V6M 22U_0603_6.3V6M 2 1 2 1 2 1 2 1
2 1
PC1097 PC1036 PC1074 PC1004
22U_0603 * 33 pcs +1U_0201*35 pcs
PC1142 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

22U_0603_6.3V6M 2 1 2 1 2 1 2 1
B
B
2 1
PC1092 PC1037 PC1070 PC1005
PC1143 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1 2 1 2 1
2 1
PC1098 PC1038 PC1061 PC1006
PC1144 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1 2 1 2 1
2 1
PC1050 PC1039 PC1071 PC1007
PC1145 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1 2 1 2 1
2 1
PC1051 PC1084 PC1066 PC1008
PC1146 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1 2 1 2 1
PC1052 PC1086 PC1073 PC1009

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
PC1053 PC1085 PC1068 PC1010

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
PC1054 PC1088 PC1075 PC1011

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
PC1126 PC1087 PC1064 PC1012

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
PC1164 PC1089 PC1065 PC1013
C
C
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

2 1
PC1125
VCC_SA Place on CPU

1U_0201_6.3V6M
+VCC_GT
22U_0603 * 12 pcs + 1U_0201*7 pcs
2 1
2
1
+
@U23E PC1188 PC1063

22U_0603_6.3V6M 330U_D2_2.5VM_R9M
2 1 2 1 2 1 2 1
2
1
+
@U23E PC1189 PC1165 PC1040 PC1133 PC1014

22U_0603_6.3V6M 330U_D2_2.5VM_R9M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
2
1
+
@U23E PC1190 @U23E PC1128 PC1041 PC1137 PC1015

+330u_D2*2 pcs
22U_0603_6.3V6M 330U_D3_2VM_R6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

2 1 2 1 2 1 2 1 2 1
@U23E PC1177 @ PC1181 PC1042 PC1129 PC1016

22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
D
D
2 1 2 1 2 1 2 1 2 1
@U23E PC1192 @ PC1180 PC1043 PC1132 PC1017

2 1 2 1 2 1 2 1 2 1
VCC_GT Place on CPU (U22)
@U23E PC1193 @ PC1191 PC1044 PC1136 PC1018

2 1 2 1 2 1 2 1 2 1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
@U23E PC1194 @ PC1179 PC1045 PC1134 PC1019

2 1 2 1 2 1 2 1 2 1
22U_0603 * 26 pcs +1U_0201*12 pcs
@U23E PC1195 @ PC1176 PC1046 PC1135 PC1020

2 1 2 1 2 1 2 1 2 1
Title
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Date:
@U23E PC1196 @ PC1178 PC1047 PC1138 PC1021

2 1 2 1 2 1 2 1 2 1
@U23E PC1197 @ PC1175 PC1048 PC1027 PC1022

2 1 2 1 2 1 2 1 2 1
@U23E PC1198 @U23E PC1182 PC1049 PC1028 PC1023

Document Number

2 1 2 1 2 1 2 1 2 1
@U23E PC1199 @U23E PC1183 PC1055 PC1130 PC1024

Wednesday, November 09, 2016
2 1 2 1 2 1 2 1 2 1
+330u_D2*3 pcs
@U23E PC1100 @U23E PC1184 PC1056 PC1029 PC1025

E
E
LA-E131P

2 1 2 1 2 1 2 1
Sheet
@U23E PC1101 @U23E PC1185 PC1131 PC1026

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
51
@U23E PC1102 @U23E PC1186

VCC_GT Place on CPU (U23E)
22U_0603_6.3V6M 22U_0603_6.3V6M
of
2 1 2 1
@U23E PC1103 @U23E PC1187

22U_0603_6.3V6M 22U_0603_6.3V6M
PROCESSOR DECOUPLING
59
22U_0603 * 48 pcs +1U_0201*12 pcs
Rev
1.0
4
3
2
1
A B C D
+PWR_SRC_AC
+SDC_IN +CHARGER_SRC
PR901
0.01_1206_1% EMC@ PL901
1UH +-20% 6.6A 5X5X3 MOLDING, A.3
1 4 2 1
2 3 +PWR_SRC
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
2200P_0402_50V7K
0.1U_0402_25V6
15U_B2_25VM_R100M
15U_B2_25VM_R100M
15U_B2_25VM_R100M
1 1 1
@EMC@ PC902
@EMC@ PC903
1
1
+ + +
PC911
PC904
PC905
PC906
PC909
PC910
PC951
@ PJP901
1 2
2
1 PAD-OPEN 4x4m 2 2 2 1
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
1
1
PC913
PC914
PC915
PC916
PC917
PC918
PC919
PC920
@ @ @
2
1
1
PR909 PR910
3.3_0402_1% 3.3_0402_1%
2
CSIP_ISL88738
CSIN_ISL88738
PC925
4.7U_0402_6.3V6M
2200P_0402_50V7K
1 2
0.1U_0402_25V6
1U_0402_25V6K
1U_0402_25V6K
1
@EMC@ PC928
@EMC@ PC929
1
1
PC926
PC927
2
2
2
2
PC930
+SDC_IN @ PR943
PD901 0_0603_5% 0.22U_0603_25V7K
1
2 1 1 2 ADP_ISL88738
+PWR_SRC
1
SDMK0340L-7-F_SOD323-2~D
1
PD903 @ PR914
PR944 0_0603_5%
2 1
+VBUS_DC_SS 442K_0402_1%
2
2 2
2
RB520SM-30T2R_EMD2-2
CSIN_ISL88738
ACIN_ISL88738
CSIP_ISL88738
BOOT1_ISL88738
UG1_ISL88738
LX1_ISL88738
LG1_ISL88738
PD904
1
2 1
+DC_IN_SS
1
PC1286 PR945 PR915
UG1_ISL88738
UG2_ISL88738
SDMK0340L-7-F_SOD323-2~D 0.1U_0402_25V6 100K_0402_5% 4.7_0402_5%
2
1 2 VDD_ISL88738
2
PR916
2
PU901
16
15
14
13
12
11
10
33
1_0805_5%~D
9
ISL88738HRTZ-T_TQFN32_4X4
PC931 1U_0603_25V6 PQ905 PQ904
ADP
CSIP
ASGATE
CSIN
BOOT1
UGATE1
PHASE1
LGATE1
PAD
1
PC932 AON6992_DFN5X6D-8-7 AON6992_DFN5X6D-8-7

1 2 @ PR960 DCIN_ISL88738 1U_0402_6.3V6K +VCHGR PQ906
2
0_0402_5% 17 8 VDDP_ISL88738 2 1 PR917 AON7409_DFN8-5
DCIN VDDP
1 2 PL902 0.005_1206_1% 1 +PBATT
D1
G1
G1
D1
2 1 VDD_ISL88738 18 7 LG2_ISL88738 .82UH +-20% MMD-06CZ-R82M-V1L 13A 2
VDD LGATE2
2
1 4 3 5
PC933 PR918 @ PR919 ACIN_ISL88738 19 6 LX2_ISL88738 7 1 2 7
1U_0402_6.3V6K 0_0402_5% ACIN PHASE2 D2/S1 D2/S1 2 3
100K_0402_1%
1 2 OTGEN/CMIN 20 5 UG2_ISL88738
4
OTGEN/CMIN UGATE2
LX1_ISL88738
LX2_ISL88738
@ PR920 0_0402_5% PC934 PR921
G2
G2
S2
S2
S2
S2
S2
S2
1
ACAV_IN1 1 2 21 4 BOOT2_ISL88738 2 1 2 1
10U_0805_25V6K
10U_0805_25V6K
<34,43> PBAT_CHARGER_SMBDAT SDA BOOT2
1
@ PR922 0_0402_5%
4.7_1206_5%
4.7_1206_5%
3
3
1
1 2 22 3
@EMC@ PR923
@EMC@ PR924
PQ909 0.22U_0603_25V7K 2.2_0603_5%
4700P_0402_25V7K
<34,43> PBAT_CHARGER_SMBCLK SCL VSYS
1
1
D
PC935
PC936
DMN65D8LW-7_SOT323-3 PR925 @ PR926 0_0402_5%
OTGPG/CMOUT
2
LG1_ISL88738
LG2_ISL88738
2 1 2 23 2 CSOP_ISL88738
PC937
154K_0402_1% <12,34,49> H_PROCHOT# PROCHOT# CSOP
AMON/BMON
<34> AC_DIS G
1SNUB_CHG1 2
1SNUB_CHG2 2
2
1
PROCHOT#_ISL88738 CSON_ISL88738
BATGONE
S <53> PROCHOT#_ISL88738
24 1
3
1
ACOK CSON @ PR929
BGATE_ISL88738
BGATE
CMOP
+PWR_SRC
PROG
ACOK_ISL88738
PSYS
1 2
VBAT
0_0402_5%
1 2
680P_0603_50V7K
680P_0603_50V7K
PR927 @ PR928
2
1M_0402_1% 0_0402_5% @ PR930 PC938

25
26
27
105K_0402_1% 28
29
30
31
BGATE_ISL88738 32
@EMC@ PC940
@EMC@ PC941
100K_0402_1% 10P_0402_50V8J
PR931 1 2 1 2 1 2
PR932 1
<34,43> PBAT_PRES# 100K_0402_1%
2
1 2
0_0402_5%
3 3
@ PC939 0.1U_0402_25V6
VBAT1_ISL88738
PR933
100K_0402_1%
1 2
+3.3V_ALW
2
@ PR951
0_0402_5%
1 2
<53> CMOUT
@ PR949
COMP_ISL88738 PC942
2
1U_0402_25V6K
1 2
1
0_0402_5%
560P_0402_50V7K
@ PR934
PR937
1
2.2_0402_1%
12.7K_0402_1%
0.1U_0402_25V6
1
1 2
@ PC943
@ PR936
PR948
0_0402_5%
1
PC947
2
2
2
PC945 PR938
@ PR947
0_0402_5%
@ PR935
0_0402_5%
0.012U_0402_16V7K
2
2
4.7U_0402_6.3V6M 2.2_0402_1%
1
1
1 2
PC944
PC946 LM393_P
2
1U_0402_25V6K @ PR950
1 2 0_0402_5%
I_SYS <34,49> 1 2
I_BATT
I_ADP
PD905
@ PR939 BAT54CW_SOT323-3 PC949
0_0402_5% 0.1U_0402_10V7K
<26,53> AC1_DISC#
1 2 3 1 2 PU903
MC74VHC1G08DFT2G SC70 5P AND
<34> I_BATT I_ADP <34> @ PR941 1
5
PR940 +PBATT 0_0402_5%
1 2 2 1
@ PR946
100_0402_1% @ PR942 0_0402_5%
P
<34,43,53> ACAV_IN_NB B <34,35> ACAV_IN
2 1 0_0402_5% 4 1 2
ACAV_IN1 1 2 2 O
Close to EC ADP_I pin A
1
2
4
PR953 4
3
@ PC950 100K_0402_1%
0.1U_0402_25V6
1
Add PR953 for IT8010 voltage leakage issue
2
Title
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D PWR CHGRGER ISL88738
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1.0
LA-E131P
A B C D
5 4 3 2 1
PD1202
SS5P10-M3/86A TO-277A
2
DCIN_AC_Detector 1
3
@ PC1201
0.01U_0402_25V7K~D
1 2
PD1801
S4 S5
+3.3V_VDD_DCIN
+DC_IN +3.3V_VDD_DCIN 3 +3.3V_VDD_DCIN PQ1213 +VBUS_DC_SS PQ1202
AON7409_DFN8-5 AON7409_DFN8-5
1 LM393_P 1 1
+AC_IN 2 2
D 2 3 5 5 3
+SDC_IN D
AO3409 P-CHANNEL SOT-23

+3.3V_VDD_PIC
1
1500P_0402_50V7K
2200P 50V K X7R 0603
BAT54CW_SOT323-3 PR1251 PR1202
499K +-1% 0402

1
PR1203 300K +-5% 0402 300K +-5% 0402
1
PQ1215
PC1202
PR1205
1.8M_0402_1%
499K +-1% 0402

1
3
S S
PC1203
1 2
2PR1207
2
2
G G
PR1206 +3.3V_VDD_PIC 2 2 PQ1203
2
1K_0402_1% AO3409 P-CHANNEL SOT-23
2
1
LM393_P
240K_0402_1%
D D
1
1
1
PR1252 +3.3V_VDD_PIC
102K_0402_1%
2
PR1201
PR1253 100K_0402_5% PR1209

PR1208
100K_0402_5% 100K_0402_5%
6 2
PU1201A
1
49.9K +-1% 0402
2
2
8
LM393DGKR_VSSOP8
PR1213
PR1214
1
3
49.9K +-1% 0402

100K_0402_5%
+ P
3
ACAV_IN_NB
PQ1214A
PR1212
(>17.6V) 1 (From TI GPIO1)
2 O ACAV_IN_NB <34,43,52,53> EN_PD_HV_1# 2 @ PR1218
3 2
2
-
G
PQ1204B
0_0402_5%
3
5 1 2
1200P_0402_50V7K
23.2K +-1% 0402
100P_0402_50V8J~D
220P_0402_50V8J~D
2
1
@ PR1220
84.5K_0402_1%
<35,53> VBUS1_ECOK
1
PQ1214B
PQ1201B
PR1219
PC1205
PC1206
<26,53> EN_PD_HV_1 0_0402_5%
4
1
6
VBUS1_ECOK
PR1217
PC1207
5 1 2 5
2
PQ1201A
2
4
1
2
2
6
PC1204
1
1
PR1216
0.1U_0402_10V7K PR1222 @ PR1223
0_0402_5%
+3.3V_VDD_PIC 100K_0402_5%
PQ1204A
2 1 0_0402_5%
2
2 1 2 AC_DISC# <34,43,53>
PR1210 @ PR1254
1M_0402_5% 0_0402_5% @
1
2
2 1 1 2
@ PR1211 PU1200
5
0_0402_5% MC74VHC1G08DFT2G SC70 5P AND
1 2 1
P
<26,53> EN_PD_HV_1 B 4
1 2 2 O
A
G
@ PR1215
3
PJP1202 0_0402_5%
1 2
1 2
JUMP_43X118
C C
EMI Part
PL1201 EMC@
+TBTA_Vbus_1 PQ1206 S3
5A_Z120_25M_0805_2P AON7409_DFN8-5
1 2 1
2
1 2 +TBTA_Vbus_1 5 3
+TBTA_VBUS PL1202 PQ1205
5A_Z120_25M_0805_2P @ PR1221 DMN65D8LW-7_SOT323-3
100P_0402_50V8J
100P_0402_50V8J
0_0402_5%
100K_0402_5%
EMC@
4
1
D
1 2 3 1
1000P_0402_50V7K
1500P_0402_50V7K
0.1U_0402_25V6
<35> DCIN1_EN
1
1
@EMC@ PC1215
EMC@ PC1208
@EMC@ PC1209
PR1227
EMC@ PC1216
499K +-1% 0402

2
PC1210
PR1228
G
2
2
2
1
+3.3V_ALW +3.3V_ALW
100K_0402_5%
2
2
100K_0402_5%
1
2
PR1224
PR1226
@ PR1225
2
0_0402_5%
@ PR1255 @ PR1235
150K_0402_1% 100K_0402_5% @ PR1233
1
2
@ PR1242 100K_0402_5% +3.3V_ALW
PC1209 can't over 1000P
1
0_0402_5%
1
<35,43> VBUS2_ECOK 1 2
2
<35,53> VBUS1_ECOK 1 2
+3.3V_ALW +3.3V_VDD_PIC PR1231 CMOUT <52>
@ PR1257 100K_0402_5%
0_0402_5% AC_DISC# <34,43,53>
DMN65D8LDW-7 2N SOT363-6
@ PR1245
3
+TBTA_Vbus_1 +3.3V_VDD_PIC +3.3V_ALW 0_0402_5% D
1
PQ1210B
1 2 5
S3 OVP G
1
@ PD1205
2
SDMK0340L-7-F_SOD323-2 PR1229 +3.3V_ALW S
4
6
1 2 +3.3V_VDD_PIC 49.9K +-1% 0402 D
2
2
6
3
PQ1211A
@ PR1238 PR1234 D D 2
150K_0402_1%
1
PC1217
0_0402_5% 2 5 G
100K_0402_1%
1500P_0402_50V7K
100K_0402_5%
PQ1211B
PR1239
1 2 G G
1
2
PR1237
PR1259 S
PQ1210A
PR1236 100K_0402_5% S S
4
1
+3.3V_ALW
100K_0402_5% @
2
1
@ PR1240 @ PR1260
@ LM393_P 100K_0402_1% PQ1209A 0_0402_5%
<26,53> EN_PD_HV_1 PROCHOT#_ISL88738 <52>
1
6
+3.3V_ALW
PQ1208A
B 2 DMN65D8LDW-7_SOT363-6 1 2 D B
2
2
2
PU1201B
3
1
D
@ PR1244 G PR1230
1
8
2
LM393DGKR_VSSOP8
PQ1216
PQ1208B
@ PR1243 0_0402_5% D 100K_0402_5% 2
5 0_0402_5% 1 2 5 S G
P
<26,52> AC1_DISC#
1
+ 7 1 2 5 PQ1209B G PR1232
1200P_0402_50V7K
S
100P_0402_50V8J
3
6 O
100K_0402_5%
0.01UF_0402_25V7K
-
G
1
100K_0402_1%
S
100P_0402_50V8J
1
1
1
PC1211
PC1213
100K_0402_1%
4
1
6
PR1246
PC1212
PC1214
D PQ1207A
PR1247
2
2
G DMN65D8LDW-7 2N SOT363-6
2
@ @ @ PR1261
2
@ @ @ 0_0402_5% S
1
1 2
OVP setting: 5.5V

@ PR1241
3
0_0402_5% D
@ PR1248 <34,43,52,53> ACAV_IN_NB 1 2 5

PT1
1
D 0_0402_5% PAD~D G PQ1207B

LPS_PROTECT#
PQ1212
2 1 2 DMN65D8LDW-7 2N SOT363-6
G S
4
1
S @ PR1250 (From EC)

3
PR1249 0_0402_5%
10K_0402_5% 1 2 EN_PD_HV_1 <26,53>
2
1 2
@ PR1258
0_0402_5%
A A
Title
TypeC_PD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-E131P
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
1
PR1302
@U23E@
<13,54> LPM_ZVM_N @ PR1303 10K_0402_1%

0_0402_5%
2
1 2
@ PR1301
0_0402_5%
1 2 EN_VCC_EDRAM
<17,34,35,42,47> RUN_ON
1
@ PR1325
@ PC1302
0.1U_0402_25V6
0_0402_5% PR1304
D 1M_0402_1% D
1 2 PJP1302
<35,49,54> IMVP_VR_ON
2
@U23E JUMP_43X79
1 2
+VCC_EDRAM_P +VCC_EDRAM
2
@U23E 1 2
13
14
15
16
17
PU1301
Vin=3~17V
TP
LPM
EN
PGND
PGND
PJP1301
+PWR_SRC 1 2 VIN_VCC_EDRAM 12
PVIN VOS
1
+VCC_EDRAM_P
10U_0805_25V6K
10U_0805_25V6K
PL1301 @U23E
1
+3.3V_ALW LX_VCC_EDRAM
+VCC_EDRAM_P
PC1303
PC1304
11 2 1 2
PVIN SW
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2
2
1
@U23E PC1305
@U23E PC1306
@ PC1307
@U23E
@U23E
10 3
AVIN SW
2
2200P_0402_50V7K
1SNUB_VCC_EDRAM
0.1U_0402_25V6
1
1
VID0_EDRAM_VR 9 4
@EMC@ PC1301
@EMC@ PC1308
VID0 PG @EMC@ PR1305
1
AGND
@U23E @ 4.7_0603_5%
VID1
FBS
PR1306 PR1307
SS
2
10K_0402_1% 10K_0402_1%
2
5
VID0_EDRAM_VR
@EMC@ PC1309 +VCC_EDRAM_P
1SS_VCC_EDRAM
VID1_EDRAM_VR
PR1308@U23E
1
VID1_EDRAM_VR
100_0402_1%
470P_0402_50V7K
2
1
@ @U23E
470P_0402_50V7K
PR1309 PR1310 PR1311
2
10K_0402_1% 10K_0402_1% @U23E
C 0_0402_5% C
2
@U23E PC1310
1 2
PR1312 VCC_EDRAM_SENSE <15>
2
@U23E
0_0402_5%
+VCC_EDRAM
1 2
VSS_EDRAM_SENSE <15>
TDC 1.7 A
Peak Current 2.4 A
OCP Current 2.9 A
TYP MAX
Choke DCR 48.0mohm
+3.3V_ALW
1
PR1313
@U23E@
<13,54> LPM_ZVM_N @ PR1314 10K_0402_1%

0_0402_5%
2
1 2
@ PR1315
0_0402_5%
1 2 EN_VCC_EOPIO
<11,17,34,42,46,47,48> SIO_SLP_SUS#
0.1U_0402_25V6
1
@
PR1326
@ PC1311
0_0402_5%
<35,49,54> IMVP_VR_ON 1 2 @U23E
2
PR1316
1M_0402_1% PJP1303
2
JUMP_43X79
@U23E 1 2
13
14
15
16
17
PU1302 +VCC_EOPIO_P 1 2 +VCC_EOPIO

B Vin=3~17V B
TP
LPM
EN
PGND
PGND
PJP1304
+PWR_SRC 1 2 VIN_VCC_EOPIO 12
PVIN VOS
1
+VCC_EOPIO_P
10U_0805_25V6K
10U_0805_25V6K
PL1302 @U23E
1
PAD-OPEN1x1m
PC1312
PC1313
1UH_1277AS-H-1R0N-P2_3.3A_30%
11
PVIN SW
2 LX_VCC_EOPIO 1 2
+VCC_EOPIO_P
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
MSM_N <13>
@U23E
@U23E
1
@U23E PC1314
@U23E PC1315
@ PC1316
10 3
AVIN SW
2
2200P_0402_50V7K
0.1U_0402_25V6
1SNUB_VCC_EOPIO
1
VID0_EOPIO_VR 9 4
@EMC@ PC1317
@EMC@ PC1318
@U23E VID0 PG @EMC@ PR1319

@
PR1317 PR1318
2
AGND
10K_0402_1% 10K_0402_1% 4.7_0603_5%

VID1
FBS
SS
2
VID0_EOPIO_VR
+VCC_EOPIO
8
SS_VCC_EOPIO 7
VID1_EOPIO_VR TDC 1.1 A

@EMC@ PC1319
+VCC_EOPIO_P Peak Current 1.5 A
1
VID1_EOPIO_VR 470P_0402_50V7K PR1322@U23E OCP Current 1.8 A

2
@ @U23E 100_0402_1%
PR1320 PR1321 TYP MAX
10K_0402_1% 10K_0402_1% Choke DCR 48.0mohm
PC1320 @U23E
470P_0402_50V7K
PR1323
2
@U23E
2
1
0_0402_5%
1 2
PR1324 VCCEOPIO_SENSE <15>
2
@U23E
0_0402_5%
1 2
A VSSEOPIO_SENSE <15> A
Title
PWR-VCCEDRAM/EOPIO
1.0
LA-E131P
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List )

Item Page# Title Date Request Issue Solution Rev.
Owner Description Description
2016
1 56 Change CPU VR version 05/24 Compal change solution version to fix PS4 funciton issue change ISL95857HRTZ to ISL95857AHRTZ X01
Change the S4 fast

turn off circuit 2016 Change the S4 fast turn off circuit Re-connect the PR1251.1 and PQ1215.3 from +VBUS_DC_SS to +AC_IN X01
2 60 05/30 Compal to avoid the leakage
to avoid the leakage
D D
Add the Circuit for

Multiple Input Add the Circuit for Multiple Input Charger:Add PR960 and depop PR919 let the PU901.20 CMIN connect to GND.
3 59 2016 Compal Detach detection & PROCHOT# Add 1 net PROCHOT#_ISL88738 X01
Detach detection 05/30
& PROCHOT# TypeC: Add PQ1216 to drive the PROCHOT# and PC1217 to do the reserve.
PR12, PR11, PR1205, PR1207 and PR1228 change to 499K from 1M ohm
4 2016 To solve the MOS leakage problem to avoid PR16, PR18, PR1212, PR1213 and PR1229 change to 49.9K from 1M ohm X01
50 MOS leakage problem 05/30 Compal the error active PR10, PR1251 and PR1202 change to 300K from 100K ohm.
Reserve the OVP function

Reserve the OVP function to protect Depop PJP1202, PR1255, PR1239, PR1246, PC1211, PR1237,
5 60 2016 the typeC device. PC1212, PD1205, PC1213, PC1214 and PR1248 X01
05/30 Compal
Change the PR1247 from 200K_0402_1% to 100K_0402_5% ohm
To decrease the charger input leakage voltage

6 59 Decrease the charger 2016 for TypeC AC Change the PD903 from SCS0340L010 to SCS00006C00. X01
input leakage voltage 05/30 Compal
Reduce footprint size Reduce PC104 footprint size for DFX request
7 51 for DFX request 2016 Change PC104 from 0805 change 0603 size for DFX request X01
07/14 Compal
Fine tune the DC-IN 2016 For Temp/Voltage test to fine tune the DC-IN
8 60 detect voltage 07/14 Compal detect voltage from 17.6V to 16.9V PR1219 change from 22.6K to 23.2K. SD034232280 X02
1. Change the charger version to B version from A version

2. Change the PC926, PC927, PC942 and PC946 from @ to 1uF/0402_25V
2016 3. Change the PC925 and PC945 from 1uF to 4.7uF/0402_10V.
9 59 Change Charger version 07/14 Compal Charger IC update version 4. Change the PR909 and PR910 from 1 Ohm to 3.3 Ohm. X02
5. Change the PR937 and PR938 from 1 Ohm to 2.2 Ohm.
6. Change the PC944 from 47nF to 12nF.
7. Change from PR932 from 118K to 105K
C
8. Change PD901 pull up source from +PBATT to +PWR_SRC C
9. Add PC1286 0.1U_0402_25V
10 2016 VCCSA change the PU606 to PU614 and PL601 to PL614

57 Location Alignment 07/20 Compal Location Alignment IA change the PU603 to PU610 and PL603 to PL610 X02
GT change the PU604 to PU612 and PL604 to PL612
2016 X02
11 56 SA OVP 08/29 Compal SA OVP when C status change 1. Change the PL614 from 1uH to 0.47uH
2. Change the PR651 from 124K to 133K
3. Change the PR636 from 1.24K to 649
4. Change the PC633 from 6800p to 3300p
5. Change the PR630 from 7.32K to 2.49K
9. Remove PC601 & PR652
2016
12 59 S5 power consumption 08/29 Compal S5 Power consumption fail because Add PR952 pull down 100K resistor to discharge UE1 pin C7 leakage
UE1 pin C7 has leakage X02
13 2016 Remove : PR410

54 Enable LPM mode 08/29 Compal Enable PRIM_CORE low power mode Stuff : PR426 X02
stuff : PR106,PR202,PR303,PR663
2016 stuff : PC112,PC204,PC302,PC662 X03
14 51 For EMI request 09/08 Compal Add some parts for EMI request
stuff : PC100,PC103,PC202,PC203,PC216,PC217,PC301,PC303,PC659,PC660
stuff : PL901
15 60 Modify symbol to 2016

2nd source 09/08 Compal Modify PD1202,PD5 to 2nd source because vendor EOL Modify PD1202,PD5 to 2nd source(SCS00005X00) because vendor EOL X03
1. Change the PR628 from 2.61K to 4.99K for U23 CPU

16 57 For U23e CPU modify 2016 Modify PR628 / PC626 value after Intel Validation test
Compal for U23e CPU 2. Change the PC626 from 0.047u to 0.022u for U23 CPU X03
B
09/23 3. Change the PR622 from 2.49K to 2.55K for U23 CPU B
4. Change the PR651 from 82K to 78.8K for U23 CPU

2016
17 51 Reserve symbol footprint 09/26 Compal Reserve symbol 3 pcs footprint 1. Reserve symbol PD100 footprint for 3V/5V enable X03
2. Reserve PR1325 / PR1326 footprint for sequence
18 61 Enable LPM mode 2016 Compal

09/26 Enable EDRAM / EOPIO low power mode 1. Un-pop : PR1302 / PR1313
2. Stuff : PR1303 / PR1314 X03
2016
19 59 Max. Power up to 125W 09/26 Compal Modify PR948 value for Max. Power 125W 1. Change the PR948 from 10.5K to 12.7K
X03
Type-C connector 2016
20 51 voltage droop 10/05 Compal Type-C connector voltage droop Add PR121 0 ohm for Type-C connector voltage droop issue
X04
21 54 2016
VCCIO design modify 10/05 Compal VCCIO design modify 1. VCCIO use local sense: PR421 change to 0 ohm, de-pop PR422,PR412
2. VCCIO change to 0.95V: De-pop PR413,PR416, pop PR415,PR414 X04
22 54 2016 Compal
11/02 Delete reserve resistor Delete PR121
A00
23
A A

Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT PWR P.I.R
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List ) LA-E131P

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D D
1 24 TBT-AR-SP(1/2) 2016/05/23 EE CPU_DP1_HPD need to PD for AR config Pop RT24 0.2(X01)
DP,PCIE
2 26 [Type C]PD 2016/05/23 EE UT5.D6 need to PD for TI suggestion Pop RT101 0.2(X01)
Controller TI
3 26 [Type C]PD 2016/05/23 EE Schematic align Add net name 0.2(X01)

Controller TI
UT5.B2 : PD1_GPIO0
UT5.C2 : EN_PD_HV_1_R
UT5.D10 : PD1_GPIO2
UT5.G11 : AC1_DISC#_R
UT5.C10 : TBTA_HPD_R
UT5.E10 : PD1_GPIO5
UT5.G10 : PD1_GPIO6
UT5.D7 : PD1_GPIO7
[Type C]PD RT111 change from 10K to 100K (SD028100380)
4 27 2016/05/23 EE TypeC PD solution (dead battery mode) CT90 change from 100P to 1U (SE00000QL10) 0.2(X01)
Power
5 33 Codec ALC3246 2016/05/23 EMI EMI request CA2/CA3 change from 2200P to 330P (SE000006I80) 0.2(X01)
C C
TBT-AR-SP(1/2) WLAN antenna noise effect AR Crystal, cause

6 24 2016/05/23 EE TBT- AR no display Change YT1 from SJ10000JC00 to SJ10000NW00 (metal shielding) 0.2(X01)
DP,PCIE
7 41 PAD, LED 2016/05/23 EE Remove HDD LED MUX feature Add RZ361 and depop QZ3, QZ2, RZ25 0.2(X01)
EC MEC5105 Add net VCI_IN1# and add PU RE507

8 34 2016/05/23 EE Schematic align Add net VCI_IN2# and add PU RE508 0.2(X01)
9 36 USH & TPM 2016/05/23 EE Atmel request for current TPM silicon Add CZ74 (pop) and RZ72(depop) for UZ12.7 0.2(X01)
10 9 CPU (4/14) 2016/05/23 EE Cardreader change to RTS5242 (PCIE) Add net MEDIACARD_IRQ# to UC1.AN8 0.2(X01)
11 31 Card Reader 2016/05/23 EE Cardreader change to RTS5242 (PCIE) Cardreader schematic change from RTS5330 (USB) to RTS5242 (PCIE) 0.2(X01)
CPU (5/14) Change net from USB3.0 port 5 to PCIE port1

12 10 2016/05/23 EE Cardreader change to RTS5242 (PCIE) Delete USB2.0 port 6 0.2(X01)
13 10 CPU (5/14) 2016/05/23 EE No support M.2 3042 (HCA) Remove PCIE port 10 0.2(X01)
B B
14 11 CPU (6/14) 2016/05/23 EE No support M.2 3042 (HCA) Assign CLKREQ_PCIE#0 to Cardreader 0.2(X01)
15 32 NGFF Card 2016/05/23 EE No support M.2 3042 (HCA) Remove PCIE port 10, CZ10, CZ11 0.2(X01)
16 37 M2 2280 Socket 2016/05/23 EE Remove HDD LED MUX feature Depop RN100 0.2(X01)
EC MEC5105 Change location RE510 to RE512

17 34 2016/05/23 EE PORT80_DET# Reserve RE513 100k (SD028100380) to GND 0.2(X01)
18 6 CPU (1/14) 2016/05/23 EE Follow Intel PDG AUX topology Delete RC179/RC180/RC181/RC182 0.2(X01)
CPU (12/14) Pop RZ120 and Depop UZ34

19 17 2016/05/23 EE S0ix(modern standy) support for VCCPLL_OC Add net name VCCSTG_EN(UZ19.4) and connect to RZ120.1 0.2(X01)
20 34 EC MEC5105 2016/05/25 EE Symbol pin name change UE1.C1 pin name change to GPIO024_nRESETI 0.2(X01)
21 26 [Type C]PD 2016/05/25 EE Symbol pin name change UT5.A6/A7/A8/B7 pin name change to GND, UT5.D6 pin name change to HRESET 0.2(X01)
Controller TI
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT EE P.I.R (1/4)
5 4 3 2 1
5 4 3 2 1

Request
D 36 USH & TPM JUSH1 change to LTCX007Q600 D
22 40 2016/05/25 ME Connector update JKBTP1 change to LTCX007Q500 0.2(X01)
Keyboard
23 41 PAD, LED 2016/05/25 ME MB ME drawing change Remove H11 and change H28 to H_5P0X4P0 0.2(X01)
24 6 CPU (1/14) 2016/05/31 EE DP HPD base on INTEL PDG Delete RC312/RC242 0.2(X01)
NGFF Card CZ28,CZ29 change from 0.047uF to 0.01uF

25 32 2016/06/01 EE Intel reviwe result CZ27 change from 0.1uF(@)_0201 to 10uF_0603 0.2(X01)
CZ32/CZ31/CZ29 place near JNGFF1.2/JNGFF1.4
CZ27/CZ30/CZ28 place near JNGFF1.72/JNGFF1.74
26 30 LAN Clarkvillie 2016/06/01 EE EMI request Change CL22 from 1500P to 150P (SE00000FA80) 0.2(X01)
& RJ45
27 33 Codec ALC3246 2016/06/01 EE Audio EA modify (meet GS mark) Change RA7, RA8 from 24.9ohm to 16.2ohm (SD00001U900) 0.2(X01)
11 CPU (6/14) Change CC21, CC22 from 15pf to 12pf
28 24 TBT-AR-SP(1/2) 2016/06/01 EE Crystal EA modify Change CT20, CT21 from 20pf to 8.2pf 0.2(X01)
DP, PCIE
C C
29 36 USH & TPM 2016/06/01 EE TPM change to Nuvoton NPCT650JBAYX All page 0.2(X01)
USH & TPM UZ12 change to NPCT650JB2YX (SA00008EL70)

30 36 2016/06/04 EE Vendor schematic review Add CZ75 4.7uF (SE00000SO00) for +UZ12_TPM 0.2(X01)
Add CC331 2.2PF (SE07122AC80) for HDA_RST#
CPU (7/14) Add CC332 2.2PF (SE07122AC80) for HDA_SDIN0 0.2(X01)
31 12 2016/06/04 RF Intel MOW request
Add CC333 2.2PF (SE07122AC80) for HDA_SDOUT
Add RZ128 0 ohm connect WWAN_COEX3 and WLAN_COEX3
NGFF Card Intel reviwe result Add RZ129 0 ohm connect WWAN_COEX2 and WLAN_COEX2 0.2(X01)
32 32 2016/06/04 RF (WWAN Coex feature support) Add RZ130 0 ohm connect WWAN_COEX1 and WLAN_COEX1
33 33 Codec ALC3246 2016/06/04 ESD ESD request Change LA10, LA11 to SM01000OZ00 0.2(X01)
34 29 eDP CONN& 2016/06/04 EMI EMI request Change LV1 to SM01000NY00 0.2(X01)
Touch screen
35 32 NGFF Card 2016/06/06 EE Debug card reserve Add RZ131, RZ132 for PORT80_DET# and HOST_DEBUG_TX 0.2(X01)
B 13 CPU (8/14) B
36 18 CPU (13/14) 2016/06/06 EE For RF noise issue layout modify-SB14 only Change CC213 to 0201 size (SE00000YB00) and remove T14 0.2(X01)
37 36 USH & TPM 2016/06/07 EE Schematic align Change loaction RZ90 to RZRZ362 0.2(X01)
38 24 USH & TPM 2016/06/14 EE TPM pre-config Reserve RZ363 ohm for GPIO2 and SIO_SLP_S3# 0.2(X01)
39 36 TBT-AR-SP(1/2) 2016/06/14 EE BOM change Change UT1 from SA00009YL0L to SA00009YL2L (C1) 0.2(X01)
DP, PCIE
40 12 CPU (7/14) 2016/06/14 RF RF request Change CC27 from 22pf to 47pf (SE071470J80) 0.2(X01)
HDMI CONN Change RV24,RV25,RV27,RV28,RV30,RV31,RV33,RV34 to 12nH (SHI0000PJ00)

41 23 2016/06/14 EMI EMI request Change RV26,RV29,RV32,RV35 to SHI0000PJ00 to 300ohm (SD028300080) 0.2(X01)
42 20 DDR4 2016/06/14 EE 2nd source align Change UD1 from SA00007WE00 to SA00007UR00 0.2(X01)
43 34 EC MEC5105 2016/07/13 EE For MEC5105K-D1-TN EC sample Change UE1 to SA00009GL00 & Depop RE361,Pop RE360,RE362 0.3(X02)
A A
44 36 USH & TPM 2016/07/13 EE TPM pre-config Pop RZ363 and depop (@) RZ111,RZ112, RZ113,QZ9 0.3(X02)
Title
5 4 3 2 1
5 4 3 2 1

Request
D D
45 35 EC MEC5105 2016/07/13 EE Board ID Change RE79 to 62Kohm (SD028620280) 0.3(X02)
Support
EC MEC5105 1.UE1.F11 add RTCRST_ON_GPIO122 & reserve RE515@ to QE12.2

46 34 2016/07/13 EE GPIO map update 2.UE1.B6 change to RTCRST_ON_GPIO141 and add RE514 to QE12.2 0.3(X02)
47 33 Codec ALC3246 2016/07/13 EE ESD request (2nd source align) Change LA10, LA11 back to SM01000NA00 0.3(X02)
USH & TPM 1.RZ10 changed to 100K -Let USH_PWR_STATE# keep low at S5
48 36 2016/07/13 EE USH BOM modify 2.DZ7 depop and pop RZ87 - X8 have no difference JUSH1 pin define with X70.3(X02)
49 32 NGFF Card 2016/07/13 EE Symbol error Re-link JSIM1 symbol and change SIM_DET to JSIM1.2 0.3(X02)
[Type C]PD
50 26 Controller TI 2016/07/13 EE For PD sample Change UT5 from SA00009W200 to SA00009W210 0.3(X02)
EC MEC5105
51 35 Support 2016/07/13 EE Vendor schematic review Add net WRST# to UE2.4 and CE500 1uf (SE000000K80) 0.3(X02)
HDMI CONN Change RV24 to LV31, RV25 to LV32, RV27 to LV33, RV28 to LV34, RV30 to LV35,
52 23 2016/07/13 EMI EMI request 0.3(X02)
RV31 to LV36, RV33 to LV37, RV34 to LV38 and from SHI0000PJ00 to SHI00006Q00
C
TBT-AR-SP(1/2) 1.Change YT1 from SJ10000NW00 to SJ10000NC00 C
53 24 DP, PCIE 2016/07/13 EE Intel reviwe result 2.TBT_CIO_PLUG_EVENT# add RT391 PU to +3.3V_ALW_PCH and 0.3(X02)
depop RT371 for back-driver issue
3.RTD3_CIO_PWR_EN add RT392 and Pop RT25,depop RT372
54 41 PAD, LED 2016/07/20 EE Intel suggestion H5, H6 cnage from 1.1mm to 1.0mm 0.3(X02)
55 29 eDP CONN & 2016/07/20 ME Factory request Change JIR1 to SP01001YO00 to avoid JTS1 and JIR1 assembly error 0.3(X02)
Touch screen
LAN
56 30 Clarkvillie 2016/07/21 EMI EMI request Change CL22 from 150P to 10P (SE167100J80) 0.3(X02)
& RJ45
57 35 EC MEC5105 2016/07/21 EE Vendor schematic review Add RE523 0 ohm for UE2 power pin soft start 0.3(X02)
Support
58 29 eDP CONN & 2016/07/22 ESD ESD request Reserve the ESD diode DV7 on USB20_N5 and USB_P5 for system damage issue 0.3(X02)
Touch screen
59 29 eDP CONN & 2016/07/25 ESD ESD request (layout limit) Change DV7 to DV7 and DV8 (SC40000AR00) 0.3(X02)
Touch screen
EC MEC5105 Change RPE12.1 to RE524 (10Kohm) for EXPANDER_GPU_SMDAT

B 60 34 2016/07/25 EE Vendor schematic review Change RPE12.2 to RE524 (10Kohm) for EXPANDER_GPU_SMCLK 0.3(X02) B
61 27 [Type C]PD 2016/07/25 EE For UT7 2nd source issue Add RT393 PD 100K ohm to +5V_PD_VDD for discharging instantly 0.3(X02)
Power
62 35 EC MEC5105 2016/08/01 EE Vendor schematic review Change RE14,RE15,RE18 from 100k ohm to 10k ohm 0.3(X02)
Support
Keyboard Chagne RZ20, RZ21 from 4.7k ohm to 2.2k ohm

63 40 2016/08/01 EE Touchpad I2C EA Change CZ80, CZ81 from 330pf to 10pf 0.3(X02)
64 14 CPU (9/14) 2016/08/01 EE Intel suggestion Change RC137 from 1k ohm to 3k ohm 0.3(X02)
65 25 TBT-AR-SP 2016/08/01 EE Crystal EA modify Change CT20, CT21 from 8.2pf to 27pf 0.3(X02)
(1/2) DP, PCIE
66 36 USH & TPM 2016/09/06 EE TPM change NPCT650VB2YX Change UZ12 from to SA00008EL70 to SA00008EL80 0.4(X03)
35 EC MEC5105 Change UE2 from SA00009VL00 to SA0000ADQ00, remove RE523
67 34 Support 2016/09/06 EE Expander I/O change to Microchip MCP23008 Change RE524, RE525 from 10Kohm to 2.2Kohm 0.4(X03)
EC MEC5105
A 68 35 EC MEC5105 2016/09/06 EE Board ID Change RE79 to 33kohm (SD028330280) 0.4(X03) A

Support
Title
5 4 3 2 1
5 4 3 2 1

Request
D D
69 35 EC MEC5105 2016/09/06 EE EC watchdog reserve Add QE13,RE530,RE531 0.4(X03)
Support
70 34 EC MEC5105 2016/09/06 EE Schematic align Reserve RE526(10K) PU for USH_DET# to +3.3V_ALW 0.4(X03)
EC MEC5105 Reserve RE505 PU for LOM_CABLE_DETECT#

71 34 2016/09/08 EE EC request for GPIO setting Add RE532 PU for BCM5882_ALERT# 0.4(X03)
72 36 USH & TPM 2016/09/13 EE EC request for GPIO setting Pop RZ8, RZ9 for USH_SMBCLK and USH_SMBDAT 0.4(X03)
73 35 EC MEC5105 2016/09/13 EE EC watchdog delete Delete QE13,RE530,RE531 0.4(X03)

Support
74 33 Codec ALC3246 2016/09/13 RF RF request Pop CA54 82pf for DMIC_CLK0 0.4(X03)
75 35 EC MEC5105 2016/09/26 EE Dell request Reserve RE536/RE537 for resistors for PCH_DPWROK circuit 0.5(X04)
Support
76 34 EC MEC5105 2016/09/26 EE WDT schematic option 2 Use Option2: pop RE361 / depop RE362 0.5(X04)
C C
77 35 EC MEC5105 2016/09/29 EE WDT schematic Add QE13, CE503, RE530 0.5(X04)
Support
78 35 EC MEC5105 2016/09/30 EE Board ID Change RE79 to 8.2kohm (SD028820180) 0.5(X04)

Support
79 35 EC MEC5105 2016/09/30 EE BITS294007 Change CE12 to 2.2uf and RE33 to 1Kohm 0.5(X04)
Support
80 34 EC MEC5105 2016/10/05 EE Prevent EOS issue on MEC5105 Add 100ohm serial resistor on CV2_ON close to UE1.H8 0.5(X04)
81 34 EC MEC5105 2016/11/04 EE Board ID Change RE79 to 4.3kohm (SD028820180) 1.0(A00)

Support
EC MEC5105 Change MEC5105 CPN to SA00009GL30

82 33 2016/11/04 EE MEC5105 change from revB to revC Depop RE361,Pop RE362 1.0(A00)
83 34 EC MEC5105 2016/11/04 EE MEC5105 revC WDT schematic Pop RE536, Depop QE13, CE503, RE530, UE7, CE5,CE6, RE348 1.0(A00)
Support
84 All All page 2016/11/04 EE 0 ohm short pad Change 0 ohm to short pad 1.0(A00)
B B
85 12 CPU (7/14) 2016/11/04 EE Service Mode Switch remove Depop SW1, RC222 and pop RC221 1.0(A00)
A A
Title
5 4 3 2 1

Dell Latitude 7480 Compal CAZ20 LA-E131P Rev 1.0 (A00) Схема

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Dell Latitude 7480 Compal CAZ20 LA-E131P Rev 1.0 (A00) Схема

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A B C D E

REV : 1.0 (A00)

@RF@ : RF Nopop Component

Steamboat 14 w/ AR Block Diagram Steamboat 12 only support one DIMM

Memory BUS (DDR4) DDR4-SO-DIMM X2

Trough eDP Cable

CPU&PCH XDP Port

USH board P36

POWER STATES AR config

S0 (Full ON) / M0 HIGH HIGH HIGH HIGH ON ON ON ON ON

S5 (SOFT OFF) / M3 LOW LOW LOW HIGH ON ON OFF OFF OFF

PM TABLE PCIE-8 SATA-1

+1.8V_PRIM +1.0V_VCCST +1.8V_RUN

S5 S4/AC ON OFF OFF

S5 S4/AC doesn't exist OFF OFF OFF

Date: Wednesday, November 09, 2016 Sheet 3 of 59

SIO_SLP_SUS# CPU PWR

2 1 CPU_DP1_CTRL_CLK E55 C47

<20> DDR_A_DQS#[0..7] <21> DDR_B_DQS#[0..7]

DDR4, Ballout for side by side(Non-Interleave) <20> DDR_A_D[0..63] <21> DDR_B_D[0..63]

<20> DDR_A_DQS[0..7] <21> DDR_B_DQS[0..7]

DDR4 COMPENSATION SIGNALS

SM_RCOMP1 RC6 1 2 80.6_0402_1%

SM_RCOMP2 RC7 1 2 100_0402_1%

PCH_SPI_CLK_1_R PCH_SPI_CLK_0_R ESPI_CLK_5105 1 2 +3.3V_RUN

LPC@ RC27 8.2K_0402_5%

<36> PCH_SPI_D0_R1 PCH_SPI_CLK_R1 3 6 PCH_SPI_CLK_0_R

<36> PCH_SPI_CLK_R1 PCH_SPI_D3_R1 4 5 PCH_SPI_D3_0_R SML1_SMBCLK 1 2 +3.3V_ALW_PCH

@RF@ CC319 33P_0402_50V8J

@ RC30 1K_0402_5% 33_0804_8P4R_5%

BOOT BIOS Destination(Bit 6)

HIGH Interleave HIGH NON AR

LOW Non-Interleave LOW AR

For SB/KW UMA w AR CC21

2 1 B 4 PCH_PLTRST#_AND @ RC325 0_0402_5% +3.3V_ALW_PCH

RC67 1K_0402_5% 100K_0402_5% @ RC73 10K_0402_5%

+1.0V_VCCST @ RC344 10K_0402_5%

SYSTEM POWER MANAGEMENT

BB15 AP16 INTRUDER# 11

<30> PM_LANPHY_ENABLE AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11 VRALERT# 14 13

POP NO Support Deep sleep

DE-POP Support Deep sleep +3.3V_RUN

@ RC215 0_0402_5% ESD Request:place near CPU side

RC75 2 1 ME_RESET# 2 RC224 1K_0402_5%

10K_0402_5% @ RC225 8.2K_0402_5% @ UC12

Compal Electronics, Inc.

Service Mode Switch:

A TOP SWAP STRAP Flash Descriptor Security override A

HIGH ENABLE HIGH DISABLE

CFG[2][5][6][7] for SKYLAKE-H CPU CFG strap pin

RSVD_E61 PROC_SELECT# +1.0V_VCCST

For Skylake , RC120 depop

2 1 CPU_XDP_PREQ# Place near JXDP1.47

TDO_XDP H_VCCST_PWRGD_XDP CPU_XDP_TRST#

+VCC_CORE: 0.3~1.35V +VCC_CORE +VCC_CORE

VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e VIDSCLK

CAD Note: Place the PU resistors close to CPU

CAD Note: Place the PU resistors close to CPU

RC208close to CPU 300 - 1500mils

UC1M CPU@ SKL-U

N64 VCCGT VCCGTX_AM58 AU58

22U_0603_6.3V6M BB32 AM30

CC296 BB41 AM42 +VCC_SA