Digital 1 Test 3 REVIEW

4-Bit Magnitude Comparator

A3 A<B
A2
A1 A=B
A0
A>B
B3
B2
B1
B0
Ia<b
Ia=b
Ia>b
7485

INPUTS OUTPUTS
A3 A2 A1 A0 B3 B2 B1 B0 A<B A=B A>B
0 0 1 0 0 0 0 1
0 0 1 0 1 0 0 0
0 1 1 0 0 0 1 1
1 0 0 1 1 0 0 0
0 0 1 0 0 1 0 1
0 0 1 0 1 0 1 0
1 0 0 1 0 1 0 1

1
 Digital 1 Test 3 REVIEW

Decimal to BCD Encoder

11 1
12 9
2 A
13
3 7
1 B
4
2 6
5 C
3
6 14
4 D
7
5
8
10
9
74147N

INPUTS OUTPUTS
I1 I2 I3 I4 I5 I6 I7 I8 I9 A3 A2 A1 A0
1 1 1 1 1 1 1 0 1
1 1 1 0 1 0 1 1 1
1 1 0 1 1 1 1 1 1
1 1 1 1 0 1 1 1 1
1 1 1 1 1 1 1 0 1
1 1 1 1 1 1 0 1 1
1 1 0 1 1 0 1 1 1
0 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 0
0 1 1 1 1 1 1 1 1

2
 Digital 1 Test 3 REVIEW

3-1 Binary to Decimal Decoder

A0 0
A1 1
A2 2
3
4
E1
5
E2
6
E3
7
74138

INPUTS ENABLE OUTPUTS

A2 A1 A0 E1 E2 E3 0 1 2 3 4 5 6 7
1 0 0 0 0 1
0 1 0 0 0 1
1 1 0 0 0 1
0 0 1 1 0 1
1 1 1 0 0 1
1 0 0 0 0 1
1 1 0 0 1 1
0 1 1 0 0 1
0 0 1 0 0 1
0 1 1 0 0 1

3
 Digital 1 Test 3 REVIEW

Multiplexer (~ = NOT)

I0
I1
I2
I3 Y
I4
~Y
I5
I6
I7

S3
S2
S1
E
74151N

I0 I1 I2 I3 I4 I5 I6 I7
1 1 0 1 0 1 0 1

ENABLE INPUTS OUTPUTS

E S3 S2 S1 Y ~Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
0 1 1 1
0 1 0 1
0 0 1 1
1 0 0 1

4
 Digital 1 Test 3 REVIEW

Label the outputs as a 1 or 0.

0
_________

_________
1

1
_________

_________
0

5
 Digital 1 Test 3 REVIEW
1
Complete the timing diagram for each flip-flop.

SET
Cp J Q

J K ~Q
RESET

K
1

SET
J Q

K ~Q
RESET

Cp

1D 1Q

1EN ~1Q

6
 Digital 1 Test 3 REVIEW

1EN

1D

1Q

SET
J Q

K ~Q
RESET

Cp

SD

RD

7
 Digital 1 Test 3 REVIEW

SET
S Q
EN
R ~Q
RESET

EN

SET

RESET

8
 Digital 1 Test 3 REVIEW

SET
J Q

K ~Q
RESET

Cp

SD

RD

9
 Digital 1 Test 3 REVIEW

SET
D Q

~Q
RESET

Cp

SD

RD

10
 Digital 1 Test 3 REVIEW
SET
J Q

K ~Q
RESET

Cp

SD

RD

11
 Digital 1 Test 3 REVIEW

Show the output of each gate in the blank provided (1 or 0).

________
0
0
________

0
0
________

________
1
____ ____
1
________
1
________
0

0 ________
________
0

1
________ ________

1
0
________

12
 Digital 1 Test 3 REVIEW

BONUS: 4 points

A3
A2
A1
A0
A3 A<B
B3 A2
A1 A=B
B2 A0
A>B
B3
B1 B2
B1
B0 B0
Ia<b
A7 A3
A2
A<B Ia=b
Ia>b
A6 A1
A0
A=B
7485
A5 A>B
B3
B2
A4 B1
B0
Ia<b
B7 Ia=b
B6 Ia>b

B5 7485

B4

Given the above circuit, complete the truth-table below.

A A A A A A A A B B B B B B B B A< A= A>
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 B B B
0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1
0 1 0 0 0 1 1 0 0 0 0 0 1 1 0 0
1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 1 1 1 0 1 1 1 0 0 1 1 1 1 1 1

13