BSIM-BULK: Accurate Compact Model for Analog

and RF Circuit Design

Chetan Gupta∗ , Ravi Goel∗ , Harshit Agarwal† , Chenming Hu† , Yogesh Singh Chauhan∗
∗Department of Electrical Engineering, Indian Institute of Technology Kanpur, India
† Department of Electrical Engineering and Computer Science, University of California Berkeley, USA
Email: chetang@iitk.ac.in, chauhan@iitk.ac.in

Abstract— In this work, we present the recent and upcoming

3
3

/dx
70 1.5

enhancements of the industry standard BSIM-BULK (formerly Solid : 3rd Deriv of IDS Black: WI VGS=1.2 V cg

csd
60 2
Dashed: 4th Deriv of IDS Blue : SI 1.0

/dVx3(x 10-3)
BSIM6) model. BSIM-BULK is the latest body referenced com- 50
VBS=0 V cb

/dx , d
1
pact model for bulk MOSFETs having a unified core, which 0.5

/dVx4
csd

(x 10 )
40

3
is developed by the BSIM group for accurate design of analog 30 0.0 0

cb
DS
and RF circuits. The model satisfies the symmetry test for DC

DS
20

/dx , d
d
-0.5 -1
and AC, correctly predicts harmonic slope, and exhibits accurate

3
d
10

results for RF and analog simulations. In order to further -1.0 -2

0
VBS=0 V

cg
improve the model accuracy for transconductance (gm ) and -10 -1.5

d
-3

output conductance (gds ), an analytical model for bulk charge -0.4 -0.2 0.0 0.2 0.4 -0.4 -0.2 0.0 0.2 0.4

effect, in both current and capacitance, is implemented. Several
other advanced models are added to capture real device physics.
These include: parasitic current at the shallow trench isolation
edges; leakage current components in zero threshold voltage
native devices; new model for NQS to capture the NQS effects
up to the millimeter wave regime; self heating effect; and heavily
halo implanted MOSFET’s anomalous gm , flicker noise and IDS
mismatch. All these enhancements have been implemented to
high standards of computational efficiency and robustness.
I. I NTRODUCTION
A compact model is an indispensable link between the
circuit designers and process development. Robust device
modeling and simulation capabilities are required to reap
the optimum performance of any circuit design. In order
to extract the device characteristics accurately, along with a
high computational efficiency, and to restrict the requirement
of the number of fitting parameters in the compact models,
the physics based real-device effects should be incorporated
inside the model. Although BSIM4 provides a very good
fitting flexibility to the analog and RF engineers while fitting
the measured data up to 28 nm technology node, it exhibits
the symmetry issue around VDS = 0 in the model, which
is very important for analog and RF design [1], [2]. To
overcome this major issue, BSIM group has developed a more
advanced model for bulk MOSFET, named by BSIM-BULK
(formerly BSIM6) [3]. BSIM-BULK is the latest industry
standard compact model for bulk MOSFET with the unified
charge based core, which had inherited all real device effects
from BSIM4 [3]–[6]. The model shows excellent convergence
in circuit simulation for RF, DC, small signal and transient
simulations, and also it is well suitable for high speed analog
applications. In addition to this, it also guarantees symmetry
around VDS = 0 [7]. As shown in Fig. 1(a) and Fig. 1(b),
the BSIM-BULK model successfully passes both DC and AC
GST tests [7], [8].
VX(V) VX(V)
(a) (b)
Fig. 1: GST: (a) DC GST for VG = 0.5V (WI) and VG =
1.2V (SI) IDS versus VX where VX = (VD - VS )/2, where
VD = −VS . (b) AC symmetry test. It indicates differential
capacitances: δcg , δcb and δcsd versus VX [7], [8].
While the similarity with BSIM4 preserves the excellent
user experience; BSIM-BULK has many advanced models
which are necessary for state-of-the art devices. We have
discussed various enhancements, which are implemented in the
DC I-V model of BSIM-BULK, which include: a) Anomalous
behavior of gm , a parameter critical to analog circuit design,
in the presence of strong halo implants [9]. b) Modeling
of punch-through and sub-surface leakage phenomena expe-
rienced by the zero threshold voltage (VT H ) native devices,
which are used for low power circuit design [10]–[12]. c)
Modeling of parasitics current due to edge effect in the shallow
trench isolation (STI). d) Analytical model for the bulk charge
effect. Furthermore, the enhancements in the RF and noise
models of BSIM-BULK have also been explained in this
paper, this consist of: a) The impedance field based compact
model to capture the anomalous trends of flicker noise [13].
b) An improved physical model capturing NQS effects in the
millimeter wave band [14], [15]. c) Modeling of self heating
effect (SHE). Finally, statistical modeling i.e., IDS mismatch
in BULK-MOSFET is also discussed in this work [16].
II. E NHANCEMENT IN DC I-V M ODEL
A. Modeling gm in Strong Halo MOSFETs
Halo or pocket implants are ion-implantations angled into
the channel of a MOSFET inducing higher doping on the
source/drain edges of the channel. They are necessary to sup-
press short channel effects and enable low leakage for digital

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 NMOS 100 L=2 m 2
10
10-2 VDS=1.21V
0.2 W=2 m

|V |=1.98V

(mA)
DS
(mA)

VB=0,-275m,-550m

A)
0

A)
10
10-5 V =0, 0.45 V
B

Solid Lines :Model

(
50
0.1

DS

(
DS
DS

Symbols :Exp Data

DS
I

I
10-8
-2
I

PMOS 10

I
L=2 m W=2 m Solid Lines : Model
Symbols : Exp. Data
-11
10 0.0 0 10
-4

0.0 0.5 1.0 1.5 2.0 -2.0 -1.5 -1.0 -0.5 0.0
VGS (V) V
GS
(V)

(a) (a)

0.2 Solid Lines : Model NMOS 0.6 100

Solid Lines : Model
0.2
Symbols : Data |V
DS
|=1.98V
Symbols : Experimental Data
g'm (mA/V2)
L=2 m

g'm (mA/V2)
gm (mA/V)

75

gm (mA/V)
W=2 m V =0, 0.45V
B

VB=0, -275m, -550mV 0.3 L=2 m

gm' data
0.1 gm' data
50
this work
W=2 m 0.1
VDS=1.21V
old model old model
this work 25

0.0 PMOS

0.0 0 0.0
0.0 0.5 1.0 1.5 2.0 -2.0 -1.5 -1.0 -0.5 0.0
VGS (V) V
GS
(V)

(b) (b)

Fig. 2: Anomalous gm behavior of halo implanted at different Fig. 3: Anomalous gm behavior of halo implanted at different
body biases for NMOSFET. (a) IDS −VGS (b) gm −VGS . The body biases for PMOSFET. (a) IDS − VGS (b) gm − VGS . The
proposed model successfully captures gm trends across body proposed model successfully captures gm trends across body
biases [9]. Solid Line: Model and Symbol: Measured data biases [9]. Solid Line: Model and Symbol: Measured data

circuit blocks [10], [17]. We have modeled the anomalous

gm trends by representing the channel and the drain side
halo region by a single BSIM-BULK MOSFET, and other
bias dependent element is used for source side halo region
of length L = LH [9]. It is clearly evident in Fig. 2(b) and

Fig. 3(b) that gm and gm of both NMOS and PMOS exhibit a
slope change. It is due to the fact that for low gate voltages,
effective length of a device is determined by the length of halo
region (LH ). However, for high VGS values, channel region
of length L − 2LH controls the conduction [9]. Also, it is
shown in Fig. 2(b) and Fig. 3(b) that new model shows a good
agreement with the measured data for both NMOS and PMOS
devices. The old conventional model, however, cannot model
these anomalous trends of gm in strong halo pocket devices.
B. Modeling of Zero VT H Native Devices
Growing demand of high performance devices with low
power consumption leads to the evolution of zero thresh-
old voltage MOS structures. These type of devices exhibit
a higher gm /COX peak, as compared to the conventional
bulk MOSFET structures. They have been used for a lot
of applications like RF and analog applications, high speed
circuits, voltage regulators, multiplexers, input/output circuits
input buffer circuits etc [10], [12]. We have implemented a
computationally efficient compact model for circuit design in
BSIM-BULK, which can account correct behavior of punch-
through leakage current, caused due to low channel doping
in zero-VT H MOSFET devices. It is clearly illustrated in
Fig. 4(a) that the proposed model successfully captures the
leakage current in the sub-threshold region for high VDS ,
but the existing BSIM-BULK model is unable to model the
current trend, as shown by blue dotted line. Fig. 4(b) shows
that the IDS of zero VT H device increases linearly with VDS
especially for low VGS values. This is because the lower gate
voltages lead to weak gate control, and hence, native devices
experience more impact of punch through effect. However,
new model shows a decent match with measured data. Fig. 5(a)
and Fig. 5(b) on the other hand, show the model validation for
the sub-surface leakage current component in the accumulation
region for different VDS values and temperatures, respectively
for nMOSFET with the gate length of 60 nm [12]. Please note

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 -4
10
L = 60 nm, W = 1 m
VBS=0V
-6
10
VDS increases V = 0.1, 0.5, 1 V

(a.u.)
(a.u.)

DS

(A)
-8
10

DS
DS

-10

I
10

DS
L=0.3um W=10um
I

I
-12
10
V = 0 V
BS

-14
10

VGS (a.u.)
-3 -2 -1 0 1

V (V)
GS

(a) (a)

VBS=0V
-4

L=0.3um W=10um 10
L = 60 nm, W = 1 m
-6
10
(a.u.)

VGS increases
(A)
-8 T = 300, 350, 375 K
10

DS
DS

I
-10
10
I

-12
10 V = 0 V
BS

-14
10

VDS (a.u.) -3 -2
V
-1

GS
(V)
0 1

(b)
Fig. 4: Measurement verification of proposed model for punch-
through leakage in weak inversion region: (a) IDS − VGS
characteristics for zero VT H nMOSFET for different VDS (0.1,
0.5, 1 V) and VSB = 0V . (b) IDS −VDS characteristics for low
VGS values [10]. Solid Line: Model and Symbol: Measured
data
(b)
Fig. 5: Measurement verification of proposed model for sub-
surface leakage in the accumulation region: (a) IDS − VGS
characteristics for zero VT H nMOSFET for different VDS (0.1,
0.5, 1 V) and VSB = 0V . (b) IDS − VGS characteristics for
different temperatures [12]. Solid Line: Model and Symbol:
TCAD data

that the operating point threshold voltage of MOSFET can be
directly extracted in BSIM-BULK [4], [18].
C. EDGEFET Model
With rapid decreasing of the feature size, it becomes desir-
able to use the shallow trench isolation (STI) over the LOCOS
bird’s peak process [19], [20]. However, the inner fringing
gate field lines associated with the STI device terminate on
the charges present in the STI edges (corners), leading to
the formation of inversion charge layer near the STI edges.
It is very important to model its effect in BSIM-BULK,
since the presence of this parasitic current will impact a key
figures of merit like gm /IDS , gm etc. We have modeled it by
adding the parasitic edge current (Iedge ) with the main channel
current [19], [21]. Also, we have validated our model for Iedge
with the measured IDS versus VGS data at VDS = 50mV
across body bias. It is evident from Fig. 6(a) and Fig. 6(b)
that the new model, which is implemented in BSIM-BULK,
excellently matches with the measured current as well as its
3rd derivative for SA = SB = 2.034 μm (where, SA, SB
represent the distances between isolation edge to Poly from
one and the other side, respectively) data for different body
bias. Fig. 7(a) and Fig. 7(b) on the other hand, show the model
validation with the measured data for SA = SB = 657 nm.
Please note that to increase the further fitting flexibility of
Iedge model, we have considered the mechanical stress effects
in EDGEFET model too (in Iedge ).
D. Bulk Charge Model
The analytical model to capture the variation of bulk charge
along the lateral direction (from source side to the drain
side) for VDS = 0 is not taken into the consideration in the
unified-core models. As a result, these models overestimate the
inversion charge density, and hence, exhibits larger channel
current. So, the transconductance (gm ), output conductance
(gds ), and capacitances of a long channel MOSFET in the
saturation region as predicted by these compact models show
a slight deviation from measured results. Though these de-
viations do not affect the accuracy significantly, rectifying
them is crucial for harmonic distortion simulations needed for

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 VDS = 50 mV
Hump

(a.u)
(a.u)
(a.u)

(a.u)
Hump
DS

DS

DS
DS
VDS= 50 mV
I

I
I
VBS= 0 to -3 V VBS = 0 to -3 V
0 1 2 3 4 5 0 1 2 3 4 5
VGS(V) VGS(V)
(a) (a)

VDS= 50 mV VDS = 50 mV

d3IDS/dVGS3(a.u)
d3IDS/dVGS3(a.u)

Hump Hump
VBS= 0 to -3 V VBS = 0 to -3 V

0 1 2 3
VGS(V)
(b)
Fig. 6: Accurate modeling of parasitic STI effect: Comparison
of the EDGEFET model with measured data for the long
channel length MOSFET. (a) IDS vs VGS (b) 3rd derivative
of IDS at VDS = 50mV across body bias for SA = SB =
2.034 μm. Solid: Model, Symbols: measured data.
RF applications. To overcome this issue, the analytical model
of bulk charge effect in-line with BSIM4 has been added in
the BSIM-BULK for both DC and capacitance modules. It
is evident from Fig. 8(a) that the model without Abulk, a
parameter representing the bulk charge effect in current and
capacitances [2], cannot give a good fit, whereas our proposed
model, which has been implemented in BSIM-BULK shows
the drastic improvement in the gds fitting. Whereas, Fig. 8(b)
shows the validation of CGG versus VGS trends with the
TCAD data, it can be seen that for the high gate and drain
bias, the model without this new model cannot give a good
fit. However, BSIM-BULK with Abulk model exhibits a large
amount of improvement in the CGG fitting.
III. E NHANCEMENT IN N OISE AND RF M ODELS
A. Flicker Noise Model for Halo Implanted MOSFETs
Strong halo implants have been found to degrade the 1/f
noise of device, particularly for a long channel devices. The
peculiar 1/f noise behavior is attributed to extra trap states
being formed due to implantation process [13], [22]. As a
result, noise behavior in strong halo pocket devices is very
different as compared to the uniformly doped devices, and
4 5 0 1 2 3 4 5
VGS(V)
(b)
Fig. 7: Accurate modeling of parasitic STI effect: Comparison
of the EDGEFET model with measured data for the long
channel length MOSFET. (a) IDS vs VGS (b) 3rd derivative
of IDS at VDS = 50mV across body bias for SA = SB = 657
nm. Solid: Model, Symbols: measured data.
hence, the existing conventional compact models for 1/f noise
for uniformly doped devices are no longer valid for halo pocket
devices [13]. Here, we have used the impedance field theory
based compact model to capture the anomalous trends of 1/f
noise [13], [23], which is also included in BSIM-BULK model.
Here, we consider two transistors in series i.e., one for source
halo and another for both channel and drain halo regions.
Total drain current noise power spectral density (PSD) for halo
implanted MOSFETs is [13]:
 2
gm,ch + gd,ch
SID =SID,h ·
gm,ch + gd,ch + gd,h
 2
gd,h
+ SID,ch · (1)
gm,ch + gd,ch + gd,h
where nq , μ, Cox , and Vt are the slope factor, effective
mobility, oxide capacitance per unit area and thermal voltage
respectively. Whereas, qs,ch , qd,ch , qs,h and qd,h are the
normalized inversion charge densities at the source and drain
ends of channel and halo transistor, respectively. Fig. 9(a)

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 (a)
(b)
Fig. 8: Effect of the Abulk model: (a) gds versus VDS
validation of new Abulk model against experimental data for
L = 1-μm and W=10-μm NMOSFET at VBS = 0.0 V and VGS
= 0.4, 0.8, 1.2 V (b) Model validation with the TCAD data
for CGG versus VGS . Solid Lines: Model including Abulk,
Dashed Lines: Model without Abulk and Symbol: Data.
shows the model data overlay for long and short channel
MOSFETs. But, the conventional models of 1/f noise already
existing in literature cannot capture the desired trends, as
already demonstrated in Fig. 9(a). Also, Fig. 9(b) illustrates the
model comparison with the measured data of a long channel
halo implanted MOSFET for different technology node.
B. Non-Quasi-Static Effect
The accurate modeling of NQS is very essential, in order
to suppress the higher order harmonics while deigning power
amplifiers, and to avoid the overestimation of transistor power
gain in RF circuits [14]. We propose and implement an
accurate and computationally efficient transmission line based
improved physical equivalent circuit model for NQS in BSIM-
BULK, to capture the NQS effects [14], [15]. The model is
applicable for a high frequency small signal analyses and for
large signal transient too. Fig. 10(a) and Fig. 10(b) prove
the accuracy of our proposed NQS model, by capturing the
significant NQS effects in Real(Y12 ) and Real(Y21 ) up to the
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(a)
(b)
Fig. 9: IDS 1/f noise PSD vs IDS at VDS = 0.55V ,
normalized to W. The proposed model successfully captures
SID trends. The conventional compact models for flicker
noise valid for uniformly doped MOSFET, can not capture a
typical low frequency behavior especially for a long channel
MOSFET [13]. Solid: Model, Symbols: measured data.
frequency range of 100 GHz with both TCAD and measured
data, however, the existing NQS models cannot fit the TCAD
data for a very high frequency range. At high frequency the
substrate network dominates over the gate network, and it
leads to a dip in both Real(Y12 ) and Real(Y21 ) (right dip), as
shown in Fig. 10(a) and Fig. 10(b). Furthermore, the left dip in
Real(Y21 ) is due to a gm term in Real(Y21 ) expression [14].
Fig. 11, on the other hand, shows the terminal currents ID and
IS of MOSFET and are validated using the proposed model.
It is evident, QS model with charge partitioning drain/source
ratios of 0/100; 50/50 and 40/60 cannot capture the transient
behavior. However, new NQS model shows a satisfactory
fitting even for dVG /dt = 5X1010 V /s.
C. Self Heating Effect (SHE)
As far as RF performance of MOSFETs is concerned, it
is severely affected by SHE, since gds changes significantly
with SHE. Therefore, for the RF circuit simulations it is
very important to accurately model the effect of SHE in the
compact model. In BSIM-BULK model, the self-heating effect
 1000
1000 420

102 400

101 950

A)
900 380

T(K)
360

(
DS
TCAD

I
1
New NQS Model 10-1
800
VDS= 1.2 V 340
10

( A)
900
Real (Y12) [mS]

VGS= 1.2 V

Real (Y21) [mS]

320
1st Order Model 700 300
10-Segmented 10-3 0.0 0.3 0.6 0.9 1.2
RTH(ohm*m*K/W)

DS
100 L=2 m Wf=5 m Nf=10 850

I
Vgs=Vds=1.5V 10 -5
IDS from SHE
10-7 800 IDS from sweeping of T
10-1
but SHE = 0
10-9
750
300 320 340 360 380 400 420
10-2 10-11
109 1010 1011 T(K)
Frequency (Hz) (a)
(a) 800
-1
10
10-2 600
-2
10 Measured data
Real (Y21) [mS]
Real (Y12) [mS]

( A)
This work
1st order NQS model
10-4
10-3 400
10-segmented model DS

10-6 Solid: SHE = 0

I

10-4
Dashed: SHE = 1
200
10-8
10-5 L=2 m Wf=5 m
10-6
Nf=10 10-10
Vgs=0.9V,Vds=0.8V 0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
10 -7
10 -12
VDS(V)
108 109 1010
Frequency (Hz) (b)
Fig. 12: (a) Benchmark test for Self heating model: Compari-
(b)
Fig. 10: Measurement verification of proposed model for son of drain current from two different approaches. Inset plot
Real(Y12 ) (Left Y-axis) and Real(Y21 ) (Right Y-axis): (a) variation of temperature and current with thermal resistance,
with TCAD data. (b) with measured data. The BSIM-BULK when self heating model is on. (b) Effect of self heating on
NQS model and 10-segmented model fail at high frequency drain current. Inset figure is the RC thermal network. Self
region [14], [15]. Solid: Model, Symbols: data. heating effect is proactive mainly at high power [5].

is modeled by employing a standard auxiliary R—C thermal

40 network, as shown in the inset of Fig. 12(b), where RT H
Solid : ID and CT H are thermal resistance and capacitance, respectively.
30 In order to check the accuracy of SHE model a self heating
Dotted : -IS benchmark test has been done. With the self heating module
I ,-I (mA)

20
enabled and for the fixed drain and gate biases, the thermal
S

resistance (RT H ) is swept. The total channel temperature and

D

drain current are then observed. It can be clearly seen in

10 L=2 m W=50 m the inset of Fig. 12(a) that the channel temperature increases,
:TCAD whereas the IDS decreases with the increase in RT H . Further,
RED :New NQS model
0 GREEN : QS (40/60)
the self-heating is disabled, and under the same biasing con-
: QS (0/100) dition, the channel current is evaluated for the same ambient
NMOS
BLUE
ORANGE : QS (50/50)
temperatures, as obtained from SHE model. Then, ideally for
-10
a good SHE model, both the channel currents, obtained from
0.0 0.2 different approaches should be the same, this is what we have
Time(nSec)
shown in Fig. 12(a). This, confirms the accuracy of our model.
Fig. 11: Drain and source terminal currents for gate switching
Fig. 12(b), on the other hand, shows the effect of SHE on
from 0 to 5V at a rate of 5X1010 V /s [14].
the IDS − VDS characteristics. Inset of Fig. 12(b), shows the
thermal network to capture the SHE on the channel current.

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 10-1
L=1 mW=1 m

D/ D
-2
VDS = 0.1 V VBS = 0 V L=1 mW=1 m
10
VDS = 1.2 V
D D
/

Normalized
-3
10

Calibrated TCAD
Our proposed model VBS = -0.6 and 0 V
10-4 Conv. model to fit WI region
Conv. to fit SI linear region Solid Lines : Model
Symbols : Measured Data
10-5
0.2 0.4 0.6 0.8 1.0 1.2 0.2 0.4 0.6 0.8 1.0 1.2
VGS(V) VGS(V)
(a) (a)

VGS = 0.6 V
Solid Lines : Model
VGS = 0.8 V
10-3 Symbols : Measured Data

D/ D
VGS = 1.1 V

T = 155, 27, -55 oC

D D

Normalized
/

L = 5 m W = 0.12 m VBS = 0 V
VDS = 1.2 V
-4
10
VBS = 0 V L=1 mW=1 m

10-1 100 0.2 0.4 0.6 0.8 1.0 1.2

VDS(V) VGS(V)
(b) (b)
Fig. 13: (a) σI2DS /IDS
2
versus VGS for a long channel halo de- Fig. 14: (a) σI2DS /IDS
2
versus VGS for a long channel halo
vice. (b) σI2DS /IDS
2
versus VDS . The proposed model success- device across Vds . (b) σI2DS /IDS
2
versus VGS across temper-
fully captures σI2DS /IDS2
trends. The conventional compact ature. The proposed model successfully captures σI2DS /IDS
2

models for IDS mismatch, can not capture a typical σIDS /IDS trends. The conventional compact models for IDS mismatch,
behavior [16]. Solid: Model, Symbols: data. can not capture a typical σIDS /IDS behavior [16]. Solid:
Model, Symbols: measured data

The power dissipation (PDiss ) in the inset of Fig. 12(b) is

given by:
V 2 (d, di) V 2 (si, s)
PDiss = IDS · V (di, si) + + (2)
RDRAIN RSOU RCE
IV. S TATISTICAL M ODELING IN BSIM-BULK
The halo-implanted devices are often used in mixed-signal
SoC applications that require the co-integration of analog
blocks with digital IPs that are also sensitive to low leakages
[16]. For the design teams to make the right decisions on
appropriate component selection for their applications, it is
important to have accurate models for degraded IDS mismatch
behaviors [16]. Presence of high doped halo regions in the de-
vice employs to a higher random-dopant fluctuations (RDFs),
that in turn results into a higher drain current mismatch.
The drain current mismatch is typically characterized by
taking the normalized standard deviation of the difference in
IDS between two devices placed in close local proximity.
σIDS /IDS is referred as the IDS mismatch or the standard
deviation of the drain current, and (σIDS /IDS )2 = σI2DS /IDS
2
is called the normalized mismatch power [16]. An analytical
model for the drain current mismatch in halo doped devices
is proposed and implemented in the compact model of BSIM-
BULK. The model is impedance field method based, that can
successfully capture the bias and temperature dependences
of matching that are critical to the analog and mixed-signal
circuit design applications [16], [24]. Fig. 13(a) shows the
model validation with the calibrated TCAD data (symbols)
for the mismatch power versus VGS at VDS = 0.1. As shown
in Fig. 13(a) that weak inversion (WI) and strong inversion
(SI) regions cannot be captured simultaneously using a single
definition of VT H based conventional model. The proposed
model, on the other hand shows a good agreement with the
TCAD data. Fig. 13(b) shows the model validation with the
measured data across VDS , here also our model excellently
matches with the data. Fig. 14(a) and Fig. 14(b) illustrate the
model validation with the measured data across Vds and T .
However for L < 2LH the device can be treated as a UD
device since the halo pockets merge together. Hence, our IF

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 based proposed model indeed reduces to the UD model.
V. C ONCLUSION
The recent and upcoming enhancements of BSIM-BULK, a
physics based and computationally efficient industry standard
model, verified for many and up to the most advanced bulk
technology nodes, are presented in this work. To capture the
variation of bulk charge in the lateral direction due to VDS , we
have implemented a new model for the bulk charge effect in
BSIM-BULK. Also, to get accurate circuit simulation results,
the models for leakage current in shallow trench isolation
(STI) as well as zero VT H MOSFETs are included. Further,
an improved equivalent circuit model, capturing NQS effects
up to the millimeter wave regime, as well as a model to
capture self heating effect has been incorporated in BSIM-
BULK. Finally, the anomalous gm , low frequency noise and
IDS mismatch trends, which are attributed to strong halo
implants, have also been included in the BSIM-BULK model
to further increase its precision in circuit design applications.
All the models show excellent matching with the data for each
region of operation, and will be available in a future release
of BSIM-BULK.
VI. ACKNOWLEDGMENT
This work was partially supported by Department of Science
and Technology and Indian Space Research Organisation.
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