High-Speed Serial Interface

Circuits and Systems

Design Exercise4 –
Charge Pump

High-Speed Circuits and Systems Lab., Yonsei University

 Charge Pump PLL

ɸref up
ɸout
PFD down CP LF VCO

ɸdiv
Divider

– Converts PFD phase error pulse (digital) to charge (analog).

– Charge is proportional to PFD pulse widths.
• Qcp = Iup * tup – Idown * tdown
– Qcp is filtered and integrated in low-pass filter.

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 Review of Charge Pump PLL

3 High-Speed Circuits and Systems Lab., Yonsei University

 Basic Charge Pump
Vdd Vdd

Pbias M2

UP
M4
Vcont Vcont

DOWN
M3

Nbias M1

– Charge pump circuit consists of 2 current sources and 2 switches.

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 Current Mismatch
Vdd

UP
Pbias M2

DOWN
UP UP
A M4
IM3
Vcont
PFD
B
DOWN IM4
M3
Net
Current
Nbias M1 Vcont
t

– Up & down current should be same.

– Current mismatch results in static phase offset, which results in
periodic ripple on the control voltage.
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 Current Mismatch Vdd
– Vcont is changed according to locking voltage.
– Current mismatch is caused by channel length modulation. Pbias M2

– Equal nmos and pmos current over entire Vcont range.

UP
M4
• Reduce phase error. Vcont

Drain Source
DOWN
M3
Gate Gate
nbias Pbias
Nbias M1
Source Drain

ID ID ID

200uA

Channel length Channel length

modulation modulation

VDS VDS Vdd/2 VDS

Available region

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 Basic CP Simulation
– PMOS size (2개 동일)
• Length : 180 nm
• Width : 5.2 um
– NMOS size (2개 동일)
• Length : 800 nm
• Width : 5.1 um
Current
– Nbias Monitor
• Voltage : 0.9 V
– Pbias
• Voltage : 0.9 V
– Target charge pump current
• Current : 200 uA

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 Simulation Condition
• Simulation condition setting
– Choose analysis
– Analysis : DC
– Design variable : cont
– Sweep range : 0 ~ 1.8
• Sweep type : Linear
• Step size : 0.1
– Enabled check
– OK

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 Simulation Results
• Plot simulation results (Current)
– Results → Direct Plot → Main Form
– Function : current
– Select : terminal
– Add to outputs check
– Schematic node choice
• DC symbol (+) node click
– OK

9 High-Speed Circuits and Systems Lab., Yonsei University

 NMOS Current
Vdd

Pbias M2 ID

Vcont (0.9V) Vcont (1.8V)

1.8V UP
M4 : 199.94uA : 200.94uA
(OFF)
Vcont

∆ ID: 1.09uA
1.8V DOWN
M3
(ON)

Nbias M1 Vcont

10 High-Speed Circuits and Systems Lab., Yonsei University

 PMOS Current
Vdd

Pbias M2 ID

0V UP Vcont (0V) Vcont (0.9V)

M4 : 204.30uA : 199.45uA
(ON)
Vcont

∆ ID: 5.38uA
0V DOWN
M3
(OFF)

Nbias M1
Vcont

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 NMOS & PMOS Current

Vdd

ID
Pbias M2
PMOS current NMOS current

0V UP
M4
(ON) Vcont : 0.5V
Vcont
∆ ID: 15uA
1.8V DOWN Vcont : 0.9V
M3
(ON) ∆ ID: 0.5uA
Vcont : 1.3V
Nbias M1 ∆ ID: 23uA Vcont

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 PMOS – NMOS Current
Vdd

Pbias M2
Icont
NMOS
0V UP current ↑
M4 Vcont : 0.5V
(ON) Icont: 15uA
Vcont

Vcont : 0.9V
1.8V DOWN PMOS
M3 Icont: 0.5uA
(ON) current ↑ Vcont : 1.3V
Icont: 23uA
Nbias M1 Vcont

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 Leakage Current
Vdd

Icont
Pbias M2
Vcont : 0.5V
Icont: 11.5pA NMOS
1.8V UP leakage ↑
M4 Vcont : 0.9V
(OFF) Icont: 3.8pA
Vcont

0V DOWN PMOS
M3
(OFF) leakage ↑
Vcont : 1.3V
Icont: -2.2pA
Nbias M1
Vcont

14 High-Speed Circuits and Systems Lab., Yonsei University

Reducing Mismatch using Replica
Replica Circuit
Vdd

Pbias
Mp1 Mp1

AMP
Vss UP
Mp2 Mp2

+
-
Cont

Mn1 Vdd DOWN Mn1

Nbias
Mn2 Mn2

Vss
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 Design Example
✓ Charge pump circuit
- Supply voltage: 1.8V
- Current of charge pump: 200uA ± 10uA
- Current mismatch: <150nA with range of Vcont larger than 0.8V

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 Simulation Schematic
– VCVS (OpAmp)
• Voltage gain : 1000
• Maximum output
voltage :1.8V
• Minimum output voltage : 0V

– RC Filter of OpAmp
• Resistor : 1Kohm
• Capacitance : 1nF

– Replica circuit
• Charge pump size same

– Load
• Capacitance : 200pF

– Nbias
• Voltage : 0.9V

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 NMOS Current

Vdd

Pbias
Mp1 Mp1 ID

1.8V UP
AMP

Mp2 Vss Mp2

+

(OFF)
-

Cont

Vdd
1.8VDOWN
Mn1 (ON) Mn1

Nbias
Mn2 Mn2
Vcont
Vss

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 PMOS Current

Vdd

Pbias
Mp1 Mp1 ID
Without FB With FB
0V UP
AMP

Mp2 Vss Mp2

+

(ON)
-

Cont

Vdd
0V DOWN
Mn1 (OFF) Mn1

Nbias
Mn2 Mn2
Vcont
Vss

– Change PMOS current though the feedback.

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 NMOS & PMOS Current

Vdd

ID
Pbias NMOS current
Mp1 Mp1
PMOS current

0V UP
AMP

Mp2 Vss Mp2

+

(ON)
-

Cont

Vdd
1.8V DOWN Vcont : 0.9V
Mn1 (ON) Mn1
∆ ID: 0.03uA
Vcont : 0.5V Vcont : 1.3V
Nbias
Mn2 Mn2 ∆ ID: 0.09uA ∆ ID: 0.12uA
Vcont
Vss

– NMOS and PMOS currents are equalized through the feedback system.

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 NMOS – PMOS Current

Vdd

Pbias
Mp1 Mp1 Icont

0V UP Without FB
AMP

Mp2 Vss Mp2

+

(ON)
-

Cont With FB

Vdd
1.8V DOWN Vcont : 0.9V
Mn1 (ON) Mn1
Icont: 0.03uA
Vcont : 0.5V Vcont : 1.3V
Nbias
Mn2 Mn2 Icont: 0.08uA Icont: 0.12uA
Vcont
Vss

– NMOS and PMOS currents are equalized through the feedback system.

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 Homework
✓ Design 500uA (±20uA) charge pump with replica circuit.

✓ Without replica circuit, verify and plot pmos and nmos current waveforms with
respect to cont voltage.
– Current mismatch : less than 60uA (cont voltage range : 0.5V ~ 1.3V)

✓ With replica circuit, verify and plot pmos and nmos current waveforms with
respect to cont voltage.
– Current mismatch : less than 400nA (cont voltage range : 0.5V ~ 1.3V)

✓ Charge pump specification

– VDD supply voltage : 1.8V
– Nbias voltage : 0.9V
– Charge pump current : 500uA (±20uA) at nbias voltage 0.9V

✓ Due: Next design class (Hardcopy)

22 High-Speed Circuits and Systems Lab., Yonsei University