A B C D E

MODEL NAME : QBLB0

PCB NO : LA-8381P
BOM P/N : 4319H631L01 (Samsung 1G)
4319H631L02(Samsung 2G)
1 4319H631L03(Hynix 1G) 1

4319H631L04(Hynix 2G)

Dell/Compal Confidential
2
Schematic Document 2

Specter MLK (Chief River)

Ivy Bridge(PGA) + Panther Point(standard)
DISCRETE VGA N13P-GT (optimus)
2011-10-26
3
Rev: X01 3

Highlight the short pad for 0 ohm

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 1 of 63
A B C D E
 A B C D E

Compal Confidential VRAM x 8 CPU XDP

GDDR5 64Mb*16 x8 =1GB FFS Fan Control
P.45 P.43 Conn. P.6
Project Code : QBLB0 Page 27, 28, 29, 30 128Mb*16 x8 =2GB

File Name : LA-8381P

Intel
PEGx16 Ivy Bridge
1
Nvidia Memory Bus (DDRIII) 204pin DDRIII SO-DIMM x2
1

N13P-GT Processor Dual Channel BANK 0, 1, 2, 3 Page 12, 13

4C 45W
DP(DIS) 2C 35W 1.5V DDRIII 1333/1600 MHz
Page 22, 23, 24, 25, 26
rPGA 989 Socket
Page 6, 7, 8, 9, 10, 11

LVDS SATA ODD Conn.

FDI x2 DMI x4 P.45
Conn. P.33 100MHz 100MHz SATA
2.7GT/s 5GT/s SATA HDD Conn.
HDMI Redriver P.45 P.45
HDMI v1.14a SIM Card P.38
Conn. P.36 Re-Driver P.36 LVDS SATA2.0
HDMI SATA3.0 SATA
RedriverP.38 MUX Mini Card (Full)
CRT CRT # mSATA
PCI-E 2.0 P.38
Conn. P.34 # WWAN
DP v1.2
USB2.0 # DMC(DP or HDMI)
2 miniDP Redriver P.35 2

Conn. P.35 Intel Mini Card (Half)

DP v1.1 Panther Point USB 2.0 Conn. x1 WLAN
DP ( USB Charger ) P.43
Re-Driver P.37
PCH DMC/Daughter Board P.38
Digital Camera P.33

PCI-E 2.0 AlienFX/ELC P.48, 49, 50

BGA 989 Balls VPK P.46

Mini Card (Full) Mini Card LAN(GbE) Card Reader BT 4.0 P.38
# mSATA
# WWAN (Half) AR8151-BL1A RTS5209
# DMC(DP or HDMI) WLAN P.39 P.40 USB3.0 USB 3.0
Combo Conn. x2 P.44
Page 14, 15, 16, 17, 18, 19, 20, 21

DMC/Daughter Board P.38 RJ45 P.39 9 in 1

Socket P.40 SPI HD Audio
Audio Codec Malcolm-EX
3 LPC Bus P.41 TPA6211A P.42
3

# : Choose ONE from three.

SPI ROM ENE 3810 ENE KB930 TI TPA6017A2 P.42 sub-woofer conn. P.42
RTC conn. 64Mbit P.14 P.47 P.47
P.52
P.41, 42
Int. Speaker Audio Jack x3
P.42 ( Combo Jack x1, HP x1, MIC x1)
Power On/Off CKT.
P.46 BIOS ROM
Touch Pad Int.KBD
P.49 P.46 1Mbit P.47
DC/DC Interface CKT. Power Circuit DC/DC Digital MIC P.42
P.32 P.51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/02/23 Deciphered Date 2012/02/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 2 of 63
A B C D E
 A B C D E

Compal Confidential
Project Code : QBLB0
File Name : LA-8381P
LA-8381P M/B
Camera
1 1

40 pin LCD Panel

Wire

Blue Tooth

Wire
LS-8382P 12 pin
80 pin
BTB conn.
LS-8384P
INDICATOR/B HDD
Wire Wire
Led-Wireless
6 pin WLAN WWAN/DMC 20 pin
Led-CapsLock
DMC/B
14 pin ODD
2 2

LS-8381P
FPC
FFC Wire FFC
20 pin
6 pin 12 pin
LS-8383P
LS-8388P LS-8385P
TP LED/B
Touch Pad FFC Led x 6
LOGO LIGHT GUIDE/B POWER BUTTON/B
4 pin on/off SW
Lid Led x 6 Led x 3

4 pin 4 pin
Wire Wire
LS-8386P LS-8387P

FRONT LIGHT L/B FRONT LIGHT R/B

3 3

Led x 2 Led x 2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 12, 2012 Sheet 3 of 63
A B C D E
 A B C D E

+3V_PCH

+3VS

2.2K 2.2K

2.2K
1 1

2.2K
SMBUS Address [0x9a]

+3VS
H14 SMBCLK PCH_SMBCLK 202
SMBDATA DMN66D0 PCH_SMBDATA SMBUS Address [A0]
C9 200 DIMMA
DMN66D0
202
+3V_PCH 200 DIMMB SMBUS Address [A0]

30
PCH
32 G Sensor
SMBUS Address [TBD]
2.2K 2.2K

XDP SMBUS Address [TBD]

C8 SML0CLK 30
SML0DATA 32 WLAN SMBUS Address [TBD]
G12

M16 E14
SML1CLK 2.2K
2 mSATA/ WWAN/ DMC SMBUS Address [TBD] 2

SML1DATA
+3V_PCH
2.2K

Power
DMN66D0 DMN66D0 +3VS
Thermal

EC_SMB_CK2 8.2K F8 Thermal

EC_SMB_DA2 +3VS
8.2K B8 Thermal
+3VSDGPU
A6 B8

TS3A225E
76/78
HP detect

2.2K
2.2K
EC_SMB_CK2
EC_SMB_DA2 VPK +3V_GPU
I2CS_SCL D9
DMN66D0 GPU
I2CS_SDA D8 SMBUS Address [0x9E]
3 KBC DMN66D0
3

+3VSDGPU

2.2K
2.2K
+3V_GPU
EC_SMB_CK2_PX
DMN66D0 GPU_Thermal
EC_SMB_DA2_PX
DMN66D0

A8 EC_SMB_CK1 100 ohm 4

A7 EC_SMB_DA1 100 ohm 5 BATTERY SMBUS Address [TBD]
CONN

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 12, 2012 Sheet 4 of 63
A B C D E
 A

Vcc 3.3V +/- 5% USB PORT# DESTINATION

Board ID Table for AD channel BOARD ID Table
Ra 100K +/- 5%
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max EC AD3 Board ID PCB Revision 0 JUSB2 (v3.0 Ext Right Side)
0 0 0 V 0 V 0.155 V 0x00-0x0C 0
1 8.2K +/- 5% 0.168 V 0.250 V 0.362 V 0x0D-0x1C 1 1 JUSB3 (v3.0 Ext Right side)
2 18K +/- 5% 0.375 V 0.503 V 0.621 V 0x1D-0x30 2
3 33K +/- 5% 0.634 V 0.819 V 0.945 V 0x31-0x49 3 2 None
4 56K +/- 5% 0.958 V 1.185 V 1.359 V 0x4A-0x69 4 SSI_X00
5 100K +/- 5% 1.372 V 1.650 V 1.838 V 0x6A-0x8E 5 PT_X01 3 None
6 200K +/- 5% 1.851 V 2.200 V 2.420 V 0x8F-0xBB 6 ST_X02
7 NC 2.433 V 3.300 V 3.300 V 0xBC-0xFF 7 QT_A00 4 JMINI1 (WLAN)
PCH
5 JMINI2 (WWAN/DMC)

6 ELC 8051
SMBUS Control Table
MINI1 MINI2 Thermal Thermal VGA Thermal 7 None
SOURCE (WLAN) (DMC) BATT SODIMM Sensor 1 Sensor 2 FFS Sensor VGA XDP Charger HP detect

8 Bluetooth
EC_SMB_CK1
EC_SMB_DA1
KB930
V
9 JUSB1 (2.0 Ext Left Side)
EC_SMB_CK2
EC_SMB_DA2
KB930 V V V V V V
10 None
PCH_SML0CLK PCH Link
PCH_SML0DATA
11 None
PCH_SML1CLK PCH
PCH_SML1DATA
12 CAMERA
MEM_SMBCLK
MEM_SMBDATA
PCH V V V V V
13 VPK
PM TABLE
+5VS
+3VS PCI EXPRESS DESTINATION
+1.8VS
POWER STATES power
1 plane +1.5VS Lane 1 10/100/1G LAN 1

Signal SLP SLP SLP S4 SLP ALWAYS SUS RUN +1.5V_CPU_VDDQ

S3# S4# S5# STATE# M# PLANE PLANE PLANE CLOCKS +5VALW
State +VCCP = +1.05VS
Lane 2 MINI CARD-2 WWAN/DMC
+3VALW
+1.5V +VCC_CORE
+3VLP
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH HIGH ON ON ON ON +VCC_GFXCORE_AXG
Lane 3 MINI CARD-1 WLAN
State +3V_PCH
+VCCSA
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH LOW ON ON OFF OFF +0.75VS Lane 4 CARD READER
+3VSDGPU
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW LOW ON OFF OFF OFF +1.5VSDGPU
Lane 5 None
+VGA_CORE
S0
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW LOW ON OFF OFF OFF
Lane 6 None
ON ON ON
S3
Lane 7 None
ON ON OFF

S5 S4/AC Lane 8 None

ON OFF OFF

DIFFERENTIAL DESTINATION S5 S4/AC don't exist OFF OFF OFF

CLKOUT_PCIE0 None SATA DESTINATION

CLKOUT_PCIE1 10/100/1G LAN CLKOUT DESTINATION SATA0 HDD

CLKOUT_PCIE2 MINI CARD-2 WWAN PCI0 PCH_LOOPBACK SATA1 m-SATA

Symbol Note :
CLK CLKOUT_PCIE3 MINI CARD-1 WLAN PCI1 EC LPC SATA2 ODD

CLKOUT_PCIE4 CARD READER FLEX CLOCKS DESTINATION

: means Digital Ground PCI2 None SATA3 None

CLKOUT_PCIE5 None CLKOUTFLEX0 None : means Analog Ground PCI3 None SATA4 None

CLKOUT_PCIE6 None CLKOUTFLEX1 None PCI4 None SATA5 None

CLKOUT_PCIE7 None CLKOUTFLEX2 None

Security Classification Compal Secret Data Compal Electronics, Inc.
CLKOUT_PEG_B None CLKOUTFLEX3 None Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 5 of 63
A
 5 4 3 2 1

PEG_RCOMPO (H22) R_COMP place close to CPU +VCCP

PEG_ICOMPI and RCOMPO signals should be shorted and routed
width 4 mils with - max length = 500 mils - typical impedance = 43 mohms
PEG_ICOMPI (J22) VCC_IO
PEG_ICOMPO signals should be routed with - max length = 500 mils

1
Trace length Max is 500 mils width 12 mils RC2 - typical impedance = 14.5 mohms
PEG_ICOMPO (J21) R_COMP 24.9_0402_1%

2
JCPU1A
J22 PEG_COMP
PEG_ICOMPI
J21
PEG_ICOMPO
(16) DMI_CRX_PTX_N0 B27 H22
DMI_RX#[0] PEG_RCOMPO
(16) DMI_CRX_PTX_N1 B25
DMI_RX#[1]
(16) DMI_CRX_PTX_N2 A25
DMI_RX#[2] PEG_GTX_C_HRX_N15
(16) DMI_CRX_PTX_N3 B24 K33 PEG_GTX_C_HRX_N[0..15] (22)
D DMI_RX#[3] PEG_RX#[0] PEG_GTX_C_HRX_N14 D
M35 PEG_GTX_C_HRX_P[0..15] (22)
PEG_RX#[1] PEG_GTX_C_HRX_N13
(16) DMI_CRX_PTX_P0 B28 L34
DMI_RX[0] PEG_RX#[2] PEG_GTX_C_HRX_N12
(16) DMI_CRX_PTX_P1 B26 J35 PEG_HTX_C_GRX_N[0..15] (22)
DMI_RX[1] PEG_RX#[3] PEG_GTX_C_HRX_N11
(16) DMI_CRX_PTX_P2 A24 J32 PEG_HTX_C_GRX_P[0..15] (22)
DMI_RX[2] PEG_RX#[4] PEG_GTX_C_HRX_N10
B23 H34

DMI
(16) DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5]
H31 PEG_GTX_C_HRX_N9
PEG_RX#[6] PEG_GTX_C_HRX_N8
(16) DMI_CTX_PRX_N0 G21 G33
DMI_TX#[0] PEG_RX#[7] PEG_GTX_C_HRX_N7
(16) DMI_CTX_PRX_N1 E22 G30
DMI_TX#[1] PEG_RX#[8] PEG_GTX_C_HRX_N6
(16) DMI_CTX_PRX_N2 F21 F35
DMI_TX#[2] PEG_RX#[9] PEG_GTX_C_HRX_N5
(16) DMI_CTX_PRX_N3 D21 E34
DMI_TX#[3] PEG_RX#[10] PEG_GTX_C_HRX_N4
E32
PEG_RX#[11] PEG_GTX_C_HRX_N3
(16) DMI_CTX_PRX_P0 G22 D33
DMI_TX[0] PEG_RX#[12] PEG_GTX_C_HRX_N2
(16) DMI_CTX_PRX_P1 D22 D31
DMI_TX[1] PEG_RX#[13] PEG_GTX_C_HRX_N1
(16) DMI_CTX_PRX_P2 F20 B33
DMI_TX[2] PEG_RX#[14] PEG_GTX_C_HRX_N0
(16) DMI_CTX_PRX_P3 C21 C32

PCI EXPRESS* - GRAPHICS

DMI_TX[3] PEG_RX#[15]
J33 PEG_GTX_C_HRX_P15
PEG_RX[0] PEG_GTX_C_HRX_P14
L35
PEG_RX[1] PEG_GTX_C_HRX_P13
K34
FDI_CTX_PRX_N0 PEG_RX[2] PEG_GTX_C_HRX_P12
(16) FDI_CTX_PRX_N0 A21 H35
FDI_CTX_PRX_N1 FDI0_TX#[0] PEG_RX[3] PEG_GTX_C_HRX_P11
(16) FDI_CTX_PRX_N1 H19 H32
FDI_CTX_PRX_N2 FDI0_TX#[1] PEG_RX[4] PEG_GTX_C_HRX_P10
(16) FDI_CTX_PRX_N2 E19 G34
FDI_CTX_PRX_N3 FDI0_TX#[2] PEG_RX[5] PEG_GTX_C_HRX_P9
(16) FDI_CTX_PRX_N3 F18 G31
FDI_CTX_PRX_N4 FDI0_TX#[3] PEG_RX[6] PEG_GTX_C_HRX_P8
B21 F33

Intel(R) FDI
(16) FDI_CTX_PRX_N4 FDI1_TX#[0] PEG_RX[7]
FDI_CTX_PRX_N5 C20 F30 PEG_GTX_C_HRX_P7
(16) FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8]
FDI_CTX_PRX_N6 D18 E35 PEG_GTX_C_HRX_P6
(16) FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9]
FDI_CTX_PRX_N7 E17 E33 PEG_GTX_C_HRX_P5
(16) FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10]
F32 PEG_GTX_C_HRX_P4
PEG_RX[11] PEG_GTX_C_HRX_P3
D34
FDI_CTX_PRX_P0 PEG_RX[12] PEG_GTX_C_HRX_P2
(16) FDI_CTX_PRX_P0 A22 E31
FDI_CTX_PRX_P1 FDI0_TX[0] PEG_RX[13] PEG_GTX_C_HRX_P1
(16) FDI_CTX_PRX_P1 G19 C33
FDI_CTX_PRX_P2 FDI0_TX[1] PEG_RX[14] PEG_GTX_C_HRX_P0
(16) FDI_CTX_PRX_P2 E20 B32
FDI_CTX_PRX_P3 FDI0_TX[2] PEG_RX[15]
(16) FDI_CTX_PRX_P3 G18
FDI_CTX_PRX_P4 FDI0_TX[3] PEG_HTX_GRX_N15 CC200 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N15
(16) FDI_CTX_PRX_P4 B20 M29 1 2
FDI_CTX_PRX_P5 FDI1_TX[0] PEG_TX#[0] PEG_HTX_GRX_N14 CC199 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N14
(16) FDI_CTX_PRX_P5 C19 M32 1 2
FDI_CTX_PRX_P6 FDI1_TX[1] PEG_TX#[1] PEG_HTX_GRX_N13 CC198 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N13
(16) FDI_CTX_PRX_P6 D19 M31 1 2
FDI_CTX_PRX_P7 FDI1_TX[2] PEG_TX#[2] PEG_HTX_GRX_N12 CC197 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N12
(16) FDI_CTX_PRX_P7 F17 L32 1 2
FDI1_TX[3] PEG_TX#[3] PEG_HTX_GRX_N11 CC196 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N11
C L29 1 2 C
FDI_FSYNC0 PEG_TX#[4] PEG_HTX_GRX_N10 CC195 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N10
(16) FDI_FSYNC0 J18 K31 1 2
FDI_FSYNC1 FDI0_FSYNC PEG_TX#[5] PEG_HTX_GRX_N9 CC194 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N9
(16) FDI_FSYNC1 J17 K28 1 2
FDI1_FSYNC PEG_TX#[6] PEG_HTX_GRX_N8 CC193 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N8
J30 1 2
FDI_INT PEG_TX#[7] PEG_HTX_GRX_N7 CC192 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N7
(16) FDI_INT H20 J28 1 2
FDI_INT PEG_TX#[8] PEG_HTX_GRX_N6 CC191 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N6
H29 1 2
FDI_LSYNC0 PEG_TX#[9] PEG_HTX_GRX_N5 CC190 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N5
(16) FDI_LSYNC0 J19 G27 1 2
FDI_LSYNC1 FDI0_LSYNC PEG_TX#[10] PEG_HTX_GRX_N4 CC189 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N4
(16) FDI_LSYNC1 H17 E29 1 2
+VCCP FDI1_LSYNC PEG_TX#[11] PEG_HTX_GRX_N3 CC188 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N3
F27 1 2
PEG_TX#[12] PEG_HTX_GRX_N2 CC187 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N2
D28 1 2
PEG_TX#[13] PEG_HTX_GRX_N1 CC186 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N1
F26 1 2
PEG_TX#[14] PEG_HTX_GRX_N0 CC185 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N0
E25 1 2
+EDP_COM PEG_TX#[15]
1 2 A18
RC36 24.9_0402_1% eDP_COMPIO PEG_HTX_GRX_P15 CC216 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P15
A17 M28 1 2
eDP_ICOMPO PEG_TX[0] PEG_HTX_GRX_P14 CC215 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P14
B16 M33 1 2
eDP_HPD# PEG_TX[1] PEG_HTX_GRX_P13 CC214 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P13
M30 1 2
PEG_TX[2] PEG_HTX_GRX_P12 CC213 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P12
L31 1 2
PEG_TX[3] PEG_HTX_GRX_P11 CC212 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P11
C15 L28 1 2
eDP_AUX PEG_TX[4] PEG_HTX_GRX_P10 CC211 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P10
D15 K30 1 2
eDP_AUX# PEG_TX[5] PEG_HTX_GRX_P9 CC210 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P9
K27 1 2
Trace length Max is 500 mils PEG_TX[6] PEG_HTX_GRX_P8 CC209 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P8
J29 1 2

eDP
PEG_TX[7] PEG_HTX_GRX_P7 CC208 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P7
C17 J27 1 2
eDP_TX[0] PEG_TX[8] PEG_HTX_GRX_P6 CC207 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P6
F16 H28 1 2
eDP_TX[1] PEG_TX[9] PEG_HTX_GRX_P5 CC206 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P5
C16 G28 1 2
R_COMP place close to CPU eDP_TX[2] PEG_TX[10] PEG_HTX_GRX_P4 CC205 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P4
G15 E28 1 2
eDP_TX[3] PEG_TX[11] PEG_HTX_GRX_P3 CC204 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P3
F28 1 2
width 4 mils PEG_TX[12] PEG_HTX_GRX_P2 CC203 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P2
C18 D27 1 2
eDP_COMPIO (A18) VCC_IO eDP_TX#[0] PEG_TX[13] PEG_HTX_GRX_P1 CC202 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P1
E16 E26 1 2
eDP_TX#[1] PEG_TX[14] PEG_HTX_GRX_P0 CC201 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P0
D16 D25 1 2
width 12 mils eDP_TX#[2] PEG_TX[15]
F15
eDP_ICOMPO (A17) R_COMP eDP_TX#[3]

TYCO_2013620-3_IVYBRIDGE
CONN@

XDP Connector ( Merged CPU-PCH ) B

+VCCP

+VCCP +3V_PCH +3VALW

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D
1 1
JXDP1 @ @

1
1 2 Item2_X02 Item2_X02
XDP_PREQ#_R GND0 GND1 RC27

CC67

CC66
(7) XDP_PREQ#_R 3 4
XDP_PRDY#_R OBSFN_A0 OBSFN_C0 RC9 2 2
(7) XDP_PRDY#_R 5 6 1 SHORT 2 0_0402_5%~D GPIO15 1K_0402_5%~D
OBSFN_A1 OBSFN_C1 GPIO15 (18)
7 8
XDP_BPM#0 GND2 GND3 RC10 1 SHORT 0_0402_5%~D USB_OC0#
(7) XDP_BPM#0 9 10 2

2
XDP_BPM#1 OBSDATA_A0 OBSDATA_C0 RC12 1 SHORT 0_0402_5%~D USB_OC1# USB_OC0# (17,44)
(7) XDP_BPM#1 11 12 2
OBSDATA_A1 OBSDATA_C1 USB_OC1# (17,44) SYS_PWROK_XDP
13 14
XDP_BPM#2 GND4 GND5 RC14 1 SHORT 0_0402_5%~D USB_OC2#
(7) XDP_BPM#2
XDP_BPM#3
15
OBSDATA_A2 OBSDATA_C2
16
RC16 1 SHORT
2
0_0402_5%~D 1.5VDDR_VID0 USB_OC2# (17,43) Place near JXDP1
(7) XDP_BPM#3 17 18 2
OBSDATA_A3 OBSDATA_C3 1.5VDDR_VID0 (17,55)
19 20
GND6 GND7
21 22
OBSFN_B0 OBSFN_D0
23 24
OBSFN_B1 OBSFN_D1
25 26
XDP_BPM#4 GND8 GND9 RC17 1 SHORT 0_0402_5%~D 1.5VDDR_VID1
(7) XDP_BPM#4 27 28 2
XDP_BPM#5 OBSDATA_B0 OBSDATA_D0 RC18 1 SHORT 0_0402_5%~D GPIO9 1.5VDDR_VID1 (17,55)
(7) XDP_BPM#5 29 30 2
OBSDATA_B1 OBSDATA_D1 GPIO9 (17)
31 32 Item2_X02
XDP_BPM#6 GND10 GND11 RC20 1 SHORT 0_0402_5%~D GPIO10
(7) XDP_BPM#6 33 34 2 GPIO10 (17)
XDP_BPM#7 OBSDATA_B2 OBSDATA_D2 RC21 1 SHORT 0_0402_5%~D GPIO14 XDP_TDO_C RC28 1 @
(7) XDP_BPM#7 35 36 2 GPIO14 (17) 2 0_0402_5%~D PCH_JTAG_TDO (14)
OBSDATA_B3 OBSDATA_D3 RC3 1 @
37 38 2 0_0402_5%~D
H_CPUPWRGD 1K_0402_5%~D 1 @ GND12 GND13 XDP_TDO_R (7)
(7,18) H_CPUPWRGD 2 RC22 H_CPUPWRGD_XDP 39 40 CLK_CPU_ITP CLK_CPU_ITP (15)
PWRGOOD/HOOK0 ITPCLK/HOOK4 CLK_CPU_ITP#
(16,47) PBTN_OUT# 41 42 CLK_CPU_ITP# (15)
HOOK1 ITPCLK#/HOOK5 XDP_TDI_C RC31 1 @
43 44 2 0_0402_5%~D PCH_JTAG_TDI (14)
1K_0402_5%~D 1 @ VCC_OBS_AB VCC_OBS_CD
(9) CFG0 2 RC24 XDP_HOOK2 45 46 XDP_RST#_R 1 @ 2 PLT_RST# PLT_RST# (7,17,38,39,40,47)
RC5 1 @ 2 0_0402_5%~D XDP_TDI_R (7)
0_0402_5%~D 1 SHORT SYS_PWROK_XDP HOOK2 RESET#/HOOK6 XDP_DBRESET#
(16,59) VGATE 2 RC26 47 48 RC25 1K_0402_5%~D
HOOK3 DBR#/HOOK7 XDP_DBRESET# (7,16)
49 50
GND14 GND15 XDP_TDO_C XDP_TMS_C RC29 1 @
(12,13,15,38,45) PCH_SMBDATA 51 52 2 0_0402_5%~D PCH_JTAG_TMS (14)
SDA TD0 XDP_TRST#_R RC7 1 @
(12,13,15,38,45) PCH_SMBCLK 53 54 XDP_TRST#_R (7) 2 0_0402_5%~D XDP_TMS_R (7)
0_0402_5%~D SCL TRST#
A
(14) PCH_JTAG_TCK 1 SHORT 2 RC30 XDP_TCK1 55 56 XDP_TDI_C A
XDP_TCK_R TCK1 TDI XDP_TMS_C
(7) XDP_TCK_R 57 58
TCK0 TMS
59 60
GND16 GND17
Item2_X02 SAMTE_BSH-030-01-L-D-A
CONN@

The resistor
for HOOK2 should be
placed such that the
Security Classification Compal Secret Data Compal Electronics, Inc.
stub is very small Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

on CFG0 net
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(1/6) DMI,FDI,PEG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 6 of 63
5 4 3 2 1
 5 4 3 2 1

PM, XDP, CLK, S3 Reduce, PLTRST

PU/PD for JTAG signals
+VCCP

JCPU1B
XDP_TMS_R 51_0402_5% 1 2 RC45

XDP_TDI_R 51_0402_5% 1 2 RC46

D D
A28 CLK_CPU_DMI_R RC37 1 SHORT 2 0_0402_5%~D
BCLK CLK_CPU_DMI (15)
C26 A27 CLK_CPU_DMI#_R RC38 1 SHORT 2 0_0402_5%~D XDP_PREQ# 51_0402_5% 1 @ 2 RC47
(18) H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# (15)

MISC

CLOCKS
XDP_TDO 51_0402_5% 1 2 RC48
AN34
SKTOCC# CLK_CPU_DPLL_R CLK_CPU_DPLL#_R 1K_0402_5%~D 1
A16 2 RC83
+VCCP DPLL_REF_CLK CLK_CPU_DPLL#_R
A15
DPLL_REF_CLK# CLK_CPU_DPLL_R 1K_0402_5%~D 1 2 RC82

PAD~D T1 H_CATERR# AL33 XDP_TCK_R 51_0402_5% 1 2 RC52

CATERR#
XDP_TRST#_R 51_0402_5% 1 2 RC54

2
RC43 H_DRAMRST#

THERMAL
(18,47) H_PECI AN33 R8
62_0402_5% PECI SM_DRAMRST#

DDR3
MISC
1
(47) H_PROCHOT# H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 RC55 1 2 140_0402_1%
RC41 56_0402_5% PROCHOT# SM_RCOMP[0] SM_RCOMP1 RC58 1
A5 2 25.5_0402_1%
SM_RCOMP[1] SM_RCOMP2 RC60 1
A4 2 200_0402_1%~D
SM_RCOMP[2]
Max 500mils
H_THERMTRIP# AN32 +3VS
(18) H_THERMTRIP# THERMTRIP#
XDP_DBRESET# RC42 1 2 1K_0402_5%~D

AP29 XDP_PRDY# RC121 1 SHORT 2 0_0402_5%~D XDP_PRDY#_R

XDP_PRDY#_R (6)
XDP_BPM#4 RC68 1 @ 2 0_0402_5%~D
CFG12 (9)
PRDY#
AP27 XDP_PREQ# RC122 1 SHORT 2 0_0402_5%~D XDP_PREQ#_R
XDP_PREQ#_R (6)
XDP_BPM#5 RC69 1 @ 2 0_0402_5%~D
CFG13 (9)
PREQ# XDP_BPM#6 RC70 @ 0_0402_5%~D
1 2 CFG14 (9)
AR26 XDP_TCK RC123 1 SHORT 2 0_0402_5%~D XDP_TCK_R XDP_BPM#7 RC71 1 @ 2 0_0402_5%~D
CFG15 (9)
TCK XDP_TCK_R (6)
AR27 XDP_TMS RC124 1 SHORT 2 0_0402_5%~D XDP_TMS_R
PM_SYNC_R TMS XDP_TMS_R (6)
1 SHORT 2 AP30 XDP_TRST# RC125 1 SHORT 2 0_0402_5%~D XDP_TRST#_R

PWR MANAGEMENT
(16) H_PM_SYNC AM34

JTAG & BPM

RC49 0_0402_5%~D PM_SYNC TRST# XDP_TRST#_R (6)
AR28 XDP_TDI RC50 1 SHORT 2 0_0402_5%~D XDP_TDI_R
TDI XDP_TDI_R (6)
AP26 XDP_TDO RC51 1 SHORT 2 0_0402_5%~D XDP_TDO_R
XDP_TDO_R (6)
TDO
(6,18) H_CPUPWRGD 1 SHORT 2 H_CPUPWRGD_R AP33
RC53 0_0402_5%~D UNCOREPWRGOOD
C C
AL35 XDP_DBRESET#_R RC56 1 SHORT 2 0_0402_5%~D XDP_DBRESET# XDP_DBRESET# (6,16)
H_CPUPWRGD_R VDDPWRGOOD_R DBR#
2 1 V8
10K_0402_5%~D RC44 SM_DRAMPWROK
AT28 XDP_BPM#0_R RC59 1 SHORT 2 0_0402_5%~D XDP_BPM#0
BPM#[0] XDP_BPM#0 (6)
AR29 XDP_BPM#1_R RC61 1 SHORT 2 0_0402_5%~D XDP_BPM#1
BPM#[1] XDP_BPM#1 (6)
AR30 XDP_BPM#2_R RC62 1 SHORT 2 0_0402_5%~D XDP_BPM#2
BPM#[2] XDP_BPM#2 (6)
BUF_CPU_RST# AR33 AT30 XDP_BPM#3_R RC63 1 SHORT 2 0_0402_5%~D XDP_BPM#3
RESET# BPM#[3] XDP_BPM#3 (6)
Avoid stub in the PWRGD path AP32 XDP_BPM#4_R RC64 1 SHORT 2 0_0402_5%~D XDP_BPM#4
BPM#[4] XDP_BPM#4 (6)
while placing resistors RC44 & RC53 AR31 XDP_BPM#5_R RC65 1 SHORT 2 0_0402_5%~D XDP_BPM#5
BPM#[5] XDP_BPM#5 (6)
AT31 XDP_BPM#6_R RC66 1 SHORT 2 0_0402_5%~D XDP_BPM#6
BPM#[6] XDP_BPM#6 (6)
AR32 XDP_BPM#7_R RC67 1 SHORT 2 0_0402_5%~D XDP_BPM#7
BPM#[7] XDP_BPM#7 (6)

+3VALW
+VCCP
TYCO_2013620-3_IVYBRIDGE
0.1U_0402_16V7K~D

1 CONN@ Close to CPU

1
CC68

75_0402_5%

2
RC32
2
5

UC2
1
P

NC
4BUFO_CPU_RST# 1 2 BUF_CPU_RST#
Y RC33 43_0402_1%
(6,17,38,39,40,47) PLT_RST# 2
A
G
3

SN74LVC1G07DCKR_SC70-5~D
RC34
@ 0_0402_5%~D
RC130
POWEROK
2

1 @ 2 Item21_X01
B B

0_0402_5%~D
+3V_PCH +3V_PCH +1.5V_CPU_VDDQ

0.1U_0402_16V7K~D

1
RC4 1
200_0402_1%~D RC8
200_0402_1%~D

CC65
2
Item4_X03

2
UC1
1 SHORT 2 D_PWG 1 5
For CPU S3 Power Reduce (16) PM_DRAM_PWRGD
(16,47) PCH_PWROK RC11 0_0402_5%~D 2
3
B
A
VCC
4 VDDPWRGOOD 1 2 VDDPWRGOOD_R
+1.5V GND Y RC57 130_0402_1%~D
74AHC1G09GW TSSOP 5P

2
RC19
1

1 @ 2 39_0402_1%
RC75 RC74 0_0402_5%~D
1K_0402_5%~D

1
QC2
BSS138_NL_SOT23-3 Item13_X02
2

1
D
1 2 DDR3_DRAMRST#_R 1 3 H_DRAMRST# RUN_ON_CPU1.5VS3# 2 QC1
D

(12,13) DDR3_DRAMRST# (32) RUN_ON_CPU1.5VS3#

RC76 1K_0402_5%~D G 2N7002K_SOT23-3
S

3
G
2

Item4_X03 RC77
(12,15) DRAMRST_CNTRL_PCH 1 SHORT 2 DRAMRST_CNTRL 4.99K_0402_1%
RC72 0_0402_5%~D
2

A (47) DRAMRST_CNTRL_EC 1 @ 2 A
RC73 0_0402_5%~D
1
CC69
0.1U_0402_10V7K~D
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(2/6) PM,XDP,CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 7 of 63
5 4 3 2 1
 5 4 3 2 1

JCPU1C JCPU1D
D D

AB6 M_CLK_DDR0 AE2 M_CLK_DDR2

(12) DDR_A_D[0..63] SA_CK[0] M_CLK_DDR0 (12) (13) DDR_B_D[0..63] SB_CK[0] M_CLK_DDR2 (13)
AA6 M_CLK_DDR#0 AD2 M_CLK_DDR#2
SA_CLK#[0] M_CLK_DDR#0 (12) SB_CLK#[0] M_CLK_DDR#2 (13)
DDR_A_D0 C5 V9 DDR_CKE0_DIMMA DDR_B_D0 C9 R9 DDR_CKE2_DIMMB
SA_DQ[0] SA_CKE[0] DDR_CKE0_DIMMA (12) SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMMB (13)
DDR_A_D1 D5 DDR_B_D1 A7
DDR_A_D2 SA_DQ[1] DDR_B_D2 SB_DQ[1]
D3 D10
DDR_A_D3 SA_DQ[2] DDR_B_D3 SB_DQ[2]
D2 C8
DDR_A_D4 SA_DQ[3] M_CLK_DDR1 DDR_B_D4 SB_DQ[3] M_CLK_DDR3
D6 AA5 M_CLK_DDR1 (12) A9 AE1 M_CLK_DDR3 (13)
DDR_A_D5 SA_DQ[4] SA_CK[1] M_CLK_DDR#1 DDR_B_D5 SB_DQ[4] SB_CK[1] M_CLK_DDR#3
C6 AB5 M_CLK_DDR#1 (12) A8 AD1 M_CLK_DDR#3 (13)
DDR_A_D6 SA_DQ[5] SA_CLK#[1] DDR_CKE1_DIMMA DDR_B_D6 SB_DQ[5] SB_CLK#[1] DDR_CKE3_DIMMB
C2 V10 DDR_CKE1_DIMMA (12) D9 R10 DDR_CKE3_DIMMB (13)
DDR_A_D7 SA_DQ[6] SA_CKE[1] DDR_B_D7 SB_DQ[6] SB_CKE[1]
C3 D8
DDR_A_D8 SA_DQ[7] DDR_B_D8 SB_DQ[7]
F10 G4
DDR_A_D9 SA_DQ[8] DDR_B_D9 SB_DQ[8]
F8 F4
DDR_A_D10 SA_DQ[9] DDR_B_D10 SB_DQ[9]
G10 AB4 F1 AB2
DDR_A_D11 SA_DQ[10] SA_CK[2] DDR_B_D11 SB_DQ[10] SB_CK[2]
G9 AA4 G1 AA2
DDR_A_D12 SA_DQ[11] SA_CLK#[2] DDR_B_D12 SB_DQ[11] SB_CLK#[2]
F9 W9 G5 T9
DDR_A_D13 SA_DQ[12] SA_CKE[2] DDR_B_D13 SB_DQ[12] SB_CKE[2]
F7 F5
DDR_A_D14 SA_DQ[13] DDR_B_D14 SB_DQ[13]
G8 F2
DDR_A_D15 SA_DQ[14] DDR_B_D15 SB_DQ[14]
G7 G2
DDR_A_D16 SA_DQ[15] DDR_B_D16 SB_DQ[15]
K4 AB3 J7 AA1
DDR_A_D17 SA_DQ[16] SA_CK[3] DDR_B_D17 SB_DQ[16] SB_CK[3]
K5 AA3 J8 AB1
DDR_A_D18 SA_DQ[17] SA_CLK#[3] DDR_B_D18 SB_DQ[17] SB_CLK#[3]
K1 W10 K10 T10
DDR_A_D19 SA_DQ[18] SA_CKE[3] DDR_B_D19 SB_DQ[18] SB_CKE[3]
J1 K9
DDR_A_D20 SA_DQ[19] DDR_B_D20 SB_DQ[19]
J5 J9
DDR_A_D21 SA_DQ[20] DDR_B_D21 SB_DQ[20]
J4 J10
DDR_A_D22 SA_DQ[21] DDR_CS0_DIMMA# DDR_B_D22 SB_DQ[21] DDR_CS2_DIMMB#
J2 AK3 DDR_CS0_DIMMA# (12) K8 AD3 DDR_CS2_DIMMB# (13)
DDR_A_D23 SA_DQ[22] SA_CS#[0] DDR_CS1_DIMMA# DDR_B_D23 SB_DQ[22] SB_CS#[0] DDR_CS3_DIMMB#
K2 AL3 DDR_CS1_DIMMA# (12) K7 AE3 DDR_CS3_DIMMB# (13)
DDR_A_D24 SA_DQ[23] SA_CS#[1] DDR_B_D24 SB_DQ[23] SB_CS#[1]
M8 AG1 M5 AD6
DDR_A_D25 SA_DQ[24] SA_CS#[2] DDR_B_D25 SB_DQ[24] SB_CS#[2]
N10 AH1 N4 AE6
DDR_A_D26 SA_DQ[25] SA_CS#[3] DDR_B_D26 SB_DQ[25] SB_CS#[3]
N8 N2
DDR_A_D27 SA_DQ[26] DDR_B_D27 SB_DQ[26]
N7 N1
DDR_A_D28 SA_DQ[27] DDR_B_D28 SB_DQ[27]
M10 M4
DDR_A_D29 SA_DQ[28] M_ODT0 DDR_B_D29 SB_DQ[28] M_ODT2
M9 AH3 M_ODT0 (12) N5 AE4 M_ODT2 (13)
DDR_A_D30 SA_DQ[29] SA_ODT[0] M_ODT1 DDR_B_D30 SB_DQ[29] SB_ODT[0] M_ODT3
N9 AG3 M_ODT1 (12) M2 AD4 M_ODT3 (13)
DDR_A_D31 SA_DQ[30] SA_ODT[1] DDR_B_D31 SB_DQ[30] SB_ODT[1]
C M7 AG2 M1 AD5 C

DDR SYSTEM MEMORY B

SA_DQ[31] SA_ODT[2] SB_DQ[31] SB_ODT[2]
DDR SYSTEM MEMORY A
DDR_A_D32 AG6 AH2 DDR_B_D32 AM5 AE5
DDR_A_D33 SA_DQ[32] SA_ODT[3] DDR_B_D33 SB_DQ[32] SB_ODT[3]
AG5 AM6
DDR_A_D34 SA_DQ[33] DDR_B_D34 SB_DQ[33]
AK6 AR3
DDR_A_D35 SA_DQ[34] DDR_B_D35 SB_DQ[34]
AK5 AP3
DDR_A_D36 SA_DQ[35] DDR_B_D36 SB_DQ[35]
AH5 DDR_A_DQS#[0..7] (12) AN3 DDR_B_DQS#[0..7] (13)
DDR_A_D37 SA_DQ[36] DDR_A_DQS#0 DDR_B_D37 SB_DQ[36] DDR_B_DQS#0
AH6 C4 AN2 D7
DDR_A_D38 SA_DQ[37] SA_DQS#[0] DDR_A_DQS#1 DDR_B_D38 SB_DQ[37] SB_DQS#[0] DDR_B_DQS#1
AJ5 G6 AN1 F3
DDR_A_D39 SA_DQ[38] SA_DQS#[1] DDR_A_DQS#2 DDR_B_D39 SB_DQ[38] SB_DQS#[1] DDR_B_DQS#2
AJ6 J3 AP2 K6
DDR_A_D40 SA_DQ[39] SA_DQS#[2] DDR_A_DQS#3 DDR_B_D40 SB_DQ[39] SB_DQS#[2] DDR_B_DQS#3
AJ8 M6 AP5 N3
DDR_A_D41 SA_DQ[40] SA_DQS#[3] DDR_A_DQS#4 DDR_B_D41 SB_DQ[40] SB_DQS#[3] DDR_B_DQS#4
AK8 AL6 AN9 AN5
DDR_A_D42 SA_DQ[41] SA_DQS#[4] DDR_A_DQS#5 DDR_B_D42 SB_DQ[41] SB_DQS#[4] DDR_B_DQS#5
AJ9 AM8 AT5 AP9
DDR_A_D43 SA_DQ[42] SA_DQS#[5] DDR_A_DQS#6 DDR_B_D43 SB_DQ[42] SB_DQS#[5] DDR_B_DQS#6
AK9 AR12 AT6 AK12
DDR_A_D44 SA_DQ[43] SA_DQS#[6] DDR_A_DQS#7 DDR_B_D44 SB_DQ[43] SB_DQS#[6] DDR_B_DQS#7
AH8 AM15 AP6 AP15
DDR_A_D45 SA_DQ[44] SA_DQS#[7] DDR_B_D45 SB_DQ[44] SB_DQS#[7]
AH9 AN8
DDR_A_D46 SA_DQ[45] DDR_B_D46 SB_DQ[45]
AL9 AR6
DDR_A_D47 SA_DQ[46] DDR_B_D47 SB_DQ[46]
AL8 AR5
DDR_A_D48 SA_DQ[47] DDR_B_D48 SB_DQ[47]
AP11 DDR_A_DQS[0..7] (12) AR9 DDR_B_DQS[0..7] (13)
DDR_A_D49 SA_DQ[48] DDR_A_DQS0 DDR_B_D49 SB_DQ[48] DDR_B_DQS0
AN11 D4 AJ11 C7
DDR_A_D50 SA_DQ[49] SA_DQS[0] DDR_A_DQS1 DDR_B_D50 SB_DQ[49] SB_DQS[0] DDR_B_DQS1
AL12 F6 AT8 G3
DDR_A_D51 SA_DQ[50] SA_DQS[1] DDR_A_DQS2 DDR_B_D51 SB_DQ[50] SB_DQS[1] DDR_B_DQS2
AM12 K3 AT9 J6
DDR_A_D52 SA_DQ[51] SA_DQS[2] DDR_A_DQS3 DDR_B_D52 SB_DQ[51] SB_DQS[2] DDR_B_DQS3
AM11 N6 AH11 M3
DDR_A_D53 SA_DQ[52] SA_DQS[3] DDR_A_DQS4 DDR_B_D53 SB_DQ[52] SB_DQS[3] DDR_B_DQS4
AL11 AL5 AR8 AN6
DDR_A_D54 SA_DQ[53] SA_DQS[4] DDR_A_DQS5 DDR_B_D54 SB_DQ[53] SB_DQS[4] DDR_B_DQS5
AP12 AM9 AJ12 AP8
DDR_A_D55 SA_DQ[54] SA_DQS[5] DDR_A_DQS6 DDR_B_D55 SB_DQ[54] SB_DQS[5] DDR_B_DQS6
AN12 AR11 AH12 AK11
DDR_A_D56 SA_DQ[55] SA_DQS[6] DDR_A_DQS7 DDR_B_D56 SB_DQ[55] SB_DQS[6] DDR_B_DQS7
AJ14 AM14 AT11 AP14
DDR_A_D57 SA_DQ[56] SA_DQS[7] DDR_B_D57 SB_DQ[56] SB_DQS[7]
AH14 AN14
DDR_A_D58 SA_DQ[57] DDR_B_D58 SB_DQ[57]
AL15 AR14
DDR_A_D59 SA_DQ[58] DDR_B_D59 SB_DQ[58]
AK15 AT14
DDR_A_D60 SA_DQ[59] DDR_B_D60 SB_DQ[59]
AL14 DDR_A_MA[0..15] (12) AT12 DDR_B_MA[0..15] (13)
DDR_A_D61 SA_DQ[60] DDR_A_MA0 DDR_B_D61 SB_DQ[60] DDR_B_MA0
AK14 AD10 AN15 AA8
DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
AJ15 W1 AR15 T7
DDR_A_D63 SA_DQ[62] SA_MA[1] DDR_A_MA2 DDR_B_D63 SB_DQ[62] SB_MA[1] DDR_B_MA2
AH15 W2 AT15 R7
SA_DQ[63] SA_MA[2] DDR_A_MA3 SB_DQ[63] SB_MA[2] DDR_B_MA3
W7 T6
SA_MA[3] DDR_A_MA4 SB_MA[3] DDR_B_MA4
V3 T2
SA_MA[4] DDR_A_MA5 SB_MA[4] DDR_B_MA5
V2 T4
SA_MA[5] DDR_A_MA6 SB_MA[5] DDR_B_MA6
W3 T3
SA_MA[6] DDR_A_MA7 SB_MA[6] DDR_B_MA7
(12) DDR_A_BS0 AE10 W6 (13) DDR_B_BS0 AA9 R2
B SA_BS[0] SA_MA[7] DDR_A_MA8 SB_BS[0] SB_MA[7] DDR_B_MA8 B
(12) DDR_A_BS1 AF10 V1 (13) DDR_B_BS1 AA7 T5
SA_BS[1] SA_MA[8] DDR_A_MA9 SB_BS[1] SB_MA[8] DDR_B_MA9
(12) DDR_A_BS2 V6 W5 (13) DDR_B_BS2 R6 R3
SA_BS[2] SA_MA[9] DDR_A_MA10 SB_BS[2] SB_MA[9] DDR_B_MA10
AD8 AB7
SA_MA[10] DDR_A_MA11 SB_MA[10] DDR_B_MA11
V4 R1
SA_MA[11] DDR_A_MA12 SB_MA[11] DDR_B_MA12
W4 T1
SA_MA[12] DDR_A_MA13 SB_MA[12] DDR_B_MA13
(12) DDR_A_CAS# AE8 AF8 (13) DDR_B_CAS# AA10 AB10
SA_CAS# SA_MA[13] DDR_A_MA14 SB_CAS# SB_MA[13] DDR_B_MA14
(12) DDR_A_RAS# AD9 V5 (13) DDR_B_RAS# AB8 R5
SA_RAS# SA_MA[14] DDR_A_MA15 SB_RAS# SB_MA[14] DDR_B_MA15
(12) DDR_A_WE# AF9 V7 (13) DDR_B_WE# AB9 R4
SA_WE# SA_MA[15] SB_WE# SB_MA[15]

TYCO_2013620-3_IVYBRIDGE TYCO_2013620-3_IVYBRIDGE
CONN@ CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(3/6) DDRIII
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 8 of 63
5 4 3 2 1
 5 4 3 2 1

D D
CFG Straps for Processor

2 1 CFG2
1K_0402_1%~D RC78

JCPU1E

PEG Static Lane Reversal - CFG2 is for the 16x

AH27 T36 PAD~D
CFG0 VCC_DIE_SENSE
1:(Default) Normal Operation; (6) CFG0 AK28
CFG[0] VSS_DIE_SENSE
AH26 T51 PAD~D
CFG1 AK29
Lane # definition matches socket pin PAD~D T54 CFG2 AL26
CFG[1]
map definition CFG3 CFG[2]
CFG2 PAD~D T59
AL27
CFG[3]
CFG4 AK26 L7 T2 PAD~D
CFG5 CFG[4] RSVD28
AL29 AG7 T3 PAD~D
CFG6 CFG[5] RSVD29
* 0:Lane Reversed CFG7
AL30
AM31
CFG[6] RSVD30
AE7
AK2
T4 PAD~D
PAD~D T210 CFG[7] RSVD31 T5 PAD~D
CFG8 AM32
PAD~D T60 CFG9 CFG[8]
AM30 W8 T6 PAD~D
PAD~D T61 CFG[9] RSVD32

CFG
CFG10 AM28
+VCC_GFXCORE_AXG PAD~D T62 CFG11 CFG[10]
PAD~D T63 AM26
@ CFG4 +VCC_CORE CFG12 CFG[11]
2 1 (7) CFG12 AN28 AT26 T7 PAD~D
1K_0402_1%~D RC81 CFG13 CFG[12] RSVD33
(7) CFG13 AN31 AM33 T8 PAD~D
CFG14 CFG[13] RSVD34
(7) CFG14 AN26 AJ27 T9 PAD~D
CFG[14] RSVD35

2
(7) CFG15 CFG15 AM27
CFG[15]

2
CFG16 AK31
PAD~D T64 CFG[16]
@ RC79 CFG17 AN29
PAD~D T65 CFG[17]
Display Port Presence Strap @ RC80 50_0402_1%
50_0402_1%

1
T8 T10 PAD~D

1
RSVD37
C
* 1 :Disabled; No Physical Display Port VCC_AXG_VAL_SENSE AJ31
RSVD38
J16
H16
T11 PAD~D
C
attached to Embedded Display Port VAXG_VAL_SENSE RSVD39 T12 PAD~D
VSS_AXG_VAL_SENSE AH31 G16 T13 PAD~D
VCC_VAL_SENSE VSSAXG_VAL_SENSE RSVD40
AJ33
VSS_VAL_SENSE VCC_VAL_SENSE
CFG4 AH33
VSS_VAL_SENSE
0 :Enabled; An external Display
Port device is connected to the AJ26 AR35
PAD~D T19 T14 PAD~D
Embedded Display Port RC79, RC80, RC90, RC91 RSVD5 RSVD_NCTF1
AT34 T15 PAD~D
RSVD_NCTF2
Please place as close as JCPU1 AT33 T16 PAD~D

RESERVED
RSVD_NCTF3
AP35 T17 PAD~D
RSVD_NCTF4
AR34 T18 PAD~D
RSVD_NCTF5
2 @ 1 CFG5 VSS_AXG_VAL_SENSE
1K_0402_1%~D RC87 PAD~D T25 F25
@ CFG6 RSVD8
2 1 PAD~D T26 F24
1K_0402_1%~D RC86 VSS_VAL_SENSE RSVD9
PAD~D T27 F23
RSVD10
PAD~D T28 D24 B34 T20 PAD~D
RSVD11 RSVD_NCTF6
PAD~D T30 G25 A33 T21 PAD~D
RSVD12 RSVD_NCTF7
2

2
PAD~D T32 G24 A34 T22 PAD~D
RSVD13 RSVD_NCTF8
PCIE Port Bifurcation Straps RC90 RC91 PAD~D T33 E23
RSVD14 RSVD_NCTF9
B35 T23 PAD~D
50_0402_1% @ @ 50_0402_1% PAD~D T34 D23 C35 T24 PAD~D
RSVD15 RSVD_NCTF10
PAD~D T35 C30
RSVD16
*11:(Default) x16 - Device 1 functions PAD~D T37 A31
1

RSVD17
1 and 2 disabled PAD~D T38 B30
RSVD18
PAD~D T39 B29
RSVD19
PAD~D T40 D30 AJ32 T29 PAD~D
RSVD20 RSVD51
10:x8, 8 - Device 1 function 1 enabled PAD~D T41 B31
RSVD21 RSVD52
AK32 T31 PAD~D
;function 2 disabled PAD~D T42 A30
RSVD22
CFG[6:5] PAD~D T43 C29
RSVD23
01: Reserved - (Device 1 function 1 BCLK_ITP
AN35 CLK_RES_ITP (15)
disabled ; function 2 enabled) PAD~D T44 J20 AM35 CLK_RES_ITP# (15)
RSVD24 BCLK_ITP#
PAD~D T45 B18
RSVD25
00: x8,x4,x4 - Device 1 functions 1
and 2 enabled J15 AT2
PAD~D T49 RSVD27 RSVD_NCTF11 T46 PAD~D
AT1 T47 PAD~D
B RSVD_NCTF12 B
AR1 T48 PAD~D
RSVD_NCTF13

B1 T50 PAD~D
KEY

TYCO_2013620-3_IVYBRIDGE
CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(4/6) RSVD,CFG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 9 of 63
5 4 3 2 1
 5 4 3 2 1

+1.5V +1.5V_CPU_VDDQ

@ Socket Edge
JCPU1F POWER 1
J8
2
+1.5V_CPU_VDDQ

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D
PAD-OPEN 4x4m
QC=94A J8 OPEN 1 1 1 1 1 1
1
+ CC166
DC=53A

1
+VCC_CORE +VCCP 330U_D2_2VM_R6M~D
+0.75VS +V_SM_VREF

CC160

CC161

CC162

CC163

CC164

CC165
2 2 2 2 2 2 2 @ 1K_0402_5%~D
D
AG35
8.5A +VCCSA RC112 D
VCC1
AG34 AH13

2
VCC2 VCCIO1
AG33 AH10 1 SHORT 2
VCC3 VCCIO2
AG32
VCC4 VCCIO3
AG10 Socket Cavity Socket Edge RC106 0_0402_5%~D
AG31 AC10
VCC5 VCCIO4

1
AG30 Y10 Item3_X02
VCC6 VCCIO5
AG29 U10 1

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D
VCC7 VCCIO6 @ 1K_0402_5%~D
AG28 P10 1
VCC8 VCCIO7 CC250 RC116
AG27 L10 1 1 1 1
VCC9 VCCIO8 + CC171
AG26 J14 0.1U_0402_10V7K~D

2
VCC10 VCCIO9 330U_D2_2VM_R6M~D 2
AF35 J13
VCC11 VCCIO10

CC167

CC168

CC169

CC170
AF34 J12
VCC12 VCCIO11 2 2 2 2 2
AF33 J11
VCC13 VCCIO12 18-mil witdh,and shoulde use differential routing with 7-milseparation.
AF32 H14
VCC14 VCCIO13
AF31 H12 Signals must have equal trace length
VCC15 VCCIO14
AF30 H11 within 25 mils and are to be routed using external layer and
VCC16 VCCIO15
AF29 G14 GND referencing (no split plane referencing). VSS_SENSE,
VCC17 VCCIO16
AF28 G13 VCC_SENSE are to use 25-mils separation from any other
VCC18 VCCIO17
AF27 G12 signal or rail.
VCC19 VCCIO18
PEG AND DDR
AF26 F14
VCC20 VCCIO19
AD35 F13
VCC21 VCCIO20
AD34 F12
VCC22 VCCIO21 +1.8VS +VCC_GFXCORE_AXG
AD33 F11
VCC23 VCCIO22
AD32
VCC24 VCCIO23
E14 Item4_X03 Socket Edge
AD31 E12 VCC_AXG_SENSE RC131 1 2 100_0402_5%~D
VCC25 VCCIO24 RC109 +1.8VS_VCCPLL VSS_AXG_SENSE
AD30 1 SHORT 2 0_0805_5%~D RC132 1 2 100_0402_5%~D
VCC26
AD29 E11 1

10U_0805_25V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
VCC27 VCCIO25

330U_D2_2.5VM_R6M~D
AD28 D14
AD27
AD26
VCC28
VCC29
VCC30
VCCIO26
VCCIO27
VCCIO28
D13
D12
1 1 1
+
+VCC_GFXCORE_AXG
JCPU1G
POWER

CC172

CC174

CC175

CC176
AC35 D11
VCC31 VCCIO29 2 2 2 2
AC34 C14
VCC32 VCCIO30
AC33 C13 33A
VCC33 VCCIO31 VCC_AXG_SENSE
AC32 C12 AT24 AK35 VCC_AXG_SENSE (59)
VCC34 VCCIO32 VAXG1 VAXG_SENSE

SENSE
LINES
AC31 C11 AT23 AK34 VSS_AXG_SENSE
VCC35 VCCIO33 VAXG2 VSSAXG_SENSE VSS_AXG_SENSE (59)
AC30 B14 AT21
VCC36 VCCIO34 VAXG3
AC29 B12 AT20
VCC37 VCCIO35 VAXG4
C AC28 A14 AT18 C
VCC38 VCCIO36 VAXG5
AC27 A13 AT17
VCC39 VCCIO37 VAXG6 +V_SM_VREF
AC26 A12 AR24 +V_SM_VREF should
VCC40 VCCIO38 VAXG7
AA35 A11 AR23 have 10 mil trace width
VCC41 VCCIO39 VAXG8
AA34 AR21
VCC42 VAXG9
AA33 J23 AR20
VCC43 VCCIO40 VAXG10 +V_SM_VREF
AA32 AR18 AL1
VCC44 VAXG11 SM_VREF
AA31 AR17
VCC45 VAXG12
AA30 AP24
VCC46 VAXG13

VREF
AA29 AP23
VCC47 VAXG14
AA28 AP21
VCC48 VAXG15 +V_DDR_REFA_R
AA27 AP20 B4 +V_DDR_REFA_R (12)
VCC49 VAXG16 SA_DIMM_VREFDQ +V_DDR_REFB_R
AA26 AP18 D1 +V_DDR_REFB_R (12)
VCC50 VIDALERT# VAXG17 SB_DIMM_VREFDQ
Y35 AP17
VCC51 VAXG18
10mil .Spacing is 10mil
CORE SUPPLY

Y34 Connect one end of series-resistor 43±5% close to AN24

VCC52 VAXG19
Y33 processor and pull-up to VCCIO through 75±5% on AN23
VCC53 VAXG20
Y32 the other end of the series-resistor towards Intel MVP 7. AN21
VCC54 VAXG21 +1.5V_CPU_VDDQ +1.5V_CPU_VDDQ +1.5V
Y31 AN20
VCC55 VAXG22
Y30 AN18
VCC56 VAXG23

DDR3 -1.5V RAILS

Y29 AN17
Y28
VCC57 +VCCP Item3_X02
AM24
VAXG24
AF7
5A CC182 2 1 0.1U_0402_10V7K~D
VCC58 VAXG25 VDDQ1

GRAPHICS
Y27 AM23 AF4
VCC59 VAXG26 VDDQ2
Y26 AM21 AF1
VCC60 RC93 75_0402_5% VAXG27 VDDQ3 CC184
V35 1 2 AM20 AC7 2 1 0.1U_0402_10V7K~D
VCC61 H_CPU_SVIDALRT# RC94 43_0402_1% VAXG28 VDDQ4
V34 AJ29 1 2 VR_SVID_ALRT# (59) AM18 AC4
VCC62 VIDALERT# VAXG29 VDDQ5
SVID

V33 AJ30 H_CPU_SVIDCLK RC92 1 SHORT 2 0_0402_5%~D AM17 AC1

VCC63 VIDSCLK VR_SVID_CLK (59) VAXG30 VDDQ6
V32 AJ28 H_CPU_SVIDDAT RC96 1 SHORT 2 0_0402_5%~D AL24 Y7 CC181 2 1 0.1U_0402_10V7K~D
VCC64 VIDSOUT VR_SVID_DAT (59) VAXG31 VDDQ7
V31 RC95 1 2 130_0402_1%~D +VCCP AL23 Y4
VCC65 VAXG32 VDDQ8
V30 AL21 Y1
VCC66 VAXG33 VDDQ9
V29
VCC67 RC95 close to CPU AL20
VAXG34 VDDQ10
U7 CC183 2 1 0.1U_0402_10V7K~D
V28 AL18 U4
VCC68 VAXG35 VDDQ11
V27 AL17 U1
VCC69 VIDSOUT: VAXG36 VDDQ12
V26 AK24 P7
VCC70 VAXG37 VDDQ13
U35 Requires a pull-up to VCCIO through a pull-up resistor of 130 ±5% close to the processor, and a pull-up AK23 P4
VCC71 VAXG38 VDDQ14
U34 to VCCIO through a pull-up resistor of 130 ±5% close to Intel MVP 7. AK21 P1
VCC72 VAXG39 VDDQ15
U33 VIDSCLK: AK20
VCC73 VAXG40
U32 Required pull-up to VCCIO through 55 ±5% close to Intel IMVP 7. AK18
VCC74 VAXG41
U31 AK17
B VCC75 VAXG42 B
U30 AJ24
VCC76 18-mil witdh,and shoulde use differential VAXG43
U29 AJ23
VCC77 VAXG44 +VCCSA
U28 routing with 7-milseparation. AJ21
VCC78 VAXG45
U27 Signals must have equal trace length AJ20
VCC79 VAXG46
U26 within 25 mils and are to be routed using external layer and AJ18 6A
VCC80 VAXG47
R35 GND referencing (no split plane referencing). VSS_SENSE, AJ17 M27
VCC81 VCC_SENSE & VSS_SENSE: VAXG48 VCCSA1
R34 VCC_SENSE are to use 25-mils separation from any other AH24 M26
VCC82 VAXG49 VCCSA2

SA RAIL
R33 signal or rail. xxxxxx AH23 L26
VCC83 VAXG50 VCCSA3
R32 100- ±1% pull-down to GND near processor AH21 J26
VCC84 VAXG51 VCCSA4
R31 AH20 J25
VCC85 VAXG52 VCCSA5
R30 AH18 J24
VCC86 +VCC_CORE VAXG53 VCCSA6
R29 AH17 H26
VCC87 RC97 1 100_0402_1%~D VAXG54 VCCSA7
R28 2 H25
VCC88 VCCSA8
AJ35 VCCSENSE_R RC98 1 SHORT 0_0402_5%~D
SENSE LINES

R27 2 VCCSENSE (59)

VCC89 VCC_SENSE
R26 AJ34 VSSSENSE_R RC99 1 SHORT 2 0_0402_5%~D
VSSSENSE (59)
VCC90 VSS_SENSE RC100 1 100_0402_1%~D
P35 2
VCC91 +VCCP
P34
VCC92 RC126
P33 1 2 10_0402_1%~D
VCC93

1.8V RAIL
P32 B10 H23
P31
VCC94 VCCIO_SENSE
A10
VCCIO_SENSE (56) 1.2A VCCSA_SENSE VCCSA_SENSE (57)
P30
VCC95 VSS_SENSE_VCCIO RC129 1 2 10_0402_1%~D
VSSIO_SENSE (56) TBD
VCC96 +1.8VS_VCCPLL
P29 B6
VCC97 VCCPLL1
P28 A6 C22 VCCSA_VID0 RC111 1 SHORT 2 0_0402_5%~D H_VCCSA_VID0 (57)
VCC98 VCCPLL2 VCCSA_VID[0]

MISC
P27 Item3_X02 A2 C24 VCCSA_VID1 RC108 1 SHORT 2 0_0402_5%~D H_VCCSA_VID1 (57)
VCC99 VCCPLL3 VCCSA_VID[1]
P26
VCC100
10mil .Spacing is 10mil

A19 H_VCCP_SEL RC88 1 SHORT 2 0_0402_5%~D VCCP_PWRCTRL (56)

VCCIO_SEL

TYCO_2013620-3_IVYBRIDGE
Item3_X02
Need PWR add new circuit on 1.05V(refer CRB)
CONN@

TYCO_2013620-3_IVYBRIDGE
CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(5/6) PWR,BYPASS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 10 of 63
5 4 3 2 1
 5 4 3 2 1

D D

JCPU1H JCPU1I

AT35 AJ22
VSS1 VSS81
AT32 AJ19
VSS2 VSS82
AT29 AJ16 T35 F22
VSS3 VSS83 VSS161 VSS234
AT27 AJ13 T34 F19
VSS4 VSS84 VSS162 VSS235
AT25 AJ10 T33 E30
VSS5 VSS85 VSS163 VSS236
AT22 AJ7 T32 E27
VSS6 VSS86 VSS164 VSS237
AT19 AJ4 T31 E24
VSS7 VSS87 VSS165 VSS238
AT16 AJ3 T30 E21
VSS8 VSS88 VSS166 VSS239
AT13 AJ2 T29 E18
VSS9 VSS89 VSS167 VSS240
AT10 AJ1 T28 E15
VSS10 VSS90 VSS168 VSS241
AT7 AH35 T27 E13
VSS11 VSS91 VSS169 VSS242
AT4 AH34 T26 E10
VSS12 VSS92 VSS170 VSS243
AT3 AH32 P9 E9
VSS13 VSS93 VSS171 VSS244
AR25 AH30 P8 E8
VSS14 VSS94 VSS172 VSS245
AR22 AH29 P6 E7
VSS15 VSS95 VSS173 VSS246
AR19 AH28 P5 E6
VSS16 VSS96 VSS174 VSS247
AR16 AH25 P3 E5
VSS17 VSS98 VSS175 VSS248
AR13 AH22 P2 E4
VSS18 VSS99 VSS176 VSS249
AR10 AH19 N35 E3
VSS19 VSS100 VSS177 VSS250
AR7 AH16 N34 E2
VSS20 VSS101 VSS178 VSS251
AR4 AH7 N33 E1
VSS21 VSS102 VSS179 VSS252
AR2 AH4 N32 D35
VSS22 VSS103 VSS180 VSS253
AP34 AG9 N31 D32
VSS23 VSS104 VSS181 VSS254
AP31 AG8 N30 D29
VSS24 VSS105 VSS182 VSS255
AP28 AG4 N29 D26
VSS25 VSS106 VSS183 VSS256
AP25 AF6 N28 D20
VSS26 VSS107 VSS184 VSS257
AP22 AF5 N27 D17
VSS27 VSS108 VSS185 VSS258
AP19 AF3 N26 C34
VSS28 VSS109 VSS186 VSS259
AP16 AF2 M34 C31
VSS29 VSS110 VSS187 VSS260
C AP13 AE35 L33 C28 C
VSS30 VSS111 VSS188 VSS261
AP10 AE34 L30 C27
VSS31 VSS112 VSS189 VSS262
AP7 AE33 L27 C25
VSS32 VSS113 VSS190 VSS263
AP4 AE32 L9 C23
VSS33 VSS114 VSS191 VSS264
AP1 AE31 L8 C10
VSS34 VSS115 VSS192 VSS265
AN30 AE30 L6 C1
VSS35 VSS116 VSS193 VSS266
AN27 AE29 L5 B22
VSS36 VSS117 VSS194 VSS267
AN25 AE28 L4 B19
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE27
AE26
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
AN16 AE9 L1 B13
VSS40 VSS121 VSS198 VSS271
AN13 AD7 K35 B11
VSS41 VSS122 VSS199 VSS272
AN10 AC9 K32 B9
VSS42 VSS123 VSS200 VSS273
AN7 AC8 K29 B8
VSS43 VSS124 VSS201 VSS274
AN4 AC6 K26 B7
VSS44 VSS125 VSS202 VSS275
AM29 AC5 J34 B5
VSS45 VSS126 VSS203 VSS276
AM25 AC3 J31 B3
VSS46 VSS127 VSS204 VSS277
AM22 AC2 H33 B2
VSS47 VSS128 VSS205 VSS278
AM19 AB35 H30 A35
VSS48 VSS129 VSS206 VSS279
AM16 AB34 H27 A32
VSS49 VSS130 VSS207 VSS280
AM13 AB33 H24 A29
VSS50 VSS131 VSS208 VSS281
AM10 AB32 H21 A26
VSS51 VSS132 VSS209 VSS282
AM7 AB31 H18 A23
VSS52 VSS133 VSS210 VSS283
AM4 AB30 H15 A20
VSS53 VSS134 VSS211 VSS284
AM3 AB29 H13 A3
VSS54 VSS135 VSS212 VSS285
AM2 AB28 H10
VSS55 VSS136 VSS213
AM1 AB27 H9
VSS56 VSS137 VSS214
AL34 AB26 H8
VSS57 VSS138 VSS215
AL31 Y9 H7
VSS58 VSS139 VSS216
AL28 Y8 H6
VSS59 VSS140 VSS217
AL25 Y6 H5
VSS60 VSS141 VSS218
AL22 Y5 H4
VSS61 VSS142 VSS219
AL19 Y3 H3
VSS62 VSS143 VSS220
AL16 Y2 H2
VSS63 VSS144 VSS221
AL13 W35 H1
VSS64 VSS145 VSS222
AL10 W34 G35
VSS65 VSS146 VSS223
AL7 W33 G32
VSS66 VSS147 VSS224
AL4 W32 G29
B VSS67 VSS148 VSS225 B
AL2 W31 G26
VSS68 VSS149 VSS226
AK33 W30 G23
VSS69 VSS150 VSS227
AK30 W29 G20
VSS70 VSS151 VSS228
AK27 W28 G17
VSS71 VSS152 VSS229
AK25 W27 G11
VSS72 VSS153 VSS230
AK22 W26 F34
VSS73 VSS154 VSS231
AK19 U9 F31
VSS74 VSS155 VSS232
AK16 U8 F29
VSS75 VSS156 VSS233
AK13 U6
VSS76 VSS157
AK10 U5
VSS77 VSS158
AK7 U3
VSS78 VSS159
AK4 U2
VSS79 VSS160
AJ25
VSS80

TYCO_2013620-3_IVYBRIDGE TYCO_2013620-3_IVYBRIDGE
CONN@ CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(6/6) PWR,VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 11 of 63
5 4 3 2 1
 5 4 3 2 1

+V_DDR_REFA +1.5V +1.5V

JDIMM1
(8) DDR_A_DQS#[0..7]
+V_DDR_REFA 1 2 +1.5V_SUS decoupling caps be located at the VDD pins of each SO-DIMM connector in the
VREF_DQ VSS DDR_A_D4
3 4 vicinity of the CMD, Clock and Control signals
(8) DDR_A_DQS[0..7]

2.2U_0402_6.3V6M~D

0.1U_0402_16V7K~D
DDR_A_D0 VSS DQ4 DDR_A_D5
5 6 Those capacitors should be placed on the same side of the motherboard as the
DDR_A_D1 DQ0 DQ5
(8) DDR_A_D[0..63] 7 8 SO-DIMM connector
DQ1 VSS DDR_A_DQS#0
1 1 9 10
VSS DQS0# DDR_A_DQS0
(8) DDR_A_MA[0..15] 11 12
DM0 DQS0
13 14
DDR_A_D2 VSS VSS DDR_A_D6
2 2
15
DQ2 DQ6
16 Layout Note:
DDR_A_D3 DDR_A_D7

CD1

CD2
17 18
19
DQ3 DQ7
20 Place near JDIMM1
DDR_A_D8 VSS VSS DDR_A_D12
21 22
DDR_A_D9 DQ8 DQ12 DDR_A_D13
23 24
DQ9 DQ13
All VREF traces should 25
VSS VSS
26
have 10 mil trace width DDR_A_DQS#1 27 28
D
DDR_A_DQS1 DQS1# DM1 DDR3_DRAMRST# D
29 30 DDR3_DRAMRST# (7,13)
DQS1 RESET# +1.5V
31 32
DDR_A_D10 VSS VSS DDR_A_D14
33 34
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 36
DQ11 DQ15
37 38
DDR_A_D16 VSS VSS DDR_A_D20
39 40

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 42 1 1 1 1
DQ17 DQ21
43 44
DDR_A_DQS#2 VSS VSS
45 46
DDR_A_DQS2 DQS2# DM2
47 48
DQS2 VSS DDR_A_D22 2 2 2 2

CD3

CD4

CD5

CD6
49 50
All VREF traces should have 10 mil trace width DDR_A_D18 VSS DQ22 DDR_A_D23
51 52
DDR_A_D19 DQ18 DQ23
53 54
DQ19 VSS DDR_A_D28
55 56
DDR_A_D24 VSS DQ28 DDR_A_D29
57 58
DDR_A_D25 DQ24 DQ29
59 60
DQ25 VSS DDR_A_DQS#3
61 62
VSS DQS3# DDR_A_DQS3
63 64
DM3 DQS3
65 66
DDR_A_D26 VSS VSS DDR_A_D30 +1.5V
67 68
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 70
DQ27 DQ31
71 72
VSS VSS

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D
(8) DDR_CKE0_DIMMA DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA DDR_CKE1_DIMMA (8)
CKE0 CKE1
75 76 1

330U_SX_2VY~D
VDD VDD DDR_A_MA15
77 78 1 1 1 1 1 1 1
DDR_A_BS2 NC A15 DDR_A_MA14 @ @ +
(8) DDR_A_BS2 79 80
BA2 A14
81 82
DDR_A_MA12 VDD VDD DDR_A_MA11
83 84
DDR_A_MA9 A12/BC# A11 DDR_A_MA7 2 2 2 2 2 2 2 2

CD7

CD8

CD9

CD10

CD11

CD12

CD13

CD14
85 86
A9 A7
87 88
DDR_A_MA8 VDD VDD DDR_A_MA6
89 90
DDR_A_MA5 A8 A6 DDR_A_MA4
91 92
A5 A4
93 94
DDR_A_MA3 VDD VDD DDR_A_MA2
95 96
DDR_A_MA1 A3 A2 DDR_A_MA0
97 98
A1 A0
C 99 100 C
M_CLK_DDR0 VDD VDD M_CLK_DDR1
(8) M_CLK_DDR0 101 102 M_CLK_DDR1 (8)
M_CLK_DDR#0 CK0 CK1 M_CLK_DDR#1
(8) M_CLK_DDR#0 103 104 M_CLK_DDR#1 (8)
CK0# CK1# +1.5V
105
VDD VDD
106 Layout Note:
DDR_A_MA10 107 108 DDR_A_BS1 DDR_A_BS1 (8)
(8) DDR_A_BS0 DDR_A_BS0 109
A10/AP BA1
110 DDR_A_RAS# DDR_A_RAS# (8)
Place near JDIMM1.203,204
BA0 RAS#
111 112
VDD VDD

1
(8) DDR_A_WE# DDR_A_WE# 113 114 DDR_CS0_DIMMA# DDR_CS0_DIMMA# (8)
DDR_A_CAS# WE# S0# M_ODT0 RD4
(8) DDR_A_CAS# 115 116 M_ODT0 (8)
CAS# ODT0 1K_0402_1%~D
117 118
DDR_A_MA13 VDD VDD M_ODT1
119 120 M_ODT1 (8)
DDR_CS1_DIMMA# A13 ODT1
(8) DDR_CS1_DIMMA# 121 122

2
S1# NC
123 124
VDD VDD +VREF_CA +0.75VS
125 126
TEST VREF_CA
127 128
DDR_A_D32 VSS VSS DDR_A_D36
129 130

2.2U_0402_6.3V6M~D

0.1U_0402_16V7K~D
DQ32 DQ36

1
DDR_A_D33 131 132 DDR_A_D37
DQ33 DQ37 RD5
133 134 1 1
DDR_A_DQS#4 VSS VSS 1K_0402_1%~D
135 136

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
DDR_A_DQS4 DQS4# DM4
137 138 1 1 1 1
DQS4 VSS DDR_A_D38
139 140

2
DDR_A_D34 VSS DQ38 DDR_A_D39 2 2

CD15

CD16
141 142
DDR_A_D35 DQ34 DQ39
143 144
DQ35 VSS DDR_A_D44 2 2 2 2

CD17

CD18

CD19

CD20
145 146
DDR_A_D40 VSS DQ44 DDR_A_D45
147 148
DDR_A_D41 DQ40 DQ45
149 150
DQ41 VSS DDR_A_DQS#5
151 152
VSS DQS5# DDR_A_DQS5
153 154
DM5 DQS5
155 156
DDR_A_D42 VSS VSS DDR_A_D46
157 158
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 160
DQ43 DQ47
161 162
DDR_A_D48 VSS VSS DDR_A_D52
163 164
DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 166
DQ49 DQ53
167 168
DDR_A_DQS#6 VSS VSS
169 170
DDR_A_DQS6 DQS6# DM6
171 172
DQS6 VSS DDR_A_D54
173 174
B
DDR_A_D50 VSS DQ54 DDR_A_D55 B
175 176
DDR_A_D51 DQ50 DQ55
177 178
DQ51 VSS DDR_A_D60
179 180
DDR_A_D56 VSS DQ60 DDR_A_D61
181 182
DDR_A_D57 DQ56 DQ61
183 184
DQ57 VSS DDR_A_DQS#7
185 186
VSS DQS7# DDR_A_DQS7
187 188
DM7 DQS7
189 190
+3VS DDR_A_D58 VSS VSS DDR_A_D62
191 192
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 194
DQ59 DQ63
195 196
VSS VSS
1 2 197 198
RD6 10K_0402_5%~D 199
1 2 201
SA0
VDDSPD
EVENT#
SDA
200
202
PCH_SMBDATA
PCH_SMBCLK
PCH_SMBDATA (6,13,15,38,45)
PCH_SMBCLK (6,13,15,38,45)
M3 @ RD8 1 2 0_0402_5%~D
0.1U_0402_16V7K~D

2.2U_0402_6.3V6M~D

RD7 10K_0402_5%~D 203 SA1 SCL +V_DDR_REFA

1 1 204 +0.75VS
VTT VTT
+0.75VS
205 206 +V_DDR_REFA 1 3

S
GND1 GND2 +V_DDR_REFA_R (10)
207 208
2 2 BOSS1 BOSS2
CD21

CD22

1
G
2
FOX_AS0A626-U2SN-7F QD1 @ RD21
BSS138_NL_SOT23-3 1K_0402_1%~D
CONN@ (7,15) DRAMRST_CNTRL_PCH DRAMRST_CNTRL_PCH

2
M1 +1.5V
@ RD9 1 2 0_0402_5%~D
1

RD1 +V_DDR_REFB
1K_0402_1%~D
+V_DDR_REFA +V_DDR_REFB

S
1 3 +V_DDR_REFB_R (10)
2

1
RD10 1 SHORT 2 0_0402_5%~D @ RD22

G
2
QD2 1K_0402_1%~D
1

A Item3_X02 BSS138_NL_SOT23-3 A

2
RD3 DRAMRST_CNTRL_PCH
1K_0402_1%~D
2

M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII DIMMA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 12 of 63
5 4 3 2 1
 5 4 3 2 1

+V_DDR_REFB +1.5V +1.5V

JDIMM2
+V_DDR_REFB 1 2
VREF_DQ VSS1 DDR_B_D4
(8) DDR_B_DQS#[0..7] 3 4
DDR_B_D0 VSS2 DQ4 DDR_B_D5
5 6

2.2U_0402_6.3V6M~D

0.1U_0402_16V7K~D
DDR_B_D1 DQ0 DQ5
(8) DDR_B_DQS[0..7] 7 8
DQ1 VSS3 DDR_B_DQS#0
1 1 9 10
VSS4 DQS#0 DDR_B_DQS0 +1.5V_SUS decoupling caps be located at the VDD pins of each SO-DIMM connector in the
(8) DDR_B_D[0..63] 11 12
DM0 DQS0 vicinity of the CMD, Clock and Control signals
13 14
DDR_B_D2 VSS5 VSS6 DDR_B_D6
(8) DDR_B_MA[0..15] 15 16 Those capacitors should be placed on the same side of the motherboard as the
2 2 DDR_B_D3 DQ2 DQ6 DDR_B_D7

CD27

CD26
17 18 SO-DIMM connector
DQ3 DQ7
19 20
DDR_B_D8 VSS7 VSS8 DDR_B_D12
21 22
DDR_B_D9 DQ8 DQ12 DDR_B_D13
23 24
DQ9 DQ13
25 26
D
DDR_B_DQS#1 VSS9 VSS10 D
27
DQS#1 DM1
28 Layout Note:
DDR_B_DQS1 29 30 DDR3_DRAMRST# DDR3_DRAMRST# (7,12)
Note: 31
DQS1 RESET#
32 Place near JDIMMB
All VREF traces should have 10 mil trace width DDR_B_D10 VSS11 VSS12 DDR_B_D14
33 34
Check voltage tolerance of DDR_B_D11 35
DQ10 DQ14
36 DDR_B_D15
DQ11 DQ15
VREF_DQ at the DIMM socket 37
VSS13 VSS14
38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 42
DQ17 DQ21
43 44
DDR_B_DQS#2 VSS15 VSS16
45 46
DDR_B_DQS2 DQS#2 DM2 +1.5V
47 48
DQS2 VSS17 DDR_B_D22
49 50
DDR_B_D18 VSS18 DQ22 DDR_B_D23
51 52
DDR_B_D19 DQ18 DQ23
53 54
DQ19 VSS19 DDR_B_D28
All VREF traces should 55 56

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
DDR_B_D24 VSS20 DQ28 DDR_B_D29
have 10 mil trace width 57 58 1 1 1 1
DDR_B_D25 DQ24 DQ29
59 60
DQ25 VSS21 DDR_B_DQS#3
61 62
VSS22 DQS#3 DDR_B_DQS3
63 64
DM3 DQS3 2 2 2 2

CD28

CD29

CD30

CD31
65 66
DDR_B_D26 VSS23 VSS24 DDR_B_D30
67 68
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 70
DQ27 DQ31
71 72
VSS25 VSS26

(8) DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB DDR_CKE3_DIMMB (8)

CKE0 CKE1 +1.5V
75 76
VDD1 VDD2 DDR_B_MA15
77 78
DDR_B_BS2 NC1 A15 DDR_B_MA14
(8) DDR_B_BS2 79 80
BA2 A14
81 82
DDR_B_MA12 VDD3 VDD4 DDR_B_MA11
83 84

330U_SX_2VY~D
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 86
A9 A7
87 88 1
DDR_B_MA8 VDD5 VDD6 DDR_B_MA6
89 90 1 1 1 1 1 1 1
DDR_B_MA5 A8 A6 DDR_B_MA4 @ @ +
91 92
A5 A4
93 94
DDR_B_MA3 VDD7 VDD8 DDR_B_MA2
C 95 96 C
DDR_B_MA1 A3 A2 DDR_B_MA0 2 2 2 2 2 2 2 2

CD32

CD33

CD34

CD35

CD36

CD37

CD38

CD39
97 98
A1 A0
99 100
M_CLK_DDR2 VDD9 VDD10 M_CLK_DDR3
(8) M_CLK_DDR2 101 102 M_CLK_DDR3 (8)
M_CLK_DDR#2 CK0 CK1 M_CLK_DDR#3
(8) M_CLK_DDR#2 103 104 M_CLK_DDR#3 (8)
CK0# CK1# +1.5V
105 106
DDR_B_MA10 VDD11 VDD12 DDR_B_BS1
107 108 DDR_B_BS1 (8)
DDR_B_BS0 A10/AP BA1 DDR_B_RAS#
(8) DDR_B_BS0 109 110 DDR_B_RAS# (8)
BA0 RAS#
111 112
VDD13 VDD14

1
(8) DDR_B_WE# DDR_B_WE# 113 114 DDR_CS2_DIMMB# DDR_CS2_DIMMB# (8)
DDR_B_CAS# WE# S0# M_ODT2 RD17
(8) DDR_B_CAS# 115 116 M_ODT2 (8)
CAS# ODT0 1K_0402_1%~D
117 118
DDR_B_MA13 VDD15 VDD16 M_ODT3
119
A13 ODT1
120 M_ODT3 (8) Layout Note:
(8) DDR_CS3_DIMMB# DDR_CS3_DIMMB# 121 122

2
123
S1# NC2
124 Place near JDIMMB.203,204
VDD17 VDD18 +VREF_CB
125 126
NCTEST VREF_CA
127 128
DDR_B_D32 VSS27 VSS28 DDR_B_D36
129 130

2.2U_0402_6.3V6M~D

0.1U_0402_16V7K~D
DQ32 DQ36

1
DDR_B_D33 131 132 DDR_B_D37
DQ33 DQ37 RD18
133 134 1 1
DDR_B_DQS#4 VSS29 VSS30 1K_0402_1%~D
135 136
DDR_B_DQS4 DQS#4 DM4
137 138
DQS4 VSS31 DDR_B_D38 +0.75VS
139 140

2
DDR_B_D34 VSS32 DQ38 DDR_B_D39 2 2

CD40

CD41
141 142
DDR_B_D35 DQ34 DQ39
143 144
DQ35 VSS33 DDR_B_D44
145 146
DDR_B_D40 VSS34 DQ44 DDR_B_D45
147 148
DDR_B_D41 DQ40 DQ45
149 150

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
DQ41 VSS35 DDR_B_DQS#5
151 152 1 1 1 1
VSS36 DQS#5 DDR_B_DQS5
153 154
DM5 DQS5
155 156
DDR_B_D42 VSS37 VSS38 DDR_B_D46
157 158
DDR_B_D43 DQ42 DQ46 DDR_B_D47 2 2 2 2

CD42

CD43

CD44

CD45
159 160
DQ43 DQ47
161 162
DDR_B_D48 VSS39 VSS40 DDR_B_D52
163 164
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 166
DQ49 DQ53
167 168
DDR_B_DQS#6 VSS41 VSS42
169 170
B
DDR_B_DQS6 DQS#6 DM6 B
171 172
DQS6 VSS43 DDR_B_D54
173 174
DDR_B_D50 VSS44 DQ54 DDR_B_D55
175 176
DDR_B_D51 DQ50 DQ55
177 178
DQ51 VSS45 DDR_B_D60
179 180
DDR_B_D56 VSS46 DQ60 DDR_B_D61
181 182
DDR_B_D57 DQ56 DQ61
183 184
DQ57 VSS47 DDR_B_DQS#7
185 186
VSS48 DQS#7 DDR_B_DQS7
187 188
DM7 DQS7
189 190
DDR_B_D58 VSS49 VSS50 DDR_B_D62
191 192
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 194
DQ59 DQ63
195 196
+3VS VSS51 VSS52
197 198
SA0 EVENT# PCH_SMBDATA
+3VS 199 200 PCH_SMBDATA (6,12,15,38,45)
VDDSPD SDA PCH_SMBCLK
2 1 201 202 PCH_SMBCLK (6,12,15,38,45)
SA1 SCL
+0.75VS 203 204 +0.75VS
VTT1 VTT2
1

RD19
10K_0402_5%~D

10K_0402_5%~D 205 206

G1 G2
RD20

1 1
0.1U_0402_16V7K~D

2.2U_0402_6.3V6M~D
2

2 2 CONN@
CD46

CD47

M1 +1.5V

1
RD15
1K_0402_1%~D +V_DDR_REFB

2
RD11 1 SHORT 2 0_0402_5%~D

1
A Item3_X02 A

RD16
1K_0402_1%~D

2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII DIMMB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 13 of 63
5 4 3 2 1
 5 4 3 2 1

+3VS

2 1 18P_0402_50V8J~D PCH_RTCX1 SERIRQ RH29 2 1 10K_0402_5%~D

CH2
PCH_GPIO21 RH32 2 1 10K_0402_5%~D

1
1
PCH_SATALED# RH35 2 1 10K_0402_5%~D
YH1 RH2
32.768KHZ_12.5PF_9H03200019 10M_0402_5%

2
2 1 PCH_RTCX2
CH3 15P_0402_50V8J~D UH1A HDA_SYNC
D D
far away hot spot
Item15_X03 A20 C38 LPC_AD0 This signal has a weak internal pull-down
RTCX1 FWH0 / LAD0 LPC_AD0 (47)
A38 LPC_AD1 On Die PLL VR is supplied by
FWH1 / LAD1 LPC_AD1 (47)
C20 B37 LPC_AD2

LPC
RTCX2 FWH2 / LAD2 LPC_AD3
LPC_AD2 (47) 1.5V when smapled high
C37 LPC_AD3 (47)
PCH_RTCRST# FWH3 / LAD3 1.8V when sampled low
D20
RTCRST# LPC_FRAME# Needs to be pulled High for Huron River platfrom
D36 LPC_FRAME# (47)
PCH_SRTCRST# FWH4 / LFRAME#
G22
+RTCVCC CMOS SRTCRST# +3V_PCH
1 E36
LDRQ0#
1

+RTCVCC RH11 1 2 SM_INTRUDER# K22 K36

RTC
CH4 CLRP1 @ 1M_0402_5%~D INTRUDER# LDRQ1# / GPIO23
1U_0402_6.3V6K~D SHORT PADS PCH_INTVRMEN C17 V5 SERIRQ SERIRQ (47) HDA_SYNC RH52 2 1 1K_0402_5%~D
2

2 PCH_RTCRST# INTVRMEN SERIRQ

1 2
RH25 20K_0402_5%~D
1 2 PCH_SRTCRST# AM3 SATA_PRX_DTX_N0 (45)
RH23 20K_0402_5%~D 1 HDA_BIT_CLK SATA0RXN
(41) HDA_BITCLK_AUDIO 1 2 N34 AM1 SATA_PRX_DTX_P0 (45)
HDA_BCLK SATA0RXP
1

RH27 33_0402_5%~D AP7 SATA_PTX_DRX_N0 CH91 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N0_C (45) HDD1

SATA0TXN

SATA 6G
CH5 CLRP2 @ HDA_SYNC L34 AP5 SATA_PTX_DRX_P0 CH90 1 2 0.01U_0402_16V7K~D
HDA_SYNC SATA0TXP SATA_PTX_DRX_P0_C (45)
1U_0402_6.3V6K~D SHORT PADS
2

2 ME CMOS HDA_SPKR T10 AM10

(41) HDA_SPKR SPKR SATA1RXN SATA_PRX_DTX_N1 (38)
AM8 SATA_PRX_DTX_P1 (38)
CLP1 & CLP2 place near DIMM HDA_RST# SATA1RXP
(41) HDA_RST_AUDIO# 1 2 K34
HDA_RST# SATA1TXN
AP11 SATA_PTX_DRX_N1 (38) mSATA +3VS
RH28 33_0402_5%~D AP10
SATA1TXP SATA_PTX_DRX_P1 (38)

(41) HDA_SDIN0 HDA_SDIN0 E34 AD7 SATA_PRX_DTX_N2 (45)

HDA_SDIN0 SATA2RXN HDA_SPKR RH37 @
AD5 SATA_PRX_DTX_P2 (45) 2 1 1K_0402_5%~D
SATA2RXP
G34 AH5 SATA_PTX_DRX_N2 CH92 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N2_RP (45) ODD
+RTCVCC HDA_SDIN1 SATA2TXN
C34
HDA_SDIN2
SATA2TXP
AH4 SATA_PTX_DRX_P2 CH93 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P2_RP (45) *LOW=Default
HIGH=No Reboot
AB8

IHDA
PCH_INTVRMEN SATA3RXN
1 2 A34 AB10
RH31 330K_0402_5%~D HDA_SDIN3 SATA3RXP
Item10_X01 AF3
@ PCH_INTVRMEN SATA3TXN
1 2 AF1
RH34 330K_0402_5%~D HDA_SDOUT SATA3TXP
(47) HDA_SDO 1 2 A36
RH24 1K_0402_5%~D HDA_SDO
Y7

* HL：

SATA
SATA4RXN
INTVRMEN 1 2 Y5

：Integrated
(41) HDA_SDOUT_AUDIO SATA4RXP
VRM enable RH30 33_0402_5%~D C36 AD3
HDA_DOCK_EN# / GPIO33 SATA4TXN
C Integrated VRM disable AD1 C

HDA_SDO
DP_PCH_HPD SATA4TXP
(35) DP_PCH_HPD N32
HDA_DOCK_RST# / GPIO13
Y3
SATA5RXN
Y1
SATA5RXP
+3V_PCH SATA5TXN
AB3 ME debug mode , this signal has a weak internal PD
(6) PCH_JTAG_TCK PCH_JTAG_TCK J3 AB1
JTAG_TCK SATA5TXP
+1.05VS_VCC_SATA
L=>security measures defined in the Flash
PCH_JTAG_TMS H7 Y11
(6) PCH_JTAG_TMS JTAG_TMS SATAICOMPO Descriptor will be in effect (default)

JTAG
PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
200_0402_5%

200_0402_5%

200_0402_5%

(6) PCH_JTAG_TDI JTAG_TDI SATAICOMPI

1

RH41 37.4_0402_1% H=>Flash Descriptor Security will be overridden

PCH_JTAG_TDO H1 Width = 10 mil, Spacing = 20 mil
(6) PCH_JTAG_TDO JTAG_TDO +1.05VS_SATA3
@ @ @ AB12 Close PCH within 500 mil
SATA3RCOMPO
SATA3_COMP
RH38

RH40

RH39

AB13 1 2
2

PCH_JTAG_TCK SATA3COMPI RH43 49.9_0402_1% +3V_PCH

PCH_JTAG_TMS
Item10_X01
PCH_JTAG_TDI PCH_SPI_CLK_R 1 2 PCH_SPI_CLK T3 AH1 RBIAS_SATA3 1 2
PCH_JTAG_TDO RH255 33_0402_5%~D SPI_CLK SATA3RBIAS RH48 750_0402_1%~D HDA_SDOUT RH42 @
2 1 1K_0402_5%~D
PCH_SPI_CS# Y14
SPI_CS0#
*Low = Disabled
100_0402_1%~D

100_0402_1%~D

100_0402_1%~D
1

T1 High = Enabled
51_0402_5%

SPI_CS1# PCH_SATALED#
P3

SPI
SATALED# PCH_SATALED# (49)
PCH_SPI_SI PCH_GPIO21 +3VS
RH44

RH46

RH45

RH53

V4 V14
SPI_MOSI SATA0GP / GPIO21
2

PCH_SPI_SO U3 P1 BBS_BIT0_R 2 1
SPI_MISO SATA1GP / GPIO19 RH276 10K_0402_5%~D

BD82PPSM-QNHN-A0_BGA989~D

+5VS
2
G

QH1
B B

(41) HDA_SYNC_AUDIO 1
RH33
2 HDA_SYNC_R
33_0402_5%~D
3 1 HDA_SYNC
+3V_PCH Item1_X03 RTC Battery
S

QH1 BSS138_NL_SOT23-3

SPI ROM FOR ME ( 8MByte )

2

1 2
RH36 @ 0_0402_5%~D
+RTCBATT
2

2
3.3K_0402_5%

3.3K_0402_5%

RH275

SPI ROM FOR ME

1M_0402_5%~D
1

2
( 8MByte )
1

+3VLP RH259
RH54

RH57

+3V_PCH Item1_X03 1K_0402_5%~D

U48

1
PCH_SPI_CS# 1 SHORT 2 PCH_SPI_CS#_R 1 8 W=20mils
RH58 0_0402_5%~D /CS VCC
W=20mils

2
PCH_SPI_SO 1 SHORT 2 PCH_SPI_SO_R 2 7 PCH_SPI_HOLD# 1 2 1
RH60 0_0402_5%~D DO /HOLD RH56 3.3K_0402_5% CH6 DH4
Item3_X02 PCH_SPI_WP# 3 6 PCH_SPI_CLK_R 0.1U_0402_16V7K~D BAT54CW_SOT323-3
/WP CLK
4 5 PCH_SPI_SI_R 1 SHORT 2 PCH_SPI_SI 2
GND DIO RH63 0_0402_5%~D

1
W25Q64FVSSIG_SO8
Item3_X02 +RTCVCC
W=20mils 1
SPI BIOS Pinout
CH95
1U_0402_6.3V6K~D
(1)CS# (5)I/O_0 2
(2)I/O_1(6)CLK
@
(3)WP# (7)HOLD#
2 1 PCH_SPI_CLK (4)GND (8)VCC
CH98 10P_0402_50V8J~D

A W25Q64 A
Reserve for RF please close to UH1

@
2 1 HDA_SDOUT
CH103 10P_0402_50V8J~D
@
2 1 HDA_BIT_CLK @ CH94 @ RH256
Security Classification Compal Secret Data Compal Electronics, Inc.
CH97 10P_0402_50V8J~D 2 1 1 2 PCH_SPI_CLK_R 2011/06/02 2012/06/02 Title
Issued Date Deciphered Date
22P_0402_50V8J~D 33_0402_5%~D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (1/8) SATA,HDA,SPI, LPC
Reserve for RF please close to UH1 Reserve for EMI please close to U48 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 14 of 63
5 4 3 2 1
 5 4 3 2 1

Item3_X02 +3V_PCH
Place TX DC blocking caps close PCH.
UH1B 1 SHORT 2 EC_LID_OUT#
EC_LID_OUT# (47)
RH68 0_0402_5%~D SMBCLK 1 2
(39) PCIE_PRX_GLANTX_N3 PCIE_PRX_GLANTX_N3 BG34 RH67 2.2K_0402_5%~D
PCIE_PRX_GLANTX_P3 PERN1 PCH_LID_SW_IN# @ LID_SW_IN# SMBDATA
(39) PCIE_PRX_GLANTX_P3 BJ34 E12 1 2 LID_SW_IN# (47,48,49) 1 2
CH9 1 PCIE_PTX_GLANRX_N3_C PERP1 SMBALERT# / GPIO11
10/100/1G LAN ---> (39) PCIE_PTX_GLANRX_N3 2 0.1U_0402_10V7K~D AV32 RH71 0_0402_5%~D RH69 2.2K_0402_5%~D
CH14 1 PETN1
(39) PCIE_PTX_GLANRX_P3 2 0.1U_0402_10V7K~D PCIE_PTX_GLANRX_P3_C AU32 H14 SMBCLK SML0CLK 1 2
PETP1 SMBCLK RH70 2.2K_0402_5%~D
PCIE_PRX_WANTX_N2 SMBDATA
MEMORY SML0DATA
(38) PCIE_PRX_WANTX_N2 BE34 C9 1 2
PCIE_PRX_WANTX_P2 PERN2 SMBDATA RH72 2.2K_0402_5%~D
(38) PCIE_PRX_WANTX_P2 BF34
MiniDMC (Mini Card 2)---> CH10 1 PCIE_PTX_WANRX_N2_C PERP2 SML1CLK
(38) PCIE_PTX_WANRX_N2 2 0.1U_0402_10V7K~D BB32 1 2
CH15 1 PETN2
(38) PCIE_PTX_WANRX_P2 2 0.1U_0402_10V7K~D PCIE_PTX_WANRX_P2_C AY32 RH73 2.2K_0402_5%~D
PETP2 DRAMRST_CNTRL_PCH SML1DATA
A12 1 2

SMBUS
SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH (7,12)
(38) PCIE_PRX_WLANTX_N1 PCIE_PRX_WLANTX_N1 BG36 RH74 2.2K_0402_5%~D
D
PCIE_PRX_WLANTX_P1 PERN3 SML0CLK LID_SW_IN# @
D
(38) PCIE_PRX_WLANTX_P1 BJ36 C8 1 2
CH11 1 PCIE_PTX_WLANRX_N1_C PERP3 SML0CLK
MiniWLAN (Mini Card 1)---> (38) PCIE_PTX_WLANRX_N1 2 0.1U_0402_10V7K~D AV34 R1790 10K_0402_5%~D
CH16 1 PETN3
(38) PCIE_PTX_WLANRX_P1 2 0.1U_0402_10V7K~D PCIE_PTX_WLANRX_P1_C AU34 G12 SML0DATA DRAMRST_CNTRL_PCH 1 2
PETP3 SML0DATA RH75 1K_0402_5%~D
(40) PCIE_PRX_CARDTX_N4 PCIE_PRX_CARDTX_N4 BF36 GPIO74 1 2
PCIE_PRX_CARDTX_P4 PERN4 R1793 10K_0402_5%~D
(40) PCIE_PRX_CARDTX_P4 BE36
CARD_READER ---> CH12 1 PCIE_PTX_CARDRX_N4_C PERP4 GPIO74 PCH_LID_SW_IN#
(40) PCIE_PTX_CARDRX_N4 2 0.1U_0402_10V7K~D AY34 C13 1 2
CH13 1 PETN4 SML1ALERT# / PCHHOT# / GPIO74
(40) PCIE_PTX_CARDRX_P4 2 0.1U_0402_10V7K~D PCIE_PTX_CARDRX_P4_C BB34 RH280 10K_0402_5%~D
PETP4 SML1CLK
E14
SML1CLK / GPIO58
BG37

PCI-E*
PERN5 SML1DATA
BH37 M16
PERP5 SML1DATA / GPIO75 CLKIN_DMI2# RH76 10K_0402_5%~D
AY36 1 2
PETN5 CLKIN_DMI2 RH78 10K_0402_5%~D
BB36 1 2
PETP5 CLKIN_DMI# RH77 10K_0402_5%~D
1 2
BJ38 CLKIN_DMI RH79 1 2 10K_0402_5%~D
PERN6 CLKIN_DOT96# RH80 10K_0402_5%~D
BG38 1 2
PERP6 CLKIN_DOT96 RH81 10K_0402_5%~D
AU36 M7 1 2

Controller
PETN6 CL_CLK1 CLKIN_SATA# RH82 10K_0402_5%~D
AV36 1 2
PETP6 CLKIN_SATA RH83 10K_0402_5%~D
1 2
BG40 T11 +3V_PCH CLK_PCH_14M RH84 1 2 10K_0402_5%~D

Link
PERN7 CL_DATA1
BJ40
PERP7 No support iAMT If use extenal CLK gen, please
AY40
BB40
PETN7
P10 place close to CLK gen
PETP7 CL_RST1#

2
else, please place close to PCH
BE38 RH141
PERN8
BC38 10K_0402_5%~D
PERP8
AW38
PETN8
AY38

1
PETP8 @
M10 PEG_A_CLKRQ# PEG_A_CLKRQ# (22) CLK_PCH_14M 2 @ 1 CH21 1 2
PAD~D T81 PEG_A_CLKRQ# / GPIO47 RH86 33_0402_5%~D 22P_0402_50V8J~D
Y40
CLKOUT_PCIE0N
PAD~D T82 Y39
CLKOUT_PCIE0P
Reserve for EMI please close to UH1
AB37 CLK_PEG_VGA# CLK_PEG_VGA# (22) @
RH91 1 GPIO73 CLKOUT_PEG_A_N CLK_PEG_VGA CLK_PCI_LPBACK 2
+3V_PCH 2 10K_0402_5%~D J2 AB38 CLK_PEG_VGA (22) @ 1 CH22 1 2

CLOCKS
PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P RH89 33_0402_5%~D 22P_0402_50V8J~D
Reserve for EMI please close to UH1
RH93 2 SHORT 1 0_0402_5%~D PCIE_LAN# AB49 AV22 CLK_CPU_DMI#
(39) CLK_PCIE_LAN# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# (7)
C 10/100/1G LAN ---> RH94 2 SHORT 1 0_0402_5%~D PCIE_LAN AB47 AU22 CLK_CPU_DMI C
(39) CLK_PCIE_LAN CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI (7)
+3VS RH95 2 1 10K_0402_5%~D
(39) LANCLK_REQ# LANCLK_REQ# M1
PCIECLKRQ1# / GPIO18 T53 PAD~D
AM12
CLKOUT_DP_N T52 PAD~D
AM13
RH96 CLKOUT_DP_P
(38) CLK_PCIE_MINI2# 2 SHORT 1 0_0402_5%~D PCIE_MINI2# AA48
RH97 PCIE_MINI2 CLKOUT_PCIE2N
(38) CLK_PCIE_MINI2 2 SHORT 1 0_0402_5%~D AA47
RH100 CLKOUT_PCIE2P
MiniDMC (Mini Card 2)---> +3VS 2 1 10K_0402_5%~D BF18 CLKIN_DMI#
MINI2CLK_REQ# CLKIN_DMI_N CLKIN_DMI
(38) MINI2CLK_REQ# V10 BE18
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P XTAL25_IN

RH101 2 SHORT 1 0_0402_5%~D PCIE_MINI1# Y37 BJ30 CLKIN_DMI2#

(38) CLK_PCIE_MINI1# CLKOUT_PCIE3N CLKIN_GND1_N
RH102 2 SHORT 1 0_0402_5%~D PCIE_MINI1 Y36 BG30 CLKIN_DMI2
(38) CLK_PCIE_MINI1 CLKOUT_PCIE3P CLKIN_GND1_P
MiniWLAN (Mini Card 1)---> +3V_PCH RH103 2 1 10K_0402_5%~D XTAL25_OUT 1 2
(38) MINI1CLK_REQ# MINI1CLK_REQ# A8 RH117 1M_0402_5%~D
PCIECLKRQ3# / GPIO25 CLKIN_DOT96#
G24
CLKIN_DOT_96N CLKIN_DOT96
E24
RH104 CLKIN_DOT_96P
(40) CLK_PCIE_CD# 2 SHORT 1 0_0402_5%~D PCIE_CD# Y43 YH2
RH106 PCIE_CD CLKOUT_PCIE4N
(40) CLK_PCIE_CD 2 SHORT 1 0_0402_5%~D Y45 1 3
RH107 CLKOUT_PCIE4P CLKIN_SATA# IN OUT
Card Reader ---> +3V_PCH 2 1 10K_0402_5%~D AK7
CDCLK_REQ# CLKIN_SATA_N CLKIN_SATA
(40) CDCLK_REQ# L12 AK5 2 4
PCIECLKRQ4# / GPIO26 CLKIN_SATA_P GND GND
1 1
25MHZ_12PF_X3G025000DC1H~D
Item3_X02 V45 K45 CLK_PCH_14M CH24 CH23
CLKOUT_PCIE5N REFCLK14IN 15P_0402_50V8J~D 15P_0402_50V8J~D
V46
CLKOUT_PCIE5P 2 2
+3V_PCH RH110 1 2 10K_0402_5%~D L14 H45 CLK_PCI_LPBACK
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK (17)

XTAL25_IN
Item27_X01
AB42 V47
CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT
AB40 V49
CLKOUT_PEG_B_P XTAL25_OUT
+3V_PCH RH112 1 2 10K_0402_5%~D GPIO56 E6
PEG_B_CLKRQ# / GPIO56
Y47 XCLK_RCOMP 1 2 +1.05VS_VCCDIFFCLKN
XCLK_RCOMP RH113 90.9_0402_1%
V40
CLKOUT_PCIE6N Width = 10 mil, Spacing = 20 mil
V42
CLKOUT_PCIE6P +3VS
Close PCH within 500 mil
B B
+3V_PCH RH116 1 2 10K_0402_5%~D GPIO45 T13 Item6_X01
PCIECLKRQ6# / GPIO45 GPIO64
Item6_X01 1 2
V38 K43 GPIO64 R1791 100K_0402_5%~D
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 DMC_PCH_DET#
V37 1 2
FLEX CLOCKS

CLKOUT_PCIE7P DMC_PCH_DET# RH109 10K_0402_5%~D

F47 DMC_PCH_DET# (38)
RH118 1 GPIO46 CLKOUTFLEX1 / GPIO65 BT_DET#
+3V_PCH 2 10K_0402_5%~D K12 1 2
PCIECLKRQ7# / GPIO46 BT_DET# RH108 10K_0402_5%~D
H47 BT_DET# (38)
CLK_CPU_ITP# RH119 CLKOUTFLEX2 / GPIO66
(6) CLK_CPU_ITP# 2 SHORT 1 0_0402_5%~D CLK_BCLK_ITP# AK14 CAM_DET# 1 2
CLK_CPU_ITP RH120 CLK_BCLK_ITP CLKOUT_ITPXDP_N CAM_DET#
(6) CLK_CPU_ITP 2 SHORT 1 0_0402_5%~D AK13 K49 CAM_DET# (33)
RH166 10K_0402_5%~D
CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67

RH121 2 @ 1 0_0402_5%~D BD82PPSM-QNHN-A0_BGA989~D

(9) CLK_RES_ITP#
RH122 2 @ 1 0_0402_5%~D
(9) CLK_RES_ITP

+3VS +3VS
Item3_X02

+3VS

2
RH98 RH99
2.2K_0402_5%~D 2.2K_0402_5%~D
2

2
QH3A

1
SML1CLK 6 1 SMBCLK 6 1
EC_SMB_CK2 (22,23,41,43,46,47,53) PCH_SMBCLK (6,12,13,38,45)
DMN66D0LDW-7_SOT363-6~D DMN66D0LDW-7_SOT363-6~D
QH4A
5

1 @ 2

5
0_0402_5%~D RH105 QH3B
SML1DATA 3 4 EC_SMB_DA2 (22,23,41,43,46,47,53)
A SMBDATA 3 4 A
DMN66D0LDW-7_SOT363-6~D PCH_SMBDATA (6,12,13,38,45)
QH4B
DMN66D0LDW-7_SOT363-6~D

1 @ 2
0_0402_5%~D RH111

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (2/8) PCIE, SMBUS, CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 15 of 63
5 4 3 2 1
 5 4 3 2 1

UH1C

(6) DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0 FDI_CTX_PRX_N0 (6) UH1D

DMI_CTX_PRX_N1 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N1 IGPU_BKLT_EN
(6) DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1 (6) (47) IGPU_BKLT_EN J47 AP43
DMI_CTX_PRX_N2 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N2 PCH_ENVDD L_BKLTEN SDVO_TVCLKINN
(6) DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2 (6) (33,47) PCH_ENVDD M45 AP45
DMI_CTX_PRX_N3 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N3 L_VDD_EN SDVO_TVCLKINP
(6) DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3 (6)
DMI3RXN FDI_RXN3 FDI_CTX_PRX_N4
BC12 FDI_CTX_PRX_N4 (6) (33) PCH_INV_PWM P45 AM42
DMI_CTX_PRX_P0 FDI_RXN4 FDI_CTX_PRX_N5 L_BKLTCTL SDVO_STALLN
(6) DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5 (6) AM40
DMI_CTX_PRX_P1 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N6 PCH_LCD_CLK SDVO_STALLP
(6) DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6 (6) (33) PCH_LCD_CLK T40
DMI_CTX_PRX_P2 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N7 PCH_LCD_DATA L_DDC_CLK
(6) DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7 (6) (33) PCH_LCD_DATA K47 AP39
DMI_CTX_PRX_P3 DMI2RXP FDI_RXN7 L_DDC_DATA SDVO_INTN
(6) DMI_CTX_PRX_P3 BJ20 AP40
DMI3RXP FDI_CTX_PRX_P0 CTRL_CLK SDVO_INTP
BG14 FDI_CTX_PRX_P0 (6) T45
DMI_CRX_PTX_N0 FDI_RXP0 FDI_CTX_PRX_P1 CTRL_DATA L_CTRL_CLK
(6) DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1 (6) P39
DMI_CRX_PTX_N1 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P2 L_CTRL_DATA
(6) DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2 (6)
D
DMI_CRX_PTX_N2 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P3 RH144 LVDS_IBG PCH_HDMI_CLK D
(6) DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 (6) 1 2 2.37K_0402_1%~D AF37 P38 PCH_HDMI_CLK (36)
DMI_CRX_PTX_N3 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P4 PAD~D T203 LVD_IBG SDVO_CTRLCLK PCH_HDMI_DAT
(6) DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4 (6) AF36 M39 PCH_HDMI_DAT (36)
DMI3TXN FDI_RXP4 FDI_CTX_PRX_P5 LVD_VBG SDVO_CTRLDATA
BG12

DMI
FDI
FDI_RXP5 FDI_CTX_PRX_P5 (6)
DMI_CRX_PTX_P0 AY24 BJ10 FDI_CTX_PRX_P6 FDI_CTX_PRX_P6 (6) AE48
(6) DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6 LVD_VREFH
DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 FDI_CTX_PRX_P7 (6) AE47 AT49
(6) DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 LVD_VREFL DDPB_AUXN
DMI_CRX_PTX_P2 AY18 AT47
(6) DMI_CRX_PTX_P2 DMI2TXP DDPB_AUXP
DMI_CRX_PTX_P3 AU18 AT40 PCH_HDMI_HPD
(6) DMI_CRX_PTX_P3 DMI3TXP DDPB_HPD PCH_HDMI_HPD (36)
AW16 FDI_INT PCH_TXCLK- AK39
FDI_INT FDI_INT (6) (33) PCH_TXCLK- LVDSA_CLK#
PCH_TXCLK+ AK40 AV42 PCH_HDMI_TXD0-

LVDS
+1.05VS (33) PCH_TXCLK+ LVDSA_CLK DDPB_0N PCH_HDMI_TXD0- (36)
BJ24 AV12 FDI_FSYNC0 AV40 PCH_HDMI_TXD0+
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 (6) DDPB_0P PCH_HDMI_TXD0+ (36)
Width = 4 mil, Spacing = 20 mil PCH_TXOUT0- PCH_HDMI_TXD1-
Close PCH within 500 mil 1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1
(33) PCH_TXOUT0-
PCH_TXOUT1-
AN48
AM47
LVDSA_DATA#0 HDMI DDPB_1N
AV45
AV46 PCH_HDMI_TXD1+
PCH_HDMI_TXD1- (36)
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 (6) (33) PCH_TXOUT1- LVDSA_DATA#1 DDPB_1P PCH_HDMI_TXD1+ (36)
RH124 49.9_0402_1% PCH_TXOUT2- PCH_HDMI_TXD2-

Digital Display Interface

(33) PCH_TXOUT2- AK47 AU48 PCH_HDMI_TXD2- (36)
RBIAS_CPY FDI_LSYNC0 LVDSA_DATA#2 DDPB_2N PCH_HDMI_TXD2+
1 2 BH21 AV14 FDI_LSYNC0 (6) AJ48 AU47 PCH_HDMI_TXD2+ (36)
RH125 750_0402_1%~D DMI2RBIAS FDI_LSYNC0 LVDSA_DATA#3 DDPB_2P PCH_HDMI_TXC-
AV47 PCH_HDMI_TXC- (36)
FDI_LSYNC1 PCH_TXOUT0+ DDPB_3N PCH_HDMI_TXC+
4mil width and place FDI_LSYNC1
BB10 FDI_LSYNC1 (6) (33) PCH_TXOUT0+ AN47
LVDSA_DATA0 DDPB_3P
AV49 PCH_HDMI_TXC+ (36)
PCH_TXOUT1+ AM49
within 500mil of the PCH (33) PCH_TXOUT1+
PCH_TXOUT2+ AK49
LVDSA_DATA1
(33) PCH_TXOUT2+ LVDSA_DATA2
AJ47 P46
Deep Sleep not implemented DSWODVREN LVDSA_DATA3 DDPC_CTRLCLK
A18 P42
DSWVRMEN DDPC_CTRLDATA
SUSACK# unconnected Item3_X02 PCH_TZCLK- AF40
(33) PCH_TZCLK- LVDSB_CLK#

System Power Management

C12 E22 PCH_DPWROK 1 SHORT 2 PCH_RSMRST#_R PCH_TZCLK+ AF39 AP47
SUSACK# DPWROK (33) PCH_TZCLK+ LVDSB_CLK DDPC_AUXN
RH126 0_0402_5%~D AP49
PCH_TZOUT0- DDPC_AUXP
(33) PCH_TZOUT0- AH45 AT38
XDP_DBRESET# WAKE# PCH_TZOUT1- LVDSB_DATA#0 DDPC_HPD
(6,7) XDP_DBRESET# K3 B9 2 SHORT 1 PCIE_WAKE# (38,39,47)
(33) PCH_TZOUT1- AH47
SYS_RESET# WAKE# RH128 0_0402_5%~D PCH_TZOUT2- LVDSB_DATA#1
(33) PCH_TZOUT2- AF49 AY47
LVDSB_DATA#2 DDPC_0N
AF45 AY49
LVDSB_DATA#3 DDPC_0P
(6,59) VGATE 1 SHORT 2 SYS_PWROK P12 N3 PM_CLKRUN# AY43
RH273 0_0402_5%~D SYS_PWROK CLKRUN# / GPIO32 PCH_TZOUT0+ DDPC_1N
(33) PCH_TZOUT0+ AH43 AY45
PCH_TZOUT1+ LVDSB_DATA0 DDPC_1P
PCH_PWROK 2 SHORT 1 PM_PWROK_R L22 G8 SUS_STAT# T76 PAD~D
(33) PCH_TZOUT1+
PCH_TZOUT2+
AH49
AF47
LVDSB_DATA1 mDP DDPC_2N
BA47
BA48
(7,47) PCH_PWROK PWROK SUS_STAT# / GPIO61 (33) PCH_TZOUT2+ LVDSB_DATA2 DDPC_2P
RH130 0_0402_5%~D AF43 BB47
LVDSB_DATA3 DDPC_3N
BB49
DDPC_3P
(47) PCH_APWROK 2 SHORT 1 L10 N14 SUSCLK 2 SHORT 1 SUSCLK_R (47)
RH131 0_0402_5%~D APWROK SUSCLK / GPIO62 RH132 0_0402_5%~D
PCH_CRT_B N48 M43 PCH_DPD_CLK PCH_DPD_CLK (37)
(34) PCH_CRT_B CRT_BLUE DDPD_CTRLCLK
C PM_DRAM_PWRGD B13 D10 PM_SLP_S5# PCH_CRT_G P49 M36 PCH_DPD_DAT PCH_DPD_DAT (37) C
(7) PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# (47,48) (34) PCH_CRT_G CRT_GREEN DDPD_CTRLDATA
PCH_CRT_R T49
(34) PCH_CRT_R CRT_RED

(47) PCH_RSMRST# 2 SHORT 1PCH_RSMRST#_R C21 H4 PM_SLP_S4#

PM_SLP_S4# (47) AT45 PCH_DPD_AUXN
PCH_DPD_AUXN (37)
RH133 0_0402_5%~D RSMRST# SLP_S4# PCH_CRT_DDC_CLK DDPD_AUXN PCH_DPD_AUXP
T39 AT43

CRT
(34) PCH_CRT_DDC_CLK CRT_DDC_CLK DDPD_AUXP PCH_DPD_AUXP (37)
PCH_CRT_DDC_DATA M40 BH41 PCH_DMC_HPD
(34) PCH_CRT_DDC_DATA CRT_DDC_DATA DDPD_HPD PCH_DMC_HPD (37)
SUSPWRDNACK K16 F4 PM_SLP_S3#
(47) SUSPWRDNACK SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# (47,48)
BB43 PCH_DPD_N0
DDPD_0N PCH_DPD_N0 (37)
RH136 1 2 33_0402_5%~D HSYNC M47 BB45 PCH_DPD_P0
2 SHORT 1 PBTN_OUT#_R
(34) PCH_CRT_HSYNC
RH138 2 33_0402_5%~D VSYNC
CRT_HSYNC DDPD_0P PCH_DPD_N1
PCH_DPD_P0 (37) DMC
(6,47) PBTN_OUT#
RH135 0_0402_5%~D
E20
PWRBTN# SLP_A#
G10 (34) PCH_CRT_VSYNC 1 M49
CRT_VSYNC DMC DDPD_1N
BF44
PCH_DPD_P1
PCH_DPD_N1 (37)
DDPD_1P
BE44
BF42 PCH_DPD_N2
PCH_DPD_P1 (37) (DP & HDMI)
DDPD_2N PCH_DPD_N2 (37)
(47) AC_PRESENT 2 SHORT 1 AC_PRESENT_R H20 G16 CRT_IREF T43 BE42 PCH_DPD_P2
PCH_DPD_P2 (37)
RH137 0_0402_5%~D ACPRESENT / GPIO31 SLP_SUS# DAC_IREF DDPD_2P PCH_DPD_N3
T42 BJ42 PCH_DPD_N3 (37)
CRT_IRTN DDPD_3N PCH_DPD_P3
BG42 PCH_DPD_P3 (37)
DDPD_3P

1
SYS_PWROK Item3_X02 GPIO72 E10 AP14 H_PM_SYNC
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC (7)
This signal should be used on the platform to indicate BD82PPSM-QNHN-A0_BGA989~D
that the processor VR power is good and therefore RH140
it can be connected to the same source as PWROK on PCH. RI# A10 K14 1K_0402_0.5%~D
RI# SLP_LAN# / GPIO29
If not using integrated

2
LAN,signal may be left as NC.
BD82PPSM-QNHN-A0_BGA989~D
Check EC for S3 S4 LED

APWROK
This is a input signal to the PCH from power monitoring circuit to indicate that all Active
Sleep Well (ASW) rails, i.e. Intel ME sub-system and LAN power rails are stable on the
platform. Connect to ASW power rail monitoring circuit on motherboard. For platform
not supporting Intel AMT it can be connected to PWROK. The ASW power must be CRT_HSYNC and CRT_VSYNC resistor
stable for at least 1ms before platform logic asserts APWROK. 33 ohm for Direct Connect
20 ohm for Dock Support
DPWROK +3VS
This is an input signal to the PCH from platform power monitoring logic to indicate that 20 ohm for Switchable Graphics Device Down Topology
all power rails associated with the PCH Deep Sx well (DSW) are valid and stable. 10 ohm for Switchable Graphics Dock Support
Connect to VccDSW3_3 power rail monitoring circuit on mother board for platforms PCH_LCD_CLK 2 1
that support Deep Sx state. This signal can be tied to RSMRST# for platforms that do 2.2K_0402_5%~D RH148
B B
not support the Deep Sx state. The DSW rails must be stable for at least 10ms before PCH_LCD_DATA 2 1
PCH_CRT_R 2 1 2.2K_0402_5%~D RH152
DPWROK is asserted to PCH.
RH156 150_0402_1%~D CTRL_CLK 2 1
@ CH106 2 1 10P_0402_50V8J~D 2.2K_0402_5%~D RH155
CTRL_DATA 2 1
+3V_PCH PCH_CRT_G 2 1 2.2K_0402_5%~D RH157
RH153 150_0402_1%~D PCH_CRT_DDC_CLK 2 1
GPIO72 RH143 1 2 10K_0402_5%~D Put close PCH 500 mil @ CH107 2 1 10P_0402_50V8J~D 2.2K_0402_5%~D RH184
+RTCVCC PCH_CRT_DDC_DATA 2 1
RI# RH145 1 2 10K_0402_5%~D PCH_CRT_B 2 1 2.2K_0402_5%~D RH185
RH149 150_0402_1%~D PM_CLKRUN# 2 1
WAKE# RH146 1 2 10K_0402_5%~D DSWODVREN RH147 2 1 330K_0402_5%~D @ CH108 2 1 10P_0402_50V8J~D 8.2K_0402_5%~D RH248

AC_PRESENT RH150 1 @ 2 10K_0402_5%~D DSWODVREN RH151 2 @ 1 330K_0402_5%~D

SUSPWRDNACK RH154 1 @ 2 10K_0402_5%~D

* HL：
Item20_X01 DSWODVREN - On Die DSW VR Enable
PCH_RSMRST# RH159 1 2 10K_0402_5%~D ：Enable
Disable
SYS_PWROK RH272 1 @ 2 10K_0402_5%~D
@
SUSCLK 2 1
CH102 10P_0402_50V8J~D IGPU_BKLT_EN 2 1
100K_0402_5%~D RH123
PCH_ENVDD 2 1
100K_0402_5%~D RH158
Reserve for RF please close to UH1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (3/8) DMI,FDI,PM,GFX,DP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 16 of 63
5 4 3 2 1
 5 4 3 2 1

UH1E
AY7
RSVD1
AV7
RSVD2
BG26 AU3
TP1 RSVD3
BJ26 BG4
TP2 RSVD4
BH25
TP3
BJ16 AT10
TP4 RSVD5
BG16 BC8
TP5 RSVD6
AH38
TP6
AH37 AU2
TP7 RSVD7
AK43 AT4
TP8 RSVD8
AK45 AT3
TP9 RSVD9
C18 AT1
TP10 RSVD10
N30 AY3
TP11 RSVD11
H3 AT5
TP12 RSVD12
AH12 AV3
D TP13 RSVD13 D
AM4
TP14 RSVD14
AV1 Intel Anti-Theft Techonlogy
AM5 BB1
TP15 RSVD15
Y13
TP16 RSVD16
BA3 High=Endabled
K24
TP17 RSVD17
BB5 NV_ALE
Low=Disable(floating)
L24
AB46
TP18
TP19
RSVD18
RSVD19
BB3
BB7 *
AB45 BE8
TP20 RSVD20
BD4

RSVD
RSVD21 +1.8VS
BF6
RSVD22
B21 AV5 NV_ALE RH160 1 @ 2 1K_0402_5%~D
TP21 RSVD23
M20 AV10
TP22 RSVD24
AY16
TP23
BG46 AT8
TP24 RSVD25
AY5
RSVD26
USB/USB3 Port Mapping RSVD27
BA2
(44) USB3RN0 BE28
USB3Rn1
USB2[0] USB3[1] (44) USB3RN1 BC30
USB3Rn2 RSVD28
AT12
BE32 BF3
USB3Rn3 RSVD29
USB2[1] USB3[2] BJ32
USB3Rn4
(44) USB3RP0 BC28
USB3Rp1
USB2[2] USB3[3] (44) USB3RP1 BE30
USB3Rp2
BF32

USB30
USB3Rp3 USB20_N0
USB2[3] USB3[4] BG32
USB3Rp4 USBP0N
C24 USB20_N0 (44)
AV26 A24 USB20_P0 USB3.0
(44) USB3TN0 USB3Tn1 USBP0P USB20_P0 (44)
BB26 C25 USB20_N1
(44) USB3TN1 USB3Tn2 USBP1N USB20_N1 (44)
AU28 B25 USB20_P1 USB3.0
USB3Tn3 USBP1P USB20_P1 (44)
AY30 C26
USB3Tn4 USBP2N
(44) USB3TP0 AU26 A26
USB3TP1 USBP2P USB20_N3
(44) USB3TP1 AY26 K28 USB20_N3 (43) Item12_X01
USB3Tp2 USBP3N USB20_P3
AV28
USB3Tp3 USBP3P
H28
USB20_N4
USB20_P3 (43) USB2.0
AW30 E28 USB20_N4 (38)
USB3Tp4 USBP4N USB20_P4
USBP4P
D28
USB20_N5
USB20_P4 (38) Mini Card(WLAN)
C28 USB20_N5 (38)
USBP5N USB20_P5
+3VS USBP5P
A28
USB20_N6
USB20_P5 (38) Mini Card(DMC/WWAN)
C29 USB20_N6 (48)
USBP6N USB20_P6
C
PCI_PIRQA# USBP6P
B29 USB20_P6 (48) ELC LED C
K40 N28
PCI_PIRQB# PIRQA# USBP7N
K38 M28
PCI_PIRQC# PIRQB# USBP7P USB20_N8
Item13_X01 H38 L30

PCI
PIRQC# USBP8N USB20_N8 (38)
PCI_PIRQD# G38 K30 USB20_P8 Bluetooth
PIRQD# USBP8P USB20_P8 (38)
G30
RH284 WL_OFF# DGPU_HOLD_RST# USBP9N
1 2 8.2K_0402_5%~D C46 E30 Item12_X01
RH285 REQ1# / GPIO50 USBP9P +3V_PCH
1 2 8.2K_0402_5%~D PCI_PIRQB# GPIO52 C44 C30

USB
RH286 PCI_PIRQD# DGPU_PWR_EN# REQ2# / GPIO52 USBP10N
1 2 8.2K_0402_5%~D Item1_X01 (31) DGPU_PWR_EN# E40 A30
RH287 PCI_PIRQC# REQ3# / GPIO54 USBP10P
1 2 8.2K_0402_5%~D L32
DMC_RADIO_OFF# USBP11N USB_OC2# RH288
(38) DMC_RADIO_OFF# D47 K32 1 2 10K_0402_5%~D
RH289 8.2K_0402_5%~D DMC_RADIO_OFF# GNT1# / GPIO51 USBP11P USB20_N12 USB_OC0# RH290
1 2 E42 G32 USB20_N12 (33) 1 2 10K_0402_5%~D
RH291 8.2K_0402_5%~D GPIO52 WL_OFF# GNT2# / GPIO53 USBP12N USB20_P12 GPIO10 RH292
1 2 (38) WL_OFF# F46 E32 USB20_P12 (33) Camera 1 2 10K_0402_5%~D
RH293 8.2K_0402_5%~D DGPU_PWR_EN# GNT3# / GPIO55 USBP12P USB20_N13 GPIO9 RH294
1 2 C32 USB20_N13 (46) 1 2 10K_0402_5%~D
RH295 8.2K_0402_5%~D FFS_INT1 USBP13N USB20_P13
1 2
FFS_INT1 USBP13P
A32 USB20_P13 (46) VPK
(45) FFS_INT1 G42 Item13_X01
RH296 PCI_PIRQA# ODD_DA# PIRQE# / GPIO2
1 2 8.2K_0402_5%~D (45) ODD_DA# G40 Within 500 mils
RH297 PIRQF# / GPIO3
1 2 8.2K_0402_5%~D DGPU_HOLD_RST#
(35) DP_CBL_DET
DP_CBL_DET C42 C33 USBRBIAS 1 2 USB_OC1# RH298 1 2 10K_0402_5%~D
RH299 ODD_DA# PIRQG# / GPIO4 USBRBIAS# 1.5VDDR_VID0
1 2 8.2K_0402_5%~D D44 RH163 22.6_0402_1% RH300 1 2 10K_0402_5%~D
PIRQH# / GPIO5 1.5VDDR_VID1 RH301 10K_0402_5%~D
1 2
B33 Net USB_BIAS route impedacnes should be 50-ohm GPIO14 RH302 1 2 10K_0402_5%~D
PAD~D T123 USBRBIAS and length less than 500-mil spacing is 15-mil.
K10
PME#
@ PCH_PLTRST# C6 A14 USB_OC0#
PLTRST# OC0# / GPIO59 USB_OC0# (6,44)
CH109 2 1 10P_0402_50V8J~D K20 USB_OC1#
OC1# / GPIO40 USB_OC1# (6,44)
B17 USB_OC2# USB_OC2# (6,43)
CLK_PCI_LPBACK OC2# / GPIO41
(15) CLK_PCI_LPBACK
RH164 2 1 22_0402_5%~D CLK_PCI0 H49 C16 1.5VDDR_VID0
1.5VDDR_VID0 (6,55)
CLK_PCI_LPC RH165 CLKOUT_PCI0 OC3# / GPIO42
(47) CLK_PCI_LPC 1 2 22_0402_5%~D CLK_PCI1 H43 L16 1.5VDDR_VID1
1.5VDDR_VID1 (6,55)
CLK_PCI2 CLKOUT_PCI1 OC4# / GPIO43 GPIO9
PAD~D T165 J48 A16 GPIO9 (6)
CLK_PCI3 CLKOUT_PCI2 OC5# / GPIO9 GPIO10
PAD~D T166 K42 D14 GPIO10 (6)
CLK_PCI4 CLKOUT_PCI3 OC6# / GPIO10 GPIO14
PAD~D T204 H40 C14 GPIO14 (6) Item12_X01
CLKOUT_PCI4 OC7# / GPIO14

BD82PPSM-QNHN-A0_BGA989~D
1 2
@ RH254 0_0402_5%~D

B +3VSDGPU B
@ Item16_X01
2 1 CLK_PCI1
CH99 10P_0402_50V8J~D 1 @ 2 DGPU_PWROK
DGPU_PWROK (18,31,35,57)

5
UH6 RH265 0_0402_5%~D
2 1 SHORT 2 PCH_PLTRST#

P
B
Reserve for RF please close to UH1 (22) PLTRST_VGA# 2 1 4
Y
RH266 0_0402_5%~D
RH170 100_0402_5%~D 1 DGPU_HOLD_RST#
A

G
SN74AHC1G08DCKR_SC70-5
Item3_X02

3
1

2
RH179
@ 10K_0402_5%~D
RH172
100K_0402_5%~D

1
+3VS 1 @ 2
RH168 0_0402_5%~D
2

@ +3VS
RH169
10K_0402_5%~D
5

UH5
1

1 PCH_PLTRST#
P

IN1
(6,7,38,39,40,47) PLT_RST# 4
O
2
IN2
G
1

SN74AHC1G08DCKR_SC70-5
3

RH171
100K_0402_5%~D
Check @ RH183
2

10K_0402_5%~D
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (4/8) PCI, USB, NVRAM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 17 of 63
5 4 3 2 1
 5 4 3 2 1

UH1F

High: CRT Plugged CRT_DET T7 C40 ODD_EN#

BMBUSY# / GPIO0 TACH4 / GPIO68 ODD_EN# (45)
A42
TACH1 / GPIO1 TACH5 / GPIO69
B41 GPIO69 T126 PAD~D DMI Termination Voltage
+3VS

D
GPIO6 H36
TACH2 / GPIO6 TACH6 / GPIO70
C41 Set to Vcc when HIGH D
NV_CLE
2

(47) EC_SCI# EC_SCI# E38 A40 Set to Vss when LOW

RH198 TACH3 / GPIO7 TACH7 / GPIO71
10K_0402_5%~D (47) EC_SMI# EC_SMI# C10
GPIO8

(38) BT_RADIO_DIS# BT_RADIO_DIS# C4

1

CRT_DET LAN_PHY_PWR_CTRL / GPIO12

GPIO15 G2 P4 GATEA20 +1.8VS
Item13_X02 (6) GPIO15 GPIO15 A20GATE GATEA20 (47)
1

D
2 AU16 PCH_PECI_R 1 @ 2 Weak internal
(34) CRT_DET# PECI H_PECI (7,47)

1
QH5 G GPIO16 U2 0_0402_5%~D RH175 PU,Do not pull low
2N7002K_SOT23-3 SATA4GP / GPIO16 KB_RST# RH161
S P5 KB_RST# (47)
3

RCIN# 2.2K_0402_5%~D
DGPU_PWROK D40 AY11

GPIO
(17,31,35,57) DGPU_PWROK TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD (6,7)

CPU/MISC

2
PCH_GPIO22 T5 AY10 H_THERMTRIP#_C 1 2 H_THERMTRIP# (7) NV_CLE 2 1 H_SNB_IVB# (7)
SCLOCK / GPIO22 THRMTRIP# 390_0402_5% RH176 1K_0402_5%~D RH162
GPIO28 E8 T14 INIT3_3V# T127 PAD~D
GPIO24 INIT3_3V#
On-Die PLL Voltage Regulator
This signal has a weak internal pull up E16 AY1 NV_CLE

：：On-Die
GPIO27 DF_TVS
H voltage regulator enable PCH_GPIO28 INIT3_3V CLOSE TO THE BRANCHING POINT
* L On-Die PLL Voltage Regulator disable
P8
GPIO28
TS_VSS1
AH8
BT_ON# This signal has weak internal
+3V_PCH (38) BT_ON# K1
STP_PCI# / GPIO34
AK11
RH161 and RH162
TS_VSS2 PU, can't pull low
GPIO35 K4
GPIO35 Follow CRB FAB2 setting
AH10
PCH_GPIO28 ODD_DETECT# TS_VSS3
1 2 (45) ODD_DETECT# V8
RH229 8.2K_0402_5%~D SATA2GP / GPIO36
AK10
PCH_GPIO37 TS_VSS4
M5
SATA3GP / GPIO37
1 @ 2 PCH_GPIO28
RH177 1K_0402_5%~D DGPU_PRSNT# N2 P37
SLOAD / GPIO38 NC_1
PCH_GPIO39 M3
SDATAOUT0 / GPIO39
FFS_INT2 V13 BG2
(45) FFS_INT2 SDATAOUT1 / GPIO48 VSS_NCTF_15
C GPIO49 V3 BG48 +3V_PCH C
SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
PCH_GPIO37 HDD_DETECT# D6 BH3 HDD_DETECT# 1 2
(45) HDD_DETECT# GPIO57 VSS_NCTF_17
FDI TERMINATION VOLTAGE OVERRIDE RH188 10K_0402_5%~D
BH47 EC_SMI# 1 2
VSS_NCTF_18 RH190 10K_0402_5%~D
LOW - Tx, Rx terminated
* to same voltage A4
VSS_NCTF_1 VSS_NCTF_19
BJ4 BT_RADIO_DIS# 1 2
RH279 10K_0402_5%~D
(DC Coupling Mode)
A44 BJ44
VSS_NCTF_2 VSS_NCTF_20 GPIO15 1 2
+3VS A45 BJ45 RH281 1K_0402_5%~D
VSS_NCTF_3 VSS_NCTF_21
A46 BJ46

NCTF
RH181 @ PCH_GPIO37 VSS_NCTF_4 VSS_NCTF_22 +3VS
2 1 1K_0402_5%~D
A5 BJ5
VSS_NCTF_5 VSS_NCTF_23
RH182 1 2 PCH_GPIO37 A6 BJ6 ODD_EN# 1 2
10K_0402_5%~D VSS_NCTF_6 VSS_NCTF_24 RH187 10K_0402_5%~D
B3 C2 CRT_DET# 1 @ 2
VSS_NCTF_7 VSS_NCTF_25 RH192 10K_0402_5%~D
B47 C48 ODD_DETECT# 1 2
VSS_NCTF_8 VSS_NCTF_26 RH193 200K_0402_5%
BD1 D1 GPIO16 1 2
VSS_NCTF_9 VSS_NCTF_27 RH274 10K_0402_5%~D
BD49 D49 BT_ON# 1 2
VSS_NCTF_10 VSS_NCTF_28 RH195 8.2K_0402_5%~D
BE1 E1 KB_RST# 1 2
VSS_NCTF_11 VSS_NCTF_29 RH196 10K_0402_5%~D
BE49 E49 PCH_GPIO22 1 2
VSS_NCTF_12 VSS_NCTF_30 RH197 10K_0402_5%~D
BF1 F1 GPIO35 1 @ 2
VSS_NCTF_13 VSS_NCTF_31 RH257 10K_0402_5%~D
BF49 F49 GPIO49 1 2
VSS_NCTF_14 VSS_NCTF_32 RH258 10K_0402_5%~D

BD82PPSM-QNHN-A0_BGA989~D
PCH_GPIO39 1 2
RH263 10K_0402_5%~D
B B
GPIO6 1 2
RH271 10K_0402_5%~D
GATEA20 1 2
RH174 10K_0402_5%~D

EC_SCI# 1 2
RH283 10K_0402_5%~D

For BIOS setting dGPU present

LOW - dGPU exist
*
+3VS

DGPU_PRSNT# 1 @ 2
RH262 10K_0402_5%~D
DGPU_PRSNT# 1 2
RH282 10K_0402_5%~D

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (5/8) GPIO, CPU, MISC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 18 of 63
5 4 3 2 1
 5 4 3 2 1

check power resistor package

PCH Power Rail Table
+1.05VS UH1G POWER Item4_X03 +3VS S0 Iccmax
J10
@ VCCCORE=1.3A max Voltage Rail Voltage Current (A)
1300mA LH1
2 1 +1.05VS_VCCCORE AA23 U48 +VCCADAC 2 1
1mA

22U_0805_6.3V6M~D
0.1U_0402_10V7K~D
VCCCORE[1] VCCADAC

0.01U_0402_16V7K~D
AC23 1 1 1 1 BLM18PG181SN1_0603~D V_PROC_IO 1.05 0.001

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
VCCCORE[2] @

CH112
1 1 1 1 AD21
PAD-OPEN 4x4m VCCCORE[3]

CRT

CH31
AD23 U47
VCCCORE[4] VSSADAC 10U_0805_25V6K~D V5REF 5 0.001

CH29

CH30
AF21
VCCCORE[5] 2 2 2 2

VCC CORE
CH28

CH25

CH26
AF23
2 2 2 2 VCCCORE[6] +3VS

CH27
AG21
VCCCORE[7]
AG23
VCCCORE[8]
V5REF_Sus 5 0.001
AG24 AK36 +VCCA_LVDS 1 SHORT 2
D VCCCORE[9] 1mA VCCALVDS D
AG26 RH199 0_0805_5%~D
VCCCORE[10] +1.8VS
AG27
VCCCORE[11] VSSALVDS
AK37 Item4_X03 Vcc3_3 3.3 0.266
AG29
VCCCORE[12] LH2
AJ23
VCCCORE[13] Near AP43
AJ26 AM37 +VCCTX_LVDS 2 1 VccADAC 3.3 0.001

LVDS
VCCCORE[14] VCCTX_LVDS[1] 0.1UH_MLF1608DR10KT_10%_1608
AJ27

22U_0805_6.3V6M~D
0.01U_0402_16V7K~D

0.01U_0402_16V7K~D
VCCCORE[15]
AJ29
VCCCORE[16] VCCTX_LVDS[2]
AM38 1 1 1 0.1uH inductor, 200mA
AJ31 VccADPLLA 1.05 0.08
+1.05VS VCCCORE[17] CH32 CH33 CH34
Item4_X03 60mA VCCTX_LVDS[3] AP36

AP37 2 2 2 VccADPLLB 1.05 0.08

+1.05VS VCCTX_LVDS[4]
2 SHORT 1 AN19
RH200 0_0603_5%~D VCCIO[28]
@ LH3 VccCore 1.05 1.3
2 @ 1+VCCAPLLEXP_R 1 2 +VCCAPLLEXP BJ22 +3VS
RH201 0_0603_5%~D 1UH_LB2012T1R0M_20%~D VCCAPLLEXP
close PCH

10U_0603_6.3V6M~D
1 V33 +3VS_VCC3_3_6 1 SHORT 2 VccDMI 1.05 0.042
@
100mil VCC3_3[6] RH202 0_0805_5%~D
AN16

HVCMOS
VCCIO[15]
Place CH40 Near BJ22 pin 1 Item4_X03
AN17 VccIO 1.05 2.925
2 VCCIO[16] CH36
CH35
V34
VCC3_3[7]
0.1U_0402_10V7K~D
AN21 2 VccASW 1.05 1.01
VCCIO[17]
AN26 AT20, AU20 (Trace needs to be at least 20
VCCIO[18]
mils width with full VSS/VCC reference plane) VccSPI 3.3 0.02
AN27 2925mA AT16 +VCCAFDI_VRM
+1.05VS VCCIO[19] VCCVRM[3]
near AN21, AN16, AN33
AP21 +VCCP_VCCDMI +1.05VS VccDSW 3.3 0.003
Item4_X03 VCCIO[20]
RH203 1 SHORT 2 0_0805_5%~D +1.05VS_VCC_EXP AP23 AT20 +VCCP_VCCDMI 1 SHORT 2
VCCIO[21] VCCDMI[1]
1 RH204 0_0805_5%~D VccpNAND 1.8 0.19
10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

AP24 +1.05VS
1 1 1 1 1 Item4_X03

DMI
VCCIO[22] CH42

VCCIO
AP26 20mA VCCCLKDMI AB36 +1.05VS_VCC_DMI_CCI 1 SHORT 2 VccRTC 3.3 6 uA
VCCIO[23] 2 1U_0402_6.3V6K~D
1 RH205 0_0805_5%~D
CH38

CH39

CH40

CH41

2 2 2 2 2
CH37

AT24 Item4_X03
VCCIO[24]
C CH43 VccSus3_3 3.3 0.119 C
close PCH 100mil 2
1U_0402_6.3V6K~D
AN33
VCCIO[25]
VccSusHDA 3.3 / 1.5 0.01
+3VS AN34 AG16
Item4_X03 VCCIO[26] VCCDFTERM[1] +VCCPNAND +1.8VS
VccVRM 1.8 / 1.5 0.16
RH206 1 SHORT 2 0_0805_5%~D +3VS_VCCA3GBG BH29 AG17 1 SHORT 2
VCC3_3[3] 190mA VCCDFTERM[2] RH207 0_0805_5%~D
1

DFT / SPI
Item4_X03 VccCLKDMI 1.05 0.02

0.1U_0402_10V7K~D
CH44 AJ16 1
0.1U_0402_10V7K~D VCCDFTERM[3]
+1.05VS 2 +VCCAFDI_VRM VccSSC 1.05 0.095

CH45
AP16
VCCVRM[2]
AJ17
VCCDFTERM[4] 2
Place CH53 Near BG6 pin
RH208 2 @ 1 0_0603_5%~D +1.05VS_VCCAPLL_FDI BG6 VccDIFFCLKN 1.05 0.055
VccAFDIPLL
Item4_X03 +3V_PCH
Item1_X03
+1.05VS 1 SHORT 2+1.05VS_VCCDPLL_FDI AP17 RH210 VccALVDS 3.3 0.001
RH209 0_0805_5%~D VCCIO[27] +3V_VCCPSPI
20mA V1 1 SHORT 2
VCCSPI
FDI

0_0805_5%~D
1 +VCCP_VCCDMI AU20
VCCDMI[2] 1 Item4_X03 VccTX_LVDS 1.8 0.06
@ CH46
1U_0402_6.3V6K~D CH47
BD82PPSM-QNHN-A0_BGA989~D 1U_0402_6.3V6K~D
2 2
AT20, AU20 (Trace needs to be at least 20
mils width with full VSS/VCC reference plane)

+3VALW

B B

+VCCAFDI_VRM
1
C432
1U_0402_6.3V6K~D U47
2 1 5 +VCCAFDI_VRM
VIN VOUT
2 1
GND
SUSP# 3 4 CH110
(32,47,55,56) SUSP# SHDN BP
Item9_X01 1U_0402_6.3V6K~D
APE8805A-15Y5P_SOT23-5 2
1
CH111

0.01U_0402_16V7K~D
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (6/8) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 19 of 63
5 4 3 2 1
 5 4 3 2 1

+1.05VS
VCC3_3 = 266mA detal waiting for newest spec
VCCDMI = 42mA detal waiting for newest spec
2 @ 1 +VCCACLK
+3V_PCH RH213 0_0603_5%~D
D
UH1J POWER QH7
D

2 SHORT 1
+3V_DSW RH214 0_0603_5%~D AD49 N26 +1.05VS_VCCUSBCORE 2 SHORT 1 +5VALW AO3419L_SOT23-3 +5V_PCH
1 VCCACLK VCCIO[29] +1.05VS
Item4_X03 RH220 0_0603_5%~D

D
CH48 P26 1 Item4_X03 2 SHORT 1 3 1
0.1U_0402_10V7K~D +VCCPDSW VCCIO[30] RH215 0_0603_5%~D
1 2 T16 3mA

0.1U_0402_10V7K~D
RH221 @ 0_0603_5%~D 2 VCCDSW3_3 CH50
P28 Item4_X03

20K_0402_5%~D
VCCIO[31]

1
1U_0402_6.3V6K~D

G
1

2
+PCH_VCCDSW 2

R22
V12 T27
+1.05VS DCPSUSBYP VCCIO[32]

C8
@ LH4 1
@ RH216 10UH_LBR2012T100M_20%~D T29
VCCIO[33] (32) PCH_PWR_EN# 2
1 2 +VCCAPLL_CPY 1 2 @ CH51 +3VS_VCC_CLKF33 T38 Item4_X03

2
0.1U_0402_10V7K~D VCC3_3[5]

10U_0603_6.3V6M~D
0_0805_5%~D @ 2 T23 +3V_VCCPUSB 2 SHORT 1
1 119mA VCCSUS3_3[7] +3V_PCH
+1.05VS +VCCAPLL_CPY_PCH BH23 RH217 0_0603_5%~D

0.1U_0402_10V7K~D
VCCAPLLDMI2 +3V_VCCAUBG
T24 1 2 SHORT 1 +3V_PCH
+VCCDPLL_CPY VCCSUS3_3[8] +5V_PCH +3V_PCH
2 SHORT 1 AL29 RH218 0_0603_5%~D

0.1U_0402_10V7K~D
2 RH219 0_0603_5%~D VCCIO[14]

CH49

CH52
V23 1
VCCSUS3_3[9]
Item4_X03

USB

2
+VCCSUS1 2 +VCCA_USBSUS

CH53
AL24 V24
DCPSUS[3] VCCSUS3_3[10] RH222 DH2
1

1U_0402_6.3V6K~D
@ P24 2 10_0402_5%~D
QH6 VCCSUS3_3[6] 1 RB751S40T1_SOD523-2~D
+3VALW +3V_DSW CH54
AO3419L_SOT23-3

@
1U_0402_6.3V6K~D

CH55
AA19

1
2 VCCASW[1] +1.05VS_VCCAUPLL
T26 2 SHORT 1 +1.05VS +PCH_V5REF_SUS
VCCIO[34] 2
S

3 1 AA21
VCCASW[2]
1010mA RH223 0_0603_5%~D 1
+1.05VM_VCCASW +PCH_V5REF_SUS CH56
Check AA24
VCCASW[3] 1mA V5REF_SUS M26 Item4_X03
2 SHORT 1 0.1U_0603_25V7K~D
G

1 1 +3V_PCH

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D
2

AA26 RH224 0_0603_5%~D 2

0.1U_0402_10V7K~D
VCCASW[4]

Clock and Miscellaneous

+VCCA_USBSUS

CH57

CH58
AN23 1
DCPSUS[4]
AA27
2 2 VCCASW[5] +3V_VCCPSUS_1

CH59
AN24
VCCSUS3_3[1]
AA29
VCCASW[6] 2
(47) PCH_VREG_EN# +1.05VS +5VS +3VS
AA31
VCCASW[7]
C 1 SHORT 2 AC26 1mA V5REF P34 +PCH_V5REF_RUN C
VCCASW[8]

2
RH225 0_0805_5%~D 1 1 1 RH226

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
Item4_X03 AC27 0_0603_5%~D RH227 DH3
VCCASW[9] +3V_VCCPSUS 2 SHORT 1 10_0402_5%~D

CH60

CH61

CH62
N20 +3V_PCH RB751S40T1_SOD523-2~D
VCCSUS3_3[2]
AC29 1 Item4_X03

PCI/GPIO/LPC
2 2 2 VCCASW[10]
N22

1
VCCSUS3_3[3] CH63 +PCH_V5REF_RUN
AC31
VCCASW[11] close PCH 100mil+3VS
P20 1U_0402_6.3V6K~D 1
VCCSUS3_3[4] 2
AD29
+3VS VCCASW[12] +3VS_VCCPCORE
P22 2 SHORT 1 CH64
VCCSUS3_3[5] RH228 0_0805_5%~D 1U_0402_6.3V6K~D
5/18 delete RH229 AD31
VCCASW[13] 1 2
W21 AA16 CH65
VCCASW[14] VCC3_3[1] 0.1U_0402_10V7K~D
LH5 W23 W16 2 +3VS
VCCASW[15] VCC3_3[8]
1 SHORT 2 +3VS_VCC_CLKF33_R 1 2 +3VS_VCC_CLKF33
RH230 0_0805_5%~D 10UH_LBR2012T100M_20%~D 1 1 W24 T34 +3VS_VCCPPCI 2 SHORT 1
10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

@ VCCASW[16] VCC3_3[4] RH231 0_0603_5%~D

Item4_X03 1
CH67

W26 Item4_X03
VCCASW[17] CH68
2 2 Item4_X03 +3VS 0.1U_0402_10V7K~D
CH66

W29
VCCASW[18] RH232 2
Item7_X03 +VCC3_3_2
W31 AJ2 2 SHORT 1
VCCASW[19] VCC3_3[2] +1.05VS_SATA3
1
W33 0_0603_5%~D
VCCASW[20] CH69
AF13 2 SHORT 1 +1.05VS
VCCIO[5] 0.1U_0402_10V7K~D
2 1 RH233 0_0805_5%~D
+1.05VS +VCCRTCEXT N16
DCPRTC Item4_X03
CH70
1 AH13
@ +1.05VM_VCCSUS VCCIO[12] 1U_0402_6.3V6K~D
2 1
RH234 0_0603_5%~D CH71 +VCCAFDI_VRM Y49 AH14 +1.05VS_SATA3 2
0.1U_0402_10V7K~D VCCVRM[4] VCCIO[13]
2
+1.05VS AF14 @ LH6 @
+1.05VS_VCCA_A_DPL VCCIO[6] 10UH_LBR2012T100M_20%~D RH236
BD47
VCCADPLLA 80mA
2 SHORT 1 +VCCDIFFCLK AK1 +VCCSATAPLL 1 2 +VCCSATAPLL_R 2 1

SATA
VCCAPLLSATA +1.05VS
RH235 0_0603_5%~D +1.05VS_VCCA_B_DPL BF47 +VCCAFDI_VRM
VCCADPLLB 80mA 0_0805_5%~D
Item4_X03 1 1

10U_0603_6.3V6M~D
B B
CH72 AF11 +VCCAFDI_VRM Item4_X03
VCCVRM[1] +1.05VS_VCC_SATA @
AF17
+1.05VS +1.05VS_VCCDIFFCLKN VCCIO[7]
1U_0402_6.3V6K~D AF33
VCCDIFFCLKN[1]
RH238 Place CH80 Near AK1 pin
2 55mA +1.05VS_VCC_SATA 2 SHORT 2

CH73
AF34 AC16 1 +1.05VS
VCCDIFFCLKN[2] VCCIO[2]
2 SHORT 1 +1.05VS_VCCDIFFCLKN AG34

1U_0402_6.3V6K~D
VCCDIFFCLKN[3]
trace width RH237 0_0603_5%~D
1 VCCIO[3]
AC17 1 0_0805_5%~D
40mil Item4_X03 CH74 +1.05VS_SSCVCC

CH75
AG33 AD17
1U_0402_6.3V6K~D VCCSSC 95mA VCCIO[4]
+1.05VS 2 2
+VCCSST V16 +1.05VS
DCPSST
2 SHORT 1
RH239 0_0603_5%~D 1 1 +1.05VM_VCCSUS
Item4_X03 CH78 1 T17 T21 +VCCME_22 RH240 2 SHORT 1 0_0603_5%~D
CH77 0.1U_0402_10V7K~D @ DCPSUS[1] VCCASW[22]
V19
1U_0402_6.3V6K~D CH76 DCPSUS[2]
MISC

+1.05VS 2 2 1U_0402_6.3V6K~D V21 +VCCME_23 RH241 2 SHORT 1 0_0603_5%~D

2 VCCASW[23]
2 SHORT 1 +V_CPU_IO BJ8
CPU

V_PROC_IO 1mA
0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

RH242 0_0603_5%~D 1 1 1 T19 +VCCME_21 RH243 2 SHORT 1 0_0603_5%~D

VCCASW[21]
Item4_X03 CH79 +RTCVCC
CH80

CH81

4.7U_0603_6.3V6K~D
2 2 2 A22 P32 +VCCSUSHDA RH244 2 SHORT 1 0_0603_5%~D
VCCRTC 10mA VCCSUSHDA +3V_PCH
RTC

Item4_X03
HDA
1U_0402_6.3V6K~D
0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1 1 1 1
LH7
10UH_LBR2012T100M_20%~D BD82PPSM-QNHN-A0_BGA989~D 0.1U_0402_10V7K~D CH85
CH82

CH83

CH84

1 2 +1.05VS_VCCA_A_DPL
+1.05VS 2 2 2 2

1 SHORT 2 +VCCA_DPLL_L 1 2 +1.05VS_VCCA_B_DPL

220U_B2_2.5VM_R35M~D

RH247 0_0805_5%~D LH8

220U_B2_2.5VM_R35M~D

10UH_LBR2012T100M_20%~D 1 1
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

Item4_X03 +
1
+
1
CH86

CH88
CH87

CH89

A A
2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (7/8) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 20 of 63
5 4 3 2 1
 5 4 3 2 1

UH1I

AY4 H46
VSS[159] VSS[259]
AY42 K18
VSS[160] VSS[260]
AY46 K26
VSS[161] VSS[261]
AY8 K39
UH1H VSS[162] VSS[262]
B11 K46
VSS[163] VSS[263]
H5 B15 K7
VSS[0] VSS[164] VSS[264]
B19 L18
D VSS[165] VSS[265] D
AA17 AK38 B23 L2
VSS[1] VSS[80] VSS[166] VSS[266]
AA2 AK4 B27 L20
VSS[2] VSS[81] VSS[167] VSS[267]
AA3 AK42 B31 L26
VSS[3] VSS[82] VSS[168] VSS[268]
AA33 AK46 B35 L28
VSS[4] VSS[83] VSS[169] VSS[269]
AA34 AK8 B39 L36
VSS[5] VSS[84] VSS[170] VSS[270]
AB11 AL16 B7 L48
VSS[6] VSS[85] VSS[171] VSS[271]
AB14 AL17 F45 M12
VSS[7] VSS[86] VSS[172] VSS[272]
AB39 AL19 BB12 P16
VSS[8] VSS[87] VSS[173] VSS[273]
AB4 AL2 BB16 M18
VSS[9] VSS[88] VSS[174] VSS[274]
AB43 AL21 BB20 M22
VSS[10] VSS[89] VSS[175] VSS[275]
AB5 AL23 BB22 M24
VSS[11] VSS[90] VSS[176] VSS[276]
AB7 AL26 BB24 M30
VSS[12] VSS[91] VSS[177] VSS[277]
AC19 AL27 BB28 M32
VSS[13] VSS[92] VSS[178] VSS[278]
AC2 AL31 BB30 M34
VSS[14] VSS[93] VSS[179] VSS[279]
AC21 AL33 BB38 M38
VSS[15] VSS[94] VSS[180] VSS[280]
AC24 AL34 BB4 M4
VSS[16] VSS[95] VSS[181] VSS[281]
AC33 AL48 BB46 M42
VSS[17] VSS[96] VSS[182] VSS[282]
AC34 AM11 BC14 M46
VSS[18] VSS[97] VSS[183] VSS[283]
AC48 AM14 BC18 M8
VSS[19] VSS[98] VSS[184] VSS[284]
AD10 AM36 BC2 N18
VSS[20] VSS[99] VSS[185] VSS[285]
AD11 AM39 BC22 P30
VSS[21] VSS[100] VSS[186] VSS[286]
AD12 AM43 BC26 N47
VSS[22] VSS[101] VSS[187] VSS[287]
AD13 AM45 BC32 P11
VSS[23] VSS[102] VSS[188] VSS[288]
AD19 AM46 BC34 P18
VSS[24] VSS[103] VSS[189] VSS[289]
AD24 AM7 BC36 T33
VSS[25] VSS[104] VSS[190] VSS[290]
AD26 AN2 BC40 P40
VSS[26] VSS[105] VSS[191] VSS[291]
AD27 AN29 BC42 P43
VSS[27] VSS[106] VSS[192] VSS[292]
AD33 AN3 BC48 P47
VSS[28] VSS[107] VSS[193] VSS[293]
AD34 AN31 BD46 P7
VSS[29] VSS[108] VSS[194] VSS[294]
AD36 AP12 BD5 R2
VSS[30] VSS[109] VSS[195] VSS[295]
AD37 AP19 BE22 R48
VSS[31] VSS[110] VSS[196] VSS[296]
AD38 AP28 BE26 T12
VSS[32] VSS[111] VSS[197] VSS[297]
AD39 AP30 BE40 T31
VSS[33] VSS[112] VSS[198] VSS[298]
AD4 AP32 BF10 T37
VSS[34] VSS[113] VSS[199] VSS[299]
AD40 AP38 BF12 T4
VSS[35] VSS[114] VSS[200] VSS[300]
AD42 AP4 BF16 W34
VSS[36] VSS[115] VSS[201] VSS[301]
AD43 AP42 BF20 T46
VSS[37] VSS[116] VSS[202] VSS[302]
C AD45 AP46 BF22 T47 C
VSS[38] VSS[117] VSS[203] VSS[303]
AD46 AP8 BF24 T8
VSS[39] VSS[118] VSS[204] VSS[304]
AD8 AR2 BF26 V11
VSS[40] VSS[119] VSS[205] VSS[305]
AE2 AR48 BF28 V17
VSS[41] VSS[120] VSS[206] VSS[306]
AE3 AT11 BD3 V26
VSS[42] VSS[121] VSS[207] VSS[307]
AF10 AT13 BF30 V27
VSS[43] VSS[122] VSS[208] VSS[308]
AF12 AT18 BF38 V29
VSS[44] VSS[123] VSS[209] VSS[309]
AD14 AT22 BF40 V31
VSS[45] VSS[124] VSS[210] VSS[310]
AD16 AT26 BF8 V36
VSS[46] VSS[125] VSS[211] VSS[311]
AF16 AT28 BG17 V39
VSS[47] VSS[126] VSS[212] VSS[312]
AF19 AT30 BG21 V43
VSS[48] VSS[127] VSS[213] VSS[313]
AF24 AT32 BG33 V7
VSS[49] VSS[128] VSS[214] VSS[314]
AF26 AT34 BG44 W17
VSS[50] VSS[129] VSS[215] VSS[315]
AF27 AT39 BG8 W19
VSS[51] VSS[130] VSS[216] VSS[316]
AF29 AT42 BH11 W2
VSS[52] VSS[131] VSS[217] VSS[317]
AF31 AT46 BH15 W27
VSS[53] VSS[132] VSS[218] VSS[318]
AF38 AT7 BH17 W48
VSS[54] VSS[133] VSS[219] VSS[319]
AF4 AU24 BH19 Y12
VSS[55] VSS[134] VSS[220] VSS[320]
AF42 AU30 H10 Y38
VSS[56] VSS[135] VSS[221] VSS[321]
AF46 AV16 BH27 Y4
VSS[57] VSS[136] VSS[222] VSS[322]
AF5 AV20 BH31 Y42
VSS[58] VSS[137] VSS[223] VSS[323]
AF7 AV24 BH33 Y46
VSS[59] VSS[138] VSS[224] VSS[324]
AF8 AV30 BH35 Y8
VSS[60] VSS[139] VSS[225] VSS[325]
AG19 AV38 BH39 BG29
VSS[61] VSS[140] VSS[226] VSS[328]
AG2 AV4 BH43 N24
VSS[62] VSS[141] VSS[227] VSS[329]
AG31 AV43 BH7 AJ3
VSS[63] VSS[142] VSS[228] VSS[330]
AG48 AV8 D3 AD47
VSS[64] VSS[143] VSS[229] VSS[331]
AH11 AW14 D12 B43
VSS[65] VSS[144] VSS[230] VSS[333]
AH3 AW18 D16 BE10
VSS[66] VSS[145] VSS[231] VSS[334]
AH36 AW2 D18 BG41
VSS[67] VSS[146] VSS[232] VSS[335]
AH39 AW22 D22 G14
VSS[68] VSS[147] VSS[233] VSS[337]
AH40 AW26 D24 H16
VSS[69] VSS[148] VSS[234] VSS[338]
AH42 AW28 D26 T36
VSS[70] VSS[149] VSS[235] VSS[340]
AH46 AW32 D30 BG22
VSS[71] VSS[150] VSS[236] VSS[342]
AH7 AW34 D32 BG24
VSS[72] VSS[151] VSS[237] VSS[343]
AJ19 AW36 D34 C22
VSS[73] VSS[152] VSS[238] VSS[344]
AJ21 AW40 D38 AP13
VSS[74] VSS[153] VSS[239] VSS[345]
AJ24 AW48 D42 M14
B VSS[75] VSS[154] VSS[240] VSS[346] B
AJ33 AV11 D8 AP3
VSS[76] VSS[155] VSS[241] VSS[347]
AJ34 AY12 E18 AP1
VSS[77] VSS[156] VSS[242] VSS[348]
AK12 AY22 E26 BE16
VSS[78] VSS[157] VSS[243] VSS[349]
AK3 AY28 G18 BC16
VSS[79] VSS[158] VSS[244] VSS[350]
G20 BG28
BD82PPSM-QNHN-A0_BGA989~D VSS[245] VSS[351]
G26 BJ28
VSS[246] VSS[352]
G28
VSS[247]
G36
VSS[248]
G48
VSS[249]
H12
VSS[250]
H18
VSS[251]
H22
VSS[252]
H24
VSS[253]
H26
VSS[254]
H30
VSS[255]
H32
VSS[256]
H34
VSS[257]
F3
VSS[258]

BD82PPSM-QNHN-A0_BGA989~D

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (8/8) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 21 of 63
5 4 3 2 1
 A B C D E

U636A GPIO I/O USAGE

+3VSDGPU
PEG_HTX_C_GRX_P0 AN12 Part 1 of 7
PEX_RX0

2
PEG_HTX_C_GRX_N0 AM12 P6 VID_4 GPIO0 O GPU_VID4
PEG_GTX_C_HRX_N[0..15] (6) PEX_RX0_N GPIO0
PEG_HTX_C_GRX_P1 AN14 M3 VID_3
PEG_GTX_C_HRX_P[0..15] (6) PEX_RX1 GPIO1
PEG_HTX_C_GRX_N1 AM14 L6 R2024
PEX_RX1_N GPIO2

5
PEG_HTX_C_GRX_P2 AP14 P5 GPU_GPIO3 1 @ 2 H_DPRSLPVR 10K_0402_5%~D @ GPIO1 O GPU_VID3
PEG_HTX_C_GRX_N[0..15] (6) PEX_RX2 GPIO3
PEG_HTX_C_GRX_N2 AP15 P7 R2064 0_0402_5%~D 1

P
PEG_HTX_C_GRX_P[0..15] (6)

1
PEG_HTX_C_GRX_P3 PEX_RX2_N GPIO4 VID_1 GPU_R_DC# IN1
AN15 L7 4
PEG_HTX_C_GRX_N3 PEX_RX3 GPIO5 VID_2 O
AM15
PEX_RX3_N GPIO6
M7
IN2
2 ACIN (46,47,48,53) GPIO2 O NC

G
PEG_HTX_C_GRX_P4 AN17 N8
PEG_HTX_C_GRX_N4 PEX_RX4 GPIO7 R2022 2
AM17 M1 1 10K_0402_5%~D +3VSDGPU U643

3
PEG_HTX_C_GRX_P5 PEX_RX4_N GPIO8 R2023 2
AP17 M2 1 10K_0402_5%~D Item14_X02@ SN74AHC1G08DCKR_SC70-5 GPIO3 O DPRSLPVR (reserve)
PEG_HTX_C_GRX_N5 PEX_RX5 GPIO9 MEM_VREF
AP18 L1 MEM_VREF (27,28,29,30)
PEG_HTX_C_GRX_P6 PEX_RX5_N GPIO10 VID_0 D73
AN18 M5

GPIO
PEG_HTX_C_GRX_N6 PEX_RX6 GPIO11 GPU_R_DC#
1
PEG_HTX_C_GRX_P7
AM18
PEX_RX6_N GPIO12
N3
VID_5
2 1 GPIO4 O NC 1
AN20 M4
PEG_HTX_C_GRX_N7 PEX_RX7 GPIO13 RB751VM-40TE-17_SOD323-2~D
AM20 N4
PEG_HTX_C_GRX_P8 PEX_RX7_N GPIO14
PEG_HTX_C_GRX_N8
AP20
PEX_RX8 GPIO15
P2
GPU_GPIO16 1
GPIO5 O GPU_VID1
AP21 R8 @ 2 H_DPRSLPVR H_DPRSLPVR (58)
PEG_HTX_C_GRX_P9 PEX_RX8_N GPIO16 VGA_mDP_HPD R2046 0_0402_5%~D R2556 2 SHORT
AN21 M6 VGA_mDP_HPD (35) 1 0_0402_5%~D GPU_DC# (47)
PEG_HTX_C_GRX_N9 PEX_RX9 GPIO17
PEG_HTX_C_GRX_P10
AM21
PEX_RX9_N GPIO18
R1 VGA_HDMI_HPD GPIO6 O GPU_VID2
AN23 P3 VGA_DMC_HPD
PEG_HTX_C_GRX_N10 PEX_RX10 GPIO19
AM23 P4 Item3_X02
PEG_HTX_C_GRX_P11 PEX_RX10_N GPIO20
PEG_HTX_C_GRX_N11
AP23
PEX_RX11 GPIO21
P1 GPIO7 O NC
AP24
PEG_HTX_C_GRX_P12 PEX_RX11_N GPIO20,21
AN24
PEG_HTX_C_GRX_N12 PEX_RX12 N13P/M = NC;
PEG_HTX_C_GRX_P13
AM24
PEX_RX12_N N13P-PES = GPIO20,21
GPIO8 I/O OVERT (10K pull High)
AN26
PEG_HTX_C_GRX_N13 PEX_RX13
AM26
PEG_HTX_C_GRX_P14 PEX_RX13_N
PEG_HTX_C_GRX_N14
AP26
PEX_RX14 GPIO9 I/O ALERT (10K pull High)
AP27
PEG_HTX_C_GRX_P15 PEX_RX14_N
AN27 AK9
PEG_HTX_C_GRX_N15 PEX_RX15 DACA_RED
AM27
PEX_RX15_N DACA_GREEN
DACA_BLUE
AL10
AL9 DACA_VDD 10K pull down, GPIO10 O MEM_VREF_CTL
DACA_VREF, DACA_REST NC

DACs
PEG_GTX_C_HRX_P0 CC218 2 1 0.22U_0402_16V7K~D PCIE_CRX_C_GTX_P0 AK14 GPIO11 O GPU_VID0
PEG_GTX_C_HRX_N0 CC219 0.22U_0402_16V7K~D PCIE_CRX_C_GTX_N0 PEX_TX0 +3VSDGPU
2 1 AJ14 AM9
PEG_GTX_C_HRX_P1 CC220 0.22U_0402_16V7K~D PCIE_CRX_C_GTX_P1 PEX_TX0_N DACA_HSYNC
2 1 AH14 AN9
PEG_GTX_C_HRX_N1 CC221 0.22U_0402_16V7K~D PCIE_CRX_C_GTX_N1 PEX_TX1 DACA_VSYNC
2 1 AG14
PEX_TX1_N GPIO12 I GPU_DC# (10K pull High)
PEG_GTX_C_HRX_P2 CC222 2 1 0.22U_0402_16V7K~D PCIE_CRX_C_GTX_P2 AK15 GPU_GPIO3 R2570 1 @ 2 10K_0402_5%~D
PEG_GTX_C_HRX_N2 CC223 0.22U_0402_16V7K~D PCIE_CRX_C_GTX_N2 PEX_TX2 DACA_VDD R2545 1 GPU_GPIO16
2 1 AJ15 AG10 2 10K_0402_5%~D R2571 1 @ 2 10K_0402_5%~D
PEG_GTX_C_HRX_P3 PCIE_CRX_C_GTX_P3 PEX_TX2_N DACA_VDD

PCI EXPRESS
CC224 2 1 0.22U_0402_16V7K~D AL16 AP9 GPIO13 O GPU_VID5
PEG_GTX_C_HRX_N3 CC225 0.22U_0402_16V7K~D PCIE_CRX_C_GTX_N3 PEX_TX3 DACA_VREF
2 1 AK16 AP8
PEG_GTX_C_HRX_P4 CC226 0.22U_0402_16V7K~D PCIE_CRX_C_GTX_P4 PEX_TX3_N DACA_RSET VGA_DDC_CLK R2026 1
2 1 AK17 2 2.2K_0402_5%~D
PEG_GTX_C_HRX_N4 CC227 0.22U_0402_16V7K~D PCIE_CRX_C_GTX_N4 PEX_TX4 VGA_DDC_DATA R2027 1
2 1 AJ17 2 2.2K_0402_5%~D GPIO14 I NC
PEG_GTX_C_HRX_P5 CC228 0.22U_0402_16V7K~D PCIE_CRX_C_GTX_P5 PEX_TX4_N
2 1 AH17
PEG_GTX_C_HRX_N5 CC229 0.22U_0402_16V7K~D PCIE_CRX_C_GTX_N5 PEX_TX5 I2CB_SCL R2028 1
2 1 AG17 2 2.2K_0402_5%~D
PEG_GTX_C_HRX_P6 CC230 0.22U_0402_16V7K~D PCIE_CRX_C_GTX_P6 PEX_TX5_N I2CB_SDA R2029 1
2 1 AK18 2 2.2K_0402_5%~D GPIO15 I NC
PEG_GTX_C_HRX_N6 CC231 0.22U_0402_16V7K~D PCIE_CRX_C_GTX_N6 PEX_TX6
2 1 AJ18
PEG_GTX_C_HRX_P7 CC232 0.22U_0402_16V7K~D PCIE_CRX_C_GTX_P7 PEX_TX6_N VGA_LCD_CLK R2030 1
2 1 AL19 2 2.2K_0402_5%~D
PEG_GTX_C_HRX_N7 CC233 0.22U_0402_16V7K~D PCIE_CRX_C_GTX_N7 PEX_TX7 VGA_DDC_CLK VGA_LCD_DATA R2031 1
2 1 AK19 R4 2 2.2K_0402_5%~D GPIO16 O DPRSLPVR (reserve)
PEG_GTX_C_HRX_P8 CC234 0.22U_0402_16V7K~D PCIE_CRX_C_GTX_P8 PEX_TX7_N I2CA_SCL VGA_DDC_DATA
2 1 AK20 R5
PEG_GTX_C_HRX_N8 CC235 0.22U_0402_16V7K~D PCIE_CRX_C_GTX_N8 PEX_TX8 I2CA_SDA I2CS_SCL R2032 1
2 2 1 AJ20 2 2.2K_0402_5%~D 2
PEG_GTX_C_HRX_P9 CC236 0.22U_0402_16V7K~D PCIE_CRX_C_GTX_P9 PEX_TX8_N I2CB_SCL I2CS_SDA R2033 1
2 1 AH20 R7 2 2.2K_0402_5%~D GPIO17 I VGA_mDP_HPD
PEG_GTX_C_HRX_N9 CC237 0.22U_0402_16V7K~D PCIE_CRX_C_GTX_N9 PEX_TX9 I2CB_SCL I2CB_SDA
2 1 AG20 R6
PEG_GTX_C_HRX_P10 CC238 0.22U_0402_16V7K~D PCIE_CRX_C_GTX_P10 PEX_TX9_N I2CB_SDA
2 1 AK21

I2C
PEG_GTX_C_HRX_N10 CC239 0.22U_0402_16V7K~D PCIE_CRX_C_GTX_N10 PEX_TX10 VGA_LCD_CLK
PEG_GTX_C_HRX_P11 CC240
2 1
0.22U_0402_16V7K~D PCIE_CRX_C_GTX_P11
AJ21
PEX_TX10_N I2CC_SCL
R2
VGA_LCD_DATA L104 +1.05VSDGPU GPIO18 I NC
2 1 AL22 R3
PEG_GTX_C_HRX_N11 CC241 0.22U_0402_16V7K~D PCIE_CRX_C_GTX_N11 PEX_TX11 I2CC_SDA BLM18PG300SN1D_2P~D
2 1 AK22
PEG_GTX_C_HRX_P12 CC242 0.22U_0402_16V7K~D PCIE_CRX_C_GTX_P12 PEX_TX11_N I2CS_SCL +PLLVDD
PEG_GTX_C_HRX_N12
2 1
PCIE_CRX_C_GTX_N12
AK23
PEX_TX12 I2CS_SCL
T4
I2CS_SDA
1 2 GPIO19 I NC
CC243 2 1 0.22U_0402_16V7K~D AJ23 T3
PEG_GTX_C_HRX_P13 CC244 0.22U_0402_16V7K~D PCIE_CRX_C_GTX_P13 PEX_TX12_N I2CS_SDA
2 1 AH23 1
PEG_GTX_C_HRX_N13 CC245 0.22U_0402_16V7K~D PCIE_CRX_C_GTX_N13 PEX_TX13
PEG_GTX_C_HRX_P14
2 1
PCIE_CRX_C_GTX_P14
AG23
PEX_TX13_N GPIO20 Reserved
CC246 2 1 0.22U_0402_16V7K~D AK24
PEX_TX14 under GPU C1948
PEG_GTX_C_HRX_N14 CC247 2 1 0.22U_0402_16V7K~D PCIE_CRX_C_GTX_N14 AJ24 22U_0805_6.3V6M~D
PEG_GTX_C_HRX_P15 CC248 0.22U_0402_16V7K~D PCIE_CRX_C_GTX_P15 PEX_TX14_N close to ball : AD8 2
PEG_GTX_C_HRX_N15 CC249
2 1
0.22U_0402_16V7K~D PCIE_CRX_C_GTX_N15
AL25
PEX_TX15 GPIO21 Reserved
2 1 AK25
PEX_TX15_N
AD8 +PLLVDD 1 2 180ohm (ESR:0.2)
PLLVDD C1949 0.1U_0402_10V7K~D
AJ11
PEX_WAKE_N +3VSDGPU
AE8 +GPU_PLLVDD L105
SP_PLLVDD BLM18PG181SN1_0603~D
(15) CLK_PEG_VGA AL13
PEX_REFCLK 150mA
(15) CLK_PEG_VGA# AK13 AD7 1 2
PEX_REFCLK_N VID_PLLVDD

2
VGA_CLKREQ#
CLK

AK12

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D
0.1U_0402_10V7K~D

0.1U_0402_10V7K~D
PEX_CLKREQ_N

4.7U_0603_6.3V6K~D
1 1 1 1 1
PEX_TSTCLK_OUT+ AJ26 H3 XTALIN N13X Design Guide page173 I2CS_SCL 1 6
PEX_TSTCLK_OUT XTAL_IN EC_SMB_CK2 (15,23,41,43,46,47,53)
1 @ 2 PEX_TSTCLK_OUT- AK26 H2 XTALOUT = 180R@100MHz(ESR=0.2)
R2036 200_0402_1%~D PEX_TSTCLK_OUT_N XTAL_OUT Q306A
PLTRST_VGA# XTAL_OUTBUFF 2 2 2 2 2 DMN66D0LDW-7_SOT363-6~D

C1950

C1951

C1954

C1955

C1956
(17) PLTRST_VGA# AJ12 J4
PEX_TREMP PEX_RST_N XTAL_OUTBUFF XTAL_SSIN
2 1 AP29 H1
R2037 2.49K_0402_1%~D PEX_TERMP XTAL_SSIN +3VSDGPU

5
under GPU
close to ball : AE8,AD7 I2CS_SDA
04/06 : Add 6bit VID Function. N13P-PES-A1_FCBGA908
4 3 EC_SMB_DA2 (15,23,41,43,46,47,53)
Q306B
+3VSDGPU DMN66D0LDW-7_SOT363-6~D
2.2K_0402_5%~D

2.2K_0402_5%~D

2.2K_0402_5%~D

2.2K_0402_5%~D

2.2K_0402_5%~D

2.2K_0402_5%~D

N13P-GT boot voltage: confirm Nvidia +3VSDGPU Y1

3 3
XTALOUT 3 1 XTALIN
OUT IN XTAL_OUTBUFF
4 2
GND GND
2

2
+3VSDGPU
1

1
R2099 R2043
@ @ @ @ @ @ Item13_X02 10K_0402_5%~D C1957 27MHZ_12PF_X3G027000FC1H-H~D C1958 10K_0402_5%~D
10P_0402_50V8J~D 10P_0402_50V8J~D

2
2
G

1
R2038

R2039

R2040

R2041

R2044

R2042
2

1 3 VGA_CLKREQ# Item27_X01
(15) PEG_A_CLKRQ#
XTAL_SSIN
D

VID_0 R2047 1 SHORT 2 0_0402_5%~D

GPU_VID_0 (58)

2
VID_1 R2048 1 SHORT 2 0_0402_5%~D
GPU_VID_1 (58) QV5
VID_2 R2049 1 SHORT 2 0_0402_5%~D R2050
GPU_VID_2 (58) 2N7002K_SOT23-3
VID_3 R2051 1 SHORT 2 0_0402_5%~D 10K_0402_5%~D
GPU_VID_3 (58)
VID_4 R2052 1 SHORT 2 0_0402_5%~D 2 RV52 1
GPU_VID_4 (58)
VID_5 R2053 1 SHORT 2 0_0402_5%~D 0_0402_5%~D
GPU_VID_5 (58)

1
@
R2054

R2055

R2056

R2057

R2058

R2059

Item3_X02
1

@ @ @ @ @ @
2.2K_0402_5%~D

2.2K_0402_5%~D

2.2K_0402_5%~D

2.2K_0402_5%~D

2.2K_0402_5%~D

2.2K_0402_5%~D
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P (1/10) PEG,DAC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 22 of 63
A B C D E
 5 4 3 2 1

+3VSDGPU

VGA Thermal Sensor ADM1032ARMZ

Closed to GPU +3VSDGPU

2
2 RV109
CV275 @ 4.7K_0402_5%~D
@
0.1U_0402_16V7K~D

1
1
UV4
U636D 1 8 EC_SMB_CK2_PX
VDD SCLK
Part 4 of 7 GPU_THERMAL_D+ 2 7 EC_SMB_DA2_PX
CV276 @ D+ SDATA
AM6
D IFPA_TXC THM_ALERT# D
AN6 P8 PAD T205 1 2 3 6
IFPA_TXC_N NC D- ALERT#
AP3 AC6
IFPA_TXD0 NC GPU_THERMAL_D- 2200P_0402_50V7K~D
AN3 AJ28 4 5 1
IFPA_TXD0_N NC THERM# GND @
AN5 AJ4
IFPA_TXD1 NC CV533
AM5 AJ5
IFPA_TXD1_N NC ADM1032ARMZ-2REEL_MSOP8 10P_0402_50V8J~D
AL6 AL11
IFPA_TXD2 NC +3VSDGPU @ 2
AK6 C15
IFPA_TXD2_N NC
Address:100_1101

NC
AJ6 D19
IFPA_TXD3 NC
AH6 D20 1 2
IFPA_TXD3_N NC RV110 @ 4.7K_0402_5%~D
D23
NC
D26
NC
AJ9 H31
IFPB_TXC NC
AH9 T8
IFPB_TXC_N NC +3VSDGPU
AP6 V32
IFPB_TXD4 NC
AP5
IFPB_TXD4_N
AM7
IFPB_TXD5
AL7
IFPB_TXD5_N
AN8
IFPB_TXD6
AM8 Item3_X02
IFPB_TXD6_N

1
AK8
IFPB_TXD7 RV105 RV106
AL8
IFPB_TXD7_N VCCSENSE_VGA_R
L4 2 SHORT 1 2.2K_0402_5%~D 2.2K_0402_5%~D
VDD_SENSE R2078 0_0402_5%~D VCCSENSE_VGA (58)
AK1 +3VSDGPU

2
IFPC_L0
AJ1
IFPC_L0_N VSSSENSE_VGA_R
AJ3 L5 2 SHORT 1 VSSSENSE_VGA (58)
@ @
IFPC_L1 GND_SENSE R2219 0_0402_5%~D
AJ2
IFPC_L1_N

2
AH3
IFPC_L2
AH4
IFPC_L2_N EC_SMB_CK2_PX
AG5 1 6 EC_SMB_CK2 (15,22,41,43,46,47,53)
IFPC_L3
AG4
IFPC_L3_N

5
@ QV4A
TEST DMN66D0LDW-7_SOT363-6~D
VGA_mDP_P0 AM1 AK11 R2082 2 1 10K_0402_5%~D EC_SMB_DA2_PX 4 3
(35) VGA_mDP_P0 IFPD_L0 TESTMODE EC_SMB_DA2 (15,22,41,43,46,47,53)
VGA_mDP_N0 AM2
(35) VGA_mDP_N0 IFPD_L0_N
VGA_mDP_P1 AM3 AM10 JTAG_TCK R2083 2 1 10K_0402_5%~D @ QV4B
(35) VGA_mDP_P1 IFPD_L1 JTAG_TCK
VGA_mDP_N1 AM4 AM11 JTAG_TDI PAD T206 DMN66D0LDW-7_SOT363-6~D
(35) VGA_mDP_N1 IFPD_L1_N JTAG_TDI
C mDP (35) VGA_mDP_P2
VGA_mDP_P2 AL3
IFPD_L2 JTAG_TDO
AP12 JTAG_TDO PAD T207 C
VGA_mDP_N2 AL4 AP11 JTAG_TMS PAD T208
(35) VGA_mDP_N2 IFPD_L2_N JTAG_TMS
VGA_mDP_P3 AK4 AN11 JTAG_TRST PAD T209
(35) VGA_mDP_P3 IFPD_L3 JTAG_TRST_N
VGA_mDP_N3
(35) VGA_mDP_N3 AK5
IFPD_L3_N MULTI LEVEL STRAPS
LVDS/TMDS

2 1
R2084 10K_0402_5%~D
AD2
IFPE_L0 +3VSDGPU
AD3
IFPE_L0_N
AD1 SERIAL
IFPE_L1
AC1
IFPE_L1_N ROM_CS#
AC2 H6 2 R2085 1 10K_0402_5%~D +3VSDGPU
IFPE_L2 ROM_CS_N ROM_SCLK
AC3 H4
IFPE_L2_N ROM_SCLK ROM_SI
AC4 H5
IFPE_L3 ROM_SI

2
AC5 H7 ROM_SO
IFPE_L3_N ROM_SO R2205 R2204 R2200 R2199 R2198 R2203 R2202 R2201

@
@ @ @ @
AE3 10K_0402_1%~D 34.8K_0402_1%~D 20K_0402_1%~D 34.8K_0402_1%~D 45.3K_0402_1%~D 10K_0402_1%~D 34.8K_0402_1%~D 4.99K_0402_1%
IFPF_L0
AE4

1
IFPF_L0_N
AF4
IFPF_L1 ROM_SCLK
AF5 GENERAL
IFPF_L1_N ROM_SI
AD4
IFPF_L2 R2086 @ ROM_SO
AD5 L2 2 1 10K_0402_5%~D
IFPF_L2_N BUFRST_N STRAP0
AG1
IFPF_L3 R2087 STRAP1
AF1 L3 2 1 10K_0402_5%~D +3VSDGPU
IFPF_L3_N CEC STRAP2
J1 MULTI_STRAP_REF0_GND 1 2 STRAP3
MULTI_STRAP_REF0_GND R2088 40.2K_0402_1%~D STRAP4
AG3
IFPC_AUX_I2CW_SCL

2
AG2
IFPC_AUX_I2CW_SDA_N STRAP0 R2213 R2212 R2208 R2207 R2206 R2211 R2210 R2209
J2
STRAP0

@
J7 STRAP1 Item11_X03 VRAM@
VGA_mDP_AUXP/DDC STRAP1 STRAP2 45.3K_0402_1%~D 24.9K_0402_1%~D 10K_0402_1%~D 45.3K_0402_1%~D 4.99K_0402_1% 10K_0402_1%~D 45.3K_0402_1%~D 15K_0402_1%~D
(35) VGA_mDP_AUXP/DDC AK3 J6
VGA_mDP_AUXN/DDC IFPD_AUX_I2CX_SCL STRAP2 STRAP3
(35) VGA_mDP_AUXN/DDC AK2 J5

1
IFPD_AUX_I2CX_SDA_N STRAP3 STRAP4
J3
STRAP4
AB3
IFPE_AUX_I2CY_SCL
AB4
IFPE_AUX_I2CY_SDA_N GPU_THERMAL_D+
K3
B THERMDP GPU_THERMAL_D- B
K4
THERMDN
AF3
IFPF_AUX_I2CZ_SCL
AF2
IFPF_AUX_I2CZ_SDA_N

N13P-PES-A1_FCBGA908
For N13P-GT strap table
ROM_SO STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
GPU Frenq. Memory Size Memory Config ROM_SCLK ROM_SI (PCIe driving) (ES PH20K)

N13P-GT 2500 MHz 64M* 16* 8 Samsung PL 45.3K

1GB SA00003RS0L PH 5K SD03445328L PH 10K PH 45K PL 45K PL 10K PL 25K PL 10K

N13P-GT 2500 MHz 64M* 16* 8 Hynix PL 34.8K

1GB SA00003WL0L PH 5K SD03434828L PH 10K PH 45K PL 45K PL 10K PL 25K PL 10K

N13P-GT 2500 MHz 128M* 16* 8 Samsung PL 30.1K

2GB SA000048E0L PH 5K SD03430128L PH 10K PH 45K PL 45K PL 10K PL 25K PL 10K

N13P-GT 2500 MHz 128M* 16* 8 Hynix PL 24.9K

2GB SA00004GD0L PH 5K SD03424928L PH 10K PH 45K PL 45K PL 10K PL 25K PL 10K

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P (2/10) mDP, Strapping
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 23 of 63
5 4 3 2 1
 5 4 3 2 1

Under GPU Near GPU

+1.05VSDGPU

1U_0603_10V7K~D

1U_0603_10V7K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D
4.7U_0603_6.3V6K~D
1 1 1 1 1

1
Design guide no define

C1965

C1966

C1967

C1968

C1969

C1970

C1971
2

2
+1.5VSDGPU 2 2 2 2 2
U636E

Near GPU Part 5 of 7

Under GPU 7200mA
AA27 AG19 +1.05VSDGPU
D FBVDDQ_0 PEX_IOVDD_0 D
AA30 AG21
22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D
FBVDDQ_1 PEX_IOVDD_1
1 1 1 1 1 1 1 1 1 1 AB27 AG22
@ @ @ @ @ FBVDDQ_2 PEX_IOVDD_2
AB33 AG24

1U_0603_10V7K~D

1U_0603_10V7K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D
4.7U_0603_6.3V6K~D
FBVDDQ_3 PEX_IOVDD_3
AC27
FBVDDQ_4 PEX_IOVDD_4
AH21 3500 mA 1 1 1 1 1

1
C2137

C2138

C2139

C2140

C1985

C1972

C1974

C1975

C1976

C1977
AD27 AH25
2 2 2 2 2 2 2 2 2 2 FBVDDQ_5 PEX_IOVDD_5
AE27
FBVDDQ_6 total 3500mA

C1978

C1979

C1980

C1981

C1982

C1983

C1984
AF27
Design guide V04

2
FBVDDQ_7 2 2 2 2 2
AG27 AG13
FBVDDQ_8 PEX_IOVDDQ_0
B13 AG15
FBVDDQ_9 PEX_IOVDDQ_1
Near GPU B16 AG16
FBVDDQ_10 PEX_IOVDDQ_2
B19 AG18
FBVDDQ_11 PEX_IOVDDQ_3
E13 AG25
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

FBVDDQ_12 PEX_IOVDDQ_4
4.7U_0603_6.3V6K~D

4.7U_0603_6.3V6K~D

4.7U_0603_6.3V6K~D

4.7U_0603_6.3V6K~D

4.7U_0603_6.3V6K~D

4.7U_0603_6.3V6K~D
E16 AH15 +3VSDGPU
1 1 1 1 1 1 1 1 FBVDDQ_13 PEX_IOVDDQ_5
@ @ @ E19 AH18 Near GPU
FBVDDQ_14 PEX_IOVDDQ_6
H10 AH26
FBVDDQ_15 PEX_IOVDDQ_7
1 SHORT 2
C2141

C2142

C2132

C2133

C1986

C1987

C1988

C1989
H11 AH27
2 2 2 2 2 2 2 2 FBVDDQ_16 PEX_IOVDDQ_8 L113 0_0603_5%~D
H12 AJ27

0.1U_0402_10V7K~D
FBVDDQ_17 PEX_IOVDDQ_9

4.7U_0603_6.3V6K~D

4.7U_0603_6.3V6K~D
H13 AK27 1 1 1 Item4_X03
FBVDDQ_18 PEX_IOVDDQ_10
H14 AL27

POWER
FBVDDQ_19 PEX_IOVDDQ_11
H15 AM28
FBVDDQ_20 PEX_IOVDDQ_12
H16 AN28
FBVDDQ_21 PEX_IOVDDQ_13 2 2 2
Near GPU

C1991

C1992

C2145
H18
FBVDDQ_22
Under GPU H19
FBVDDQ_23
H20
FBVDDQ_24 150mA +PEX_PLL_HVDD
370mA
H21 AH12
1U_0603_10V7K~D

1U_0603_10V7K~D

1U_0603_10V7K~D

1U_0603_10V7K~D

1U_0603_10V7K~D

1U_0603_10V7K~D
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

FBVDDQ_25 PEX_PLL_HVDD +1.05VSDGPU

1 1 H22
FBVDDQ_26
1

@ @ @ @ @ H23 Under GPU Near GPU L107

FBVDDQ_27
H24 1 SHORT 2
FBVDDQ_28 0_0603_5%~D
H8 AG12

1U_0603_10V7K~D
2

0.1U_0402_10V7K~D
FBVDDQ_29 PEX_SVDD_3V3

4.7U_0603_6.3V6K~D
2 2
C1994

C1995

H9 1 1 Item4_X03
FBVDDQ_30

1
N13P
C2143

C2144

C1996

C1997

C1990

C1973

L27
FBVDDQ_31
M27
FBVDDQ_32 +PEX_PLLVDD
150mA Reference Sch = 120R@100MHz
N27 AG26

C2001 2
FBVDDQ_33 PEX_PLLVDD 2 2

C2000

C2002
P27
FBVDDQ_34
R27
FBVDDQ_35 Q309
T27
FBVDDQ_36 +VDD33
120mA AO3419L_SOT23-3
T30 J8
FBVDDQ_37 VDD33_0
C T33
FBVDDQ_38 VDD33_1
K8 Design guide no define C

D
V27 L8 3 1
FBVDDQ_39 VDD33_2
W27 M8

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D
FBVDDQ_40 VDD33_3
W30 1 1
FBVDDQ_41
W33

G
2
FBVDDQ_42
Y27
FBVDDQ_43 +IFPAB_PLLVDD R2546 1
AH8 2 10K_0402_5%~D
IFPAB_PLLVDD 2 2

C2005

C2003
AJ8
IFPAB_RSET
DGPU_PWR_EN_R# (31)
+1.5VSDGPU AG8 +IFPAB_IOVDD R2547 1 2 10K_0402_5%~D
IFPA_IOVDD
AG9
FB_VDDQ_SENSE IFPB_IOVDD
1 2 F1
R2093 100_0402_1%~D FB_VDDQ_SENSE +3VSDGPU
Under GPU (one per pin)
AF7 +IFPC_PLLVDD R2094 1 2 10K_0402_5%~D
FB_GND_SENSE IFPC_PLLVDD
1 2 F2 AF8 1 SHORT 2
+1.5VSDGPU R2095 100_0402_1%~D FB_GND_SENSE IFPC_RSET R2089

1U_0603_10V7K~D
0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

4.7U_0603_6.3V6K~D
AF6 +IFPC_IOVDD R2097 1 2 10K_0402_5%~D 1 1 1 0_0603_5%~D
IFPC_IOVDD

1
1 2 FB_CAL_PD_VDDQ J27 Item4_X03
R2098 40.2_0402_1%~D FB_CAL_PD_VDDQ
AG7 +IFPD_PLLVDD

C2008 2
FB_CAL_PU_GND IFPD_PLLVDD R2101 1 2 2 2
2 1K_0402_1%~D

C2006

C2004

C2009
1 2 H27 AN2
R2100 40.2_0402_1%~D FB_CAL_PU_GND IFPD_RSET
AG6 +IFPD_IOVDD
FB_CAL_TERM_GND IFPD_IOVDD
1 2 H25
R2103 60.4_0402_1%~D FB_CAL_TERM_GND
AB8 +IFPEF_PLLVDD R2104 1 2 10K_0402_5%~D
IFPEF_PLVDD
AD6
IFPEF_RSET L110 +3VSDGPU
Near GPU
AC7 +IFPEF_IOVDD R2548 1 2 10K_0402_5%~D Under GPU Near GPU FCM1608CF-301T03
IFPE_IOVDD
AC8 1 2
IFPF_IOVDD

1U_0603_10V7K~D
0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

4.7U_0603_6.3V6K~D
1 1 1 1 MMZ1608R301AT

1
300R@100MHz, ESR=0.25 ohm
N13P

C2068 2
N13P-PES-A1_FCBGA908 2 2 2 2 Reference Sch = 300R@100MHz

C2134

C2135

C2067

C2066
B B

+1.05VSDGPU
L112
Under GPU Near GPU
2 1
BLM15AG121SN1D_2P~D

1U_0603_10V7K~D
0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

4.7U_0603_6.3V6K~D
1 1 1 Item5_X02

1
BLM18AG221SN1D
220R@100MHz, ESR=0.3 ohm

C2071 2
2 2 2

C2136

C2070

C2069
N13P
Reference Sch = 220R@100MHz

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P (3/10) POWER & GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 24 of 63
5 4 3 2 1
 5 4 3 2 1

+VGA_CORE
U636F +VGA_CORE
U636G
Part 6 of 7
A2 D2
GND_0 GND_100 Part 7 of 7
AA17 D31 V17
GND_1 GND_101 VDD_56
AA18 D33 AA12 V18
GND_2 GND_102 VDD_0 VDD_57
AA20 E10 AA14 V20
GND_3 GND_103 VDD_1 VDD_58
AA22 E22 AA16 V22
GND_4 GND_104 VDD_2 VDD_59
AB12 E25 AA19 W12
D GND_5 GND_105 VDD_3 VDD_60 D
AB14 E5 AA21 W14
GND_6 GND_106 VDD_4 VDD_61
AB16 E7 AA23 W16
GND_7 GND_107 VDD_5 VDD_62
AB19 F28 AB13 W19
GND_8 GND_108 VDD_6 VDD_63
AB2 F7 AB15 W21
GND_9 GND_109 VDD_7 VDD_64
AB21 G10 AB17 W23
GND_10 GND_110 VDD_8 VDD_65
A33 G13 AB18 Y13
GND_11 GND_111 VDD_9 VDD_66
AB23 G16 AB20 Y15
GND_12 GND_112 VDD_10 VDD_67
AB28 G19 AB22 Y17
GND_13 GND_113 VDD_11 VDD_68
AB30 G2 AC12 Y18
GND_14 GND_114 VDD_12 VDD_69
AB32 G22 AC14 Y20
GND_15 GND_115 VDD_13 VDD_70
AB5 G25 AC16 Y22
GND_16 GND_116 VDD_14 VDD_71
AB7 G28 AC19
GND_17 GND_117 VDD_15
AC13 G3 AC21
GND_18 GND_118 VDD_16
AC15 G30 AC23 U1
GND_19 GND_119 VDD_17 XVDD_1
AC17 G32 M12 U2
GND_20 GND_120 VDD_18 XVDD_2
AC18 G33 M14 U3
GND_21 GND_121 VDD_19 XVDD_3

POWER
AA13 G5 M16 U4
GND_22 GND_122 VDD_20 XVDD_4
AC20 G7 M19 U5
GND_23 GND_123 VDD_21 XVDD_5
AC22 K2 M21 U6
GND_24 GND_124 VDD_22 XVDD_6
AE2 K28 M23 U7
GND_25 GND_125 VDD_23 XVDD_7
AE28 K30 N13 U8
GND_26 GND_126 VDD_24 XVDD_8
AE30 K32 N15
GND_27 GND_127 VDD_25
AE32 K33 N17
GND_28 GND_128 VDD_26
AE33 K5 N18 V1
GND_29 GND_129 VDD_27 XVDD_9
AE5 K7 N20 V2
GND_30 GND_130 VDD_28 XVDD_10
AE7 M13 N22 V3
GND_31 GND_131 VDD_29 XVDD_11
AH10 M15 P12 V4
GND_32 GND_132 VDD_30 XVDD_12
AA15 M17 P14 V5
GND_33 GND_133 VDD_31 XVDD_13
AH13 M18 P16 V6
GND_34 GND_134 VDD_32 XVDD_14
AH16 M20 P19 V7
GND_35 GND_135 VDD_33 XVDD_15
AH19 M22 P21 V8
GND_36 GND_136 VDD_34 XVDD_16
AH2 N12 P23
GND_37 GND_137 VDD_35
AH22 N14 R13
GND_38 GND_138 VDD_36
AH24 N16 R15 W2
GND_39 GND_139 VDD_37 XVDD_17
AH28 N19 R17 W3
GND_40 GND_140 VDD_38 XVDD_18
AH29 N2 R18 W4
GND_41 GND_141 VDD_39 XVDD_19
AH30 N21 R20 W5
GND_42 GND_142 VDD_40 XVDD_20
GND
C AH32 N23 R22 W7 C
GND_43 GND_143 VDD_41 XVDD_21
AH33 N28 T12 W8
GND_44 GND_144 VDD_42 XVDD_22
AH5 N30 T14
GND_45 GND_145 VDD_43
AH7 N32 T16
GND_46 GND_146 VDD_44
AJ7 N33 T19 Y1
GND_47 GND_147 VDD_45 XVDD_23
AK10 N5 T21 Y2
GND_48 GND_148 VDD_46 XVDD_24
AK7 N7 T23 Y3
GND_49 GND_149 VDD_47 XVDD_25
AL12 P13 U13 Y4
GND_50 GND_150 VDD_48 XVDD_26
AL14 P15 U15 Y5
GND_51 GND_151 VDD_49 XVDD_27
AL15 P17 U17 Y6
GND_52 GND_152 VDD_50 XVDD_28
AL17 P18 U18 Y7
GND_53 GND_153 VDD_51 XVDD_29
AL18 P20 U20 Y8
GND_54 GND_154 VDD_52 XVDD_30
AL2 P22 U22
GND_55 GND_155 VDD_53
AL20 R12 V13
GND_56 GND_156 VDD_54
AL21 R14 V15 AA1
GND_57 GND_157 VDD_55 XVDD_31
AL23 R16 AA2
GND_58 GND_158 XVDD_32
AL24 R19 AA3
GND_59 GND_159 XVDD_33
AL26 R21 AA4
GND_60 GND_160 XVDD_34
AL28 R23 AA5
GND_61 GND_161 XVDD_35
AL30 T13 AA6
GND_62 GND_162 XVDD_36
AL32 T15 AA7
GND_63 GND_163 XVDD_37
AL33 T17 AA8
GND_64 GND_164 XVDD_38
AL5 T18
GND_65 GND_165
AM13 T2
GND_66 GND_166
AM16 T20
GND_67 GND_167
AM19 T22
GND_68 GND_168 N13P-PES-A1_FCBGA908
AM22 AG11
GND_69 GND_169
AM25 T28
GND_70 GND_170
AN1 T32
GND_71 GND_171
AN10 T5
GND_72 GND_172
AN13 T7
GND_73 GND_173
AN16 U12
GND_74 GND_174
AN19 U14
GND_75 GND_175
AN22 U16
GND_76 GND_176
AN25 U19
AN30
GND_77
GND_78
GND_177
GND_178
U21 SEQUENCE
AN34 U23
GND_79 GND_179
AN4 V12
B GND_80 GND_180 B
AN7 V14
GND_81 GND_181
AP2 V16
AP33
B1
GND_82
GND_83
GND_84
GND_182
GND_183
GND_184
V19
V21
GPU Power Up Power Rail Sequence GPU Power Up Sub-system Sequence
B10
GND_85 GND_185
V23 T1
B22
GND_86 GND_186
W13 T8
B25 W15
GND_87 GND_187
B28
GND_88 GND_188
W17 Driver call
B31 W18 to enable GPU
GND_89 GND_189
B34
GND_90 GND_190
W20 +3V_GPU
B4 W22
GND_91 GND_191
B7
GND_92 GND_192
W28 Power EN
C10 Y12
GND_93 GND_193
C13
GND_94 GND_194
Y14 +GPU_CORE
C19
GND_95 GND_195
Y16 NV3V3Pgood
C22 Y19
GND_96 GND_196
C25 Y21
GND_97 GND_197
C28
GND_98 GND_198
Y23 +1.5V_GPU 27Mhz
C7 AH11
GND_99 GND_199
C16
GND_OPT
GND_OPT
W32 GPU all PG
+1.05V_GPU
The ramp time for any rail must be more than 40us. CLK REQ#
N13P-PES-A1_FCBGA908
100MHz

GPU Power Down Sequence GPU Reset#

First rail to power down PCIe Training

A Toff < 10ms T9 T2 T3 T4 T5 T6 T7 A

Last rail to power down
GPU Power Up Sub-system Sequence

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P (4/10) POWER & GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 25 of 63
5 4 3 2 1
 A

VRAM Interface (27) MDA[15..0]

(27) MDA[31..16]
MDA[15..0]

MDA[31..16] (29) MDC[15..0]

MDC[15..0]

MDC[31..16]
MDA[47..32] (29) MDC[31..16]
(28) MDA[47..32] MDC[47..32]
MDA[63..48] (30) MDC[47..32]
(28) MDA[63..48] MDC[63..48]
(30) MDC[63..48]

U636B U636C
CMDA[31..0] (27,28) CMDC[31..0] (29,30)
Part 2 of 7 Part 3 of 7
MDA0 L28 U30 CMDA0 MDC0 G9 D13 CMDC0
MDA1 FBA_D0 FBA_CMD0 CMDA1 MDC1 FBB_D0 FBB_CMD0 CMDC1
M29 T31 E9 E14
MDA2 FBA_D1 FBA_CMD1 CMDA2 MDC2 FBB_D1 FBB_CMD1 CMDC2
L29 U29 G8 F14
MDA3 FBA_D2 FBA_CMD2 CMDA3 MDC3 FBB_D2 FBB_CMD2 CMDC3
M28 R34 F9 A12
MDA4 FBA_D3 FBA_CMD3 CMDA4 MDC4 FBB_D3 FBB_CMD3 CMDC4
N31 R33 F11 B12
MDA5 FBA_D4 FBA_CMD4 CMDA5 MDC5 FBB_D4 FBB_CMD4 CMDC5
P29 U32 G11 C14
MDA6 FBA_D5 FBA_CMD5 CMDA6 MDC6 FBB_D5 FBB_CMD5 CMDC6
R29 U33 F12 B14
MDA7 FBA_D6 FBA_CMD6 CMDA7 MDC7 FBB_D6 FBB_CMD6 CMDC7
P28 U28 G12 G15
MDA8 FBA_D7 FBA_CMD7 CMDA8 MDC8 FBB_D7 FBB_CMD7 CMDC8
J28 V28 G6 F15
MDA9 FBA_D8 FBA_CMD8 CMDA9 MDC9 FBB_D8 FBB_CMD8 CMDC9
H29 V29 F5 E15
MDA10 FBA_D9 FBA_CMD9 CMDA10 MDC10 FBB_D9 FBB_CMD9 CMDC10
J29 V30 E6 D15
MDA11 FBA_D10 FBA_CMD10 CMDA11 MDC11 FBB_D10 FBB_CMD10 CMDC11
H28 U34 F6 A14
MDA12 FBA_D11 FBA_CMD11 CMDA12 MDC12 FBB_D11 FBB_CMD11 CMDC12
G29 U31 F4 D14
MDA13 FBA_D12 FBA_CMD12 CMDA13 MDC13 FBB_D12 FBB_CMD12 CMDC13
E31 V34 G4 A15
MDA14 FBA_D13 FBA_CMD13 CMDA14 MDC14 FBB_D13 FBB_CMD13 CMDC14 +1.5VSDGPU
E32 V33 E2 B15
MDA15 FBA_D14 FBA_CMD14 CMDA15 +1.5VSDGPU MDC15 FBB_D14 FBB_CMD14 CMDC15
F30 Y32 F3 C17
MDA16 FBA_D15 FBA_CMD15 CMDA16 MDC16 FBB_D15 FBB_CMD15 CMDC16
C34 AA31 C2 D18
MDA17 FBA_D16 FBA_CMD16 CMDA17 MDC17 FBB_D16 FBB_CMD16 CMDC17 CMDC14 R2178 2 10K_0402_5%~D
D32 AA29 D4 E18 1
MDA18 FBA_D17 FBA_CMD17 CMDA18 CMDA14 FBB_D17 FBB_CMD17
B33 AA28 2 R2179 1 10K_0402_5%~D MDC18 D3 F18 CMDC18 CMDC30 1 R2180 2 10K_0402_5%~D
MDA19 FBA_D18 FBA_CMD18 CMDA19 CMDA30 MDC19 FBB_D18 FBB_CMD18 CMDC19
C33 AC34 2 R2181 1 10K_0402_5%~D C1 A20
MDA20 FBA_D19 FBA_CMD19 CMDA20 MDC20 FBB_D19 FBB_CMD19 CMDC20
F33 AC33 B3 B20
MDA21 FBA_D20 FBA_CMD20 CMDA21 MDC21 FBB_D20 FBB_CMD20 CMDC21
F32 AA32 C4 C18
MDA22 FBA_D21 FBA_CMD21 CMDA22 MDC22 FBB_D21 FBB_CMD21 CMDC22 CMDC13 R2182 2 10K_0402_5%~D
H33 AA33 B5 B18 1
MDA23 FBA_D22 FBA_CMD22 CMDA23 CMDA13 FBB_D22 FBB_CMD22
H32 Y28 2 R2177 1 10K_0402_5%~D MDC23 C5 G18 CMDC23 CMDC29 1 R2183 2 10K_0402_5%~D
MDA24 FBA_D23 FBA_CMD23 CMDA24 CMDA29 MDC24 FBB_D23 FBB_CMD23 CMDC24
2 R2184 1 10K_0402_5%~D
MEMORY INTERFACE
P34 Y29 A11 G17
MDA25 FBA_D24 FBA_CMD24 CMDA25 MDC25 FBB_D24 FBB_CMD24 CMDC25
P32 W31 C11 F17
FBA_D25 FBA_CMD25 FBB_D25 FBB_CMD25

MEMORY INTERFACE B
MDA26 P31 Y30 CMDA26 MDC26 D11 D16 CMDC26
MDA27 FBA_D26 FBA_CMD26 CMDA27 MDC27 FBB_D26 FBB_CMD26 CMDC27
P33 AA34 B11 A18
MDA28 FBA_D27 FBA_CMD27 CMDA28 MDC28 FBB_D27 FBB_CMD27 CMDC28
L31 Y31 D8 D17
MDA29 FBA_D28 FBA_CMD28 CMDA29 MDC29 FBB_D28 FBB_CMD28 CMDC29
L34 Y34 A8 A17
MDA30 FBA_D29 FBA_CMD29 CMDA30 MDC30 FBB_D29 FBB_CMD29 CMDC30
L32 Y33 C8 B17
MDA31 FBA_D30 FBA_CMD30 CMDA31 MDC31 FBB_D30 FBB_CMD30 CMDC31
L33 V31 B8 E17
MDA32 FBA_D31 FBA_CMD31 MDC32 FBB_D31 FBB_CMD31
AG28 F24
MDA33 FBA_D32 MDC33 FBB_D32
AF29 G23
MDA34 FBA_D33 MDC34 FBB_D33
AG29 E24
MDA35 FBA_D34 MDC35 FBB_D34
AF28 R32 G24 C12
MDA36 FBA_D35 FBA_CMD_RFU0 MDC36 FBB_D35 FBB_CMD_RFU0
AD30 AC32 D21 C20
MDA37 FBA_D36 FBA_CMD_RFU1 MDC37 FBB_D36 FBB_CMD_RFU1
AD29 E21
MDA38 FBA_D37 +1.5VSDGPU MDC38 FBB_D37 +1.5VSDGPU
AC29 G21
MDA39 FBA_D38 MDC39 FBB_D38
AD28 F21
FBA_D39 FBB_D39
A

MDA40 AJ29 R28 FBA_DEBUG0 R2060 2 @ 1 60.4_0402_1%~D MDC40 G27 G14 FBB_DEBUG0 R2061 2 @ 1 60.4_0402_1%~D
MDA41 FBA_D40 FBA_DEBUG0 FBB_D40 FBB_DEBUG0
AK29 AC28 FBA_DEBUG1 R2062 2 @ 1 60.4_0402_1%~D MDC41 D27 G20 FBB_DEBUG1 R2063 2 @ 1 60.4_0402_1%~D
MDA42 FBA_D41 FBA_DEBUG1 MDC42 FBB_D41 FBB_DEBUG1
AJ30 G26
MDA43 FBA_D42 MDC43 FBB_D42
AK28 E27
MDA44 FBA_D43 MDC44 FBB_D43
AM29 E29
MDA45 FBA_D44 MDC45 FBB_D44
AM31 R30 CLKA0 (27) F29 D12 CLKC0 (29)
MDA46 FBA_D45 FBA_CLK0 MDC46 FBB_D45 FBB_CLK0
AN29 R31 CLKA0# (27) E30 E12 CLKC0# (29)
MDA47 FBA_D46 FBA_CLK0_N MDC47 FBB_D46 FBB_CLK0_N
AM30 AB31 CLKA1 (28) D30 E20 CLKC1 (30)
MDA48 FBA_D47 FBA_CLK1 MDC48 FBB_D47 FBB_CLK1
AN31 AC31 CLKA1# (28) A32 F20 CLKC1# (30)
MDA49 FBA_D48 FBA_CLK1_N MDC49 FBB_D48 FBB_CLK1_N
AN32 C31
MDA50 FBA_D49 MDC50 FBB_D49
AP30 C32
MDA51 FBA_D50 MDC51 FBB_D50
AP32 B32
MDA52 FBA_D51 MDC52 FBB_D51
AM33 K31 WCKA0 (27) D29 F8 WCKC0 (29)
MDA53 FBA_D52 FBA_WCK01 MDC53 FBB_D52 FBB_WCK01
AL31 L30 WCKA0_N (27) A29 E8 WCKC0_N (29)
MDA54 FBA_D53 FBA_WCK01_N MDC54 FBB_D53 FBB_WCK01_N
AK33 H34 WCKA1 (27) C29 A5 WCKC1 (29)
MDA55 FBA_D54 FBA_WCK23 MDC55 FBB_D54 FBB_WCK23
1 AK32 J34 WCKA1_N (27) B29 A6 WCKC1_N (29) 1

MDA56 FBA_D55 FBA_WCK23_N MDC56 FBB_D55 FBB_WCK23_N

AD34 AG30 WCKA2 (28) B21 D24 WCKC2 (30)
MDA57 FBA_D56 FBA_WCK45 MDC57 FBB_D56 FBB_WCK45
AD32 AG31 WCKA2_N (28) C23 D25 WCKC2_N (30)
MDA58 FBA_D57 FBA_WCK45_N MDC58 FBB_D57 FBB_WCK45_N
AC30 AJ34 WCKA3 (28) A21 B27 WCKC3 (30)
MDA59 FBA_D58 FBA_WCK67 MDC59 FBB_D58 FBB_WCK67
AD33 AK34 WCKA3_N (28) C21 C27 WCKC3_N (30)
MDA60 FBA_D59 FBA_WCK67_N MDC60 FBB_D59 FBB_WCK67_N
AF31 B24
MDA61 FBA_D60 MDC61 FBB_D60
AG34 C24
MDA62 FBA_D61 MDC62 FBB_D61
AG32 B26
MDA63 FBA_D62 MDC63 FBB_D62
AG33 J30 C26 D6
FBA_D63 FBA_WCKB01 FBB_D63 FBB_WCKB01
(27) DQMA[3..0] J31 (29) DQMC[3..0] D7
DQMA0 FBA_WCKB01_N DQMC0 FBB_WCKB01_N
P30 J32 E11 C6
DQMA1 FBA_DQM0 FBA_WCKB23 DQMC1 FBB_DQM0 FBB_WCKB23
F31 J33 E3 B6
DQMA2 FBA_DQM1 FBA_WCKB23_N DQMC2 FBB_DQM1 FBB_WCKB23_N
F34 AH31 A3 F26
DQMA3 FBA_DQM2 FBA_WCKB45 DQMC3 FBB_DQM2 FBB_WCKB45
(28) DQMA[7..4] M32 AJ31 (30) DQMC[7..4] C9 E26
DQMA4 FBA_DQM3 FBA_WCKB45_N DQMC4 FBB_DQM3 FBB_WCKB45_N
AD31 AJ32 F23 A26
DQMA5 FBA_DQM4 FBA_WCKB67 DQMC5 FBB_DQM4 FBB_WCKB67
AL29 AJ33 F27 A27
DQMA6 FBA_DQM5 FBA_WCKB67_N DQMC6 FBB_DQM5 FBB_WCKB67_N
AM32 C30
DQMA7 FBA_DQM6 DQMC7 FBB_DQM6
AF34 A24
FBA_DQM7 FBB_DQM7
(27) EDCA[3..0] (29) EDCC[3..0]
EDCA0 M31 E1 FB_CLAMP 1 2 EDCC0 D10
EDCA1 FBA_DQS_WP0 FB_CLAMP R2544 10K_0402_5%~D EDCC1 FBB_DQS_WP0
G31 D5
FBA_DQS_WP1 FBB_DQS_WP1
EDCA2 E33
FBA_DQS_WP2 Under GPU EDCC2 C3
FBB_DQS_WP2
EDCA3 M33 EDCC3 B9
(28) EDCA[7..4]
EDCA4 AE31
FBA_DQS_WP3
K27
close to ball : K27 (30) EDCC[7..4]
EDCC4 E23
FBB_DQS_WP3
H17 +FB_PLLAVDD N13P-PES=1.05V
EDCA5 FBA_DQS_WP4 FB_DLL_AVDD EDCC5 FBB_DQS_WP4 FBB_PLL_AVDD
AK30
FBA_DQS_WP5 100mA E28
FBB_DQS_WP5 100mA N13P/M=1.0V
EDCA6 AN33 1 2 C1959 EDCC6 B30

0.1U_0402_10V7K~D
EDCA7 FBA_DQS_WP6 0.1U_0402_10V7K~D EDCC7 FBB_DQS_WP6
AF33 A23
FBA_DQS_WP7 +FB_PLLAVDD FBB_DQS_WP7
U27 1
FBA_PLL_AVDD +FB_PLLAVDD L106 +1.05VSDGPU
300mA

C1961
M30 D9
FBA_DQS_RN0 FBB_DQS_RN0
H30 1 2 C1960 E4 BLM18PG300SN1D_2P~D
FBA_DQS_RN1 0.1U_0402_10V7K~D FBB_DQS_RN1 +FB_PLLAVDD
E34 B2 1 2
FBA_DQS_RN2 FBB_DQS_RN2 2

1U_0402_6.3V6K~D
M34 H26 A9
FBA_DQS_RN3 FB_VREF FBB_DQS_RN3 30ohm (ESR:0.05)
AF30 D22 1

22U_0805_6.3V6M~D
1U_0402_6.3V6K~D
FBA_DQS_RN4 FBB_DQS_RN4
AK31
FBA_DQS_RN5 Under GPU D28
FBB_DQS_RN5 1 1

C1964
CV48 Under GPU

C1962

C1963
AM34 close to ball : U27 A30
FBA_DQS_RN6 FBB_DQS_RN6
AF32 B23
FBA_DQS_RN7 FBB_DQS_RN7 close to ball : H17 2
2 2

Near GPU
N13P-PES-A1_FCBGA908 N13P-PES-A1_FCBGA908

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P (5/10) VRAM interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 26 of 63
A
 5 4 3 2 1

Memory Partition A - Lower 32 bits

UV20 UV21

MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

A4 MDA0 A4 MDA24
EDCA0 DQ24 DQ0 MDA1 EDCA3 DQ24 DQ0 MDA25
C2 A2 C2 A2
D EDC0 EDC3 DQ25 DQ1 MDA2 EDC0 EDC3 DQ25 DQ1 MDA26 D
(26) MDA[0..31] C13 B4 C13 B4
EDCA2 EDC1 EDC2 DQ26 DQ2 MDA3 EDCA1 EDC1 EDC2 DQ26 DQ2 MDA27
R13
EDC2 EDC1 DQ27 DQ3
B2 BYTE0 R13
EDC2 EDC1 DQ27 DQ3
B2
R2 E4 MDA4 R2 E4 MDA28 BYTE3
EDC3 EDC0 DQ28 DQ4 MDA5 EDC3 EDC0 DQ28 DQ4 MDA29
(26) EDCA[3..0] E2 E2
DQ29 DQ5 MDA6 DQ29 DQ5 MDA30
F4 F4
DQMA0 DQ30 DQ6 MDA7 DQMA3 DQ30 DQ6 MDA31
D2 F2 D2 F2
DBI0# DBI3# DQ31 DQ7 DBI0# DBI3# DQ31 DQ7
(26) DQMA[3..0] D13 A11 D13 A11
DQMA2 DBI1# DBI2# DQ16 DQ8 DQMA1 DBI1# DBI2# DQ16 DQ8
P13 A13 P13 A13
DBI2# DBI1# DQ17 DQ9 DBI2# DBI1# DQ17 DQ9
P2 B11 P2 B11
DBI3# DBI0# DQ18 DQ10 DBI3# DBI0# DQ18 DQ10
(26) CMDA[15..0] B13 B13
CLKA0 DQ19 DQ11 CLKA0 DQ19 DQ11
J12 E11 J12 E11
CLKA0# CK DQ20 DQ12 CLKA0# CK DQ20 DQ12
J11 E13 J11 E13
CMDA14 CK# DQ21 DQ13 CMDA14 CK# DQ21 DQ13
J3 F11 J3 F11
CKE# DQ22 DQ14 CKE# DQ22 DQ14
F13 F13
DQ23 DQ15 MDA16 DQ23 DQ15 MDA8
U11 U11
CMDA2 DQ8 DQ16 MDA17 CMDA3 DQ8 DQ16 MDA9
H11 U13 H11 U13
CMDA4 BA0/A2 BA2/A4 DQ9 DQ17 MDA18 CMDA1 BA0/A2 BA2/A4 DQ9 DQ17 MDA10
K10 T11 K10 T11
CMDA3 BA1/A5 BA3/A3 DQ10 DQ18 MDA19 CMDA2 BA1/A5 BA3/A3 DQ10 DQ18 MDA11
Follow DG v04 K11
BA2/A4 BA0/A2 DQ11 DQ19
T13 K11
BA2/A4 BA0/A2 DQ11 DQ19
T13 BYTE1
CMDA1 H10 N11 MDA20 BYTE2 CMDA4 H10 N11 MDA12
BA3/A3 BA1/A5 DQ12 DQ20 MDA21 BA3/A3 BA1/A5 DQ12 DQ20 MDA13
N13 N13
DQ13 DQ21 MDA22 DQ13 DQ21 MDA14
M11 M11
CLKA0 CMDA6 DQ14 DQ22 MDA23 CMDA10 DQ14 DQ22 MDA15
(26) CLKA0 1 2 K4 M13 K4 M13
RV347 40.2_0402_1%~D CMDA11 A8/A7 A10/A0 DQ15 DQ23 CMDA7 A8/A7 A10/A0 DQ15 DQ23
H5 U4 H5 U4
CMDA10 A9/A1 A11/A6 DQ0 DQ24 CMDA6 A9/A1 A11/A6 DQ0 DQ24
H4 U2 H4 U2
CMDA7 A10/A0 A8/A7 DQ1 DQ25 CMDA11 A10/A0 A8/A7 DQ1 DQ25
K5 T4 K5 T4
CMDA9 A11/A6 A9/A1 DQ2 DQ26 CMDA9 A11/A6 A9/A1 DQ2 DQ26
J5 T2 J5 T2
A12/RFU/NC DQ3 DQ27 A12/RFU/NC DQ3 DQ27
N4 N4
DQ4 DQ28 DQ4 DQ28
A5 N2 A5 N2
VPP/NC DQ5 DQ29 +1.5VSDGPU VPP/NC DQ5 DQ29
U5 M4 U5 M4
CLKA0# VPP/NC DQ6 DQ30 VPP/NC DQ6 DQ30
(26) CLKA0# 1 2 1 RV345 2 M2 1 RV284 2 M2
RV348 40.2_0402_1%~D 1K_0402_1%~D DQ7 DQ31 1K_0402_1%~D DQ7 DQ31
J1 +1.5VSDGPU J1 +1.5VSDGPU
RV346 1 MF MF
2 1K_0402_1%~D J10 RV286 1 2 1K_0402_1%~D J10
RV352 1 SEN SEN
1 2 121_0402_1%~D J13 B1 RV288 1 2 121_0402_1%~D J13 B1
ZQ VDDQ ZQ VDDQ
D1 D1
CV536 VDDQ VDDQ
F1 F1
0.01U_0402_16V7K~D CMDA8 VDDQ CMDA8 VDDQ
J4 M1 J4 M1
2 CMDA12 ABI# VDDQ CMDA15 ABI# VDDQ
C
CMDA0
G3
G12
RAS#
CS#
CAS#
WE#
VDDQ
VDDQ
P1
T1 CMDA5
G3
G12
RAS#
CS#
CAS#
WE#
VDDQ
VDDQ
P1
T1 GDDR5 Mode H Mapping C

CMDA15 L3 G2 CMDA12 L3 G2
CMDA5 CAS# RAS# VDDQ CMDA0 CAS# RAS# VDDQ
L12
WE# CS# VDDQ
L2 L12
WE# CS# VDDQ
L2 DATA Bus
B3 B3
VDDQ VDDQ
VDDQ
D3
VDDQ
D3 Address 0..31 32..63
F3 F3
VDDQ VDDQ
(26) WCKA0_N
WCKA0_N D5
WCK01# WCK23# VDDQ
H3 WCKA1_N D5
WCK01# WCK23# VDDQ
H3 CMD0 CS#
WCKA0 D4 K3 WCKA1 D4 K3
(26) WCKA0 WCK01 WCK23 VDDQ WCK01 WCK23 VDDQ
VDDQ
M3
VDDQ
M3 CMD1 A3_BA3
WCKA1_N P5 P3 WCKA0_N P5 P3
(26) WCKA1_N WCK23# WCK01# VDDQ WCK23# WCK01# VDDQ
WCKA1 P4 T3 WCKA0 P4 T3 CMD2 A2_BA0
(26) WCKA1 WCK23 WCK01 VDDQ WCK23 WCK01 VDDQ
E5 E5
VDDQ VDDQ
+1.5VSDGPU VDDQ
N5
VDDQ
N5 CMD3 A4_BA2
+FBA_VREFD_L A10 E10 +FBA_VREFD_L A10 E10
VREFD VDDQ VREFD VDDQ
U10
VREFD VDDQ
N10 U10
VREFD VDDQ
N10 CMD4 A5_BA1
+FBA_VREFC0 J14 B12 +FBA_VREFC0 J14 B12
VREFC VDDQ VREFC VDDQ
1

RV292 VDDQ
D12
VDDQ
D12 CMD5 WE#
F12 F12
VDDQ VDDQ
549_0402_1%~D
VDDQ
H12
VDDQ
H12 CMD6 A7_A8
CMDA13 J2 K12 CMDA13 J2 K12
RESET# VDDQ RESET# VDDQ
M12 M12 CMD7 A6_A11
2

RV293 +FBA_VREFC0 VDDQ VDDQ

1 2 P12 P12
VDDQ VDDQ
931_0402_1%
VDDQ
T12
VDDQ
T12 CMD8 ABI#
1

1 16 mil VDDQ
G13
VDDQ
G13
1.33K_0402_1%~D
RV294

H1
VSS VDDQ
L13 H1
VSS VDDQ
L13 CMD9 A12_RFU
CV537 K1 B14 K1 B14
VSS VDDQ VSS VDDQ
2
820P_0402_50V7K~D B5
VSS VDDQ
D14 B5
VSS VDDQ
D14 CMD10 A0_A10
G5 F14 G5 F14
2

VSS VDDQ VSS VDDQ

L5
VSS VDDQ
M14 L5
VSS VDDQ
M14 CMD11 A1_A9
T5 P14 T5 P14
VSS VDDQ VSS VDDQ
B10
VSS VDDQ
T14 B10
VSS VDDQ
T14 CMD12 RAS#
D10 D10
VSS VSS
G10
VSS
G10
VSS CMD13 RST#
L10 A1 L10 A1
VSS VSSQ VSS VSSQ
P10
VSS VSSQ
C1 P10
VSS VSSQ
C1 CMD14 CKE#
T10 E1 T10 E1
+1.5VSDGPU VSS VSSQ VSS VSSQ
B
H14
VSS VSSQ
N1 H14
VSS VSSQ
N1 CMD15 CAS# B
K14 R1 K14 R1
+1.5VSDGPU VSS VSSQ +1.5VSDGPU VSS VSSQ
VSSQ
U1
VSSQ
U1 CMD16 CS#
1

H2 H2
RV295 VSSQ VSSQ
G1
VDD VSSQ
K2 G1
VDD VSSQ
K2 CMD17 A3_BA3
549_0402_1%~D L1 A3 L1 A3
VDD VSSQ VDD VSSQ
RV296 G4
VDD VSSQ
C3 G4
VDD VSSQ
C3 CMD18 A2_BA0
L4 E3 L4 E3
2

VDD VSSQ VDD VSSQ

1 2 +FBA_VREFD_L C5 N3 C5 N3 CMD19 A4_BA2
820P_0402_50V7K~D

931_0402_1% VDD VSSQ VDD VSSQ

R5 R3 R5 R3
1.33K_0402_1%~D

VDD VSSQ VDD VSSQ

1

1 1 C10
VDD VSSQ
U3 C10
VDD VSSQ
U3 CMD20 A5_BA1
RV297

R10 C4 R10 C4
VDD VSSQ VDD VSSQ
CV539 D11
VDD VSSQ
R4 D11
VDD VSSQ
R4 CMD21 WE#
820P_0402_50V7K~D
CV538

G11 F5 G11 F5
VDD VSSQ VDD VSSQ
1

D 2 2 L11 M5 L11 M5 CMD22 A7_A8

2

VDD VSSQ VDD VSSQ

2 P11 F10 P11 F10
(22,28,29,30) MEM_VREF VDD VSSQ VDD VSSQ
G QV15 G14
VDD VSSQ
M10 G14
VDD VSSQ
M10 CMD23 A6_A11
S L14 C11 L14 C11
3

VDD VSSQ VDD VSSQ

2N7002KW_SOT323-3
VSSQ
R11
VSSQ
R11 CMD24 ABI#
A12 A12
VSSQ VSSQ
VSSQ
C12
VSSQ
C12 CMD25 A12_RFU
E12 E12
VSSQ VSSQ
VSSQ
N12
VSSQ
N12 CMD26 A0_A10
R12 R12
VSSQ VSSQ
170-BALL
VSSQ
U12 170-BALL
VSSQ
U12 CMD27 A1_A9
H13 H13
VSSQ VSSQ
SGRAM GDDR5
VSSQ
K13 SGRAM GDDR5
VSSQ
K13 CMD28 RAS#
A14 A14
VSSQ VSSQ
VSSQ
C14
VSSQ
C14 CMD29 RST#
E14 E14
VSSQ VSSQ
VSSQ
N14
VSSQ
N14 CMD30 CKE#
R14 R14
VSSQ VSSQ
VSSQ
U14
VSSQ
U14 CMD31 CAS#
VRAM@ VRAM@

H5GQ1H24AFR-T2L_BGA170 H5GQ1H24AFR-T2L_BGA170

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P (6/10) VRAM A Lower
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8381P
Date: Thursday, January 12, 2012 Sheet 27 of 63
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Upper 32 bits

D D
UV22 UV23

MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

A4 MDA32 A4 MDA56
EDCA4 DQ24 DQ0 MDA33 EDCA7 DQ24 DQ0 MDA57
C2 A2 C2 A2
EDC0 EDC3 DQ25 DQ1 MDA34 EDC0 EDC3 DQ25 DQ1 MDA58
(26) MDA[63..32] C13 B4 C13 B4
EDCA6 EDC1 EDC2 DQ26 DQ2 MDA35 EDCA5 EDC1 EDC2 DQ26 DQ2 MDA59
R13
EDC2 EDC1 DQ27 DQ3
B2 BYTE4 R13
EDC2 EDC1 DQ27 DQ3
B2
R2 E4 MDA36 R2 E4 MDA60 BYTE7
EDC3 EDC0 DQ28 DQ4 MDA37 EDC3 EDC0 DQ28 DQ4 MDA61
(26) EDCA[7..4] E2 E2
DQ29 DQ5 MDA38 DQ29 DQ5 MDA62
F4 F4
DQMA4 DQ30 DQ6 MDA39 DQMA7 DQ30 DQ6 MDA63
D2 F2 D2 F2
DBI0# DBI3# DQ31 DQ7 DBI0# DBI3# DQ31 DQ7
(26) DQMA[7..4] D13 A11 D13 A11
DQMA6 DBI1# DBI2# DQ16 DQ8 DQMA5 DBI1# DBI2# DQ16 DQ8
P13 A13 P13 A13
DBI2# DBI1# DQ17 DQ9 DBI2# DBI1# DQ17 DQ9
P2 B11 P2 B11
DBI3# DBI0# DQ18 DQ10 DBI3# DBI0# DQ18 DQ10
(26) CMDA[31..16] B13 B13
CLKA1 DQ19 DQ11 CLKA1 DQ19 DQ11
J12 E11 J12 E11
CLKA1# CK DQ20 DQ12 CLKA1# CK DQ20 DQ12
J11 E13 J11 E13
CMDA30 CK# DQ21 DQ13 CMDA30 CK# DQ21 DQ13
J3 F11 J3 F11
CKE# DQ22 DQ14 CKE# DQ22 DQ14
F13 F13
DQ23 DQ15 MDA48 DQ23 DQ15 MDA40
U11 U11
CMDA18 DQ8 DQ16 MDA49 CMDA19 DQ8 DQ16 MDA41
H11 U13 H11 U13
CMDA20 BA0/A2 BA2/A4 DQ9 DQ17 MDA50 CMDA17 BA0/A2 BA2/A4 DQ9 DQ17 MDA42
K10 T11 K10 T11
CMDA19 BA1/A5 BA3/A3 DQ10 DQ18 MDA51 CMDA18 BA1/A5 BA3/A3 DQ10 DQ18 MDA43
K11
BA2/A4 BA0/A2 DQ11 DQ19
T13 K11
BA2/A4 BA0/A2 DQ11 DQ19
T13 BYTE5
CMDA17 H10 N11 MDA52 BYTE6 CMDA20 H10 N11 MDA44
BA3/A3 BA1/A5 DQ12 DQ20 MDA53 BA3/A3 BA1/A5 DQ12 DQ20 MDA45
N13 N13
DQ13 DQ21 MDA54 DQ13 DQ21 MDA46
M11 M11
CMDA22 DQ14 DQ22 MDA55 CMDA26 DQ14 DQ22 MDA47
K4 M13 K4 M13
CMDA27 A8/A7 A10/A0 DQ15 DQ23 CMDA23 A8/A7 A10/A0 DQ15 DQ23
H5 U4 H5 U4
CMDA26 A9/A1 A11/A6 DQ0 DQ24 CMDA22 A9/A1 A11/A6 DQ0 DQ24
H4 U2 H4 U2
CMDA23 A10/A0 A8/A7 DQ1 DQ25 CMDA27 A10/A0 A8/A7 DQ1 DQ25
K5 T4 K5 T4
CMDA25 A11/A6 A9/A1 DQ2 DQ26 CMDA25 A11/A6 A9/A1 DQ2 DQ26
J5 T2 J5 T2
A12/RFU/NC DQ3 DQ27 A12/RFU/NC DQ3 DQ27
N4 N4
DQ4 DQ28 DQ4 DQ28
A5 N2 A5 N2
VPP/NC DQ5 DQ29 +1.5VSDGPU VPP/NC DQ5 DQ29
U5 M4 U5 M4
VPP/NC DQ6 DQ30 VPP/NC DQ6 DQ30
1 RV299 2 M2 1 RV300 2 M2
1K_0402_1%~D DQ7 DQ31 1K_0402_1%~D DQ7 DQ31
C J1 +1.5VSDGPU J1 +1.5VSDGPU C
RV350 1 MF MF
2 1K_0402_1%~D J10 RV349 1 2 1K_0402_1%~D J10
RV303 1 SEN SEN
2 121_0402_1%~D J13 B1 RV302 1 2 121_0402_1%~D J13 B1
ZQ VDDQ ZQ VDDQ
D1 D1
VDDQ VDDQ
F1 F1
CMDA24 VDDQ CMDA24 VDDQ
Follow DG v04 J4
ABI# VDDQ
M1 J4
ABI# VDDQ
M1
GDDR5 Mode H Mapping
CMDA28 G3 P1 CMDA31 G3 P1
CMDA16 RAS# CAS# VDDQ CMDA21 RAS# CAS# VDDQ
G12 T1 G12 T1
CLKA1 CMDA31 CS# WE# VDDQ CMDA28 CS# WE# VDDQ
(26) CLKA1 1 2 L3
CAS# RAS# VDDQ
G2 L3
CAS# RAS# VDDQ
G2 DATA Bus
RV304 40.2_0402_1%~D CMDA21 L12 L2 CMDA16 L12 L2
WE# CS# VDDQ WE# CS# VDDQ
VDDQ
B3
VDDQ
B3 Address 0..31 32..63
D3 D3
VDDQ VDDQ
VDDQ
F3
VDDQ
F3 CMD0 CS#
WCKA2_N D5 H3 WCKA3_N D5 H3
(26) WCKA2_N WCK01# WCK23# VDDQ WCK01# WCK23# VDDQ
WCKA2 D4 K3 WCKA3 D4 K3 CMD1 A3_BA3
(26) WCKA2 WCK01 WCK23 VDDQ WCK01 WCK23 VDDQ
M3 M3
CLKA1# WCKA3_N VDDQ WCKA2_N VDDQ
(26) CLKA1# 1 2 (26) WCKA3_N P5
WCK23# WCK01# VDDQ
P3 P5
WCK23# WCK01# VDDQ
P3 CMD2 A2_BA0
RV306 40.2_0402_1%~D WCKA3 P4 T3 WCKA2 P4 T3
(26) WCKA3 WCK23 WCK01 VDDQ WCK23 WCK01 VDDQ
VDDQ
E5
VDDQ
E5 CMD3 A4_BA2
N5 N5
VDDQ VDDQ
1 +FBA_VREFD_H A10
VREFD VDDQ
E10 +FBA_VREFD_H A10
VREFD VDDQ
E10 CMD4 A5_BA1
CV556 U10 N10 U10 N10
VREFD VDDQ VREFD VDDQ
0.01U_0402_16V7K~D +FBA_VREFC1 J14
VREFC VDDQ
B12 +FBA_VREFC1 J14
VREFC VDDQ
B12 CMD5 WE#
D12 D12
2 VDDQ VDDQ
+1.5VSDGPU VDDQ
F12
VDDQ
F12 CMD6 A7_A8
H12 H12
CMDA29 VDDQ CMDA29 VDDQ
J2
RESET# VDDQ
K12 J2
RESET# VDDQ
K12 CMD7 A6_A11
M12 M12
VDDQ VDDQ
1

RV307 VDDQ
P12
VDDQ
P12 CMD8 ABI#
T12 T12
VDDQ VDDQ
549_0402_1%~D
VDDQ
G13
VDDQ
G13 CMD9 A12_RFU
RV308 H1 L13 H1 L13
VSS VDDQ VSS VDDQ
K1 B14 K1 B14 CMD10 A0_A10
2

+FBA_VREFC1 VSS VDDQ VSS VDDQ

1 2 B5 D14 B5 D14
VSS VDDQ VSS VDDQ
931_0402_1% G5
VSS VDDQ
F14 G5
VSS VDDQ
F14 CMD11 A1_A9
1

1 L5 M14 L5 M14
VSS VDDQ VSS VDDQ
1.33K_0402_1%~D
RV309

T5
VSS VDDQ
P14 T5
VSS VDDQ
P14 CMD12 RAS#
CV557 B10 T14 B10 T14
B VSS VDDQ VSS VDDQ B
2
820P_0402_50V7K~D D10
VSS
D10
VSS CMD13 RST#
G10 G10
2

VSS VSS
L10
VSS VSSQ
A1 L10
VSS VSSQ
A1 CMD14 CKE#
16 mil P10
VSS VSSQ
C1 P10
VSS VSSQ
C1
T10
VSS VSSQ
E1 T10
VSS VSSQ
E1 CMD15 CAS#
H14 N1 H14 N1
VSS VSSQ VSS VSSQ
+1.5VSDGPU
K14
VSS VSSQ
R1
+1.5VSDGPU
K14
VSS VSSQ
R1 CMD16 CS#
U1 U1
+1.5VSDGPU VSSQ VSSQ
VSSQ
H2
VSSQ
H2 CMD17 A3_BA3
G1 K2 G1 K2
VDD VSSQ VDD VSSQ
L1
VDD VSSQ
A3 L1
VDD VSSQ
A3 CMD18 A2_BA0
1

G4 C3 G4 C3
RV310 VDD VSSQ VDD VSSQ
L4
VDD VSSQ
E3 L4
VDD VSSQ
E3 CMD19 A4_BA2
549_0402_1%~D C5 N3 C5 N3
VDD VSSQ VDD VSSQ
RV311 R5
VDD VSSQ
R3 R5
VDD VSSQ
R3 CMD20 A5_BA1
C10 U3 C10 U3
2

+FBA_VREFD_H VDD VSSQ VDD VSSQ

1 2 R10
VDD VSSQ
C4 R10
VDD VSSQ
C4 CMD21 WE#
931_0402_1% D11 R4 D11 R4
VDD VSSQ VDD VSSQ
1

1 1 G11 F5 G11 F5 CMD22 A7_A8

820P_0402_50V7K~D

VDD VSSQ VDD VSSQ

1.33K_0402_1%~D
RV312

L11 M5 L11 M5
VDD VSSQ VDD VSSQ
CV559 P11
VDD VSSQ
F10 P11
VDD VSSQ
F10 CMD23 A6_A11
1

D 820P_0402_50V7K~D
CV558

G14 M10 G14 M10

2 2 VDD VSSQ VDD VSSQ
2 L14 C11 L14 C11 CMD24 ABI#
2

(22,27,29,30) MEM_VREF G QV17 VDD VSSQ VDD VSSQ

R11 R11
VSSQ VSSQ
S A12 A12 CMD25 A12_RFU
3

2N7002KW_SOT323-3 VSSQ VSSQ

C12 C12
VSSQ VSSQ
VSSQ
E12
VSSQ
E12 CMD26 A0_A10
N12 N12
VSSQ VSSQ
VSSQ
R12
VSSQ
R12 CMD27 A1_A9
170-BALL U12 170-BALL U12
VSSQ VSSQ
VSSQ
H13
VSSQ
H13 CMD28 RAS#
SGRAM GDDR5 K13 SGRAM GDDR5 K13
VSSQ VSSQ
VSSQ
A14
VSSQ
A14 CMD29 RST#
C14 C14
VSSQ VSSQ
VSSQ
E14
VSSQ
E14 CMD30 CKE#
N14 N14
VSSQ VSSQ
VSSQ
R14
VSSQ
R14 CMD31 CAS#
A U14 U14 A
VSSQ VSSQ
VRAM@ VRAM@

H5GQ1H24AFR-T2L_BGA170 H5GQ1H24AFR-T2L_BGA170

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P (7/10) VRAM A Upper
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8381P
Date: Thursday, January 12, 2012 Sheet 28 of 63
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Lower 32 bits

UV24

MF=0 MF=1 MF=1 MF=0 UV25

(26) MDC[0..31]
A4 MDC0 MF=0 MF=1 MF=1 MF=0
EDCC0 DQ24 DQ0 MDC1
C2 A2
D EDC0 EDC3 DQ25 DQ1 MDC2 MDC24 D
(26) EDCC[3..0] C13 B4 A4
EDCC2 EDC1 EDC2 DQ26 DQ2 MDC3 EDCC3 DQ24 DQ0 MDC25
R13 B2 C2 A2
EDC2 EDC1 DQ27 DQ3 MDC4 EDC0 EDC3 DQ25 DQ1 MDC26
R2
EDC3 EDC0 DQ28 DQ4
E4 BYTE0 C13
EDC1 EDC2 DQ26 DQ2
B4
E2 MDC5 EDCC1 R13 B2 MDC27
(26) DQMC[3..0] DQ29 DQ5 EDC2 EDC1 DQ27 DQ3
F4 MDC6 R2 E4 MDC28 BYTE3
DQMC0 DQ30 DQ6 MDC7 EDC3 EDC0 DQ28 DQ4 MDC29
D2 F2 E2
DBI0# DBI3# DQ31 DQ7 DQ29 DQ5 MDC30
(26) CMDC[15..0] D13 A11 F4
DQMC2 DBI1# DBI2# DQ16 DQ8 DQMC3 DQ30 DQ6 MDC31
P13 A13 D2 F2
DBI2# DBI1# DQ17 DQ9 DBI0# DBI3# DQ31 DQ7
P2 B11 D13 A11
DBI3# DBI0# DQ18 DQ10 DQMC1 DBI1# DBI2# DQ16 DQ8
B13 P13 A13
CLKC0 DQ19 DQ11 DBI2# DBI1# DQ17 DQ9
J12 E11 P2 B11
CLKC0# CK DQ20 DQ12 DBI3# DBI0# DQ18 DQ10
J11 E13 B13
CMDC14 CK# DQ21 DQ13 CLKC0 DQ19 DQ11
J3 F11 J12 E11
CKE# DQ22 DQ14 CLKC0# CK DQ20 DQ12
F13 J11 E13
DQ23 DQ15 MDC16 CMDC14 CK# DQ21 DQ13
U11 J3 F11
CMDC2 DQ8 DQ16 MDC17 CKE# DQ22 DQ14
H11 U13 F13
CMDC4 BA0/A2 BA2/A4 DQ9 DQ17 MDC18 DQ23 DQ15 MDC8
K10 T11 U11
CMDC3 BA1/A5 BA3/A3 DQ10 DQ18 MDC19 CMDC3 DQ8 DQ16 MDC9
K11 T13 H11 U13
CMDC1 BA2/A4 BA0/A2 DQ11 DQ19 MDC20 CMDC1 BA0/A2 BA2/A4 DQ9 DQ17 MDC10
H10 N11 K10 T11
BA3/A3 BA1/A5 DQ12 DQ20 MDC21 CMDC2 BA1/A5 BA3/A3 DQ10 DQ18 MDC11
DQ13 DQ21
N13 BYTE2 K11
BA2/A4 BA0/A2 DQ11 DQ19
T13 BYTE1
M11 MDC22 CMDC4 H10 N11 MDC12
CMDC6 DQ14 DQ22 MDC23 BA3/A3 BA1/A5 DQ12 DQ20 MDC13
K4 M13 N13
CMDC11 A8/A7 A10/A0 DQ15 DQ23 DQ13 DQ21 MDC14
H5 U4 M11
CMDC10 A9/A1 A11/A6 DQ0 DQ24 CMDC10 DQ14 DQ22 MDC15
H4 U2 K4 M13
CMDC7 A10/A0 A8/A7 DQ1 DQ25 CMDC7 A8/A7 A10/A0 DQ15 DQ23
K5 T4 H5 U4
CMDC9 A11/A6 A9/A1 DQ2 DQ26 CMDC6 A9/A1 A11/A6 DQ0 DQ24
J5 T2 H4 U2
A12/RFU/NC DQ3 DQ27 CMDC11 A10/A0 A8/A7 DQ1 DQ25
N4 K5 T4
DQ4 DQ28 CMDC9 A11/A6 A9/A1 DQ2 DQ26
A5 N2 J5 T2
VPP/NC DQ5 DQ29 A12/RFU/NC DQ3 DQ27
U5 M4 N4
VPP/NC DQ6 DQ30 DQ4 DQ28
1 RV313 2 M2 A5 N2
1K_0402_1%~D DQ7 DQ31 +1.5VSDGPU VPP/NC DQ5 DQ29
U5 M4
+1.5VSDGPU VPP/NC DQ6 DQ30
J1 1 RV314 2 M2
RV351 1 MF DQ7 DQ31
2 1K_0402_1%~D J10 1K_0402_1%~D
RV280 1 SEN +1.5VSDGPU
2 121_0402_1%~D J13 B1 J1
ZQ VDDQ RV316 MF
D1 1 2 1K_0402_1%~D J10
VDDQ RV218 SEN
F1 1 2 121_0402_1%~D J13 B1
CMDC8 VDDQ ZQ VDDQ
Follow DG v04 J4
ABI# VDDQ
M1
VDDQ
D1
C CMDC12 G3 P1 F1 C
CMDC0 RAS# CAS# VDDQ CMDC8 VDDQ
G12 T1 J4 M1
CLKC0 CMDC15 CS# WE# VDDQ CMDC15 ABI# VDDQ
(26) CLKC0 1
RV319
2
40.2_0402_1%~D CMDC5
L3
L12
CAS#
WE#
RAS#
CS#
VDDQ
VDDQ
G2
L2 CMDC5
G3
G12
RAS#
CS#
CAS#
WE#
VDDQ
VDDQ
P1
T1 GDDR5 Mode H Mapping
B3 CMDC12 L3 G2
VDDQ CAS# RAS# VDDQ
VDDQ
D3 CMDC0 L12
WE# CS# VDDQ
L2 DATA Bus
F3 B3
VDDQ VDDQ
(26) WCKC0_N
WCKC0_N D5
WCK01# WCK23# VDDQ
H3
VDDQ
D3 Address 0..31 32..63
WCKC0 D4 K3 F3
(26) WCKC0 WCK01 WCK23 VDDQ VDDQ
M3 WCKC1_N D5 H3 CMD0 CS#
CLKC0# WCKC1_N VDDQ WCKC1 WCK01# WCK23# VDDQ
(26) CLKC0# 1 2 (26) WCKC1_N P5 P3 D4 K3
WCKC1 WCK23# WCK01# VDDQ WCK01 WCK23 VDDQ
RV321 40.2_0402_1%~D
(26) WCKC1 P4
WCK23 WCK01 VDDQ
T3
VDDQ
M3 CMD1 A3_BA3
E5 WCKC0_N P5 P3
VDDQ WCKC0 WCK23# WCK01# VDDQ
VDDQ
N5 P4
WCK23 WCK01 VDDQ
T3 CMD2 A2_BA0
1 +FBC_VREFD_L A10 E10 E5
VREFD VDDQ VDDQ
U10
VREFD VDDQ
N10
VDDQ
N5 CMD3 A4_BA2
CV576 +FBC_VREFC0 J14 B12 +FBC_VREFD_L A10 E10
VREFC VDDQ VREFD VDDQ
2
0.01U_0402_16V7K~D
VDDQ
D12 U10
VREFD VDDQ
N10 CMD4 A5_BA1
F12 +FBC_VREFC0 J14 B12
VDDQ VREFC VDDQ
VDDQ
H12
VDDQ
D12 CMD5 WE#
CMDC13 J2 K12 F12
RESET# VDDQ VDDQ
VDDQ
M12
VDDQ
H12 CMD6 A7_A8
P12 CMDC13 J2 K12
VDDQ RESET# VDDQ
+1.5VSDGPU VDDQ
T12
VDDQ
M12 CMD7 A6_A11
G13 P12
VDDQ VDDQ
H1
VSS VDDQ
L13
VDDQ
T12 CMD8 ABI#
K1 B14 G13
VSS VDDQ VDDQ
1

RV322
B5
VSS VDDQ
D14 H1
VSS VDDQ
L13 CMD9 A12_RFU
G5 F14 K1 B14
VSS VDDQ VSS VDDQ
549_0402_1%~D L5
VSS VDDQ
M14 B5
VSS VDDQ
D14 CMD10 A0_A10
RV323 T5 P14 G5 F14
VSS VDDQ VSS VDDQ
B10 T14 L5 M14 CMD11 A1_A9
2

+FBC_VREFC0 VSS VDDQ VSS VDDQ

1 2 D10 T5 P14
VSS VSS VDDQ
931_0402_1% G10
VSS
B10
VSS VDDQ
T14 CMD12 RAS#
1 L10 A1 D10
VSS VSSQ VSS
1

P10
VSS VSSQ
C1 G10
VSS CMD13 RST#
1.33K_0402_1%~D
RV324

CV577 T10 E1 L10 A1

VSS VSSQ VSS VSSQ
B 2
820P_0402_50V7K~D H14
VSS VSSQ
N1 P10
VSS VSSQ
C1 CMD14 CKE# B
K14 R1 T10 E1
+1.5VSDGPU VSS VSSQ VSS VSSQ
U1 H14 N1 CMD15 CAS#
2

VSSQ VSS VSSQ

H2 K14 R1
VSSQ +1.5VSDGPU VSS VSSQ
G1
VDD VSSQ
K2
VSSQ
U1 CMD16 CS#
L1 A3 H2
VDD VSSQ VSSQ
G4
VDD VSSQ
C3 G1
VDD VSSQ
K2 CMD17 A3_BA3
L4 E3 L1 A3
VDD VSSQ VDD VSSQ
C5
VDD VSSQ
N3 G4
VDD VSSQ
C3 CMD18 A2_BA0
R5 R3 L4 E3
+1.5VSDGPU VDD VSSQ VDD VSSQ
C10
VDD VSSQ
U3 C5
VDD VSSQ
N3 CMD19 A4_BA2
R10 C4 R5 R3
VDD VSSQ VDD VSSQ
D11
VDD VSSQ
R4 C10
VDD VSSQ
U3 CMD20 A5_BA1
1

G11 F5 R10 C4
RV325 VDD VSSQ VDD VSSQ
L11
VDD VSSQ
M5 D11
VDD VSSQ
R4 CMD21 WE#
549_0402_1%~D P11 F10 G11 F5
VDD VSSQ VDD VSSQ
RV326 G14
VDD VSSQ
M10 L11
VDD VSSQ
M5 CMD22 A7_A8
L14 C11 P11 F10
2

VDD VSSQ VDD VSSQ

1 2 +FBC_VREFD_L
VSSQ
R11 G14
VDD VSSQ
M10 CMD23 A6_A11
931_0402_1% A12 L14 C11
VSSQ VDD VSSQ
1

1 1 C12 R11 CMD24 ABI#

820P_0402_50V7K~D

VSSQ VSSQ
1

D
1.33K_0402_1%~D
RV327

E12 A12
VSSQ VSSQ
(22,27,28,30) MEM_VREF
2 CV579
VSSQ
N12
VSSQ
C12 CMD25 A12_RFU
QV19 820P_0402_50V7K~D
CV578

G R12 E12
2 2 VSSQ VSSQ
S 170-BALL U12 N12 CMD26 A0_A10
3

2N7002KW_SOT323-3 VSSQ VSSQ

H13 R12
VSSQ VSSQ
SGRAM GDDR5
VSSQ
K13 170-BALL
VSSQ
U12 CMD27 A1_A9
A14 H13
VSSQ VSSQ
VSSQ
C14 SGRAM GDDR5
VSSQ
K13 CMD28 RAS#
E14 A14
VSSQ VSSQ
VSSQ
N14
VSSQ
C14 CMD29 RST#
R14 E14
VSSQ VSSQ
VSSQ
U14
VSSQ
N14 CMD30 CKE#
R14
VSSQ
VRAM@
VSSQ
U14 CMD31 CAS#
H5GQ1H24AFR-T2L_BGA170 VRAM@

A H5GQ1H24AFR-T2L_BGA170 A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P (8/10) VRAM B Lower
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8381P
Date: Thursday, January 12, 2012 Sheet 29 of 63
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Upper 32 bits

UV26
UV27
MF=0 MF=1 MF=1 MF=0
D D
MF=0 MF=1 MF=1 MF=0
A4 MDC32
(26) MDC[63..32] DQ24 DQ0
EDCC4 C2 A2 MDC33 A4 MDC56
EDC0 EDC3 DQ25 DQ1 MDC34 EDCC7 DQ24 DQ0 MDC57
C13 B4 C2 A2
EDCC6 EDC1 EDC2 DQ26 DQ2 MDC35 EDC0 EDC3 DQ25 DQ1 MDC58
(26) EDCC[7..4] R13
EDC2 EDC1 DQ27 DQ3
B2 BYTE4 C13
EDC1 EDC2 DQ26 DQ2
B4
R2 E4 MDC36 EDCC5 R13 B2 MDC59
EDC3 EDC0 DQ28 DQ4 MDC37 EDC2 EDC1 DQ27 DQ3 MDC60
DQ29 DQ5
E2 R2
EDC3 EDC0 DQ28 DQ4
E4 BYTE7
F4 MDC38 E2 MDC61
(26) DQMC[7..4] DQ30 DQ6 DQ29 DQ5
DQMC4 D2 F2 MDC39 F4 MDC62
DBI0# DBI3# DQ31 DQ7 DQMC7 DQ30 DQ6 MDC63
D13 A11 D2 F2
DQMC6 DBI1# DBI2# DQ16 DQ8 DBI0# DBI3# DQ31 DQ7
(26) CMDC[31..16] P13 A13 D13 A11
DBI2# DBI1# DQ17 DQ9 DQMC5 DBI1# DBI2# DQ16 DQ8
P2 B11 P13 A13
DBI3# DBI0# DQ18 DQ10 DBI2# DBI1# DQ17 DQ9
B13 P2 B11
CLKC1 DQ19 DQ11 DBI3# DBI0# DQ18 DQ10
J12 E11 B13
CLKC1# CK DQ20 DQ12 CLKC1 DQ19 DQ11
J11 E13 J12 E11
CMDC30 CK# DQ21 DQ13 CLKC1# CK DQ20 DQ12
J3 F11 J11 E13
CKE# DQ22 DQ14 CMDC30 CK# DQ21 DQ13
F13 J3 F11
DQ23 DQ15 MDC48 CKE# DQ22 DQ14
U11 F13
CMDC18 DQ8 DQ16 MDC49 DQ23 DQ15 MDC40
H11 U13 U11
CMDC20 BA0/A2 BA2/A4 DQ9 DQ17 MDC50 CMDC19 DQ8 DQ16 MDC41
K10 T11 H11 U13
CMDC19 BA1/A5 BA3/A3 DQ10 DQ18 MDC51 CMDC17 BA0/A2 BA2/A4 DQ9 DQ17 MDC42
K11 T13 K10 T11
CMDC17 BA2/A4 BA0/A2 DQ11 DQ19 MDC52 CMDC18 BA1/A5 BA3/A3 DQ10 DQ18 MDC43
H10
BA3/A3 BA1/A5 DQ12 DQ20
N11 BYTE6 K11
BA2/A4 BA0/A2 DQ11 DQ19
T13 BYTE5
N13 MDC53 CMDC20 H10 N11 MDC44
DQ13 DQ21 MDC54 BA3/A3 BA1/A5 DQ12 DQ20 MDC45
M11 N13
CMDC22 DQ14 DQ22 MDC55 DQ13 DQ21 MDC46
K4 M13 M11
CMDC27 A8/A7 A10/A0 DQ15 DQ23 CMDC26 DQ14 DQ22 MDC47
H5 U4 K4 M13
CMDC26 A9/A1 A11/A6 DQ0 DQ24 CMDC23 A8/A7 A10/A0 DQ15 DQ23
H4 U2 H5 U4
CMDC23 A10/A0 A8/A7 DQ1 DQ25 CMDC22 A9/A1 A11/A6 DQ0 DQ24
K5 T4 H4 U2
CMDC25 A11/A6 A9/A1 DQ2 DQ26 CMDC27 A10/A0 A8/A7 DQ1 DQ25
J5 T2 K5 T4
A12/RFU/NC DQ3 DQ27 CMDC25 A11/A6 A9/A1 DQ2 DQ26
N4 J5 T2
DQ4 DQ28 A12/RFU/NC DQ3 DQ27
A5 N2 N4
VPP/NC DQ5 DQ29 DQ4 DQ28
U5 M4 A5 N2
VPP/NC DQ6 DQ30 +1.5VSDGPU VPP/NC DQ5 DQ29
1 RV328 2 M2 U5 M4
1K_0402_1%~D DQ7 DQ31 VPP/NC DQ6 DQ30
1 RV329 2 M2
+1.5VSDGPU 1K_0402_1%~D DQ7 DQ31
J1
RV330 MF +1.5VSDGPU
1 2 1K_0402_1%~D J10 J1
RV331 SEN MF
1 2 121_0402_1%~D J13 B1 RV333 1 2 1K_0402_1%~D J10
ZQ VDDQ RV332 SEN
C D1 1 2 121_0402_1%~D J13 B1 C
VDDQ ZQ VDDQ
F1 D1
CMDC24 VDDQ VDDQ
Follow DG v04 J4
ABI# VDDQ
M1
VDDQ
F1
CMDC28 G3 P1 CMDC24 J4 M1
CMDC16 RAS# CAS# VDDQ CMDC31 ABI# VDDQ
G12 T1 G3 P1
(26) CLKC1
CLKC1 1 2 CMDC31 L3
CS#
CAS#
WE#
RAS#
VDDQ
VDDQ
G2 CMDC21 G12
RAS#
CS#
CAS#
WE#
VDDQ
VDDQ
T1 GDDR5 Mode H Mapping
RV334 40.2_0402_1%~D CMDC21 L12 L2 CMDC28 L3 G2
WE# CS# VDDQ CAS# RAS# VDDQ
VDDQ
B3 CMDC16 L12
WE# CS# VDDQ
L2 DATA Bus
D3 B3
VDDQ VDDQ
VDDQ
F3
VDDQ
D3 Address 0..31 32..63
WCKC2_N D5 H3 F3
(26) WCKC2_N WCK01# WCK23# VDDQ VDDQ
WCKC2 D4 K3 WCKC3_N D5 H3 CMD0 CS#
(26) WCKC2 WCK01 WCK23 VDDQ WCK01# WCK23# VDDQ
M3 WCKC3 D4 K3
CLKC1# WCKC3_N VDDQ WCK01 WCK23 VDDQ
(26) CLKC1# 1 2 (26) WCKC3_N P5
WCK23# WCK01# VDDQ
P3
VDDQ
M3 CMD1 A3_BA3
RV336 40.2_0402_1%~D WCKC3 P4 T3 WCKC2_N P5 P3
(26) WCKC3 WCK23 WCK01 VDDQ WCK23# WCK01# VDDQ
VDDQ
E5 WCKC2 P4
WCK23 WCK01 VDDQ
T3 CMD2 A2_BA0
N5 E5
VDDQ VDDQ
1 +FBC_VREFD_H A10
VREFD VDDQ
E10
VDDQ
N5 CMD3 A4_BA2
CV596 U10 N10 +FBC_VREFD_H A10 E10
+FBC_VREFC1 VREFD VDDQ VREFD VDDQ
0.01U_0402_16V7K~D J14
VREFC VDDQ
B12 U10
VREFD VDDQ
N10 CMD4 A5_BA1
D12 +FBC_VREFC1 J14 B12
2 VDDQ VREFC VDDQ
VDDQ
F12
VDDQ
D12 CMD5 WE#
H12 F12
CMDC29 VDDQ VDDQ
J2
RESET# VDDQ
K12
VDDQ
H12 CMD6 A7_A8
M12 CMDC29 J2 K12
VDDQ RESET# VDDQ
VDDQ
P12
VDDQ
M12 CMD7 A6_A11
T12 P12
+1.5VSDGPU VDDQ VDDQ
VDDQ
G13
VDDQ
T12 CMD8 ABI#
H1 L13 G13
VSS VDDQ VDDQ
K1
VSS VDDQ
B14 H1
VSS VDDQ
L13 CMD9 A12_RFU
1

B5 D14 K1 B14
RV337 VSS VDDQ VSS VDDQ
G5
VSS VDDQ
F14 B5
VSS VDDQ
D14 CMD10 A0_A10
549_0402_1%~D L5 M14 G5 F14
VSS VDDQ VSS VDDQ
RV338 T5
VSS VDDQ
P14 L5
VSS VDDQ
M14 CMD11 A1_A9
B10 T14 T5 P14
2

VSS VDDQ VSS VDDQ

1 2 +FBC_VREFC1 D10
VSS
B10
VSS VDDQ
T14 CMD12 RAS#
931_0402_1% G10 D10
VSS VSS
1

B 1 L10
VSS VSSQ
A1 G10
VSS CMD13 RST# B
1.33K_0402_1%~D
RV339

P10 C1 L10 A1
VSS VSSQ VSS VSSQ
CV597 T10
VSS VSSQ
E1 P10
VSS VSSQ
C1 CMD14 CKE#
820P_0402_50V7K~D H14 N1 T10 E1
2 VSS VSSQ VSS VSSQ
K14 R1 H14 N1 CMD15 CAS#
2

+1.5VSDGPU VSS VSSQ VSS VSSQ

U1 K14 R1
VSSQ +1.5VSDGPU VSS VSSQ
VSSQ
H2
VSSQ
U1 CMD16 CS#
G1 K2 H2
VDD VSSQ VSSQ
L1
VDD VSSQ
A3 G1
VDD VSSQ
K2 CMD17 A3_BA3
G4 C3 L1 A3
VDD VSSQ VDD VSSQ
L4
VDD VSSQ
E3 G4
VDD VSSQ
C3 CMD18 A2_BA0
C5 N3 L4 E3
+1.5VSDGPU VDD VSSQ VDD VSSQ
R5
VDD VSSQ
R3 C5
VDD VSSQ
N3 CMD19 A4_BA2
C10 U3 R5 R3
VDD VSSQ VDD VSSQ
R10
VDD VSSQ
C4 C10
VDD VSSQ
U3 CMD20 A5_BA1
1

D11 R4 R10 C4
RV340 VDD VSSQ VDD VSSQ
G11
VDD VSSQ
F5 D11
VDD VSSQ
R4 CMD21 WE#
549_0402_1%~D L11 M5 G11 F5
VDD VSSQ VDD VSSQ
RV341 P11
VDD VSSQ
F10 L11
VDD VSSQ
M5 CMD22 A7_A8
G14 M10 P11 F10
2

VDD VSSQ VDD VSSQ

1 2 +FBC_VREFD_H L14
VDD VSSQ
C11 G14
VDD VSSQ
M10 CMD23 A6_A11
931_0402_1% R11 L14 C11
VSSQ VDD VSSQ
1

1 1 A12 R11 CMD24 ABI#

820P_0402_50V7K~D

VSSQ VSSQ
1.33K_0402_1%~D
RV342

C12 A12
VSSQ VSSQ
CV599
VSSQ
E12
VSSQ
C12 CMD25 A12_RFU
1

D 820P_0402_50V7K~D
CV598

N12 E12
2 2 VSSQ VSSQ
2 R12 N12 CMD26 A0_A10
2

(22,27,28,29) MEM_VREF G QV21 170-BALL VSSQ VSSQ

U12 R12
VSSQ VSSQ
S H13 170-BALL U12 CMD27 A1_A9
3

2N7002KW_SOT323-3 SGRAM GDDR5 VSSQ VSSQ

K13 H13
VSSQ VSSQ
VSSQ
A14 SGRAM GDDR5
VSSQ
K13 CMD28 RAS#
C14 A14
VSSQ VSSQ
VSSQ
E14
VSSQ
C14 CMD29 RST#
N14 E14
VSSQ VSSQ
VSSQ
R14
VSSQ
N14 CMD30 CKE#
U14 R14
VSSQ VSSQ
VSSQ
U14 CMD31 CAS#
VRAM@
A VRAM@ A
H5GQ1H24AFR-T2L_BGA170
H5GQ1H24AFR-T2L_BGA170

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P (9/10) VRAM B Upper
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8381P
Date: Thursday, January 12, 2012 Sheet 30 of 63
5 4 3 2 1
 A
B
C
D

+1.5VSDGPU
+1.5VSDGPU
0.1U_0402_10V7K~D 10U_0603_6.3V6M~D 0.1U_0402_10V7K~D 10U_0603_6.3V6M~D

2
1
2
1
2
1
2
1
CV635 CV572 CV619 CV540

(17) DGPU_PWR_EN#
0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D 0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D

2
1
2
1
2
1
2
1
CV631 CV571 CV620 CV541

0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D 0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D

5
5

2
1
2
1
2
1
2
1

UV22 SIDE
UV20 SIDE
Item7_X02
CV632 CV563 CV621 CV542

Item30_X01
0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D 0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D

2
1
2
1
2
1
2
1
CV633 CV565 CV622 CV543

0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D 0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D

2
G

Item13_X02

2
1
2
1
2
1
2
1
Q294
CV634 CV562 CV623 CV544
3 1 2 1

S
D
+3VS

0.1U_0402_10V7K~D 1U_0402_6.3V6K~D 0.1U_0402_10V7K~D 1U_0402_6.3V6K~D

2
1
2
1
2
1
2
1
2N7002K_SOT23-3
RZ19

CV636 CV560 CV624 CV545

2
1
1U_0402_6.3V6K~D 1U_0402_6.3V6K~D

2
1
2
1
CZ8
10K_0402_5%~D

CV564 CV546 DGPU_PWR_EN

1U_0402_6.3V6K~D 1U_0402_6.3V6K~D

2
1
2
1
CV561 CV547
0.1U_0402_25V6K~D
2
QZ19A

1 6 2 1
+3VALW

DMN66D0LDW-7_SOT363-6~D
RZ18

+1.5VSDGPU
+1.5VSDGPU
0.1U_0402_10V7K~D 10U_0603_6.3V6M~D 0.1U_0402_10V7K~D 10U_0603_6.3V6M~D

4
4

100K_0402_5%~D

2
1
2
1
2
1
2
1
DGPU_PWR_EN_R#

CV641 CV575 CV629 CV555

0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D 0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D

2
1
2
1
2
1
2
1
CV637 CV574 CV625 CV554
5

QZ19B

0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D 0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D

4 3 2 1

2
1
2
1
2
1
2
1

UV23 SIDE
UV21 SIDE
B+_BIAS

CV638 CV569 CV626 CV551 DMN66D0LDW-7_SOT363-6~D

2
G
QZ20

0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D 0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D

R1945

3 1 2 1

2
1
2
1
2
1
2
1
S
D
+3VS
DGPU_UP

CV639 CV573 CV627 CV553

DGPU_PWR_EN_R#
RZ20

0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D 0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D 2 1

40.2K_0402_1%~D

(24)

2
1
2
1
2
1
2
1
CV640 CV568 CV628 CV550
100K_0402_5%~D
RZ17

2N7002K_SOT23-3
R1947

Item13_X02
CZ1

0.1U_0402_10V7K~D 1U_0402_6.3V6K~D 0.1U_0402_10V7K~D 1U_0402_6.3V6K~D

DGPU_CORE_EN

2
1
2
1
2
1
2
1
2
1

Item1_X01
+3VS

CV642 CV566 CV630 CV548

1 SHORT 2

Item3_X02

150K_0402_5%~D
5
6
7
8

1U_0402_6.3V6K~D 1U_0402_6.3V6K~D

2
1
2
1
0_0402_5%~D

CV570 CV552
@

1U_0402_6.3V6K~D 1U_0402_6.3V6K~D 4
10U_0603_6.3V6M~D

2
1

2
1
2
1
Item35_X01 QZ1
AO4304L_SO8

CZ7

CV567 CV549
DGPU_CORE_EN
3
2
1

3
3

CZ5
+3VS to +3VSDGPU

(58)
2
1
+3VSDGPU

0.1U_0402_25V6K~D
1.4A

+1.5VSDGPU
+1.5VSDGPU

0.1U_0402_10V7K~D 10U_0603_6.3V6M~D 0.1U_0402_10V7K~D 10U_0603_6.3V6M~D

2
1
2
1
2
1
2
1
10U_0603_6.3V6M~D

CV665 CV615 CV647 CV595

Issued Date
0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D 0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D

Security Classification
2
1
2
1
2
1
2
1

CV661 CV614 CV643 CV594

(17,18,35,57)

0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D 0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D

2
1
2
1
2
1
2
1

UV26 SIDE
UV24 SIDE

CV662 CV603 CV644 CV591

0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D 0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D

DGPU_PWROK

DGPU_PWR_EN_R#

2
1
2
1
2
1
2
1

2011/06/02
CV663 CV613 CV645 CV593
2
Q296A

0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D 0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D

R1939

1 6 2 1
470_0402_5%~D

2
1
2
1
2
1
2
1
Item6_X02

CV664 CV602 CV646 CV590 2N7002DW-7-F_SOT363-6~D

2

+1.5VSDGPU

0.1U_0402_10V7K~D 1U_0402_6.3V6K~D 0.1U_0402_10V7K~D 1U_0402_6.3V6K~D

QZ21A

2
1
2
1
2
1
2
1

1 6 2 1
CV666 CV600 CV648 CV588
+3VALW

DMN66D0LDW-7_SOT363-6~D
1U_0402_6.3V6K~D 1U_0402_6.3V6K~D
RZ22

2
2

2
1
2
1

CV604 CV592
Compal Secret Data
Deciphered Date
1U_0402_6.3V6K~D 1U_0402_6.3V6K~D
100K_0402_5%~D

DGPU_PWR_EN_R#

2
1
2
1
5

CV601 CV589
5

Q296B
R1940
QZ21B

4 3 2 1
470_0402_5%~D

4 3 2 1
2N7002DW-7-F_SOT363-6~D
B+_BIAS

DMN66D0LDW-7_SOT363-6~D
+1.05VSDGPU
RZ21

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
2012/06/02

2 1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+1.5VSDGPU
+1.5VSDGPU

0.1U_0402_10V7K~D 10U_0603_6.3V6M~D 0.1U_0402_10V7K~D 10U_0603_6.3V6M~D

RZ23
40.2K_0402_1%~D

2
1
2
1
2
1
2
1

CV659 CV612 CV653 CV587 C1919

2
1

0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D 0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D 10U_0603_6.3V6M~D

1

150K_0402_5%~D

DGPU_PWR_EN_R#
R1946

2
1
2
1
2
1
2
1

CV655 CV611 CV649 CV586

Size
Title

Date:
2
G

0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D 0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D

RZ16
+1.05VS

2
5
6
7
8

Item1_X01

3 1 2 1
470_0402_5%~D

2
1
2
1
2
1
2
1
S
D

UV27 SIDE
UV25 SIDE
+3VSDGPU
U632

CV656 CV608 CV650 CV583

2N7002K_SOT23-3
0_0402_5%~D

0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D 0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D

QZ18
4
Document Number
2
1
2
1
2
1
2
1
2
1

CV657 CV610 CV651 CV585

LA-8381P
C1922
SI4634DY-T1-E3_SO8~D

0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D 0.1U_0402_10V7K~D 4.7U_0603_6.3V6K~D

3
2
1

Item13_X02

Thursday, January 12, 2012

2
1
2
1
2
1
2
1

1
1

8A

C1920

CV658 CV607 CV652 CV582

2
1

0.1U_0402_10V7K~D 1U_0402_6.3V6K~D 0.1U_0402_10V7K~D 1U_0402_6.3V6K~D

0.1U_0402_25V6K~D

DGPU_PWR_EN_R#

0.1U_0402_16V7K~D
2
1
2
1
2
1
2
1
+1.05VSDGPU

2
G

CV660 CV605 CV654 CV580 C1921

Sheet
2
1

RZ15

1U_0402_6.3V6K~D 1U_0402_6.3V6K~D 3 1 2 1 10U_0603_6.3V6M~D

470_0402_5%~D

S
D
+1.05V to +1.05VSDGPU Transfer

2
1
2
1

31
+VGA_CORE

CV609 CV584
2N7002K_SOT23-3
QZ17
Compal Electronics, Inc.

of

1U_0402_6.3V6K~D 1U_0402_6.3V6K~D
N13P (10/10) DC/DC interface
2
1
2
1

63

CV606 CV581
Item13_X02

Rev
1.0
A
B
C
D
 A B C D E

+5VALW to +5VS
+5VALW +5VS
Q26
SI4800BDY-T1-E3_SO8
8 1
7 2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

2
1 1 6 3 1 1

1U_0402_6.3V6K~D
5 C338
R267
470_0603_5%

4
2 2 2 2

C335

C336

C337

1
1 1

+5VS_D
Item3_X02
R271

6
B+_BIAS 1 2 SHORT
R270

0.1U_0603_50V_X7R
102K_0402_1% 0_0402_5%~D1 Q285A

3
@ 2 SUSP
C340 R273
Q285B 0_0402_5%~D DMN66D0LDW-7_SOT363-6~D

1
SUSP 5 2

DMN66D0LDW-7_SOT363-6~D

+3VALW to +3VS
+3VALW +3VS
Item35_X01 Q27
AO4304L_SO8
8 1
7 2
+1.5V to +1.5V_CPU_VDDQ
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D
1 1 6 3 1 1
5
C348
1U_0402_6.3V6K~D
4

2 2 2 2
C345

C346

C347
+1.5V
Item35_X01 QC3 +1.5V_CPU_VDDQ
2 Item3_X02 +3VALW B+_BIAS AO4304L_SO8
2

R276 8 1
1 2 SHORT 7 2

100K_0402_5%~D
B+_BIAS

10U_0603_6.3V6M~D
1

1
R279 6 3 1

20K_0402_5%~D
100K_0402_5%~D
0.1U_0603_50V_X7R

102K_0402_1% 0_0402_5%~D1

RC101
Item37_X01 5
1

1
D

RC103
SUSP Q30 C354 R281

RC102
2

4
G 2N7002K_SOT23-3 2

CC138
1M_0402_5%~D

2
S 2
Item13_X02
3

RUN_ON_CPU1.5VS3
2

3
QC5B

330K_0402_1%

0.1U_0603_50V_X7R
1
2N7002DW-7-F_SOT363-6~D
1
RUN_ON_CPU1.5VS3# 5 +5VALW

RC105

CC139
4
2

2N7002DW-7-F_SOT363-6~D

2
6

1
QC5A

(19,47,55,56) SUSP# RC104 1 @ 2 0_0402_5%~D 2 R288

100K_0402_5%~D
+3VALW to +3V_PCH

2
(47) CPU1.5V_S3_GATE RC107 1 SHORT 2 0_0402_5%~D SUSP

1
+3VALW D
Item3_X02 1
SUSP# Q33
2
JP3 @ CC217 @ G 2N7002K_SOT23-3
RUN_ON_CPU1.5VS3# (7)
1 2 0.1U_0402_10V7K~D S

0.1U_0603_50V_X7R

3
1 2

1
2
JUMP_43X79 +3V_PCH R291
1
@
Item13_X02
Q41 100K_0402_5%~D
SI4800BDY-T1-E3_SO8 40mil 2

C360
8 1

2
7 2
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1 1 6 3 1 1
3
5 3
C352
1U_0402_6.3V6K~D
4

2 2 2 2
C349

C350

C351

Item3_X02
R277
B+_BIAS 1 2 SHORT
0_0402_5%~D

R280
0.1U_0603_50V_X7R

102K_0402_1% 0_0402_5%~D1
2N7002K_SOT23-3

Q31 @
1

D
PCH_PWR_EN# 2
C355

R282

2
G
Item13_X02 S
3

+5VALW
+3VALW +5VALW

1
2

1
+1.5V_CPU_VDDQ +0.75VS
R286 R295
10K_0402_5%~D R287 100K_0402_5%~D
1

100K_0402_5%~D

2
R292 R293 SYSON#

2
+1.5VS +VCCP +3V_PCH +3VS +1.5V 220_0402_5%~D 22_0402_5%~D PCH_PWR_EN#
(20) PCH_PWR_EN#

1
D

1
D Q35
(47,55) SYSON 2
2

2 Q32 G 2N7002K_SOT23-3

0.1U_0603_50V_X7R
(47) PCH_PWR_EN
1

2N7002K_SOT23-3
+1.5V_CPU_VDDQ_CHG

+DDR_CHG

G 1 S Item13_X02

3
1
R296 R297 R298 R299 R289 S Item13_X02 @

0.1U_0603_50V_X7R

3
1
1 R300
470_0402_5%~D 470_0402_5%~D 470_0402_5%~D 470_0402_5%~D 470_0402_5%~D R290 @ @ 100K_0402_5%~D
2

C361
100K_0402_5%~D
2

C359
4 4

2
RUN_ON_CPU1.5VS3# 2

2
+1.5VS_D

+VCCP_D

+3V_D

+3VS_D

+1.5V_D

2N7002KW_SOT323-3

2N7002KW_SOT323-3
2N7002KW_SOT323-3

2N7002KW_SOT323-3

2N7002KW_SOT323-3

D D
6

Q37

Q38

2 2
Q4 Q36 Q34 G G
1

D D Q5A Q5B D
S S
3

SUSP 2 SUSP 2 PCH_PWR_EN# 2 SUSP 5 SYSON# 2

G G DMN66D0LDW-7_SOT363-6~D
G
Security Classification Compal Secret Data Compal Electronics, Inc.
S DMN66D0LDW-7_SOT363-6~D
S S 2011/06/02 2012/06/02 Title
Issued Date Deciphered Date
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 32 of 63
A B C D E
 5 4 3 2 1

+LCDVDD B+ R1835 1 @ 2 0_0805_5%~D +INV_PWR_SRC

+LCDVDD +5VALW
W=60mils +3VS

10U_0603_6.3V6M~D
0.1U_0402_16V7K~D
LCD POWER 1 1 1

2
CV367

CV368
Item26_X01 R377 +3VS
R1847 47K_0402_5%~D 0.1U_0402_16V7K~D 60mil

CV369
2 2 22_0603_5%~D 2 Q70
B+ SI3457BDV-T1-E3_TSOP6~D 60mil

1 1

1
R378 +INV_PWR_SRC_R R2015 1 SHORT 2 0_0805_5%~D +INV_PWR_SRC

D
3
D 56K_0402_5%
S
AO3419L_SOT23-3 6

S
G
Q288 2 2 1 2 Q289 4 5 Item4_X03
2N7002KW_SOT323-3 G W=60mils 2
S 1

100K_0402_5%~D
3

1000P_0402_50V7K~D

1
+LCDVDD

G
1 1 1

0.47U_0603_16V7K~D
D
C1126 R1242

3
C549 +LCDVDD C1127
D D
0.1U_0603_50V_X7R

4.7U_0603_6.3V6K~D
DV7 2 2 2
1 1

2
(16,47) PCH_ENVDD PCH_ENVDD 2 C551

1
D 0.1U_0402_16V7K~D PWR_SRC_ON
1 2 Q290

1
2 2

C1869
G BSS138_NL_SOT23-3

1
(47) EC_ENVDD EC_ENVDD 3 S R1243

3
R2572 100K_0402_5%~D
BAT54CW-7-F_SOT323-3~D 10K_0402_5%~D
Item3_X02

2
2
R2005

1
0_0402_5%~D D
(47) EN_INVPWR 2 SHORT 1 +LCDVDD_R 2
G
Q71
2N7002KW_SOT323-3
LVDS Conn.
R2006 S

3
0_0402_5%~D
+LCDVDD 2 @ 1
JLVDS
PCH_TXOUT0- 1
(16) PCH_TXOUT0- 1
PCH_TXOUT0+ 2
(16) PCH_TXOUT0+ 2
3
PCH_TXOUT1- 3
(16) PCH_TXOUT1- 4
+3VS PCH_TXOUT1+ 4
(16) PCH_TXOUT1+ 5
5
6
PCH_TXOUT2- 6
Check (16) PCH_TXOUT2- 7
7
1

PCH_TXOUT2+ 8
+3VS +3VS (16) PCH_TXOUT2+ 8
@ R382 9
PCH_TXCLK- 9
(16) PCH_TXCLK- 10
@ 4.7K_0402_5%~D PCH_TXCLK+ 10
(16) PCH_TXCLK+ 11
11

1
D69 12
2

BKOFF# DISPOFF# PCH_TZOUT0- 12

(47) BKOFF# 1 2 (16) PCH_TZOUT0- 13
@ R394 PCH_TZOUT0+ 13
(16) PCH_TZOUT0+ 14
14
1

5
U54 10K_0402_5%~D 15
CH751H-40PT_SOD323-2~D PCH_TZOUT1- 15
1 16

P
(47) EC_INV_PWM (16) PCH_TZOUT1-

2
D72 10K_0402_5%~D IN1 INV_PWM PCH_TZOUT1+ 16
4 (16) PCH_TZOUT1+ 17
R2021 PCH_INV_PWM O 17
2 1 (16) PCH_INV_PWM 2 18
IN2 18

1
G
C PCH_TZOUT2- 19 C
(16) PCH_TZOUT2-
2

SN74AHC1G08DCKR_SC70-5 R2194 PCH_TZOUT2+ 19

(16) PCH_TZOUT2+ 20

3
CH751H-40PT_SOD323-2~D 100K_0402_5%~D 20
21
PCH_TZCLK- 21
Item3_X02 (16) PCH_TZCLK- 22
PCH_TZCLK+ 22
(16) PCH_TZCLK+ 23

2
LCD_TEST 23
(47) LCD_TEST 24
PCH_LCD_CLK R379 2 SHORT EDID_CLK_LCD 24
(16) PCH_LCD_CLK 1 0_0402_5%~D 25
@ PCH_LCD_DATA R1836 2 SHORT 25
1 2 (16) PCH_LCD_DATA 1 0_0402_5%~D EDID_DATA_LCD 26
R2192 0_0402_5%~D INV_PWM_R 26
27
@ DISPOFF# 27
1 2 28
R2193 0_0402_5%~D USB20_P12_C 28
29
USB20_N12_C 29
30 41
CAM_DET# 30 G1
(15) CAM_DET# 31 42
DMIC_CLK_R 31 G2
Item18_X01 32 43
32 G3
33 44
R2624 1 33 G4
2 0_0402_5%~D (41) DMIC0
DMIC0 34 45
34 G5
+3VS_CAM 35 46
L114 35 G6
+3VS 36 47
USB20_P12 USB20_P12_C 36 G7
(17) USB20_P12 1
1 2
2 W=60mils +LCDVDD 37
37 G8
48
38 49
@ 38 G9
39 50
USB20_N12 USB20_N12_C 39 G10
(17) USB20_N12 4 3 +INV_PWR_SRC 40 51
4 3 40 G11
WCM-2012-900T_4P JAE_FI-G40SB-VF25-R2000-DT~D
LCD Backlight Selector R2625 1 2 0_0402_5%~D W=60mils
CONN@

D50
DMIC_CLK 6 1 USB20_N12_C
V I/O V I/O

+5VS 5 2
V BUS Ground
DMIC0 4 3 USB20_P12_C
V I/O V I/O
IP4223CZ6_SO6~D

B B

+3VS +3VS_CAM
Q47
SI2301CDS-T1-GE3_SOT23-3 +INV_PWR_SRC

+5VALW

D
3 1

1
@

10U_0805_25V6K~D
R2013
1

1
820_0805_1%

G
2 1

2
R1653 @ R2014

C2149
C1748 100K_0402_5%~D 100K_0402_5%~D

3 2
0.1U_0402_16V7K~D @
1 2
2

2
@
Item14_X03 Q305B
5
DMN66D0LDW-7_SOT363-6~D
1

6
D
Item13_X02

4
2 @
(47) EN_CAM
G Q42 Q305A
S 2N7002K_SOT23-3 +LCDVDD_R 2
3

DMN66D0LDW-7_SOT363-6~D

1
EN_CAM control circuit
Discharg Circuit

R1949
0_0402_5%~D
INV_PWM 2 SHORT 1 0_0402_5%~D INV_PWM_R DMIC_CLK 2 SHORT 1 DMIC_CLK_R
(41) DMIC_CLK
A R1950 1 A
1 Item3_X02 @ CU64
Item4_X03 @ CU63 470P_0402_50V7K~D
680P_0402_50V7K~D 2
2

close to JLVDS

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS SW-6038 /camera conn.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 33 of 63
5 4 3 2 1
 5 4 3 2 1

+5VS +R_CRT_VCC +CRT_VCC

D66 D15 D67
CRT DAN217_SC59-3 DAN217_SC59-3 DAN217_SC59-3
W=40mils 2
D68
1 1
FV3
2
W=40mils

1
@ @ @ 3 NC

1
1.1A_6VDC_FUSE 1
BAT1000-7-F_SOT23-3~D R1857 C535
2 0_1206_5%~D
1 0.1U_0402_16V7K~D
R2012 @ 100K_0402_5%~D
+3VS 2

2
0.1U_0402_16V7K~D CU55
(18) CRT_DET#
2 1 JCRT1
Item3_X02 6
PAD~D T83 @ 11
LU6 0_0603_5%~D CRT_R_L 1
D D
PCH_CRT_R 1 SHORT 2 CRT_R_C L31 1 2 CRT_R_L 7
(16) PCH_CRT_R
BLM18BB600SN1D_0603~D CRT_DDC_DATA 12
LU7 0_0603_5%~D CRT_G_L 2
PCH_CRT_G 1 SHORT 2 CRT_G_C L32 1 2 CRT_G_L 8 G 16
(16) PCH_CRT_G
BLM18BB600SN1D_0603~D CRT_HSYNC 13 17
G
LU8 0_0603_5%~D CRT_B_L 3
PCH_CRT_B 1 SHORT 2 CRT_B_C L103 1 2 CRT_B_L 9
(16) PCH_CRT_B
BLM18BB600SN1D_0603~D CRT_VSYNC 14
1 1 1 Item24_X01 4

150_0402_1%~D

150_0402_1%~D

150_0402_1%~D
10P_0402_50V8J~D

10P_0402_50V8J~D

10P_0402_50V8J~D

22P_0402_50V8J~D

22P_0402_50V8J~D

22P_0402_50V8J~D

10P_0402_50V8J~D

10P_0402_50V8J~D

10P_0402_50V8J~D
1

1
10
1

1
SM010007S0L For EMI CRT_DDC_CLK 15
@ @ @ C540 C541 C542 5

100P_0402_50V8J~D
2 2 2

R366
CU56

CU57

CU58

R1832

R1833
1
2

2
SUYIN_070546HR015M25CZR

C537

C538

C539
2

2
CONN@
2

C543
+CRT_VCC

C545
+3VS +3VS +3VS +CRT_VCC +CRT_VCC 0.1U_0402_16V7K~D
2 1 2

5
1
2.2K_0402_5%~D

2.2K_0402_5%~D

2.2K_0402_5%~D

2.2K_0402_5%~D
R1160

OE#
P
R1834 R370 R371 R372 2 4 D_CRT_HSYNC 1 SHORT 2 0_0603_5%~D CRT_HSYNC
(16) PCH_CRT_HSYNC A Y

G
U625
1

1
C 74AHCT1G125GW_SOT353-5 C

3
2
G
Item3_X02

CRT_DDC_DATA R1161
(16) PCH_CRT_DDC_DATA 3 1
D_CRT_VSYNC 1 SHORT 2 0_0603_5%~D CRT_VSYNC
D
S

+CRT_VCC
1 1
Q286 C546 R373

15P_0402_50V8J~D

15P_0402_50V8J~D
2

2N7002KW_SOT323-3 0.1U_0402_16V7K~D 10K_0402_5%~D C552 C553

G

1 2 1 2
2 2
3 1 CRT_DDC_CLK

5
1
(16) PCH_CRT_DDC_CLK
D
S

OE#
P
(16) PCH_CRT_VSYNC 2 4
Q287 A Y

G
2N7002KW_SOT323-3 U628
74AHCT1G125GW_SOT353-5

3
Item12_X02

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Conn.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 34 of 63
5 4 3 2 1
 5 4 3 2 1

X76 BOM option table

PARADE:
U5 = SA00004ZM00
C2018 = SE00000888L (2.2uF_0402) DP Re-Driver config
R2633 = SD02800008L
Other = NC* +3VS_DPR
+3VS_DPR
TI:
U5 = SA00004ZK0L
C2018 = SE000000K8L (1uF_0402)
DP Redriver DP_RST# R2527 2 10K_0402_1%~D

12
25
32
36
1

1
6
R2641 = SD02800008L Near to NV U5 mDP@
DP_PEQ R2526 1 mDP@ 2 4.7K_0402_5%~D

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
D R2642 = SD02800008L D

Other = NC* (23) VGA_mDP_P0

0.1U_0402_16V7K~D 2 1 C70 DISP_C_A0P 38
IN0p OUT0p
23 DISP_A0P_R C92 2 1 0.1U_0402_16V7K~D DISP_A0P DP_CFG1_INPUT R2528 1 @ 2 4.7K_0402_5%~D
0.1U_0402_16V7K~D 2 1 C74 DISP_C_A0N 39 22 DISP_A0N_R C45 2 1 0.1U_0402_16V7K~D DISP_A0N
(23) VGA_mDP_N0 IN0n OUT0n
0.1U_0402_16V7K~D 2 1 C75 DISP_C_A1P 41 20 DISP_A1P_R C39 2 1 0.1U_0402_16V7K~D DISP_A1P DP_CFG0 R2524 1 @ 2 4.7K_0402_5%~D
(23) VGA_mDP_P1 IN1p OUT1p
PERICOM: (23) VGA_mDP_N1
0.1U_0402_16V7K~D 2 1 C78 DISP_C_A1N 42
IN1n OUT1n
19 DISP_A1N_R C52 2 1 0.1U_0402_16V7K~D DISP_A1N
0.1U_0402_16V7K~D 2 1 C72 DISP_C_A2P 44 17 DISP_A2P_R C58 2 1 0.1U_0402_16V7K~D DISP_A2P Item9_X02 OC_1 R2631 1 mDP@ 2 4.7K_0402_5%~D
U5 = SA00004ZN0L (23) VGA_mDP_P2
0.1U_0402_16V7K~D 2 1 C76 DISP_C_A2N 45
IN2p OUT2p
16 DISP_A2N_R C55 2 1 0.1U_0402_16V7K~D DISP_A2N
(23) VGA_mDP_N2 IN2n OUT2n
R2526 = SD02847018L (4.7K_0402) (23) VGA_mDP_P3
0.1U_0402_16V7K~D 2 1 C79 DISP_C_A3P 47 14 DISP_A3P_R C50 2 1 0.1U_0402_16V7K~D DISP_A3P OC_0 R2632 1 @ 2 4.7K_0402_5%~D
0.1U_0402_16V7K~D C77 DISP_C_A3N IN3p OUT3p DISP_A3N_R C51 0.1U_0402_16V7K~D DISP_A3N
R2631 = SD02847018L (4.7K_0402) (23) VGA_mDP_N3 2 1 48 13 2 1
IN3n OUT3n DISP_DAT_AUXN_CONN 1 2
Other = NC* R57 100K_0402_5%~D
Item9_X02 OC_1 3 40 DP_CFG1_INPUT DISP_CLK_AUXP_CONN 1 2
I2C_ADDR CFG1 R59 100K_0402_5%~D
DP_PEQ 4 46 OC_0 Item9_X02
DP_CFG0 SCL_CTL/PEQ NC
5
SDA_CTL/CFG0 DP_RST# DISP_HPD_SINK
35 1 2
+3VS +3VS_DPR RST# RV24 100K_0402_5%~D
26 10 DP_CBL_DET DP_PEQ R2525 1 @ 2 4.7K_0402_5%~D
R235 1 SHORT PD# CAD_SNK
2 0_0805_5%~D
4.99K_0402_1% 1 2 R2514 7 11 DISP_HPD_SINK DP_CFG1_INPUT R2529 1 @ 2 4.7K_0402_5%~D
REXT HPD_SINK
Item4_X03 DP_CFG0 R2523 @
8 1 2 4.7K_0402_5%~D
0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

CAD_SRC
1 1 1 1
VGA_mDP_HPD_C 9 28 R2641 2 mDP@ 1 0_0402_5%~DDISP_CLK_AUXP_CONN
HPD_SRC AUX_SNKP R2642
27 2 mDP@ 1 0_0402_5%~DDISP_DAT_AUXN_CONN
AUX_SNKN DP_RST# C2019 2.2U_0402_6.3V6M~D
Item19_X01 1 2
2 2 2 2
C40

C33

C46

C34

PAD~D T85 33 Item11_X02

PAD~D T84 SCL_DDC VGA_mDP_AUXP/DDC
34 1 2
SDA_DDC RV353 100K_0402_5%~D
2
CEXT VGA_mDP_AUXN/DDC
15 1 2
PAD~D T87 NC2 RV354 100K_0402_5%~D
30 21
PAD~D T86 AUX_SRCP NC3 OC_1 R2633 1 mDP@ 2 0_0402_5%~D
29 37 1 Item9_X02
AUX_SRCN NC4 C2018
43
NC5 mDP@ OC_0 R2634 @
1 2 4.7K_0402_5%~D
2.2U_0402_6.3V6M~D
2

GND1
GND2
GND3
EPAD
C +3VS_DPR Item19_X01 C
CV667

18
24
31
49
2 1 PS8330BQFN48GTR-A0_QFN48_7X7

0.01U_0402_16V7K~D
5

1
P

IN1 DGPU_PWROK (17,18,31,57)

VGA_mDP_HPD 4
(22) VGA_mDP_HPD O
2 VGA_mDP_HPD_C
IN2
G

UV28
3

SN74AHC1G08DCKR_SC70-5
1

RV355
100K_0402_5%~D

RV356 1 @ 2 0_0402_5%~D
Co-lay
2

+3VS FV4 1 2 1.5A_6V_1206L150PR~D

1 1 1 1

0.1U_0402_10V7K~D
RV23 2 @ 1 0_1206_5%~D

10U_0603_6.3V6M~D

22U_0805_6.3V6M~D
0.1U_0402_16V7K~D
2 2 2 2

CV35
CV26

CV37

CV36
B+_BIAS +5VS DP_CAD_DET
1

B+_BIAS +5VS RV359 RV357

5
100K_0402_5%~D @ 2N7002DW-7-F_SOT363-6~D 2N7002DW-7-F_SOT363-6~D
100K_0402_5%~D
1

6 1 4 3
2

RV360 RV358
100K_0402_5%~D @ QV24B JMDP2
100K_0402_5%~D DP_CAD_DET QV24A
2

B B
0.1U_0402_10V7K~D 2 1 C301 DISP_CLK_AUXP_CONN
(23) VGA_mDP_AUXP/DDC
QV22A 0.1U_0402_10V7K~D 2 1 C298 DISP_DAT_AUXN_CONN 1
(23) VGA_mDP_AUXN/DDC GND
DISP_HPD_SINK 2 HPD
2 DISP_A0P 3 LANE0_P
3

QV23B QV23A DP_CBL_DET 4

(17) DP_CBL_DET CONFIG1
QV22B 2N7002DW-7-F_SOT363-6~D DISP_A0N 5
1

LANE0_N
3 4 1 6 DISP_CEC 6 CONFIG2
DP_CBL_DET 5 7 GND
8 GND
2N7002DW-7-F_SOT363-6~D 2N7002DW-7-F_SOT363-6~D 2N7002DW-7-F_SOT363-6~D DISP_A1P 9
4

2
LANE1_P
DISP_A3P 10 LANE3_P
DISP_A1N 11 LANE1_N
DISP_A3N 12 LANE3_N
DP_CAD_DET 13 GND
Item19_X01 Item19_X01 14 GND
DISP_A2P 15 LANE2_P
DISP_CLK_AUXP_CONN 16 AUXCH_P
DISP_A2N 17 LANE2_N
DISP_DAT_AUXN_CONN 18 AUXCH_N
19 GND
20 DP_PWR
+3V_PCH

Place close JDP1 21

22
1

1
23

GROUND
RV361 DP_CBL_DET 24
+3VALW @ DV5 @ DV6 RV26
100K_0402_5%~D DISP_A0P 1 10 DISP_A0P DISP_A3P 1 10 DISP_A3P 5.1M_0402_5%

1
FOX_3V112M3-RH1HH7-7H
2

2
DISP_A0N 2 9 DISP_A0N DISP_A3N 2 9 DISP_A3N
RV276 CONN@
(14) DP_PCH_HPD
1

DISP_A1P 4 7 DISP_A1P DISP_A2P 4 7 DISP_A2P 1M_0402_5%~D

RV362

2
3

DISP_A1N 5 6 DISP_A1N DISP_A2N 5 6 DISP_A2N

QV25B 100K_0402_5%~D
3 3
2

5
A 8 8 A
4

2N7002DW-7-F_SOT363-6~D RCLAMP0524P.TCT~D RCLAMP0524P.TCT~D

QV25A

2 DISP_HPD_SINK

2N7002DW-7-F_SOT363-6~D
1

Item29_X01
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini Display Port
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8381P
Date: Thursday, January 12, 2012 Sheet 35 of 63
5 4 3 2 1
 5 4 3 2 1

+3VS
+3VS_HD
X76 BOM option table +5VS

PARADE: R245 1 SHORT 2 0_0805_5%~D

DDC_CLK_HDMI R2217 2 1 2.2K_0402_5%~D
UV2 = SA00003VV00

10U_0603_6.3V6M~D
Item4_X03 DDC_DAT_HDMI R2216 2 1 2.2K_0402_5%~D

0.1U_0402_10V7K~D
R1896 = SD03449908L (499 ohm) 1 1

C196
C1822 = SE00000888L (2.2U 6.3V) @
W=40mils RV11 0_1206_5%~D
R1904 = SD02847018L (4.7K ohm) +3VS_HD 2 1 +HDMI_5V_OUT
R2635 = SD02800008L (0 ohm) 2 2 +3VS_HD

C198
DV4 FV5
Other = NC* 2 1 2 1
+5VS

10U_0603_6.3V6M~D
0.1U_0402_10V7K~D
3 NC 1 1

1
D
PERICOM: 1.5A_6V_1206L150PR~D
D
BAT1000-7-F_SOT23-3~D CV38 CV39
UV2 = SA00005KO00 R2549
R1896 = SD02847018L (4.7K ohm) 10K_0402_5%~D 2 2

15
21
26
40
46
2
C1822 = SD02847018L (4.7K ohm) UV2 HDMI@

2
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
R2566 = SD02847018L (4.7K ohm) HDMI_OE#
R2568 = SD02847018L (4.7K ohm) (16) PCH_HDMI_TXD0+
PCH_HDMI_TXD0+ C1796 1 2 0.1U_0402_16V7K~D PCH_HDMI_C_TXD0+ 39
IN1p
PCH_HDMI_TXD0- C1793 1 2 0.1U_0402_16V7K~D PCH_HDMI_C_TXD0- 38
R2569 = SD02847018L (4.7K ohm) (16) PCH_HDMI_TXD0- IN1n

1
PCH_HDMI_TXD1+ C1794 0.1U_0402_16V7K~D PCH_HDMI_C_TXD1+ D QV1 JHDMI1
(16) PCH_HDMI_TXD1+ 1 2 42
R2639 = SD02847018L (4.7K ohm) PCH_HDMI_TXD1- C1791 0.1U_0402_16V7K~D PCH_HDMI_C_TXD1- IN2p HDMI_SINK_HPD
(16) PCH_HDMI_TXD1- 1 2 41 2 19
PCH_HDMI_TXD2+ C1798 0.1U_0402_16V7K~D PCH_HDMI_C_TXD2+ IN2n TMDS_TX0P G HP_DET
R2564 = SD02800008L (0 ohm) (16) PCH_HDMI_TXD2+ 1 2 45
IN3p OUT1p
22 18
+5V
PCH_HDMI_TXD2- C1797 1 2 0.1U_0402_16V7K~D PCH_HDMI_C_TXD2- 44 23 TMDS_TX0N S 17
R2565 = SD02800008L (0 ohm) (16) PCH_HDMI_TXD2-

3
IN3n OUT1n DDC/CEC_GND

1
PCH_HDMI_TXC+ C1792 1 2 0.1U_0402_16V7K~D PCH_HDMI_C_TXC+ 48 19 TMDS_TX1P 2N7002E-T1-E3_SOT23-3 DDC_DAT_HDMI 16
(16) PCH_HDMI_TXC+ IN4p OUT2p SDA
R2567 = SD02800008L (0 ohm) (16) PCH_HDMI_TXC-
PCH_HDMI_TXC- C1795 1 2 0.1U_0402_16V7K~D PCH_HDMI_C_TXC- 47
IN4n OUT2n
20 TMDS_TX1N R515 DDC_CLK_HDMI 15
SCL
16 TMDS_TX2P 100K_0402_5%~D 14
R2640 = SD02800008L (0 ohm) OUT3p TMDS_TX2N Reserved
17 13
Other = NC* OUT3n TMDS_TXCP TMDS_L_TXCN CEC
13 12 20

2
OUT4p TMDS_TXCN CK- GND
14 11 21
+3VS_HD HDMI_SINK_HPD OUT4n TMDS_L_TXCP CK_shield GND
30 10 22
HPD_SINK TMDS_L_TX2N CK+ GND
9 23
D0- GND
8
TMDS_L_TX2P D0_shield
32 7
DDC_BUFF_EQ_0 DDC_EN TMDS_L_TX1N D0+
34 6
DDCBUF D1-
5
HDMI_OE# PCH_HDMI_HPD TMDS_L_TX1P D1_shield
25 7 PCH_HDMI_HPD (16) 4
OE# HPDX TMDS_L_TX0N D1+
3
D2-
2
TMDS_L_TX0P D2_shield
1
D2+
8 PCH_HDMI_DAT (16)
DDC_DAT_HDMI SDA SUYIN_100042MR019S153ZL
Item15_X02 29 9 PCH_HDMI_CLK (16)
DDC_CLK_HDMI SDA_SINK SCL CONN@
28
PIO_OC_1 SCL_SINK
4
+3VS_HD R2643 PIO
2 1 0_0402_5%~D RESERVE_0 1
RESERVE_1 ASQ0
12
APD ASQ1
Item22_X01 11
EMI_0 APD
27
R2214 PCH_HDMI_CLK EMI_1 EMI0
1 2 2.2K_0402_5%~D 33
EMI1
C C
R2215 1 2 2.2K_0402_5%~D PCH_HDMI_DAT R1896 2 HDMI@ 1 499_0402_1%~D REXT_OC_2 6
PEQ_OC_0 REXT
3
PEQ

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
R1901 2 @ 1 4.7K_0402_5%~D PRE_EQ_1 C1822 2 1 2.2U_0402_6.3V6M~D CEXT_OC_3 10
HDMI@ PRE_EQ_1 CEXT
35
R1899 @ PRE
2 1 4.7K_0402_5%~D EMI_0
PS8171QFN48G_QFN48_7X7

5
18
24
31
36
37
43
49
R1907 @ 1 4.7K_0402_5%~D PEQ_OC_0
2 Place close JHDMI1
R1904 DDC_BUFF_EQ_0
Item18_X01
2 1 4.7K_0402_5%~D
HDMI@ @
R2564 2 1 0_0402_5%~D EMI_1 RV42 1 2 9NH_0402HS-9N0EJTS_5%~D
HDMI@
R2565 2 1 0_0402_5%~D APD LV5 @
HDMI@ TMDS_TXCN 1 2 TMDS_L_TXCN 1 2
R2635 1 2
2 1 0_0402_5%~D RESERVE_1 CV668 4.7P_0402_50V8C~D
HDMI@ @
R2636 2 @ 1 4.7K_0402_5%~D PIO_OC_1 TMDS_TXCP 4 3 TMDS_L_TXCP 1 2
4 3 CV669 4.7P_0402_50V8C~D
R2637 2 @ 1 4.7K_0402_5%~D REXT_OC_2 MURATA DLW21SN900HQ2L
@
R2638 2 @ 1 4.7K_0402_5%~D CEXT_OC_3 RV47 1 2 9NH_0402HS-9N0EJTS_5%~D
Item10_X02 @
RV50 1 2 9NH_0402HS-9N0EJTS_5%~D

LV6 @
TMDS_TX0N 1 2 TMDS_L_TX0N 1 2
1 2 CV670 4.7P_0402_50V8C~D
@
TMDS_TX0P 4 3 TMDS_L_TX0P 1 2
R2566 PRE_EQ_1 4 3
2 1 4.7K_0402_5%~D CV671 4.7P_0402_50V8C~D
HDMI@ MURATA DLW21SN900HQ2L
R2567 2 1 0_0402_5%~D EMI_0 @
HDMI@ RV49 1 2 9NH_0402HS-9N0EJTS_5%~D
R2568 2 1 4.7K_0402_5%~D PEQ_OC_0
HDMI@ @
R2569 2 1 4.7K_0402_5%~D DDC_BUFF_EQ_0 RV41 1 2 9NH_0402HS-9N0EJTS_5%~D
B B
HDMI@
R1900 2 @ 1 4.7K_0402_5%~D EMI_1 LV7 @
TMDS_TX1N 1 2 TMDS_L_TX1N 1 2
R1903 @ APD 1 2
2 1 4.7K_0402_5%~D CV672 4.7P_0402_50V8C~D
@
R2639 2 1 4.7K_0402_5%~D PIO_OC_1 TMDS_TX1P 4 3 TMDS_L_TX1P 1 2
HDMI@ 4 3 CV673 4.7P_0402_50V8C~D
R2640 2 1 0_0402_5%~D RESERVE_1 MURATA DLW21SN900HQ2L
HDMI@ @
Item10_X02 RV44 1 2 9NH_0402HS-9N0EJTS_5%~D

@
RV46 1 2 9NH_0402HS-9N0EJTS_5%~D

LV8 @
TMDS_TX2N 1 2 TMDS_L_TX2N 1 2
1 2 CV674 4.7P_0402_50V8C~D
@
TMDS_TX2P 4 3 TMDS_L_TX2P 1 2
4 3 CV675 4.7P_0402_50V8C~D
MURATA DLW21SN900HQ2L
@
RV48 1 2 9NH_0402HS-9N0EJTS_5%~D

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI SW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 36 of 63
5 4 3 2 1
 5 4 3 2 1

+3VS +3VS_DMC
PCH/GPU AUX&LANE SW for DMC
R251 1 SHORT 2 0_0805_5%~D

Item4_X03

10U_0603_6.3V6M~D

0.1U_0402_10V7K~D
1 1
+3VS_DMC

2 2

C195

C197
Item14_X01
DP_DMC_CAD R2623 1 @ 2 4.7K_0402_5%~D

DMC_PEQ R2537 1 @ 2 4.7K_0402_5%~D

+3VS_DMC Item22_X01 +3VS_DMC
D D
DMC_CFG1 R1885 1 @ 2 4.7K_0402_5%~D
R2530 2 1 2.2K_0402_5%~D PCH_DPD_CLK
DMC_CFG0 R2534 1 @ 2 4.7K_0402_5%~D
R2531 2 1 2.2K_0402_5%~D PCH_DPD_DAT
DMC_PIO R2541 1 @ 2 4.7K_0402_5%~D

23
31
32
33
45
9
U6 DMC_DAT_AUXN_CONN 1 2
100K_0402_5%~D R2542

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
DMC_CLK_AUXP_CONN 1 2
C1905 1 2 0.1U_0402_16V7K~D PCH_DPD_SW_P0 37 11 DP_DMC_ML0P_R C1899 1 2 0.1U_0402_16V7K~D DP_DMC_ML0P_RCC 100K_0402_5%~D R2543
(16) PCH_DPD_P0 IN_D0p OUT_D0p DP_DMC_ML0P_RCC (38)
C1904 1 2 0.1U_0402_16V7K~D PCH_DPD_SW_N0 38 10 DP_DMC_ML0N_R C1916 1 2 0.1U_0402_16V7K~D DP_DMC_ML0N_RCC
(16) PCH_DPD_N0 IN_D0n OUT_D0n DP_DMC_ML0N_RCC (38)
C1907 1 2 0.1U_0402_16V7K~D PCH_DPD_SW_P1 40 8 DP_DMC_ML1P_R C1898 1 2 0.1U_0402_16V7K~D DP_DMC_ML1P_RCC
(16) PCH_DPD_P1 IN_D1p OUT_D1p DP_DMC_ML1P_RCC (38)
C1906 1 2 0.1U_0402_16V7K~D PCH_DPD_SW_N1 41 7 DP_DMC_ML1N_R C1917 1 2 0.1U_0402_16V7K~D DP_DMC_ML1N_RCC DP_DMC_HPD R513 1 @ 2 100K_0402_5%~D
(16) PCH_DPD_N1 IN_D1n OUT_D1n DP_DMC_ML1N_RCC (38)
C1909 1 2 0.1U_0402_10V7K~D PCH_DPD_SW_P2 43 5 DP_DMC_ML2P_R C1912 1 2 0.1U_0402_16V7K~D DP_DMC_ML2P_RCC
(16) PCH_DPD_P2 IN_D2p OUT_D2p DP_DMC_ML2P_RCC (38)
C1908 1 2 0.1U_0402_10V7K~D PCH_DPD_SW_N2 44 4 DP_DMC_ML2N_R C1914 1 2 0.1U_0402_16V7K~D DP_DMC_ML2N_RCC DMC_PEQ R2540 1 @ 2 4.7K_0402_5%~D
(16) PCH_DPD_N2 IN_D2n OUT_D2n DP_DMC_ML2N_RCC (38)
C1911 1 2 0.1U_0402_10V7K~D PCH_DPD_SW_P3 46 2 DP_DMC_ML3P_R C1913 1 2 0.1U_0402_16V7K~D DP_DMC_ML3P_RCC
(16) PCH_DPD_P3 IN_D3p OUT_D3p DP_DMC_ML3P_RCC (38)
C1910 1 2 0.1U_0402_10V7K~D PCH_DPD_SW_N3 47 1 DP_DMC_ML3N_R C1915 1 2 0.1U_0402_16V7K~D DP_DMC_ML3N_RCC DMC_CFG1 R1880 1 @ 2 4.7K_0402_5%~D
(16) PCH_DPD_N3 IN_D3n OUT_D3n DP_DMC_ML3N_RCC (38)
DMC_CFG0 R2536 1 @ 2 4.7K_0402_5%~D
12 29 DMC_CFG0
I2C_CTL_EN CFG0 DMC_CFG1 DMC_PIO R2535 @
30 1 2 4.7K_0402_5%~D
DMC_PEQ CFG1
42
PEQ DP_DMC_CAD R2573
13 1 2 1M_0402_5%~D
PS0/SCL_CTL
14
SDA_CTL
DP_DMC_CAD
Item4_X01
6 35 DP_DMC_CAD (38)
PD OUT_CA_DET
R1878 2 1 4.99K_0402_1% 15 34 DP_DMC_HPD
REXT OUT_HPD DP_DMC_HPD (38)
DMC_PIO 36
PIO
48 22 DMC_CLK_AUXP_CONN
(16) PCH_DMC_HPD IN_HPDX OUT_AUXp_SCL DMC_CLK_AUXP_CONN (38)
21 DMC_DAT_AUXN_CONN
OUT_AUXn_SDA DMC_DAT_AUXN_CONN (38)

(16) PCH_DPD_CLK 18
IN_DDC_SCL
C (16) PCH_DPD_DAT 17 20 C2146 1 2 0.1U_0402_16V7K~D C
IN_DDC_SDA AC_AUXp
19 C2147 1 2 0.1U_0402_16V7K~D
AC_AUXn
C2023 1 2 0.1U_0402_16V7K~D PCH_DPD_AUXP_R 25
(16) PCH_DPD_AUXP IN_AUXp
C2022 1 2 0.1U_0402_16V7K~D PCH_DPD_AUXN_R 24
(16) PCH_DPD_AUXN IN_AUXn
16
CEXT

GND1
GND2
GND3
GND4
GND5
EPAD
1

C1821

3
26
27
28
39
49
PS8311QFN48GTR-A0_QFN48_7X7 2 2.2U_0603_10V7K~D

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DMC MUX/Redriver
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8381P
Date: Thursday, January 12, 2012 Sheet 37 of 63
5 4 3 2 1
 A B C D E

X76 BOM option table

PERICOM (PI3EQX6741):
m-SATA ReDriver BlueTooth
U637 = SA00004H100 +3VS +3VS +3VS
RS318 = SD02800008L (0 ohm)
Other = NC* 110mA

0.1U_0402_16V7K~D
+3VS +3VS
1

1K_0402_1%~D

1K_0402_1%~D

1K_0402_1%~D

1K_0402_1%~D

1K_0402_1%~D

1K_0402_1%~D

1K_0402_1%~D
2 RS302 1

2 RS301 1

2 mSATA@1

2 mSATA@1

2 RS303 1

2 RS304 1

2 RS305 1
PARADE (PS8520B):

mSATA@

mSATA@
@ 1
U637 = SA00004WF00 CU1

CS31
RS317 = SD02800008L (0 ohm) 2 0.1U_0402_16V7K~D CU2
RS320 = SD02800008L (0 ohm) 1U_0402_6.3V6K~D

3
2
S
U637 mSATA@
RS321 = SD02800008L (0 ohm) @ @ @ @ @ BT_ON#
G

RS317

RS318
6 10 (18) BT_ON# 1 2 2
1 NC VDD QU1 1
Other = NC* 16
NC VDD
20 RS319 1 @ 2 0_0402_5%~D RU1 10K_0402_5%~D
D AO3419L_SOT23-3

1
RS320 1 mSATA@2 0_0402_5%~D 3 13 RS321 1 mSATA@2 0_0402_5%~D Item31_X01
TDet_B# TDet_A#
TI (SN75LVCP601RTJR): RS307 1 @ 2 1K_0402_1%~D 17
A_EQ B_EQ
19 RS308 1 @ 2 1K_0402_1%~D CU3 W=40mils
RS306 1 @ 2 1K_0402_1%~D 9 8 RS309 1 @ 2 1K_0402_1%~D
U637 = SA00003ZX0L 7
A_EM B_EM
18 RS310 1 mSATA@2 1K_0402_1%~D 0.1U_0402_16V7K~D
+3VS_BT
EN TDeT_EN

1
4.7U_0603_6.3V6K~D
RS310 = SD02800008L (0 ohm) 1
RS318 = SD02800008L (0 ohm) (14) SATA_PTX_DRX_P1 SATA_PTX_DRX_P1 CS42 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P1_R 1 15 SATA_PTX_DRX_P1_RC CS55 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P1_C CU5 RU2
SATA_PTX_DRX_N1 CS43 1 SATA_PTX_DRX_N1_R AI+ AO+ SATA_PTX_DRX_N1_RC SATA_PTX_DRX_N1_C
(14) SATA_PTX_DRX_N1 2 0.01U_0402_16V7K~D 2 14 CS56 1 2 0.01U_0402_16V7K~D 300_0603_5%
RS320 = SD02800008L (0 ohm) AI- AO-
RS321 = SD02800008L (0 ohm) SATA_PRX_DTX_N1 CS53 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N1_RC 4 SATA_PRX_DTX_N1_R CS57 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N1_C 2

CU4
(14) SATA_PRX_DTX_N1 12

2
SATA_PRX_DTX_P1 CS54 1 SATA_PRX_DTX_P1_RC 5 BO- BI- SATA_PRX_DTX_P1_R SATA_PRX_DTX_P1_C
Other = NC* (14) SATA_PRX_DTX_P1 2 0.01U_0402_16V7K~D 11 CS58 1 2 0.01U_0402_16V7K~D
BO+ BI+ 0.1U_0402_16V7K~D
21
GND

1
D
2 QU2
G 2N7002K_SOT23-3
PI3EQX6741STZDEX_TQFN20_4X4 S Item13_X02

3
Item28_X01
+3VS_BT
C191
1 2

+1.5VS +1.5VS 0.1U_0402_16V7K~D

U641
9
VDD

1
11 4 PCIE_PTX_WWANRX_P1_M
VDD A0+ PCIE_PTX_WWANRX_N1_M R89 JBT
13 5
VDD A0- 10K_0402_5%~D
19 1
VDD PCIE_PRX_WWANTX_P1_M 1
2 26 6 (15) BT_DET# 2 2
VDD A1+ PCIE_PRX_WWANTX_N1_M COEX1 2
28 7 3

2
VDD A1- 3
4
SATA_PTX_DRX_P1_C RV43 mSATA_DET# 4
24 3 2 SHORT 1 0_0402_5%~D 5
SATA_PTX_DRX_N1_C B0+ SEL 5
23 6
SATA_PRX_DTX_N1_C B0- BT_RADIO_DIS# 6
22 Item3_X02 (18) BT_RADIO_DIS# 7
SATA_PRX_DTX_P1_C B1+ COEX2 7
21 1 8
PCIE_PTX_WANRX_P2 B1- GND 8
18 10 9
(15) PCIE_PTX_WANRX_P2 PCIE_PTX_WANRX_N2 C0+ GND 9
17 12 (17) USB20_N8 10
(15) PCIE_PTX_WANRX_N2 PCIE_PRX_WANTX_P2 C0- GND 10
16 14 (17) USB20_P8 11 13
(15) PCIE_PRX_WANTX_P2 PCIE_PRX_WANTX_N2 C1+ GND 11 G1
15 20 12 14
(15) PCIE_PRX_WANTX_N2 C1- GND 12 G2
25
GND LOTES_YBA-WTB-015-K01~D
2 27
NC GND
8 29
NC TPAD
PI2DBS6212ZHEX TQFN 28P
SEL Source CONN@

100P_0402_50V8J~D
Item33_X01 0 SATA

33P_0402_50V8J~D

1 10K_0402_5%~D

@ C193
1 PCIe 1 1

C192

R167
To DMC PCB connector
2 2

2
JWDB1
82 81
G2 G1

PCIE_WAKE# PLT_RST#
(16,39,47) PCIE_WAKE#
COEX2
80
78
Reserved Reserved
79
77
PLT_RST# (6,7,17,39,40,47) SIM card board 4.7uF change to 1uF
Reserved Reserved PCH_SMBCLK (6,12,13,15,45)
COEX1 76
Reserved Reserved
75 PCH_SMBDATA (6,12,13,15,45) for Tiger detect issue.
WL_OFF# 74 73
(17) WL_OFF# Reserved Reserved
(15) MINI1CLK_REQ# 72 71 USB20_N4 (17)
VPP_Test SDIO_GPIO2_BLT
70 69 USB20_P4 (17)
3 SDIO_PWR#_BLT SDIO_GPIO1_BLT +UICC_PWR +UICC_PWR +UICC_PWR 3
68 67
(15) CLK_PCIE_MINI1#
(15) CLK_PCIE_MINI1 66
SDIO_RST#_BLT
SDIO_CMD_BLT
SDIO_D3_BLT
SDIO_D2_BLT
65 DMC_RADIO_OFF#
DMC_RADIO_OFF# (17) SIM Connector

1
64 63 +UICC_PWR
VSS SDIO_D1_BLT

1
(15) PCIE_PRX_WLANTX_N1 PCIE_PRX_WLANTX_N1 62 61 DP_DMC_CAD R2644
SDIO_CLK_BLT SDIO_D0_BLT DP_DMC_CAD (37)
(15) PCIE_PRX_WLANTX_P1 PCIE_PRX_WLANTX_P1 60 59 UICC_VPP R88 0_0402_5%~D R95
VSS VSS 10K_0402_5%~D 10K_0402_5%~D
58 57 Item8_X03 @
PCIE_PTX_WLANRX_N1 Ser_TX BLT_USB3_HOST+ UICC_RESET @ JSIM1 CONN@ @
(15) PCIE_PTX_WLANRX_N1 56 55

2
PCIE_PTX_WLANRX_P1 Ser_RX BLT_USB3_HOST-
(15) PCIE_PTX_WLANRX_P1 54 53 1 5

2
VSS VSS UICC_DATA UICC_RESET VCC GND UICC_VPP
52 51 2 6
mSATA_DET# BLT_USB2_BioMetric+ BLT_USB1_WWAN_Data+ UICC_CLK RST VPP UICC_DATA
mSATA_DET pin at pin 50 50
BLT_USB2_BioMetric- BLT_USB1_WWAN_Data-
49 3
CLK I/O
7
BT_RADIO_DIS# 48 47 UICC_CLK 4 8
VSS VSS NC NC
(47) EC_TX 46 45 9
VSS VSS GND
(47) EC_RX 44 43 USB20_N5 (17) 10
DMC_PCH_DET# VDD 3.3v VDD 3.3v GND
(15) DMC_PCH_DET# 42 41 USB20_P5 (17)
VDD 3.3v VDD 3.3v DP_DMC_HPD MOLEX_475531001~D
40 39 DP_DMC_HPD (37)
DMC_DAT_AUXN_CONN VDD 3.3v VDD 3.3v
(37) DMC_DAT_AUXN_CONN 38 37
DMC_CLK_AUXP_CONN VDD 3.3v VDD 3.3v DP_DMC_ML3N_RCC
(37) DMC_CLK_AUXP_CONN 36 35
VSS VSS DP_DMC_ML3P_RCC DP_DMC_ML3N_RCC (37)
34 33 1 1 1
DP_DMC_ML2N_RCC VSS VSS DP_DMC_ML3P_RCC (37)
(37) DP_DMC_ML2N_RCC 32 31
DP_DMC_ML2P_RCC M_Clk VSS DP_DMC_ML1N_RCC @ C428 @ C429 @ C430
(37) DP_DMC_ML2P_RCC 30 29
VSS BLT_USB_Port1_Dir DP_DMC_ML1P_RCC DP_DMC_ML1N_RCC (37) 1U_0402_6.3V6K~D 0.1U_0402_16V7K~D
28 27 4.7U_0603_6.3V6K~D
DP_DMC_ML0N_RCC I2S_BCLK RST_BLT# DP_DMC_ML1P_RCC (37) 2 2 2
(37) DP_DMC_ML0N_RCC 26 25
DP_DMC_ML0P_RCC I2S_DOUT SMBALERT_1 PCIE_PTX_WWANRX_P1_M
(37) DP_DMC_ML0P_RCC 24 23
I2S_DIN SMBDATA_1 PCIE_PTX_WWANRX_N1_M
22 21
I2S_LRC SMBCLK_1
(15) MINI2CLK_REQ# 20 19
VSS VSS PCIE_PRX_WWANTX_P1_M
18 17 Item16_X02
NC NC PCIE_PRX_WWANTX_N1_M
16 15
BLT_LED_1# NC
14 13
VSS VSS U41 @
12 11 CLK_PCIE_MINI2# (15)
NC eDP_CH1_p
+3VS 10
NC eDP_CH1_n
9 CLK_PCIE_MINI2 (15) Reserve for SIM card does not meet UICC_VPP 3
V I/O V I/O
4 UICC_RESET
8 7 rise time and pull-up is needed.
VSS VSS
6 5 2 5 +UICC_PWR
LID_Cl# Radio_disable# Ground V BUS
4 3 1
BLT_Sus# PAID_IN UICC_CLK UICC_DATA @ C431
1 2 1 +1.5VS 1 6
VSS VSS V I/O V I/O
1
+ @ C1924 HRS_DF12(3.0)-80DP-0.5V86 IP4223CZ6_SO6~D 0.1U_0402_16V7K~D
Item17_X03 C1946 47P_0402_50V8J~D CONN@
1
@
1
C1925 2
330U_D2E_6.3VM_R25~D C2148 47P_0402_50V8J~D
4
2 2 22U_0805_6.3V6M~D
For ESD 4

2 2
@ Reserve for RF please
close to JWDB1
Reserve for RF please
close to JWDB1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini Card -WLAN / DMC / BT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 38 of 63
A B C D E
 5 4 3 2 1

UL1
Atheros +LAN_IO
(15) PCIE_PRX_GLANTX_P3 2 1 PCIE_PRX_GLANTX_P3_C 30 AR8151 AL1A 11 LAN_MDIP0 RL2 2 1 49.9_0402_1% +LAN0 CL3 1 2 1000P_0402_50V7K~D
CL2 0.1U_0402_16V7K~D TX_P TRXP0 LAN_MDIN0 RL1 49.9_0402_1% CL4 0.1U_0402_16V7K~D
12 2 1 1 2
PCIE_PRX_GLANTX_N3_C TRXN0 LAN_MDIP1 RL3 49.9_0402_1% +LAN1 CL5 1000P_0402_50V7K~D
(15) PCIE_PRX_GLANTX_N3 2 1 29 14 2 1 1 2
TX_N TRXP1

1
CL1 0.1U_0402_16V7K~D 15 LAN_MDIN1 RL4 2 1 49.9_0402_1% CL6 1 2 0.1U_0402_16V7K~D
PCIE_PTX_GLANRX_P3 TRXN1 LAN_MDIP2 RL5 49.9_0402_1% +LAN2 CL7 1000P_0402_50V7K~D RL6
(15) PCIE_PTX_GLANRX_P3 35 17 2 1 1 2
RX_P TRXP2 LAN_MDIN2 RL7 49.9_0402_1% CL8 0.1U_0402_16V7K~D 0_0402_5%~D
18 2 1 1 2
PCIE_PTX_GLANRX_N3 TRXN2 LAN_MDIP3 RL8 49.9_0402_1% +LAN3 CL9 1000P_0402_50V7K~D
(15) PCIE_PTX_GLANRX_N3 36 20 2 1 1 2
RX_N TRXP3 LAN_MDIN3 RL9 49.9_0402_1% CL10 0.1U_0402_16V7K~D
21 2 1 1 2

2
CLK_PCIE_LAN TRXN3
(15) CLK_PCIE_LAN 33
REFCLK_P PLT_RST# @
close to Lan chip 1000p reserved for EMI 1 2 4.7K_0402_5%~D
CLK_PCIE_LAN# 32 RL10
(15) CLK_PCIE_LAN# REFCLK_N
13 +AVDDL PCIE_WAKE# 1 @ 2 4.7K_0402_5%~D
AVDDL
(15) LANCLK_REQ# 2 SHORT 1 CLKREQ_LAN#_R 4 19 RL11
RL12 0_0402_5%~D CLKREQ# AVDDL CLKREQ_LAN#_R @
31 1 2 4.7K_0402_5%~D
PLT_RST# AVDDL RL13
(6,7,17,38,40,47) PLT_RST# 2 34
D PERST# AVDDL D

(16,38,47) PCIE_WAKE#
Item3_X02 PCIE_WAKE# 3
WAKE#
AVDDL_REG
6
PCH side was mounted
16 +AVDDH W=40mils
AVDDH 2.2UH +-20% 1225AS-H-2R2M-P2 1.3A
25
SMCLK AVDDH
22 W=20mils
26 9
SMDATA AVDDH_REG LL1
28 +LX 1 2 +VDDCT +DVDDL
TEST_RST +DVDDL
27 24

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D
1000P_0402_50V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D
TESTMODE DVDDL
41 37
GND DVDDL_REG
LAN_X1
W=40mils 1 1 1 1 1 1 1
LAN_X2
7
XTLO W=40mils CL11 CL12 CL13 CL14 CL16 CL17
8 1 +LAN_IO
XTLI VDD33

CL15
YL1 2 2 2 2 2 2 2
4 3 40 +LX
NC OSC LX
LAN_ACTIVITY VDDCT
5 +VDDCT close to Lan pin40
1 2 38
OSC NC LAN_LINK#_R LED_0 +RBIAS 1 RL14 2
39 10
25MHZ_12PF_X3G025000DC1H~D LAN_LED2#_R LED_1 RBIAS 2.37K_0402_1%~D
23
LED_2 close to Lan pin5
2

RL16
close to Lan pin37 close to Lan pin24
1 1
5.1K_0402_1%~D AR8151-BL1A
CL18 CL19
18P_0402_50V8J~D 18P_0402_50V8J~D
1

2 2

Item27_X01

W=40mils
W=40mils
+3VALW QL1
C C
FDC655BN_NL_SSOT6~D
+LAN_IO
W=20mils W=20mils
close to Lan pin19
D

6 1A
S

1 5 4 +LAN_IO_R R2016 1 2 close to Lan pin9 close to Lan pin16 close to Lan pin6 close to Lan pin31
CL20 2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D
1000P_0402_50V7K~D

0.1U_0402_16V7K~D
1U_0402_6.3V6K~D 1 0_0805_5%~D +AVDDH +AVDDL

1U_0402_6.3V6K~D
G

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D
B+_BIAS 2
1 1 1 1 1
3

+3VALW 1 1 1 1 1 1 1 1 1 1
Item36_X01 CL31 CL32 CL33 CL34 CL35
CL21 CL22 CL23 CL24 CL25 CL26 CL27 CL28 CL29 CL30
2

2 2 2 2 2
RL18 2 2 2 2 2 2 2 2 2 2
2

330K_0402_5%~D
RL28
10K_0402_5%~D
1

EN_WOL close to Pin 1

1

D
1 close to Lan pin22
1.5M_0402_5%~D

2 QL2 close to Lan pin34 close to Lan pin13

(47) EN_WOL#
G 2N7002KW_SOT323-3 RL19 CL36
S 0.1U_0402_25V6K~D
3

2
1

2 1 LAN_LED2#_R
RL26 470_0402_5%~D
LL2 TS1 2 1 LAN_LINK#_R
RL21 RL27 130_0402_1%~D
+VDDCT 2 1 +VDDCT_L 1 24 RJ45_CT3 1 2
BLM15AG601SN1D_2P LAN_MDIP3 TCT1 MCT1 RJ45_MDI3+ 75_0402_1%~D JLAN1
2 23
LAN_MDIN3 TD1+ MX1+ RJ45_MDI3- RJ45_MDI0+ CL49 470P_0402_50V7K~D
3 22 1
TD1- MX1- RL22 PR1+ LAN_LED2#
Item4_X02 9 1 2
RJ45_CT2 RJ45_MDI0- LDE_ORANGE- CL38 470P_0402_50V7K~D
4 21 1 2 2
B
LAN_MDIP2 TCT2 MCT2 RJ45_MDI2+ 75_0402_1%~D PR1- LAN_LINK# B
5 20 10 2 1
LAN_MDIN2 TD2+ MX2+ RJ45_MDI2- RJ45_MDI1+ LDE_GREEN-
6 19 3 Item3_X02
TD2- MX2- RL23 PR2+ LAN_LED_VCC1
11 2 SHORT 1 RL20 +LAN_IO
RJ45_CT1 RJ45_MDI2+ A2 0_0402_5%~D CL50 470P_0402_50V7K~D
7 18 1 2 4
LAN_MDIP1 TCT3 MCT3 RJ45_MDI1+ 75_0402_1%~D PR3+ LAN_ACTIVITY_R
8 17 12 2 1LAN_ACTIVITY 1 2
LAN_MDIN1 TD3+ MX3+ RJ45_MDI1- RJ45_MDI2- LED_YELLOW+ RL25 330_0402_5%
9 16 5
TD3- MX3- RL24 PR3- @
13
RJ45_CT0 RJ45_MDI1- LED_YELLOW-
10 15 1 2 6
LAN_MDIP0 TCT4 MCT4 RJ45_MDI0+ 75_0402_1%~D PR2-
11 14 14
LAN_MDIN0 TD4+ MX4+ RJ45_MDI0- RJ45_MDI3+ NC
12 13 7

SHLD1

SHLD2
TD4- MX4- PR4+
RJ45_MDI3- 8
PR4-
2
350UH_GST5009-CLF FOX_JM36113-P2651-9F~D

15

16
TIMAG: S X'FORM_ IH-160 LAN , SP050006F00 CL39
BOTHHAND: S X'FORM_ GST5009-D LF LAN,SP050006B00 1000P_1808_3KV7K~D
1

CONN@ Item25_X01
1U_0402_6.3V6K~D

1000P_0402_50V7K~D

0.1U_0402_16V7K~D

1000P_0402_50V7K~D

0.1U_0402_16V7K~D

1000P_0402_50V7K~D

0.1U_0402_16V7K~D

1000P_0402_50V7K~D

0.1U_0402_16V7K~D
CL41

CL42

CL43

CL44

CL45

CL46

CL47

CL48

1 2 1 2 1 2 1 2 1

close to LL2 CL40

@ @ @ @
2 1 2 1 2 1 2 1 2

close to TS1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GLAN AR8151 AL1A/ RJ45
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 39 of 63
5 4 3 2 1
 5 4 3 2 1

Item4_X03
+3VS R2017 1 SHORT 2 +3VS_CR
0_0805_5%~D

check IC support 9 in 1 function

+3VS_CR

D D
Zdiff = 100 ohm U135 +ODR_PWR
R1563
(15) PCIE_PTX_CARDRX_P4 PCIE_PTX_CARDRX_P4 1 48 RREF 2 1
HSIP RREF CR27
6.2K_0402_1%~D
(15) PCIE_PTX_CARDRX_N4 PCIE_PTX_CARDRX_N4 2 47 2 1
HSIN 3V3_IN

10U_0603_6.3V6M~D
(15) CLK_PCIE_CD CLK_PCIE_CD 3 46 CDCLK_REQ# CR5 CR6
CDCLK_REQ# (15)

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D
REFCLKP CLK_REQ# 0.1U_0402_10V7K~D

1
1 CR4 1 1

10K_0402_5%~D

1
(15) CLK_PCIE_CD# CLK_PCIE_CD# 4 45 PLT_RST# RR3 CR3
REFCLKN PERST# PLT_RST# (6,7,17,38,39,47)
CR24 4.7U_0603_6.3V6K~D
1 2 AV12 5 44

2
AV12 EEDO 2 2 2

2
PCIE_PRX_CARDTX_P4 1 2 PCIE_PRX_CARDTX_P4_C 6 43
(15) PCIE_PRX_CARDTX_P4 HSOP EECS
CR15 0.1U_0402_10V7K~D For ver:ES2-B0
PCIE_PRX_CARDTX_N4 1 2 PCIE_PRX_CARDTX_N4_C 7 42
(15) PCIE_PRX_CARDTX_N4 HSON EESK
CR16 0.1U_0402_10V7K~D
8 41
GND GPIO/EEDI
+ODR_PWR 1 2 DV12 9 40 MS_INS#
CR22 0.1U_0402_10V7K~D DV12 MS_INS#
10 39 SD_CD# Place CR3 close to socket pin 22
+3VS_CR Card1_3V3 SD_CD#
11 38 SP15_SDWP_XDD7 Item3_X02 Place CR4 close to socket pin 11
3V3_IN SP15
1 12 37 SP14_MSCLK_XDD6 1 SHORT 2 SP14_MSCLK_XDD6_R 1 Place CR5 close to socket pin 11
Card2_3V3 SP14
1

CR28 CR19 RR22 0_0402_5%~D

XD_CD# 13 36 SP13_MSD7_XDD5 @ CR26 Place CR6 close to socket pin 18
10U_0603_6.3V6M~D 0.1U_0402_10V7K~D XD_CD# SP13 5P_0402_50V8C~D
2

2 DV33_18 14 35 SP12_MSD3_XDD4 2
DV33_18 SP12
1
CR23 15 34 SP11_MSD6_XDD3
0.1U_0402_10V7K~D GND SP11
SP1_SDD7_XDRDY 16 33 SP10_MSD2_XDD2
2 SP1 SP10
Removed CR17 SP2_SDD6_XDRE# 17 32 SP9_MSD0_XDD1
SP2 SP9
C SP3_SDD5_XDCE# 18 31 SP8_MSD4_XDD0 C
SP3 SP8
SP4_SDD4_XDWE# 19 30 SP7_MSD1_XDWP#
SP4 SP7
CR20
SD_D1_R 1 SHORT 2 SD_D1 20 29 SP6_MSD5_XDALE
RR20 0_0402_5%~D SD_D1 SP6
1 2
SD_D0_R 1 SHORT 2 SD_D0 21 28 SP5_MSBS_XDCLE
CR25 SD_D0 SP5
@ RR19 0_0402_5%~D 4.7U_0603_6.3V6K~D
1 2SD_CLK_R 1 2 SD_CLK 22 27 DV12_S 1 2
RR23 33_0402_1% SD_CLK DV12_S CR21
SD_CMD_R 1 SHORT 2 SD_CMD 23 26 0.1U_0402_10V7K~D
5P_0402_50V8C~D RR24 0_0402_5%~D SD_CMD GND
Reserved SD_D3_R 1 SHORT 2 SD_D3 24 25 SD_D2 1 SHORT 2 SD_D2_R
RR21 0_0402_5%~D SD_D3 SD_D2 RR12 0_0402_5%~D

RTS5209-GR_LQFP48_7X7
Item3_X02
Item3_X02

+ODR_PWR +ODR_PWR Reserve for EMI please close to JREAD1

JREAD CONN@ Co-lay connector for 2nd. 2010/11/26
22 11
XD-VCC SD4-VDD
18
SP8_MSD4_XDD0 MS9-VCC @ @ +ODR_PWR +ODR_PWR
30
SP9_MSD0_XDD1 XD10-D0 SD_CLK_R
29 9 1 RR8 2 2 1 CR14
SP10_MSD2_XDD2 XD11-D1 SD5-CLK SD_D0_R 33_0402_5%~D 22P_0402_50V8J~D JREAD1 CONN@
28 4
B
SP11_MSD6_XDD3 XD12-D2 SD7-DAT0 SD_D1_R B
27 3 24 12
SP12_MSD3_XDD4 XD13-D3 SD8-DAT1 SD_D2_R XD-VCC SD-VDD/MMC-VDD
26 21 19
SP13_MSD7_XDD5 XD14-D4 SD9-DAT2 SD_D3_R SP8_MSD4_XDD0 MS-VCC
25 19 32
SP14_MSCLK_XDD6_R XD15-D5 SD1-DAT3 SD_CMD_R SP9_MSD0_XDD1 XD-D0 SD_CLK_R
24 16 31 10
SP15_SDWP_XDD7 XD16-D6 SD2-CMD SD_CD# SP10_MSD2_XDD2 XD-D1 MMC-CLK/SD-CLK SD_D0_R
23 1 30 4
XD17-D7 SD-CD SP15_SDWP_XDD7 SP11_MSD6_XDD3 XD-D2 MMC-DAT/SD-DAT0 SD_D1_R
2 29 3
SP4_SDD4_XDWE# SD-WP SP12_MSD3_XDD4 XD-D3 SD-DAT1 SD_D2_R
33 28 22
XD07-WE XD-D4 SD-DAT2
SP7_MSD1_XDWP# 32 6 Reserve for EMI SP13_MSD7_XDD5 27 20 SD_D3_R
SP6_MSD5_XDALE XD08-WP SD6-VSS SP14_MSCLK_XDD6_R XD-D5 MMC-RSV/SD-DAT3 SD_CMD_R
34 13 please close to JREAD1 26 17
XD_CD# XD06-ALE SD3-VSS SP15_SDWP_XDD7 XD-D6 SD-CMD/MMC-CMD SD_CD#
39 25 1
SP1_SDD7_XDRDY XD01-CD XD-D7 SD-CD SP15_SDWP_XDD7
38 2
SP2_SDD6_XDRE# XD02-R/B @ SP4_SDD4_XDWE# SD-WP
37 35 5
SP3_SDD5_XDCE# XD03-RE SP14_MSCLK_XDD6_R 1 RR11 SP7_MSD1_XDWP# XD-WE SD-CD
36 17 2 34
SP5_MSBS_XDCLE XD04-CE MS8-SCLK SP9_MSD0_XDD1 33_0402_5%~D SP6_MSD5_XDALE XD-WP SP14_MSCLK_XDD6_R
35 10 36 18
XD05-CLE MS4-DATA0 SP7_MSD1_XDWP# XD_CD# XD-ALE MS-SCLK SP9_MSD0_XDD1
8 41 11
MS3-DATA1 SP10_MSD2_XDD2 SP1_SDD7_XDRDY XD-CD MS-SDIO/DATA0 SP7_MSD1_XDWP#
31 12 40 9
XD GND MS5-DATA2 SP12_MSD3_XDD4 SP2_SDD6_XDRE# XD-R/-B MS-DATA1 SP10_MSD2_XDD2
40 15 1 39 13
XD GND MS7-DATA3 MS_INS# SP3_SDD5_XDCE# XD-RE MS-DATA2 SP12_MSD3_XDD4
14 38 16
MS6-INS SP5_MSBS_XDCLE CR18 SP5_MSBS_XDCLE XD-CE MS-DATA3 MS_INS#
7 37 15
MS2-BS @ 22P_0402_50V8J~D XD-CLE MS-INS SP5_MSBS_XDCLE
5 8
MS1-VSS 2 MS-BS
41 20 6
SD CD/WP GND MS10-VSS MS-VSS
42 33 21
SD CD/WP GND XD-GND MS-VSS
42
T-SOL_144-1300002600_NR XD-GND
14
SD-VSS/MMC-VSS1
43 23
GND SD-VSS/MMC-VSS2
44 7
GND SD-VSS/MMC-VSS2

ALPS_SCDG4B0102_NR

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Card Reader RTS5209
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 40 of 63
5 4 3 2 1
 5 4 3 2 1

+3VS +3.3V_DVDD +3.3V_DVDD +3.3V_AVDD +3.3V_DVDD

1 SHORT 2
RA35 0_0805_5%~D RA37 1 SHORT 2 0_0402_5%~D
Item4_X03 RA36 1 SHORT 2 0_0402_5%~D 2 2 2 2 1
+1.2VS +3.3V_AVDD RA38 1 SHORT 2 0_0402_5%~D
CA1 CA2 CA3 CA4 CA5
+1.5VS 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 10U_0603_6.3V6M~D
+3VS UA1 +3.3V_DVDD 1 1 1 1 2
RA50 @ DVDD_HDAIO
Item4_X03
1 2 0_0402_5%~D 9 38
DVDD_1 AVDD
20 29
RA51 DVDD_2 PORTA_VDD +3.3V_AVDD +1.2VS
1 SHORT 2 0_0402_5%~D 48 34
+3.3V_DVDD DVDD_3 PORTD_VDD
15 10 +1.2VS
Item3_X02 Item3_X02 FBDC VDD_SW_1
11
VDD_SW_2

20 mil
RA39 1 SHORT 2 0_0603_5%~D 54 16 1 2 2 2 2 2
D +3.3V_DVDD DVDD_HDAIO DVDD_IO VDDQ_SW D
6
DVDD_HDAIO CA6 CA7 CA8 CA9 CA10 CA11
12 1 2
SWOUT LA1 4.7UH_CBC2012T4R7M_20%~D 10U_0603_6.3V6M~D
19 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D
@ VDDQ_PLL 2 1 1 1 1 1
2
CA30 2 1 10P_0402_50V8J~D 28 HP1_A_L
PORTA_L HP1_A_L (42)
5 26 HP1_A_R CA12
(14) HDA_BITCLK_AUDIO HDA_BCLK PORTA_R HP1_A_R (42)
(14) HDA_SDIN0 1 2 7 24 47U_0805_6.3V6M~D
RA40 33_0402_5%~D HDA_SDI PORTA_S 1 AGND
4 27
(14) HDA_SDOUT_AUDIO HDA_SDO PORTA_VCOM
3
(14) HDA_SYNC_AUDIO HDA_SYNC LINE_B_L
2 44 LINE_B_L (42)
(14) HDA_RST_AUDIO# HDA_RSTN PORTB_L LINE_B_R
43

SENSE A# 47
PORTB_R
45 MIC1_C_L CA13 1
LINE_B_R (42)
2 1U_0603_16V6K~D MIC1
PC BEEP
RA64 1 SENSE_A PORTC_L
2 10K_0402_1%~D 37 46
RA42 1 SENSE_B PORTC_R
AGND 2 20K_0402_1%~D 36
SENSE_I HP2_D_L
(42) MIC_BIAS_B 33
PORTD_L HP2_D_R
31
CA15 1 PORTD_R +3.3V_AVDD
AGND 2 2200P_0402_25V7K~D MIC_BIAS_B 42 35 C7
CA24 1 MIC_BIAS_C MIC_BIASB PORTD_S R4 PC_BEEP
AGND 2 100P_0402_50V8J~D 41 32 (47) BEEP# 1 2 1 2 PC_BEEP (42)
MIC_BIASC PORTD_VCOM

1
@

2 1 23 AMP_LEFT 1U_0402_6.3V6K~D 560_0402_5%

PORTG_L AMP_LEFT (42)
CA16 15P_0402_50V8J~D RA43 1 SHORT 2 0_0402_5%~D 55 22 AMP_RIGHT RA44
(33) DMIC_CLK DMIC_MCLK / MPIO1 PORTG_R AMP_RIGHT (42)
RA45 1 SHORT 2 0_0402_5%~D 51 @ 5.11K_0402_1%~D
(33) DMIC0 DMIC_DATA0 / MPIO3
56 C1870 @
SPDIF OUT0 / MPIO2 R5
50 (14) HDA_SPKR 1 2 1 2

2
SPDIF IN / MPIO4
Item3_X02 40
VREF_FILT

1
53 1 2 1U_0402_6.3V6K~D 560_0402_5%
PCBEEP / MPIO5
13
EC_EAPD# VSS_SW_1 CA17
(47) EC_EAPD# 1 SHORT 2 EAPD# 52 14 CA18 Item32_X01 R6 @
RA66 0_0402_5%~D EAPD / MPIO0 VSS_SW_2 100U_1206_6.3V6M 10K_0402_5%~D
17 0.1U_0402_25V6K~D
VSSQ_SW 2 1
1

2
DVSS_1
8 39
DVSS_2 AVSS
21 25
DVSS_3 PORTA_VSS
49 30
DVSS_4 PORTD_VSS
18
VSSQ_PLL AGND
57
Thermal PAD
C MALCOLM-EX_QFN56_7X7~D C

1 2 1 2 AGND
SENSE pin
RA53 0_0805_5%~D RA54 0_0805_5%~D
1 2 1 2
RA55 0_0805_5%~D RA56 0_0805_5%~D
1 2 1 2
RA57 0_0805_5%~D RA58 0_0805_5%~D Close to chip side

PJP407 @ PJP408 @
1 2 1 2 HP1_A_PLUG# 1 2 SENSE A#
1 2 1 2 (42) HP1_A_PLUG# RA46 39.2K_0402_1%
JUMP_43X79 JUMP_43X79 MIC_B_PLUG# 1 2
(42) MIC_B_PLUG# RA47 20K_0402_1%~D
Item6_X03 Item6_X03 MIC_C_PLUG# 1 2
RA48 10K_0402_1%~D
HP2_D_PLUG# 1 2
AGND AGND RA49 5.11K_0402_1%~D
GND GND

HeadPhone / Mic. combo JACK

B +3.3V_AVDD B

JHP4 CONN@
7
L_MIC1 3
HP2_D_L 1 + 2 HP2_D_L_R 1 SHORT 2 0_0603_5%~D HP2_D_L_C 1
HP2_D_PLUG# CA20 220U_B2_4VM_R35M LA2
+3.3V_AVDD
1

5
Item13_X02 Item3_X02
1

RA70 @ @ RA71
10K_0402_5%~D 10K_0402_5%~D QA1 D
AGND RA73 2 1 100K_0402_1%~D HP2_D_PLUG 6
2 1 SHORT 2 HP2_D_PLUG
2

0_0402_5%~D HP2_D_R HP2_D_R_R 1 SHORT 2 0_0603_5%~D HP2_D_R_C

+

G 1 2 2
2N7002K_SOT23-3 S RA63 CA21 220U_B2_4VM_R35M LA3 SLEEVE 4
1 Item4_X03 1 1
10U_0603_6.3V6M~D
3

CA22 CA23 SINGA_2SJ3061-005111F

RA68 1 SHORT 2 0_0402_5%~D HP_SCL @ 100P_0402_50V8J~D 100P_0402_50V8J~D
(15,22,23,43,46,47,53) EC_SMB_CK2

1
AGND
CA25

RA69 1 SHORT 2 0_0402_5%~D HP_SDA 2 RA60 RA61 2 2 +RTCVCC

2 SHORT

2 SHORT
(15,22,23,43,46,47,53) EC_SMB_DA2
0_0402_5%~D 0_0402_5%~D
Item3_X02 +3.3V_AVDD

1
Item15_X01 +3.3V_AVDD

2N7002DW-7-F_SOT363-6~D
AGND AGND RA74
1

3
UA3 Item15_X01 100K_0402_1%~D
QA2B

1
R2553 A1 +3VALW
+3.3V_AVDD 10K_0402_5%~D INL
5
A3 RA75
2

INR

2N7002DW-7-F_SOT363-6~D
DEPOP# B1 10K_0402_5%~D
(42,47) DEPOP#

4
/MUTE

2
6
B2 QA2A
VDD
1

CA28 2 1 B3
MIC_BIAS_C RA72 SET
Item3_X02 2

GND
0_0402_5%~D
@ UA2 0.01U_0402_16V7K~D
13 9 RA59 1 SHORT 2 0_0402_5%~DHP2_D_L_C
A Item3_X03 A

1
VDD TIP_SENSE
1

16 5 HP2_D_PLUG
2

A2

RA62 VDD DET_TRIGGER AGND MAX9892ERT+T_UCSP6~D

3.3K_0402_5% HP_SCL 1 14 Item8_X01
HP_SDA SCL RING2_SENSE L_MIC1
2
SDA RING2
7 Setting the Turn-Off Time: AGND AGND
1 SHORT 2 4 Ton (ms) = 0.02 x Cset (pF)
2

RA65 0_0402_5%~D ADDR_SEL AGND

15
MIC_C_PLUG# SLEEVE_SENSE SLEEVE
8 6
MIC1 MIC_PRESENT SLEEVE
11 17
MIC_P GND
1 SHORT 2 12 3
RA67 0_0402_5%~D MIC_N GND
10
Item3_X02
GND Security Classification Compal Secret Data Compal Electronics, Inc.
TS3A225ERTER_PWQFN16_3X3 2011/06/02 2012/06/02 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Codec Malcolm-EX
AGND AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
AGND 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 41 of 63
5 4 3 2 1
 5 4 3 2 1

Line Out/HeadPhone
JHP1
3

+5VAMP +5VAMP HP1_A_L 1 2 HP1_A_L_R L8 1 SHORT 2 0_0603_5%~D HP1_A_L_C

+
(41) HP1_A_L 1
+5VS +5VAMP CA26 220U_B2_4VM_R35M
Subwoofer support 3W HP1_A_R 1 2 HP1_A_R_R L9 1 SHORT 2 0_0603_5%~D HP1_A_R_C

+
(41) HP1_A_R 2
+5VAMP CA27 220U_B2_4VM_R35M 5
2

2
GAIN0 GAIN1 L1 1 2 Item3_X02
FBMA-L11_0805
W=40mil Item15_X01 (41) HP1_A_PLUG# 6

1
R23 R24 0 0 6dB UA4 Item15_X01
100K_0402_1%~D 100K_0402_1%~D L2 1 2 R2225 R2224
0 1 10dB

0.1U_0402_16V7K~D
@ FBMA-L11_0805 +3VALW A1 R2554 1 SHORT 2 0_0402_5%~D 100_0402_1%~D 100_0402_1%~D 4 SHLD1
2 1

2 1

4.7U_0603_6.3V6K~D
GAIN0 GAIN1 1 0 15.6dB INL @ @
1 1
A3 R2555 1 SHORT 2 0_0402_5%~D
1 1 21.6dB

2
D INR DEPOP# D
B1 DEPOP# (41,47) SINGA_2SJ2285-112252
R26 R27 /MUTE
2 2

C21

C27
100K_0402_1%~D 100K_0402_1%~D +3.3V_AVDD Item3_X02 CONN@
@ B2 AGND AGND
1

VDD CA29 2
B3 1
SET

GND
1
AGND AGND 0.01U_0402_16V7K~D
AGND R25
U3 10K_0402_5%~D Item3_X03

A2
MAX9892ERT+T_UCSP6~D AGND
16 12
W=20mil

2
VDD NC
6
PVDD Setting the Turn-Off Time:
15 Ton (ms) = 0.02 x Cset (pF)
PVDD SPK_MUTE# AGND
19 SPK_MUTE# (47)
SHUTDOWN
GAIN0 2
GAIN0 SPKL-
LOUT-
8 Close Q308
GAIN1 3 2
GAIN1 SPKR- CA32 0.1U_0402_16V7K~D
14
ROUT-
SPKL+
Mic. JACK
4
LOUT+

2
1

G
0.47U_0603_16V7K~D Item12_X03 AGND
1 2 AMP_LEFT_C-1 C29 1 2 AMP_LEFT_C 5 18 SPKR+ Q308
(41) AMP_LEFT LIN- ROUT+
C26 0.015U_0603_50V7K~D 3 1 1 2
(41) MIC_BIAS_B
AMP_RIGHT_C-1 C32 AMP_RIGHT_C R35 2.2K_0402_5%~D JHP3

D
(41) AMP_RIGHT 1 2 1 2 17
C28 0.015U_0603_50V7K~D RIN- AO3419L_SOT23-3
1 3
0.47U_0603_16V7K~D GND
9 11
LIN+ GND LINE_B_L LINE_B_L_R L10 1 SHORT
13 (41) LINE_B_L 1 2 2 0_0603_5%~D LINE_B_L_C 1
GND C1938 2.2U_0805_10V6K~D
7 20
RIN+ GND LINE_B_R LINE_B_R_R L11 1 SHORT
21 (41) LINE_B_R 1 2 2 0_0603_5%~D LINE_B_R_C 2
GND C2015 2.2U_0805_10V6K~D
1 1 5
10 Item3_X02
C30 BYPASS
1 (41) MIC_B_PLUG# 6
0.47U_0603_16V7K~D C31
1

3
2 2 0.47U_0603_16V7K~D TPA6017A2PWPR_TSSOP20 C41 Item17_X01

1
R28 R29 2.2U_0603_10V7K~D 4 SHLD1
ANPEC

PJDLC05C_SOT23-3
10K_0402_5%~D 10K_0402_5%~D 2 RA34 RA33
24.9K_0402_1%~D 24.9K_0402_1%~D D7
C
APA2031RI-TRG Item10_X03 UA5 @ @
C
Item7_X01 SINGA_2SJ2285-112252
2

Item1_X02 SA00001RZ10

2
AGND AGND +3VALW A1 RA76 1 2 0_0402_5%~D CONN@
AGND AGND INL
A3 RA77 1 2 0_0402_5%~D @

1
INR DEPOP#
B1 DEPOP# (41,47)
/MUTE AGND
Item3_X02 AGND AGND
B2
VDD CA31 2
B3 1
SET
Int. Speaker Connector

GND
0.01U_0402_16V7K~D

20mil Item3_X02

A2
MAX9892ERT+T_UCSP6~D AGND JSPK
SPKL+ R19 1 SHORT 2 0_0603_5%~D SPK_L+ 1
1
Setting the Turn-Off Time: SPKL- R21 1 SHORT 2 0_0603_5%~D SPK_L- 2
2
SPKR+ R20 1 SHORT 2 0_0603_5%~D SPK_R+ 3
AGND
Ton (ms) = 0.02 x Cset (pF) SPKR- R1848 SHORT 0_0603_5%~D SPK_R- 3
1 2 4
4
1 2 5
C1927 0.015U_0402_16V7K GND
1 C22 6
GND

2
@ 220P_0402_50V8J
R1981 1 2 12K_0402_5%~D MOLEX_53780-0470
D2 D4 C23 CONN@
2 @ 1 220P_0402_50V8J

PESD5V0U2BT_SOT23-3~D

PESD5V0U2BT_SOT23-3~D
+5VAMP
1 2
C1926 0.015U_0402_16V7K C24
2 @ 1 220P_0402_50V8J
R1980 1 2 12K_0402_5%~D 1 C25
4

C1931 0.033U_0603_25V7M~D @ @ @ @ 220P_0402_50V8J

1
+5VAMP AMP_RIGHT 1 2 1 2 5 C1933 @ 2
P

C1930 0.015U_0402_16V7K +
7 1 2 AMP_RIGHT_C
+5VAMP OUT 2
@ 6
-
G

1U_0603_16V6K~D
TLV2464_TSSOP14
For ESD
11
4

C1929 0.033U_0603_25V7M~D @ U634B

1

AMP_LEFT 1 2 1 2 3 C1932 @ 1 R1985 2

P

B + B
C1928 0.015U_0402_16V7K 1 1 2 AMP_LEFT_C R1987
OUT 4.7K_0603_1% 10K_0402_5%~D
@ 2
-
1
G

+5VAMP 1U_0603_16V6K~D @
TLV2464_TSSOP14 R1989 AGND 1 2
11

U634A 10K_0402_5%~D C1934 0.012U_0603_50V7K~D

1

1 R1984 2 @
R1986 AGND 1 2
2

4.7K_0603_1% 10K_0402_5%~D C1935 0.012U_0603_50V7K~D

1

+5VAMP
R1988 AGND AGND
W=20mil W=40mil
2

10K_0402_5%~D
1 1
2

AGND C1886 C1885

0.1U_0402_16V7K~D 4.7U_0603_10V6K~D
SPK_MUTE# 2 2
AGND either one option.
Item1_X02

6
U633
PC_BEEP 1 2 R32 1 2 0_0402_5%~D MONO_OUT 1 @ 2 1 2 AMP_LEFT_R 1 2 AMP_LEFT_RR 3 AGND

VDD
(41) PC_BEEP IN+
C920 0.47U_0603_16V7K~D R1990 1K_0603_1% C1889 R1879 3.48K_0603_1% JWFER2
0.47U_0603_16V7K~D 5 SUB_L+ 1
MONO_OUT 1 @ SUB_AMP AMP_RIGHT_R AMP_RIGHT_RR VO+ SUB_R- 1
R1993 2 1 2 1 2 1 2 4 2
R1992 0_0603_5%~D @ R1991 698_0402_1% C1888 R1861 3.48K_0603_1% IN- 2
SUB_AMP 1 @ 2 1 2 0.47U_0603_16V7K~D MOLEX_53261-0271~D

2
100K_0402_1%~D C1939 1U_0603_16V6K~D 1 8 CONN@
R2002 SHUTDOWN VO-
1 1

GND
GND
+5VAMP 20K_0402_1%~D @ 2
C1936 C1937 BYPASS
AMP_LEFT 2.2U_0402_6.3V6M~D 0.22U_0402_16V7K~D TPA6211A1DGNRG4_MSOP8
11

1 2 1

7
9
R1994 3.3K_0402_5% C1940 AGND @ TLV2464_TSSOP14 2 2
4

Item7_X01 1 2 9 @ R1996 @ 2 C1887

G

- @ @ 0.22U_0603_25V7K~D
8 1 2 1 2 12
P

AMP_RIGHT 1U_0603_16V6K~D OUT R1995 1K_0402_1%~D 1K_0402_1%~D + @ AMP_RIGHT_RR C1945 @ 2

1 2 10
+ OUT
14 1 2 1 2
ANPEC
P

R1997 3.3K_0402_5% 13 C1941 1U_0603_16V6K~D R1998 20K_0402_1%~D 1U_0603_16V6K~D

-
G

+5VAMP AGND AGND 1

2 APA0714XAI-TRG
4

U634C TLV2464_TSSOP14 AGND AGND

11

+5VAMP C1942 U634D

A
SA000059X00 A
1

1U_0603_16V6K~D @
R2000 1 AGND
10K_0402_1%~D @
AGND
1 2

R2001
10K_0402_1%~D @
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

AGND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Amp TPA6017/subwoofer/ Audio Jack
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 42 of 63
5 4 3 2 1
 A B C D E

Power share +5VALW

1 1
C263 +5V_CHGUSB
C262
2
10U_0603_6.3V6M~D
2
0.1U_0402_16V7K~D +5VALW 2.0A
U29
CB Function 1
GND OC1#
8 USB_OC2# (6,17)
2 7
IN OUT1
L auto detection charger identification active 3
EN1# OUT2
6
(47) PWRSHARE_EN_EC# 4 5
EN2# OC2#
H DP/DM=TDP/TDM
TPS2062ADR_SO8~D
1 1

+5VALW

1
UI5
PWRSHARE_OE# 8 1 R204
(47) PWRSHARE_OE# SB INT
7 2 SW_USB20_N3 10K_0402_1%~D
(17) USB20_N3 Y- D-
Item12_X01 6 3 SW_USB20_P3
(17) USB20_P3

2
Y+ D+ SEL +5VALW
5 4
VDD SEL
9
GND

1
close to JUSB1
+5VALW PI5USB1457AZAEX_TDFN8_2X2~D
Item34_X01 @ R203
10K_0402_1%~D D26 @
6 1
USB CONN

2
V I/O V I/O +5V_CHGUSB
2
C261 5 2
V BUS Ground 2.0A
0.1U_0402_16V7K~D 4 3
1 V I/O V I/O JUSB1

150U_B2_6.3VM_R35M
Item18_X01 IP4223CZ6_SO6~D 1 1

0.1U_0402_16V7K~D
USB20_P3_CONN GND
2 1
USB20_N3_CONN USB_P +
3
R262 1 @ +5V_CHGUSB USB_N
2 0_0402_5%~D 4 C303 C265
VCC
5
GND 2 2
6
WCM-2012-900T_4P GND
7
SW_USB20_P3 USB20_P3_CONN GND
4 3 8
4 3 GND
SUYIN_020173MR004S52KZL
SW_USB20_N3 1 2 USB20_N3_CONN CONN@
1 2
L40 L40 close to JUSB1

R222 1 @ 2 0_0402_5%~D
2 2

System Thermal Sensor 1 +5VS

Diode circuit s used for skin temp sensor Item4_X03

2
+3VS
(placed between CPU and VGA). R2018

1 SHORT
Place C1814 close to Q283 as possible. 0_0805_5%~D

0.1U_0402_10V7K~D
+3VS
1 C1923
SENSOR_DIODE_P1 R1796 1 SHORT 2 0_0402_5%~D REMOTE_P1 +5VS_FAN

C1816
2 1
U615
1
1

2
C C1815 2 1 8 EC_SMB_CK2
1

10K_0402_5%~D

10K_0402_5%~D
VDD SMCLK EC_SMB_CK2 (15,22,23,41,46,47,53) 2.2U_0402_6.3V6M~D

2
2 470P_0402_50V7K~D R1802
@ C1814 B 2 7 EC_SMB_DA2
100P_0402_50V8J~D E Q283
Item3_X02 2 DP SMDATA EC_SMB_DA2 (15,22,23,41,46,47,53) 10K_0402_5%~D

R1800

R1801
3

2 MMBT3904WT1G_SC70-3~D SENSOR_DIODE_N1 R1797 1 SHORT 2 0_0402_5%~D REMOTE_N1 3 6

1
DN ALERT JFAN1

1
+3VS 1 2 4 5 1
THERM#/ADDR GND SYSTEM_FAN_PWM 1
(47) SYSTEM_FAN_PWM 2
R1798 4.7K_0402_1%~D SYSTEM_FAN_FB 2
EMC1412-A-ACZL-TR_MSOP8 (47) SYSTEM_FAN_FB 2 1 3 5
D65 3 G5
4 6
CH751H-40PT_SOD323-2~D 4 G6
1 3 MOLEX_53398-0471
D

(54,60) MAINPWON
3 3
@ Q303 CONN@
2N7002KW_SOT323-3
G
2

+3VS

System Thermal Sensor 2

Diode circuit s used for skin temp sensor
(placed around DIMM). +3VS
0.1U_0402_10V7K~D

Place C1871 close to Q279 as possible.

1
SENSOR_DIODE_P2 R1851 1 SHORT 2 0_0402_5%~D REMOTE_P2
C1872

U627
1
1

C C1873 2 1 8 EC_SMB_CK2
1 VDD SMCLK
2 470P_0402_50V7K~D
@ C1871 B
Item3_X02 2 7 EC_SMB_DA2
100P_0402_50V8J~D E Q279 2 DP SMDATA
3

2 MMBT3904WT1G_SC70-3~D SENSOR_DIODE_N2 R1853 1 SHORT 2 0_0402_5%~D REMOTE_N2 3 6

DN ALERT

+3VS 1 2 4 5
THERM#/ADDR GND
R1856 6.8K_0402_1%~D EMC1412-A-ACZL-TR_MSOP8

MAINPWON 1 3
D

4 @ Q304 4
2N7002KW_SOT323-3
G
2

+3VS

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB conn.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 43 of 63
A B C D E
 5 4 3 2 1

+USB3_VCCB
Item18_X01 +5VALW
R137 1 @ 2 0_0402_5%~D +USB3_VCCB

WCM-2012-900T_4P
CI74 UI4 2.0A W=80mils
0.1U_0402_16V7K~D 1 8
USB20_N0 USB20_N0- GND OC1# RI47 JUSB2 CONN@
(17) USB20_N0 4 3 1 2 2 7
4 3 IN OUT1 10K_0402_5%~D USB3TP0_D+
3 6 9
EN1# OUT2 SSTX+
(47) USB_PWR_EN# 4 5 1 2 USB_OC0# USB_OC0# (6,17) 1
USB20_P0 USB20_P0+ EN2# OC2# USB3TN0_D- VBUS
(17) USB20_P0 1 2 8
1 2 TPS2062ADR_SO8~D USB20_P0+ SSTX-
3
L16 D+
7
R138 1 @ GND
2 0_0402_5%~D USB20_N0- 2 10 USBGND1
USB3RP0_D+ D- GND
6 11
SSRX+ GND
4 12
D
USB3RN0_D- GND GND D
5 13
SSRX- GND
R136 1 2 0_0402_5%~D SUYIN_020053GR009M2106L

L19
USB3RN0 1 2 USB3RN0_D- +USB3_VCCB
(17) USB3RN0 1 2
@
Item18_X01 RI49 1 2 0_0603_5%~D
USB3RP0 4 3 USB3RP0_D+
(17) USB3RP0 4 3 +USB3_VCCB RI50 1 2 0_0603_5%~D
DLW21SN900SQ2_0805~D For ESD request 1
R133 1 2 0_0402_5%~D DI2 1 CI77 1 2 0.1U_0402_16V7K~D
USB3TP0_D+ 1 8 CI28 + CI29
USB3TN0_D- R- VCC 150U_B2_6.3VM_R35M 10U_0603_6.3V6M~D
2 7
USB20_N0- 3
R+ GND
6 USB3RN0_D- For ESD request
USB20_P0+ T- D- USB3RP0_D+ 2 2
4 5
R134 1 T+ D+
2 0_0402_5%~D
LXES4XBAA6-027_MSOP8
DLW21SN900HQ2L_0805_4P~D
USB3TN0 1 2 USB3T_N0 1 2 USB3TN0_D-
(17) USB3TN0 1 2
C107 0.1U_0402_10V7K~D
@
USB3TP0 1 2 USB3T_P0 4 3 USB3TP0_D+
(17) USB3TP0 4 3
C106 0.1U_0402_10V7K~D
L12
For EMI request
R135 1 2 0_0402_5%~D

C C

+USB3_VCCA
Item18_X01 JUSB3 CONN@
For EMI request +5VALW +USB3_VCCA USB3TP1_D+ 9
R131 1 @ SSTX+
2 0_0402_5%~D
WCM-2012-900T_4P
CI73 UI3 2.0A W=80mils USB3TN1_D-
1
8
VBUS
SSTX-
0.1U_0402_16V7K~D 1 8 USB20_P1+ 3
USB20_N1 USB20_N1- GND OC1# RI42 D+
(17) USB20_N1 4 3 1 2 2 7 7
4 3 IN OUT1 10K_0402_5%~D USB20_N1- GND USBGND2
3 6 2 10
USB_PWR_EN# EN1# OUT2 D- GND
4 5 1 2 USB_OC1# USB_OC1# (6,17)
USB3RP1_D+ 6 11
USB20_P1 USB20_P1+ EN2# OC2# SSRX+ GND
(17) USB20_P1 1 2 4 12
1 2 TPS2062ADR_SO8~D USB3RN1_D- GND GND
5 13
L17 SSRX- GND
R132 1 @ 2 0_0402_5%~D SUYIN_020053GR009M2106L

+USB3_VCCA

RI51 1 2 0_0603_5%~D
R130 1 2 0_0402_5%~D
RI52 1 2 0_0603_5%~D
L15 1
USB3RN1 1 2 USB3RN1_D- +USB3_VCCA CI78 1 2 0.1U_0402_16V7K~D
(17) USB3RN1 1 2 For ESD request CI30 +
1
CI31
@ DI1 150U_B2_6.3VM_R35M 10U_0603_6.3V6M~D
USB3RP1 4 3 USB3RP1_D+ USB3TP1_D+ 1 8
(17) USB3RP1 4 3 R- VCC 2 2
USB3TN1_D- 2 7
DLW21SN900SQ2_0805~D USB20_N1- 3
R+ GND
6 USB3RN1_D- For ESD request
R127 1 USB20_P1+ T- D- USB3RP1_D+
2 0_0402_5%~D 4 5
T+ D+
LXES4XBAA6-027_MSOP8

B B
R128 1 2 0_0402_5%~D
DLW21SN900HQ2L_0805_4P~D
USB3TN1 1 2 USB3T_N1 1 2 USB3TN1_D-
(17) USB3TN1 1 2
C105 0.1U_0402_10V7K~D
@
USB3TP1 1 2 USB3T_P1 4 3 USB3TP1_D+
(17) USB3TP1 4 3
C104 0.1U_0402_10V7K~D
L13
R129 1 2 0_0402_5%~D

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB conn.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 44 of 63
5 4 3 2 1
 A B C D E F G H

X76 BOM option table

PERICOM (PI3EQX6741): +3VS
US2 = SA00004H100
RS322 = SD02800008L (0 ohm)
Other = NC* +3VS +5VS_HDD2 0.1U_0402_16V7K~D

RS61 0_0402_5%~D
1K_0402_5%~D

1K_0402_5%~D

0_0402_5%~D
1

0.1U_0402_16V7K~D
PARADE (PS8520B): 1 1 1 1 1

1K_0402_5%~D

1K_0402_5%~D

1K_0402_5%~D
CS19 CS20 CS21 CS22
US2 = SA00004WF00

2 HDD@ 1
CS23

CS27

2 HDD@ 1
RS23 = SD02800008L (0 ohm) 2 0.1U_0402_16V7K~D 10U_0603_6.3V6M~D

1
@ @ 2 2 2 2 2
RS55 = SD02800008L (0 ohm)
1 RS61 = SD02800008L (0 ohm) 1000P_0402_50V7K~D 1U_0402_6.3V6K~D
1

RS311

RS312
2

2
Other = NC* US2 HDD@ @ @ @

RS322

RS314

RS315

RS316
6 10

2
NC VDD RS323 1 @
16 20 2 0_0402_5%~D
NC VDD
TI (SN75LVCP601RTJR):
RS55 1 HDD@ 2 0_0402_5%~D 3 13 RS23 1 HDD@ 2 0_0402_5%~D
US2 = SA00003ZX0L RS18 1 @ 2 0_0402_5%~D 17
TDet_B# TDet_A#
19 RS19 1 @ 2 0_0402_5%~D
RS23 = SD02800008L (0 ohm) RS20 1 @ A_EQ B_EQ
2 0_0402_5%~D 9 8 RS21 1 @ 2 0_0402_5%~D
A_EM B_EM RS24
RS24 = SD02800008L (0 ohm) 7 18 1 HDD@ 2 0_0402_5%~D
EN TDeT_EN JHDD
RS55 = SD02800008L (0 ohm) (14) SATA_PTX_DRX_P0_C SATA_PTX_DRX_P0_C 1 15 SATA_PTX_DRX_P0_RC CS30 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P0_RC1 1
AI+ AO+ 1
RS322 = SD02800008L (0 ohm) (14) SATA_PTX_DRX_N0_C SATA_PTX_DRX_N0_C 2
AI- AO-
14 SATA_PTX_DRX_N0_RC CS32 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N0_RC1 SATA_PTX_DRX_P0_RC1 2
2
SATA_PTX_DRX_N0_RC1 3
Other = NC* SATA_PRX_DTX_N0 CS33 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N0_C 4 12 SATA_PRX_DTX_N0_RC 0.01U_0402_16V7K~D 4
3
(14) SATA_PRX_DTX_N0 BO- BI- 4
SATA_PRX_DTX_P0 CS35 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_P0_C 5 11 SATA_PRX_DTX_P0_RC SATA_PRX_DTX_N0_RC 1 2 CS26 SATA_PRX_DTX_N0_RC1 5
(14) SATA_PRX_DTX_P0 BO+ BI+ 5
SATA_PRX_DTX_P0_RC 1 2 SATA_PRX_DTX_P0_RC1 6
CS28 6
21 7
GND 0.01U_0402_16V7K~D 7
8
RS17 SHORT +3VS_VCC3.3 8
+3VS 1 2 9
0_0805_5%~D 9
10
PI3EQX6741STZDEX_TQFN20_4X4 10
11
HDD_DETECT# 11
12
(18) HDD_DETECT# 12
Item9_X03 13
13
14
Free Fall Sensor +5VS RS22 1 SHORT 2 +5VS_HDD2
0_0805_5%~D
15
16
14
15
16
17 21
+3VS +5VS FFS_INT2_CONN 17 GND1
18 22
+3VS 18 GND2
19 23
19 GND3
20 24
20 GND4

1
FFS_INT1 connect to PCH GPIO & EC FOX_GS12201-1011-9F
0.1U_0402_16V7K~D

1
@ R159 CONN@
discuss with BIOS to use which pin
10U_0603_6.3V6M~D

1 1 100K_0402_5%~D
R2559

2
100K_0402_5%~D
2 U19 FFS_INT2_CONN 2

3
2 2
C189

C190

LNG3DM
1
VDD_IO
RES
RES
10
13 By Pass circuit
14 15 5
VDD RES Q23B
16
FFS_INT1 RES DMN66D0LDW-7_SOT363-6~D
(17) FFS_INT1 11

4
INT 1

6
FFS_INT2 9 5
(18) FFS_INT2 INT 2 GND
12 Item28_X01
GND
7
SDO/SA0 FFS_INT2 2
(6,12,13,15,38) PCH_SMBDATA 6
SDA / SDI / SDO Q23A
(6,12,13,15,38) PCH_SMBCLK 4
SCL/SPC DMN66D0LDW-7_SOT363-6~D
2

1
NC
8 3
CS NC
LNG3DMTR_LGA16_3X3~D

+3VS

MAXIM main TI 2nd

+3VS
0.01U_0402_16V7K~D

0.1U_0402_16V7K~D

+5VS_ODD Placea caps. near ODD CONN. P/N SA00003LH1L SA00003ZX0L

1 1
@ @
CS47

CS48

+5VS_ODD 0.1U_0402_16V7K~D
RS43 RS44 pop depop
1

2
2 2

0_0402_5%~D

0_0402_5%~D

0_0402_5%~D

0_0402_5%~D
@ @ 1 1 1 1

RS45

RS46
RS324 CS37 CS38 CS39
RS43

RS44
0_0402_5%~D @ @ CS40
@ 10U_0603_6.3V6M~D
US3 @ 2 2 2 2 RS47 RS48 depop pop
2

1
7 6 HDD_DEW2
RS325 1 @ EN VCC
2 0_0402_5%~D 18 10 1000P_0402_50V7K~D 1U_0402_6.3V6K~D
3 CAD VCC HDD_DEW1 3
SATA_PTX_DRX_P2_RP 1
VCC
16
20
RS53 RS54 pop depop
(14) SATA_PTX_DRX_P2_RP AINP VCC
(14) SATA_PTX_DRX_N2_RP SATA_PTX_DRX_N2_RP 2
AINM HDD_PE1
9
CS49 @1 0.01U_0402_16V7K~D SATA_PRX_DTX_N2_RP 4 PA HDD_PE2
(14) SATA_PRX_DTX_N2 2 8
CS50 @ 0.01U_0402_16V7K~D
@1 SATA_PRX_DTX_P2_RP 5 BOUTM PB
(14) SATA_PRX_DTX_P2 2
BOUTP SATA_PTX_DRX_P2_P
15
AOUTP SATA_PTX_DRX_N2_P
3 14
GND AOUTM
10K_0402_5%~D

10K_0402_5%~D

+3VS 13 Item4_X03 Item4_X03

GND
1

1
0_0402_5%~D

0_0402_5%~D

HDD_EQ1 17 11 SATA_PRX_DTX_P2_P @ @ @ @
GND BINP
RS47

RS48

RS49

RS50

19 12 SATA_PRX_DTX_N2_P SATA_PTX_DRX_P2_RP RS35 2 SHORT 1 0_0402_5%~D SATA_PTX_DRX_P2_B RS36 2 SHORT 1 0_0402_5%~D SATA_PTX_DRX_P2_C
GND BINM SATA_PTX_DRX_N2_RP SATA_PTX_DRX_N2_B RS38
HDD_EQ2 21 RS37 2 SHORT 1 0_0402_5%~D 2 SHORT 1 0_0402_5%~D SATA_PTX_DRX_N2_C
EP
10K_0402_5%~D

10K_0402_5%~D
1

@ @ MAX4951BECTP+TGH7_TQFN20_4X4~D SATA_PRX_DTX_N2 RS39 2 SHORT 1 0_0402_5%~D SATA_PRX_DTX_N2_B RS40 2 SHORT 1 0_0402_5%~D SATA_PRX_DTX_N2_P
2

SATA_PRX_DTX_P2 RS41 2 SHORT 1 0_0402_5%~D SATA_PRX_DTX_P2_B RS42 2 SHORT 1 0_0402_5%~D SATA_PRX_DTX_P2_P

RS51

RS52
2

SATA ODD Conn.

1

1
0_0402_5%~D

0_0402_5%~D

JODD1
QS1
RS53

RS54

@ @ +5VS
FDC655BN_NL_SSOT6~D +5VS_ODD @ 27 28
SATA_PTX_DRX_P2_P 27 28
Item5_X03 CS51 2 1 0.01U_0402_16V7K~D SATA_PTX_DRX_P2_C 25 26
2

25 26
D

6 Item16_X03 SATA_PTX_DRX_N2_P CS52 2 @ 1 0.01U_0402_16V7K~D SATA_PTX_DRX_N2_C 23 24

S

23 24
1 5 4 21 22
CS41 RS326 SATA_PRX_DTX_N2_P CS44 1 21 22
2 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N2_C 19 20
SATA_PRX_DTX_P2_P 19 20
1 1 2 CS45 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_P2_C 17 18
1U_0402_6.3V6K~D 0_0402_5%~D 17 18
15 16
G

B+_BIAS 2 15 16
13 14
3

RS28 1 SHORT ODD_DETECT#_R 13 14

(18) ODD_DETECT# 2 0_0402_5%~D 11 12
11 12
Item4_X03 +5VS_ODD 9 10
9 10
7 8
7 8
2

ODD_DA#_R ODD_DA# 1 3 @ ODD_DA#_C 1 SHORT 2 0_0402_5%~D ODD_DA#_R 5 6

D

(17) ODD_DA# 5 6
4 RS26 RS29 3 4 4
2N7002KW_SOT323-3 QS4 3 4
470K_0402_5% 1 2
1 2
G
2

E-T_6900-Q14N-00R
1
1

D ODD_EN CONN@
2 QS3 ODD_EN# Item3_X01
(47) ODD_EJECT
1

G 2N7002KW_SOT323-3 D
1
1.5M_0402_5%~D

0.1U_0402_25V6K~D
1

Item2_X01 S ODD_EN# 2 QS2

(18) ODD_EN#
3

G 2N7002KW_SOT323-3 RS27 CS46

RS60 S
3

10K_0402_5%~D 2
Security Classification Compal Secret Data Compal Electronics, Inc.
1
2

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FFS /HDD/ ODD Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 45 of 63
A B C D E F G H
 A B C D E

KSI[0..7]

ON/OFF switch Power Button KSO[0..16]

KSI[0..7] (47)
CONN@
+3VALW_EC
INT_KBD Conn. KSO[0..16] (47)

TYCO_3-2041084-0

2
KB_DET# 30 32
(47) KB_DET# 30 GND
R263 KSO10
KB detect pin KSO11
29
28
29 GND
31

100K_0402_5%~D KSO9 28
TOP Side 27
KSO14 27
26

1
SW6 D27 KSO13 26
25
SMT1-05-A_4P KSO16 C1918 1 100P_0402_50V8J~D KB_DET# C434 1 100P_0402_50V8J~D KSO15 25
2 ON/OFF (47) 2 2 24
ON/OFFBTN# KSO16 24
1 3 1 23
KSO15 C306 1 100P_0402_50V8J~D KSO7 C310 1 100P_0402_50V8J~D KSO12 23
3 51ON# (52) 2 2 22
22

3
2 4 1 Item23_X01 KSO0 21
1
D28 DAN202UT106_SC70-3 KSO14 C304 1 100P_0402_50V8J~D KSO6 C305 1 100P_0402_50V8J~D KSO2 21 1
2 2 20
C326 6251VDD KSO1 20
19
6
5

0.1U_0402_25V6K~D PESD24VS2UT_SOT23-3~D KSO13 C312 1 100P_0402_50V8J~D KSO5 C307 1 100P_0402_50V8J~D KSO3 19

2 2 18
2 51ON# KSO8 18
17
KSO12 C308 1 100P_0402_50V8J~D KSO4 C309 1 100P_0402_50V8J~D KSO6 17
2 2 16

1
16

1
KSO7 15
R2630 CA@ KSO4 15
14
KSI0 C328 1 100P_0402_50V8J~D KSO3 C311 1 100P_0402_50V8J~D KSO5 14
100K_0402_5%~D 2 2 13
KSI0 13
ON/OFFBTN# (49) 12
12

6
D Q310A KSO11 C327 1 100P_0402_50V8J~D KSI4 C313 1 100P_0402_50V8J~D KSI3
Bottom Side 2 2 11

2
KSI1 11
2 10
SW5 CA@ G CA@ KSO10 C314 1 100P_0402_50V8J~D KSO2 C315 1 100P_0402_50V8J~D KSI5 10
2 2 9
9

3
SMT1-05-A_4P Q310B D KSI2 8
KSI1 C316 1 100P_0402_50V8J~D KSO1 C317 1 100P_0402_50V8J~D KSI4 8
1 3 Item13_X02 (47,60) BATT_TEMP 5 S 2 2 7

1
7

1
D G DMN66D0LDW-7_SOT363-6~D KSI6 6
EC_ON Q24 KSI7 6
2 4 (47,54) EC_ON 2 5
G KSI2 C318 1 100P_0402_50V8J~D KSO0 C319 1 100P_0402_50V8J~D 5
S 2 2 4

4
4

2
S 2N7002K_SOT23-3 DMN66D0LDW-7_SOT363-6~D 3
6
5

3
R264 KSO9 C320 1 100P_0402_50V8J~D KSI5 C321 1 100P_0402_50V8J~D 3
2 2 2
2
1
10K_0402_5%~D KSI3 C322 1 100P_0402_50V8J~D KSI6 C323 1 100P_0402_50V8J~D 1
2 2

1
D
JKB
1

2 Q311 KSO8 C324 1 2 100P_0402_50V8J~D KSI7 C325 1 2 100P_0402_50V8J~D

(22,47,48,53) ACIN
G
Test Only S

3
2N7002E-T1-E3_SOT23-3 CA@

FD1 FD2 FD3 FD4

VPK +3VS
U626 VPK@
2 2
@ @ @ @ 11 9 KSO13_VPK
1

AVCC1 A8/VeREF+/P5.0 KSO14_VPK

10
A9/VeREF-/P5.1 XTAL25_IN_VPK

VPK@

VPK@

VPK@

VPK@
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 15 57

10U_0603_6.3V6M~D
0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D
DVCC1 XT2IN/P5.2 XTAL25_OUT_VPK RH139
1 1 1 1 40 58 2 VPK@ 1
VPK@ DVCC2 XT2OUT/P5.3 KSO15_VPK 1M_0402_5%~D
12
XIN/P5.4 VPK_KB_DET#
C2014 2 1 0.47U_0603_16V7K~D 17 13 1 VPK@ 2 KB_DET#
H63 H64 H60 H61 VCORE XOUT/P5.5 R2550 0_0402_5%~D 24MHZ_12PF_7V24000020
H_1P9N H_3P9x1P9N H_3P3 H_3P3 CLIP1 2 2 2 2 C2013 1 0.22U_0402_16V7K~D VPK_A0

C2011

C2010

C2012

CD73
2 55 1
EMI_CLIP CONN@ V18 CB0/A0/P6.0 VPK_A1
2 1 3
CONN@ JKBBL2 +5VS_KB VPK@ KSI0_VPK CB1/A1/P6.1 VPK_A2 1 3
18 3
@ @ @ @ +5VS_KB KSI1_VPK P1.0/TA0CLK/ACLK CB2/A2/P6.2 VPK_A3 GND GND
1 1 19 4 1 1
1

GND 1 KSI2_VPK P1.1/TA0.0 CB3/A3/P6.3 VPK_A4 YH3

2 20 5

15P_0402_50V8J~D

15P_0402_50V8J~D
2 KB_LED_B4_DRV#_A# KSI3_VPK P1.2/TA0.1 CB4/A4/P6.4 VPK_A5 CH104 2 VPK@ 4 CH105
3 21 6
H39 H40 H58 H59 3 KB_LED_G4_DRV#_A# KSI4_VPK P1.3/TA0.2 CB5/A5/P6.5 VPK_A6 VPK@ VPK@
4 22 7
H_3P3 H_3P3 H_3P3 H_3P3 4 KB_LED_R4_DRV#_A# KSI5_VPK P1.4/TA0.3 CB6/A6/P6.6 VPK_A7 2 2
5 23 8
5 KB_LED_B3_DRV#_A# KSI6_VPK P1.5/TA0.4 CB7/A7/P6.7
6 24
CLIP2 6 KB_LED_G3_DRV#_A# KSI7_VPK P1.6/TA1CLK/CBOUT @ T66 PAD~D
7 25 60
@ @ @ @ EMI_CLIP CONN@ 7 KB_LED_R3_DRV#_A# P1.7/TA1.0 TDO/PJ.0 @ T67 PAD~D
8 61
1

8 KB_LED_B2_DRV#_A# KSO0_VPK TDI/TCLK/PJ.1 @ T68 PAD~D

9 26 62
9 KB_LED_G2_DRV#_A# KSO1_VPK P2.0/TA1.1 TMS/PJ.2 @ T69 PAD~D
1 10 27 63
GND 10 KB_LED_R2_DRV#_A# KSO2_VPK P2.1/TA1.2 TCK/PJ.3
11 28
11 KB_LED_B1_DRV#_A# KSO3_VPK P2.2/TA2CLK/SMCLK USB20_N13_C R2561 1 VPK@ 2 0_0402_5%~D USB20_N13
12 29 50 USB20_N13 (17)
H32 H33 H34 H35 12 KB_LED_G1_DRV#_A# KSO4_VPK P2.3/TA2.0 DP/PU.0 USB20_P13_C R2562 1 VPK@ 2 0_0402_5%~D USB20_P13
13 Item4_X03 30 52 USB20_P13 (17)
H_3P8 H_3P8 H_3P8 H_3P8 13 KB_LED_R1_DRV#_A# KSO5_VPK P2.4/TA2.1 DM/PU.1 PUR RV10 1 VPK@ 2 100_0402_5%~D
14 31 51 +3VS
14 KSO6_VPK P2.5/TA2.2 PUR
15 32
CLIP3 15 VPK_G R2560 KSO7_VPK P2.6/RTCCLK/DMAE0
16 2 SHORT 1 0_0603_5%~D 33 64 R227 2 VPK@ 1 47K_0402_5%~D +3VS
@ @ @ @ EMI_CLIP CONN@ 16 VPK_A1 P2.7/UCB0STE/UCA0CLK RST#/NMI/SBWTDIO VPK@
T55 PAD~D
17 59
1

17 VPK_A0 KSO8_VPK TEST/SBWTCK

18 34
18 VPK_A3 KSO9_VPK P3.0/UCB0SIMO/UCB0SDA R1578 1 VPK@
1 19 35 53 2 0_0603_5%~D +5VS
GND 19 VPK_A2 KSO10_VPK P3.1/UCB0SOMI/UCB0SCL VBUS R1574 1 VPK@
20 36 54 2 0_0603_5%~D +3VS
H36 H37 H38 20 KSO11_VPK P3.2/UCB0CLK/UCA0STE VUSB
21 37
H_3P8 H_3P8 H_3P8 21 VPK_A7 KSO12_VPK P3.3/UCA0TXD/UCA0SIMO
22 38
22 VPK_A5 P3.4/UCA0RXD/UCA0SOMI

VPK@

VPK@

VPK@
23

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D
23 VPK_A4 VPK_SPI_CLK
24 41 1 1 1

1U_0805_10V7
@ @ @ 24 P4.0/PM_UCB1STE/PM_UCA1CLK
25 (15,22,23,41,43,47,53) EC_SMB_DA2 42 49
1

25 VPK_A6 P4.1/PM_UCB1SIMO/PM_USB1SDA VSSU

26 (15,22,23,41,43,47,53) EC_SMB_CK2 43
26 VPK_SPI_CS# P4.2/PM_UCB1SOMI/PM_UCB1SCL
27 44 16
3 GND VPK_SPI_SI P4.3/PM_UCB1CLK/PM_UCA1STE DVSS1 2 2 2 3

C289

C1731

C1734
28 45 39
2 3.3K_0402_5%
2 3.3K_0402_5%

2 3.3K_0402_5%
2 3.3K_0402_5%

2 3.3K_0402_5%
2 3.3K_0402_5%

2 3.3K_0402_5%
2 3.3K_0402_5%

ZZZ1 GND VPK_SPI_SO P4.4/PM_UCA1TXD/PM_UCA1SIMO DVSS2

46
H42 H43 H51 H45 H47 +3VS PAD~D T56 @ P4.5/PM_UCA1RXD/PM_UCA1SOMI
47 14
H_2P7 H_2P7 H_2P7 H_2P7 H_2P7 TYCO_2-2041070-6~D PAD~D T57 @ P4.6/PM_NONE AVSS1
48 56
P4.7/PM_NONE AVSS2
65
R2551 2 VPK@ GND_PAD
1 0_0603_5%~D
@ @ @ @ @ MSP430F5508IRGCR_VQFN64_9X9
1

PCB-MB
Analog Keys
1

@R2552
1VPK@
1VPK@

1VPK@
1VPK@

1VPK@
1VPK@

1VPK@
1VPK@

H46 H48 H49 H50 H44 H41

Item13_X01 Item13_X01
0_0603_5%~D
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 USB20_N13_C R2563 1 @ 2 0_0402_5%~D PUR
2

KSI0 R2575 VPK@ 2 0_0402_5%~D KSI0_VPK KSO4 R2576 VPK@ 2 0_0402_5%~D KSO4_VPK
R1820
R1821

R1822
R1823

R1824
R1825

R1826
R1827

1 1
@ @ @ @ @ @ KSI1 R2577 1 VPK@ 2 0_0402_5%~D KSI1_VPK KSO5 R2578 1 VPK@ 2 0_0402_5%~D KSO5_VPK
1

KSI2 R2579 1 VPK@ 2 0_0402_5%~D KSI2_VPK KSO6 R2580 1 VPK@ 2 0_0402_5%~D KSO6_VPK
KSI3 R2581 1 VPK@ 2 0_0402_5%~D KSI3_VPK KSO7 R2582 1 VPK@ 2 0_0402_5%~D KSO7_VPK

+3VALW

1Mb SPI ROM

0.1U_0402_10V7K~D
KSI4 R2583 1 VPK@ 2 0_0402_5%~D KSI4_VPK KSO8 R2584 1 VPK@ 2 0_0402_5%~D KSO8_VPK
KSI5 R2585 1 VPK@ 2 0_0402_5%~D KSI5_VPK KSO9 R2586 1 VPK@ 2 0_0402_5%~D KSO9_VPK
K/B Backlight CONN ( co-lay VPK ) KSI6
KSI7
R2587
R2589
1
1
VPK@ 2
VPK@ 2
0_0402_5%~D
0_0402_5%~D
KSI6_VPK
KSI7_VPK
KSO10
KSO11
R2588
R2590
1
1
VPK@ 2
VPK@ 2
0_0402_5%~D
0_0402_5%~D
KSO10_VPK
KSO11_VPK @
1
+5VS

C302
JKBBL1 U38 @ 2
1 +5VS_KB 2 1 F3 VPK_SPI_CS# 1 8
1 0.5A_13.2V_NANOSMDC050F-13.2-2 VPK_SPI_SO CS# VCC
2 2 7
2 KB_LED_B4_DRV#_A# KSO0 R2591 VPK@ 2 0_0402_5%~D KSO0_VPK KSO12 R2592 VPK@ 2 0_0402_5%~D KSO12_VPK SO HOLD# VPK_SPI_CLK
3 KB_LED_B4_DRV#_A# (50) 1 1 3 6
3 KB_LED_G4_DRV#_A# KSO1 R2593 VPK@ 2 0_0402_5%~D KSO1_VPK KSO13 R2594 VPK@ 2 0_0402_5%~D KSO13_VPK WP# SCLK VPK_SPI_SI
4 KB_LED_G4_DRV#_A# (50) 1 1 4 5
4 KB_LED_R4_DRV#_A# KSO2 R2595 VPK@ 2 0_0402_5%~D KSO2_VPK KSO14 R2596 VPK@ 2 0_0402_5%~D KSO14_VPK GND SI
5 KB_LED_R4_DRV#_A# (50) 1 1
5 KB_LED_B3_DRV#_A# KSO3 R2597 VPK@ 2 0_0402_5%~D KSO3_VPK KSO15 R2598 VPK@ 2 0_0402_5%~D KSO15_VPK MX25L1006EMI-10G SOP 8P
6 KB_LED_B3_DRV#_A# (50) 1 1
6 KB_LED_G3_DRV#_A#
7 KB_LED_G3_DRV#_A# (50)
7 KB_LED_R3_DRV#_A#
8 KB_LED_R3_DRV#_A# (50)
8 KB_LED_B2_DRV#_A#
4 9 KB_LED_B2_DRV#_A# (50)
4
9 KB_LED_G2_DRV#_A#
10
10
11 KB_LED_R2_DRV#_A#
KB_LED_G2_DRV#_A#
KB_LED_R2_DRV#_A#
(50)
(50)
8/17 @ C2131 @ R2533
11 KB_LED_B1_DRV#_A# VPK_SPI_CLK
12
12
13 KB_LED_G1_DRV#_A#
KB_LED_B1_DRV#_A# (50) 1, Analog keys connector and F/P temporary use. 2 1 1 2
13 KB_LED_G1_DRV#_A# (50)
14
14
15
KB_LED_R1_DRV#_A#
KB_LED_R1_DRV#_A# (50) 2, check pin assignment. 22P_0402_50V8J~D
Reserve for EMI please close to U48
33_0402_5%~D
15
16
16 VPK_G 3, check VPK K/B layout.
17
GND
18
GND Security Classification Compal Secret Data Compal Electronics, Inc.
TYCO_1-2041070-6~D 2011/06/02 2012/06/02 Title
Issued Date Deciphered Date
CONN@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWRBTN/SCREWH/KB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 46 of 63
A B C D E
 5 4 3 2 1

check GPIO table with BIOS team

+3VALW_EC
+3VALW_EC +3VALW L43
FBMA-L1_0603 KSI[0..7]
KSI[0..7] (46)
1 @ 2 0.1U_0402_16V7K~D 0.1U_0402_16V7K~D +3VALW_EC 1 2 +EC_VCCA
R216 1 1 1 1 2 2 KSO[0..16]
KSO[0..16] (46)
0_0805_5%~D C277 C276 C278 C279 C280 C281 1
+3VLP
1 2 KSO1 1000P_0402_50V7K~D C282 Board ID
R231 47K_0402_5%~D 2 2 2 2 1 1 +3VALW_EC
1 2 KSO2 1 SHORT 2 0.1U_0402_16V7K~D 0.1U_0402_16V7K~D 1000P_0402_50V7K~D 2 0.1U_0402_16V7K~D

ECAGND
R232 47K_0402_5%~D R2558 0_0402_5%~D

2
10/1 ENE Recommand
Item4_X03 R219
D D
Ra 100K_0402_5%~D

111
125
22
33
96

67
U34

9
1 @ 2 EC_SMI#

1
R239 1K_0402_1%~D AD_BID0

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
1 @ 2 SPK_MUTE#

2
R241 10K_0402_5%~D Item5_X01 1
1 2 EC_ESB_CLK R225 C283
R242 4.7K_0402_5%~D GATEA20 1 21 Rb
(18) GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F
1 2 EC_ESB_DAT (18) KB_RST#
KB_RST# 2 23 BEEP#
BEEP# (41)
100K_0402_5%~D
R243 4.7K_0402_5%~D SERIRQ KBRST#/GPIO01 BEEP#/PWM2/GPIO10 SYSTEM_FAN_PWM 2
3 26 SYSTEM_FAN_PWM (43)

1
(14) SERIRQ SERIRQ# FANPWM1/GPIO12
1 2 LID_SW_IN# (14) LPC_FRAME#
LPC_FRAME# 4 27 ACOFF
ACOFF (52,53)
0.1U_0402_16V7K~D
R1952 10K_0402_5%~D C284 LPC_AD3 LFRAME# ACOFF/FANPWM2/GPIO13 ECAGND
(14) LPC_AD3 5 2 1
@ LAD3
1 2 PCIE_WAKE#_R @ 22P_0402_50V8J~D
(14) LPC_AD2
LPC_AD2 7 PWM Output C286 100P_0402_50V8J~D
R2019 10K_0402_5%~D R226 2 LPC_AD1 LAD2 BATT_TEMP
2 1 1 @ 33_0402_5%~D(14) LPC_AD1 8 63 BATT_TEMP (46,60) Analog Board ID definition,
LAD1 BATT_TEMP/AD0/GPIO38
2 EC_SMB_CK1 LPC_AD0
LAD0 LPC & MISC
1 (14) LPC_AD0 10 64
R229 2.2K_0402_5%~D BATT_OVP/AD1/GPIO39 ADP_I Please see page 4.
65 ADP_I (52,53)
ADP_I/AD2/GPIO3A
1 2 EC_SMB_DA1 (17) CLK_PCI_LPC
CLK_PCI_LPC 12 AD Input 66 AD_BID0
R230 2.2K_0402_5%~D PLT_RST# PCICLK AD3/GPIO3B +3VS +5VS
(6,7,17,38,39,40) PLT_RST# 13 75
PCIRST#/GPIO05 AD4/GPIO42
1 2 KB_DET# +3VALW_EC R221 2 1 47K_0402_5%~D EC_RST# 37 76 Item11_X01
R2574 100K_0402_5%~D EC_SCI# ECRST# SELIO2#/AD5/GPIO43
(18) EC_SCI# 20
C285 0.1U_0402_16V7K~D EN_CAM SCI#/GPIO0E TP_CLK @
Item8_X02 2 1 (33) EN_CAM 38 2 1 2 1
CLKRUN#/GPIO1D GPU_DC# R2626 4.7K_0402_5%~D 4.7K_0402_5%~D R223
68 GPU_DC# (22)
DAC_BRIG/DA0/GPIO3C AC_SEL TP_DATA @
70 AC_SEL (52) 2 1 2 1
EN_DFAN1/DA1/GPIO3D IREF R2627 4.7K_0402_5%~D 4.7K_0402_5%~D R224
Item13_X01 Item13_X01 DA Output IREF/DA2/GPIO3E
71 IREF (53)
KSI0_EC 55 72 CHGVADJ
KSI0/GPIO30 DA3/GPIO3F CHGVADJ (53)
KSI0 R2599 1 SHORT 2 0_0402_5%~D KSI0_EC KSO4 R2600 1 SHORT 2 0_0402_5%~D KSO4_EC KSI1_EC 56
KSI1/GPIO31 X1
KSI1 R2601 1 SHORT 2 0_0402_5%~D KSI1_EC KSO5 R2602 1 SHORT 2 0_0402_5%~D KSO5_EC KSI2_EC 57 Item3_X02 SPK_MUTE#
KSI2 R2603 SHORT 0_0402_5%~D KSI2_EC KSO6 R2604 SHORT 0_0402_5%~D KSO6_EC KSI3_EC KSI2/GPIO32 EC_MUTE# R228 2 SHORT 1 0_0402_5%~D EC_CRY1 EC_CRY2
1 2 1 2 58 83 SPK_MUTE# (42) 1 2
KSI3 R2605 SHORT 0_0402_5%~D KSI3_EC KSO7 R2606 SHORT 0_0402_5%~D KSO7_EC KSI4_EC KSI3/GPIO33 PSCLK1/GPIO4A PWRSHARE_EN_EC# @
1 2 1 2 59 84 PWRSHARE_EN_EC# (43)
KSI5_EC KSI4/GPIO34 PSDAT1/GPIO4B AC_PRESENT
60 85 AC_PRESENT (16) 1 1
KSI6_EC KSI5/GPIO35 PSCLK2/GPIO4C H_PROCHOT#_EC @ C287 32.768KHZ_12.5PF_9H03200019 C288 @
61
KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D
86
Item3_X02 KSI7_EC 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK (49)
KSO0_EC 39 88 TP_DATA 27P_0402_50V8J~D 27P_0402_50V8J~D
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA (49) 2 2
KSI4 R2607 1 SHORT 2 0_0402_5%~D KSI4_EC KSO8 R2608 1 SHORT 2 0_0402_5%~D KSO8_EC KSO1_EC 40
KSI5 R2609 SHORT 0_0402_5%~D KSI5_EC KSO9 R2610 SHORT 0_0402_5%~D KSO9_EC KSO2_EC KSO1/GPIO21
1 2 1 2 41
KSI6 R2611 SHORT 0_0402_5%~D KSI6_EC KSO10 R2612 SHORT 0_0402_5%~D KSO10_EC KSO3_EC KSO2/GPIO22 ODD_EJECT
1 2 1 2 42 97 ODD_EJECT (45) Item2_X01
KSI7 R2613 SHORT 0_0402_5%~D KSI7_EC KSO11 R2614 SHORT 0_0402_5%~D KSO11_EC KSO4_EC KSO3/GPIO23 SDICS#/GPXOA00 EN_WOL#
1 2 1 2 43 98 EN_WOL# (39)
KSO5_EC KSO4/GPIO24 SDICLK/GPXOA01 HDA_SDO
KSO5/GPIO25 Int. K/B
C 44 99 HDA_SDO (14)
C
KSO6_EC SDIDO/GPXOA02 LID_SW_IN#
45 109
KSO7_EC KSO6/GPIO26 Matrix SDIDI/GPXID0 LID_SW_IN# (15,48,49)
46
KSO7/GPIO27 SPI Device Interface
KSO8_EC 47
KSO0 R2615 1 SHORT KSO0_EC KSO12 R2616 KSO12_EC KSO9_EC KSO8/GPIO28 FRD#
2 0_0402_5%~D 1 SHORT 2 0_0402_5%~D 48 119
KSO1 R2617 1 SHORT KSO9/GPIO29 SPIDI/RD#
2 0_0402_5%~D KSO1_EC KSO13 R2618 1 SHORT 2 0_0402_5%~D KSO13_EC KSO10_EC 49 120 R234 1 2 33_0402_5%~D FWR#
KSO2 R2619 1 SHORT KSO2_EC KSO14 R2620 KSO14_EC KSO11_EC KSO10/GPIO2A SPIDO/WR# R_SPI_CLK
2 0_0402_5%~D 1 SHORT 2 0_0402_5%~D 50 SPI Flash ROM 126 R236 1 2 33_0402_5%~D SPI_CLK
KSO3 R2621 1 SHORT KSO11/GPIO2B SPICLK/GPIO58
2 0_0402_5%~D KSO3_EC KSO15 R2622 1 SHORT 2 0_0402_5%~D KSO15_EC KSO12_EC 51 128 R237 1 2 33_0402_5%~DFSEL#
KSO13_EC KSO12/GPIO2C SPICS#
52
KSO14_EC KSO13/GPIO2D
53
KSO15_EC KSO14/GPIO2E PCH_VREG_EN#
54 73 PCH_VREG_EN# (20)
KSO16 KSO15/GPIO2F CIR_RX/GPIO40
1 SHORT 2 KSO16_EC KSO16_EC 81 74 EC_PECI 1 2 H_PECI (7,18)
R2557 0_0402_5%~D DEPOP# KSO16/GPIO48 CIR_RLC_TX/GPIO41 FSTCHG R240 43_0402_1%
(41,42) DEPOP# 82 89 FSTCHG (53)
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 BATT_CHG_LED#
90 BATT_CHG_LED# (48)
BATT_CHGI_LED#/GPIO52 CAPS_LED# Please place R240 close
91 CAPS_LED# (49)
EC_SMB_CK1 CAPS_LED#/GPIO53 BATT_LOW_LED# to EC with in 750mil
(60) EC_SMB_CK1 77
SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54
92 BATT_LOW_LED# (48)
EC_SMB_DA1 78 93 EN_INVPWR
(60) EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 EN_INVPWR (33)
EC_SMB_CK2 79 SM Bus 95 SYSON
(15,22,23,41,43,46,53) EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON (32,55)
EC_SMB_DA2 80 121 VR_ON CH100
(15,22,23,41,43,46,53) EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON (59)
127 ACIN R_SPI_CLK 2 1
AC_IN/GPIO59 ACIN (22,46,48,53)
Item3_X02 2 1 @
+3VS C550 100P_0402_50V8J~D 10P_0402_50V8J~D
Item2_X03 R249 1 SHORT
(16,48) PM_SLP_S3# 2 0_0402_5%~D PM_SLP_S3#_R 6 100 PCH_RSMRST#
PCH_RSMRST# (16)
CH101
BKOFF# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03
1 @ 2 (16,48) PM_SLP_S5#
R250 1 SHORT 2 0_0402_5%~D PM_SLP_S5#_R 14 101 EC_LID_OUT#
EC_LID_OUT# (15)
EC_ESB_CLK_R 2 1
R217 10K_0402_5%~D EC_SMI# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_ON @
(18) EC_SMI# 15 102 EC_ON (46,54)
@ EC_SMI#/GPIO08 EC_ON/GPXO05
1 2 EC_SCI# (52) PS_ID
PS_ID 16 103 10P_0402_50V8J~D
EC_ESB_CLK R252 1 SHORT LID_SW#/GPIO0A EC test PSID EC_SWI#/GPXO06
R218 10K_0402_5%~D 2 0_0402_5%~D EC_ESB_CLK_R 17 104 PCH_PWROK
PCH_PWROK (7,16)
SUSP#/GPIO0B ICH_PWROK/GPXO06
1 2 M_THERMAL# EC_ESB_DAT 18 GPO 105 BKOFF#
BKOFF# (33)
R1943 10K_0402_5%~D SUSPWRDNACK PBTN_OUT#/GPIO0C BKOFF#/GPXO08 CPU1.5V_S3_GATE
(16) SUSPWRDNACK 19
EC_PME#/GPIO0D GPIO WL_OFF#/GPXO09
106 CPU1.5V_S3_GATE (32)
1 2 EC_SMB_CK2 (33) EC_INV_PWM 25 107 PCH_APWROK
PCH_APWROK (16) Reserve for RF please close to U34
R244 2.2K_0402_5%~D SYSTEM_FAN_FB EC_THERM#/GPIO11 GPXO10 +VCCSA_PWRGD
(43) SYSTEM_FAN_FB 28 108 +VCCSA_PWRGD (57)
FAN_SPEED1/FANFB1/GPIO14 GPXO11
1 2 EC_SMB_DA2 (32) PCH_PWR_EN
PCH_PWR_EN 29
R247 2.2K_0402_5%~D EC_TX FANFB2/GPIO15
(38) EC_TX 30
EC_RX EC_TX/GPIO16 PM_SLP_S4#
(38) EC_RX 31 110 PM_SLP_S4# (16)
ON/OFF EC_RX/GPIO17 PM_SLP_S4#/GPXID1 IGPU_BKLT_EN
Item6_X01 32 112 IGPU_BKLT_EN (16)
(46) ON/OFF KB_DET# ON_OFF/GPIO18 ENBKL/GPXID2 EC_EAPD#
(46) KB_DET# 34 114 EC_EAPD# (41)
USB_PWR_EN# PWR_LED#/GPIO19 GPXID3 M_THERMAL#
Item8_X02 Item6_X01 (44) USB_PWR_EN# 36
NUMLED#/GPIO1A GPI GPXID4
115
116 SUSP#
B GPXID5 SUSP# (19,32,55,56) B
117 PBTN_OUT#
GPXID6 PBTN_OUT# (6,16)
Item3_X02 118 PCIE_WAKE#_R 1 SHORT 2
GPXID7 PCIE_WAKE# (16,38,39)
EC_CRY1 122 R1944 0_0402_5%~D
EC_CRY2 XCLK1 +V18R
(16) SUSCLK_R 1 SHORT 2 123 124 Item3_X02
XCLK0 V18R

4.7U_0603_6.3V6K~D
R253 0_0402_5%~D 1
AGND
GND
GND
GND
GND
GND
2

+3VS
1
R1979 U620
C1947 KB930QF A1 LQFP 128P 2 EC_ESB_CLK

C293
(52,59) VR_HOT# 1 13
11
24
35
94
113

69

100K_0402_5%~D 20P_0402_50V8J~D ESB_CLK TEST_EN#

2 20mil L44
1 (53) CP_SEL 2 14 EC_ENVDD (33)
1

ECAGND 2 GPIO00 GPIO08/CAS_DAT

1
2

C1943 FBMA-L1_0603 RST# 3 15

R265 0.1U_0402_16V7K~D <BOM Structure> RST# GPIO09
Item3_X02
1 SHORT

2 EC_ESB_DAT 4 16
0_0402_5%~D ESB_DAT GPIO0A
5 17 PWRSHARE_OE#
GPIO01 GPIO0B PWRSHARE_OE# (43)
5

U635
6 18
P

(53) EMC_ALERT# GPIO02 GPIO0C/PWM0 WLES ON/OFF LED# (49)

(7) H_PROCHOT# H_PROCHOT# 4 2 H_PROCHOT#_EC
Y A
NC

7 19
GPIO03 GPIO0D/PWM1
G

SN74LVC1G06DCKR_SC70-5 Dyn_Turbo_Sel 8 20
(52) Dyn_Turbo_Sel
1

R1999 GPIO04 GPIO0E/PWM2

1
C1944 100K_0402_5%~D 9 21
(7) DRAMRST_CNTRL_EC GPIO05 GPIO0F/PWM3 EN_TPLED# (49)
47P_0402_50V8J~D
10 22 LCD_TEST (33)
1

2 GPIO06 GPIO10/ESB_RUN#

(16,33) PCH_ENVDD 11 23 3V_F347_ON (48)

+3VALW_EC GPIO07/CAS_CLK GPIO11/BaseAddOpt
near POWER item 60 mil
12 24

GND
GND VCC +3VALW_EC
1

0.1U_0402_16V7K~D
R248 1
47K_0402_5%~D KC3810_QFN24_4X4 C294

25
SPI ROM 128KB
2

RST# 2
A 2 A

+3VALW_EC C292
U36 0.1U_0402_16V7K~D
20mils 8 4 1
VCC VSS @ @
1
C297 3 R257 C296
0.1U_0402_16V7K~D W SPI_CLK_R 2 1 1 2
7 33_0402_5%~D 22P_0402_50V8J~D
2 HOLD
FSEL# 1 SHORT 2 SPI_FSEL# 1 Reserve for EMI please close to U36
R258 0_0402_5%~D S Security Classification Compal Secret Data Compal Electronics, Inc.
SPI_CLK 1 SHORT 2 SPI_CLK_R 6 2011/06/02 2012/06/02 Title
C Issued Date Deciphered Date
R259 0_0402_5%~D SP07000F500 S SOCKET WIESON G6179-100000 EC ENE-KB930/ ENE3810
FWR# 1 SHORT 2 SPI_FWR# 5 SPI_SO 2 1 SHORT 2 FRD#
R260 0_0402_5%~D D Q R261 0_0402_5%~D 8P SPIFLASH THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
MX25L1006EMI-10G SOP 8P WIESO_G6179-100000_8P 1.0
Item3_X02 Item3_X02 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 47 of 63
5 4 3 2 1
 5 4 3 2 1

+3.3V_F347 +3.3V_F347

R1569 1 SHORT 2 0_0603_5%~D +3.3V_F347_VDD

C1705
1 1
C1706
Item3_X02 C1707
1 2

1
C1708
1U_0805_10V7 0.1U_0402_16V7K~D 0.1U_0402_16V7K~D 22P_0402_50V8J~D R1570 R1571
2 2 2 1 4.7K_0402_1%~D 4.7K_0402_1%~D

2
U602
6 2 SPI_MOCLK
VDD P0.0 SPI_MOSO
1
R1572 USB20_P6 P0.1 SPI_MOSI
(17) USB20_P6 4 32
@ 0_0603_5%~D USB20_N6 D+ P0.2 SPI_MOCS#
(17) USB20_N6 5 31
D D- P0.3 I2C_DAT +3.3V_F347
D
+5VALW 1 2 30 I2C_DAT (49,50)
P0.4 I2C_CLK
W=40mils +3.3V_F347 7
REGIN P0.5
29 I2C_CLK (49,50)
+5VS 1 SHORT 2 +5VALW_VBUS 8 28 C1710 @ 1 2 0.1U_0402_16V7K~D
VBUS P0.6 R1576 2
27 1
R1575 P0.7
+3.3V_F347 1 2 9
0_0603_5%~D RST#/C2CK SLP_S3 1K_0402_5%~D
Item3_X02 10 26
R1577 P3.0/C2D P1.0 CHRG_STATE
1 1 25
C1711 C1712 1K_0402_1%~D P1.1 ACIN#
18 24
P2.0 P1.2 LID_SW_IN#
17 23 LID_SW_IN# (15,47,49)
1U_0805_10V7 0.1U_0402_16V7K~D P2.1 P1.3 BATT_LOW_LED
16 22
2 2 P2.2 P1.4 SLP_S5
15 21
P2.3 P1.5 C1713 @ 1 0.1U_0402_16V7K~D
14 20 2
P2.4 P1.6 C1714 @ 1 0.1U_0402_16V7K~D
13 19 2
P2.5 P1.7
12
P2.6
11 3
P2.7 GND
C8051F347-GQ_LQFP32_7X7

0.1U_0402_16V7K~D
C1715

0.1U_0402_16V7K~D
C1716

0.1U_0402_16V7K~D
C1717

0.1U_0402_16V7K~D
C1718
1 1 1 1
+3.3V_F347
@ @ @ @
JP1 2 2 2 2
1
1
2
2
5 3
G1 3

0.1U_0402_16V7K~D
C1719

0.1U_0402_16V7K~D
C1720

0.1U_0402_16V7K~D
C1721

0.1U_0402_16V7K~D
C1722
6 4 1 1 1 1 +3.3V_F347 +3.3V_F347 +3.3V_F347
G2 4
MOLEX_53398-0471~D

1
CONN@ @ @ @ @ 1
2 2 2 2 R1580 C1723

1
10K_0402_5%~D
R1581 R1582 0.1U_0402_16V7K~D
10K_0402_5%~D 10K_0402_5%~D 2

2
U604
SPI_MOCS# 1 8

2
CE# VDD R1583 1 15_0402_5% SPI_MOCLK
3 6 2
WP# SCK R1584 1 15_0402_5% SPI_MOSI
C 7 5 2 C
HOLD# SI R1585 1 15_0402_5% SPI_MOSO
4 2 2
VSS SO
1
EN25F80-75HCP_SOP8
C1724
22P_0402_50V8J~D
+3.3V_F347 2
+3.3V_F347
1

1
R1586
100K_0402_1%~D
R1587
100K_0402_1%~D
2

SLP_S3
2

SLP_S5
1

D
+3.3V_F347 behavior
1

Q210 D
(16,47) PM_SLP_S3# 2
G 2N7002K_SOT23-3 2 Q211
(16,47) PM_SLP_S5#
G 2N7002K_SOT23-3 +3VALW +3.3V_F347
S STATE
3

Item13_X02 S @
3

Item13_X02 J11
2
2 1
1 S0 S3 S4 S5 DEVICE SMBUS ADDRESS
+3.3V_F347 JUMP_43X118
+3.3V_F347
MAXIM - LED 0100 000b
Q212 AC IN ON ON ON ON
MAXIM - GPIO 0100 001b
1

FDC655BN_NL_SSOT6~D
1

BAT only ON ON OFF OFF I2C EEPROM 1010 000b

D
R1588 6

S
100K_0402_1%~D R1664 5 4
100K_0402_1%~D 2 AC mode battery full in S5:turn off ELC controller
2

ACIN# 1 1
2

1
BATT_LOW_LED C1725
G
1

D 4.7U_0603_6.3V6K~D R1589
1
3
1

Q213 D 100K_0402_1%~D
(22,46,47,53) ACIN 2
G 2N7002K_SOT23-3 2 Q249 C1726 2
(47) BATT_LOW_LED#
S G 2N7002K_SOT23-3 0.1U_0402_25V6K~D
3

2
B 2 B
Item13_X02 S +3VALW B+_BIAS
3

Item13_X02 R1591
100K_0402_1%~D
1

1 2

R1590
1

+3.3V_F347 100K_0402_1%~D D

1
2 Q214

1M_0402_5%~D
1
2

G 2N7002K_SOT23-3 C1727
1

S Item13_X02
3
1

D R1951 0.1U_0402_25V6K~D
R1592 2 Q215 2
(47) 3V_F347_ON
2

100K_0402_1%~D G 2N7002K_SOT23-3
1

S Item13_X02
2

CHRG_STATE R1593
100K_0402_1%~D
1

D
2 Q216
(47) BATT_CHG_LED#
2

G 2N7002K_SOT23-3
S
3

Item13_X02

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ELC (1)/STATUS CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 48 of 63
5 4 3 2 1
 5 4 3 2 1

Touchpad LED CONN Indicator CONN

+5VS_TP_LED
(50) 7313_INT#
+3.3V_F347
+3.3V_F347 +5VS
C603
L/R Headlight, Logo +5VS
R1595
1 0.1U_0402_16V7K~D
1 2 C1728 C605
0.1U_0402_16V7K~D JTPMB 1
close to JTPMB 7/26 0.1U_0402_16V7K~D 1 C1729
4.7K_0402_1%~D U605 1
1
2 2 0.1U_0402_16V7K~D
R1594 7313_INT# 2
22 21 3
D
4.7K_0402_1%~D INT#/O16 V+ TP_CLK 3 2 D
+3VALW 4
I2C_CLK LSPK_LED_R_DRV# TP_DATA TP_POWER 4 JCAP
(48,50) I2C_CLK 19 1 5
I2C_DAT SCL P0 LSPK_LED_G_DRV# TP_DATA 5
(48,50) I2C_DAT 20 2 (47) TP_DATA 6 1
2

SDA P1 LSPK_LED_B_DRV# TP_CLK 6 LED_R_7313#_1 1

3 (47) TP_CLK 7 2
P2 7 2

2
AD0_0 18 4 RSPK_LED_R_DRV# LID_SW_IN# 8 LED_B_7313#_1 3
AD0_1 AD0 P3 RSPK_LED_G_DRV# TP_LED_R_DRV# 8 LED_G_7313#_1 3
23 5 9 4
AD0_2 AD1 P4 RSPK_LED_B_DRV# D70 TP_LED_G_DRV# 9 CAPS_LED_A# 4
24 6 10 5
AD2 P5 10 5
1

7 TP_LED_B_DRV# 11 WLAN_BT_LED_A# 6
P6 11 6
1

TP_LED_R_DRV# PESD5V0U2BT_SOT23-3~D LSPK_LED_R_DRV#

R1596 R1597 TP_LED_G_DRV#
14
15
P12 P7
8
10
5/18 delete LSPK_LED_G_DRV#
12
13
12
7
8
GND
4.7K_0402_1%~D 4.7K_0402_1%~D TP_LED_B_DRV# P13 P8 LOGO_LED_R_DRV# LSPK_LED_B_DRV# 13 GND
16 11 14
P14 P9 LOGO_LED_G_DRV# RSPK_LED_R_DRV# 14 TYCO_2041183-6
17 12 15
2

P15 P10 LOGO_LED_B_DRV# RSPK_LED_G_DRV# 15 CONN@

13 16
2

1
P11 RSPK_LED_B_DRV# 16
9 25 17
GND GND 17
18
MAX7313ATG+T_TQFN24_4X4 18
19
19
20
20
+3VS +5VS 21
GND1
Item11_X01 22
+3.3V_F347 GND2 +5VS
HRS_FH28E-20S-0.5SH(11)
2 1 TP_POWER 1 @ 2 LOGO_LED_R_DRV_1#

1
+3.3V_F347 R2628 0_0402_5%~D R2629 0_0402_5%~D CONN@ +5VS R1969
CAP, Media, Eyes, Rim 1

3
C1733 4.7K_0402_1%~D
0.1U_0402_16V7K~D

2
U608
1

2 R1970 LOGO_LED_R_DRV 5
4.7K_0402_1%~D

4.7K_0402_1%~D

4.7K_0402_1%~D
1

7313_INT# 22 21 4.7K_0402_1%~D Q298B

INT#/O16 V+

6
2N7002DW-7-F_SOT363-6~D

4
R1598 R1599 R1600 I2C_CLK 19 1

2
I2C_DAT SCL P0 +5VS
20 2
2

SDA P1 LOGO_LED_R_DRV# Q298A

3 2
2

P2

1
AD2_0 18 4 LED_R_7313#_1 2N7002DW-7-F_SOT363-6~D
AD2_1 AD0 P3 LED_G_7313#_1
23 5

1
AD2_2 AD1 P4 LED_B_7313#_1 +5VS R1975
24 6
AD2 P5 100K_0402_5%~D
C 7 C
P6
1

HDD_R_7313# 14 8

2
P12 P7

1
R1601 HDD_G_7313# 15 10 WLAN_BT_LED_A#
4.7K_0402_1%~D HDD_B_7313# P13 P8 PWR_R_7313# R1976
16 11
P14 P9

3
17 12 PWR_G_7313# 100K_0402_5%~D
P15 P10 PWR_B_7313# +5VS
13
2

P11
9 25

2
GND GND WLAN_BT_LED 5 LOGO_LED_G_DRV_1#

1
MAX7313ATG+T_TQFN24_4X4 Q301B +5VS

6
2N7002DW-7-F_SOT363-6~D R1971

3
4.7K_0402_1%~D
HDD_B

1
+5VALW 2 Q301A
(47) WLES ON/OFF LED#

2
2N7002DW-7-F_SOT363-6~D R1972 LOGO_LED_G_DRV 5
4.7K_0402_1%~D Q299B
check with EC Item13_X02

1
1

6
D 2N7002DW-7-F_SOT363-6~D

4
1
2 Q233

2
G 2N7002K_SOT23-3 R1603
S 100K_0402_5%~D LOGO_LED_G_DRV# 2 Q299A
3

+5VS 2N7002DW-7-F_SOT363-6~D
HDD_B_7313# +5VS

1
LID_SW
1

1
HDD_R D
R1602 LID_SW_IN# 2 Q232 +5VS R1977
(15,47,48) LID_SW_IN#
100K_0402_5%~D G 2N7002K_SOT23-3
S 100K_0402_5%~D
D Item13_X02
3
1

Item13_X02
2

2
1
SATA_LED_ACT 2 Q234 CAPS_LED_A# +5VS
G 2N7002K_SOT23-3 R1978
1

3
D LOGO_LED_B_DRV_1#
S
3

1
PCH_SATALED# 2 Q235 100K_0402_5%~D
(14) PCH_SATALED# +5VS
G 2N7002K_SOT23-3 HDD_R_7313# SATA_LED_ACT R1973

3
S CAPS_LED 5 4.7K_0402_1%~D
3

Item13_X02 Q302B

1
HDD_G 2N7002DW-7-F_SOT363-6~D

2
1

D R1974 LOGO_LED_B_DRV 5
LID_SW 2 Q224 4.7K_0402_1%~D Q300B

6
B B
Item13_X02 G 2N7002K_SOT23-3 CAPS_LED# 2 Q302A 2N7002DW-7-F_SOT363-6~D
(47) CAPS_LED#

4
1

D
S Item13_X02 2N7002DW-7-F_SOT363-6~D
3

2
2 Q225

1
G 2N7002K_SOT23-3 LOGO_LED_B_DRV# 2 Q300A
S 2N7002DW-7-F_SOT363-6~D
3

1
HDD_G_7313#

Q45
Reference AD2 AD1 AD0 MAX7313 +5VS FDC655BN_NL_SSOT6~D +5VS_TP_LED

PWR BTN Board CONN

D

6
LOGO Board CONN
S

B+_BIAS 5 4
U605 0 1 0 L/R Headlight , Logo, TP 2
1
1 1
2

C1746
G

R173 0.1U_0402_16V7K~D C184 +5VS

3

470K_0402_5% 1U_0402_6.3V6K~D
2 2
Num, CAP , SCR +5VS
1
1

EN_TPLED C1732
EJECT, REV, PLAY/PAUSE 0.1U_0402_16V7K~D JBTN
1

D
FFWD, Vol_DWN, Vol_UP R1654
1
2 JLOGO ON/OFFBTN#
1
1
(47) EN_TPLED# 2 20mil (46) ON/OFFBTN# 2
2
2M_0402_5%~D C185 HDD_R
Wireless ON/OFF G
Q44 0.1U_0402_25V6K~D LID_SW
1
1 HDD_G
3
3
U608 0 1 1 S 2 4
3

2N7002KW_SOT323-3 2 LOGO_LED_R_DRV_1# 2 HDD_B 4

AWCC Button 3 5
2

LOGO_LED_G_DRV_1# 3 5
4 +5VALW 6
LOGO_LED_B_DRV_1# 4 LID_SW 6
Alien Adrenaline 5
6
5 PWR_R_7313#
7
8
7
6 PWR_G_7313# 8
Power Button Eyes 7
8
GND PWR_B_7313#
9
10
9
GND 10
Power Button Rim Touchpad LED circuit TYCO_0-1775737-6
11
12
11
CONN@ 12
A 13 A
G1
14
G2

FCI_10089708-012010-LF

CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ELC (2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 49 of 63
5 4 3 2 1
 5 4 3 2 1

K/B Backlight
+3.3V_F347
(49) 7313_INT#

AD2 AD1 AD0

1
R1605 R1606
0 0 1 +3.3V_F347
4.7K_0402_1%~D 4.7K_0402_1%~D

2
U609
22 21
D INT#/O16 V+ D
I2C_CLK 19 1 KB_LED_R1_DRV#
(48,49) I2C_CLK SCL P0
I2C_DAT 20 2 KB_LED_G1_DRV#
(48,49) I2C_DAT SDA P1
3 KB_LED_B1_DRV#
AD3_0 P2 KB_LED_R2_DRV#
18 4
AD3_1 AD0 P3 KB_LED_G2_DRV#
23 5
AD3_2 AD1 P4 KB_LED_B2_DRV#
24 6
AD2 P5 KB_LED_R3_DRV# +3VS
7
P6
1

14 8 KB_LED_G3_DRV#
R1608 R1609 P12 P7 KB_LED_B3_DRV# KB_LED_G1_DRV#_A#
15 10 KB_LED_G1_DRV#_A# (46)
P13 P8

1
4.7K_0402_1%~D 4.7K_0402_1%~D 16 11 KB_LED_R4_DRV# +3VS
P14 P9 KB_LED_G4_DRV# R1618
17 12
P15 P10

6
13 KB_LED_B4_DRV# 4.7K_0402_1%~D
2

P11
9 25
GND GND

1
Q271A

2
MAX7313ATG+T_TQFN24_4X4 R1619 KB_LED_G1_DRV 2 DMN66D0LDW-7_SOT363-6~D +3VS
4.7K_0402_1%~D

3
KB_LED_B1_DRV#_A#
KB_LED_B1_DRV#_A# (46)

1
2
Q271B +3VS R1624

6
KB_LED_G1_DRV# 5 DMN66D0LDW-7_SOT363-6~D 4.7K_0402_1%~D

1
Q273A

2
R1625 KB_LED_B1_DRV 2 DMN66D0LDW-7_SOT363-6~D
4.7K_0402_1%~D

1
+3VS

2
Q273B
KB_LED_R1_DRV#_A# KB_LED_B1_DRV# 5 DMN66D0LDW-7_SOT363-6~D
KB_LED_R1_DRV#_A# (46)
1

+3VS R1612

4
6

4.7K_0402_1%~D
1

Q277A
2

R1613 KB_LED_R1_DRV 2 DMN66D0LDW-7_SOT363-6~D

4.7K_0402_1%~D
3

+3VS
1

C C
2

Q277B KB_LED_G2_DRV#_A#
KB_LED_G2_DRV#_A# (46)

1
KB_LED_R1_DRV# 5 DMN66D0LDW-7_SOT363-6~D
+3VS R1610

6
4.7K_0402_1%~D
4

1
Q282A

2
R1611 KB_LED_G2_DRV 2 DMN66D0LDW-7_SOT363-6~D +3VS
4.7K_0402_1%~D KB_LED_B2_DRV#_A#
KB_LED_B2_DRV#_A# (46)

1
2
Q282B +3VS R1616

6
KB_LED_G2_DRV# 5 DMN66D0LDW-7_SOT363-6~D 4.7K_0402_1%~D

1
Q267A

2
R1617 KB_LED_B2_DRV 2 DMN66D0LDW-7_SOT363-6~D
4.7K_0402_1%~D

1
+3VS

2
KB_LED_R2_DRV#_A# Q267B
KB_LED_R2_DRV#_A# (46)
KB_LED_B2_DRV# 5 DMN66D0LDW-7_SOT363-6~D
1

+3VS
6

R1604

4
4.7K_0402_1%~D
1

Q262A
R1607 KB_LED_R2_DRV 2 DMN66D0LDW-7_SOT363-6~D
3 2

4.7K_0402_1%~D
1
2

Q262B +3VS
KB_LED_R2_DRV# 5 DMN66D0LDW-7_SOT363-6~D
KB_LED_G3_DRV#_A#
KB_LED_G3_DRV#_A# (46)
1
4

+3VS R1628

6
4.7K_0402_1%~D
+3VS
1

Q269A
2

R1629 KB_LED_G3_DRV 2 DMN66D0LDW-7_SOT363-6~D KB_LED_B3_DRV#_A#

KB_LED_B3_DRV#_A# (46)

1
B B
4.7K_0402_1%~D
3

+3VS R1630

6
4.7K_0402_1%~D
2

Q269B

1
KB_LED_G3_DRV# 5 DMN66D0LDW-7_SOT363-6~D Q278A

2
R1631 KB_LED_B3_DRV 2 DMN66D0LDW-7_SOT363-6~D
4.7K_0402_1%~D
4

3
+3VS

1
2
KB_LED_R3_DRV#_A# Q278B
KB_LED_R3_DRV#_A# (46)
1

KB_LED_B3_DRV# 5 DMN66D0LDW-7_SOT363-6~D
+3VS R1622
6

4.7K_0402_1%~D

4
1

Q268A
2

R1623 KB_LED_R3_DRV 2 DMN66D0LDW-7_SOT363-6~D

4.7K_0402_1%~D
3

1
2

Q268B
KB_LED_R3_DRV# 5 DMN66D0LDW-7_SOT363-6~D +3VS

KB_LED_G4_DRV#_A#
KB_LED_G4_DRV#_A# (46)
4

+3VS R1620
6

4.7K_0402_1%~D
1

Q265A +3VS
2

R1621 KB_LED_G4_DRV 2 DMN66D0LDW-7_SOT363-6~D

4.7K_0402_1%~D KB_LED_B4_DRV#_A#
KB_LED_B4_DRV#_A# (46)
3

1
1

+3VS R1626
2

6
Q265B 4.7K_0402_1%~D
KB_LED_G4_DRV# 5 DMN66D0LDW-7_SOT363-6~D

1
+3VS Q266A

2
R1627 KB_LED_B4_DRV 2 DMN66D0LDW-7_SOT363-6~D
4

KB_LED_R4_DRV#_A# 4.7K_0402_1%~D
KB_LED_R4_DRV#_A# (46)
1

3
A A

1
R1614 2
6

4.7K_0402_1%~D Q266B
+3VS KB_LED_B4_DRV# 5 DMN66D0LDW-7_SOT363-6~D
Q264A
2

KB_LED_R4_DRV 2 DMN66D0LDW-7_SOT363-6~D

4
1

R1615
1

4.7K_0402_1%~D
3

Security Classification Compal Secret Data Compal Electronics, Inc.

2

Q264B
KB_LED_R4_DRV# 5 DMN66D0LDW-7_SOT363-6~D 2011/06/02 2012/06/02 Title
Issued Date Deciphered Date
ELC (3)
4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8381P
Date: Thursday, January 12, 2012 Sheet 50 of 63
5 4 3 2 1
 5 4 3 2 1

Power block

D D
CPU OTP
Page 59

Turn Off

Input B+
DC IN Switch Page 51 +3VALWP: TDC:4.8A efficiency: 93%
Always
+5VALWP: TDC:6A efficiency: 90%
RT8205L Page 53

CHARGER
CC:0A~3A +1.8VP: TDC:1.25A SUSP#
C
CV:14.8V(8cell) SYN470DBC efficiency: 88% C

ISL6251AHAZ-T Page 55

Page 52

+VCCPP: TDC:12.8A SUSP#

Battery TPS51212DSCR efficiency: 82%

Page 55

+1.5VSDGPUP: TDC:5.6A DGPU_PWR_EN

TPS51212DSCR efficiency: 83%
Page 56

+GPU CORE efficiency: 88%

DGPU_PWR_EN +1.5VP: TDC:7A
TDC:36.8A
SYSON
B ISL62883CHRTZ-T +0.75VSP: TDC:1A B

Page 57 RT8207M efficiency: 84% Page 54

CPU CORE efficiency: 86%

VR_ON
TDC: 52A
ISL95836HRTZ-T +VCCSAP: TDC:4.2A VTTPWRGOOD
Page 58
TPS51461RGER efficiency: 80%
Page 56

GFX CORE efficiency: 85%

VR_ON +1.5VSP: TDC:1.26A
A TDC: 21.5A SUSP# A

ISL95836HRTZ-T SYN470DBC efficiency: 89%

Page 58 Page 54

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
POWER BLOCK DIAGRAM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6801P
Date: Thursday, January 12, 2012 Sheet 51 of 63
5 4 3 2 1
 5 4 3 2 1

PL1
BLM18BD102SN1D_0603~D
PSID 2 1 DETECT_PSID
ADPIN VIN

PJDCIN
5 PL2
DETECT C8B BPH 853025_2P~D
9
GND_4
1 1 2 PreCHG @ PQ1
D DC+_1 @ PR1 TP0610K-T1-E3_SOT23-3
D
8
GND_3 VIN B+
2 1K_1206_5% @ PD1
DC+_2
1 2 2 1 3 1
7 3
GND_2 DC-_1 @ PR2 RLS4148_LL34-2

1000P_0402_50V7K~D

1000P_0402_50V7K~D
6 4 1K_1206_5%

100P_0402_50V8J~D

100P_0402_50V8J~D
GND_1 DC-_2

1
PC2

PC4
1 2

PC1

PC3

470K_0402_5%

470K_0402_5%
1

1
@ PR3

2
FOX_JPD113D-DB570-7F 1K_1206_5%

PR4

PR5

2
1 2
CONN@ @ @
@ PR6

2
1K_1206_5%
1 2

1
@PR7
@ PR7
470K_0402_5%

1 2
@ PQ2
+5VALW +3VALW @ PD2 DTC115EUA_SC70-3
(47,53) ACOFF 2 @ PQ3
Item16_X02_power 1 2 DTC115EUA_SC70-3
+5VALW 3
2

DA204U_SOT323~D
RB715F_SOT323-3
PR8

3
3

2
PD3
@ 0_0402_5%~D

2.2K_0402_5%~D
1 2

3
2
PR9
PR10

1
33_0402_5%~D

1
DETECT_PSID 1 3 1 2
D

S
PS_ID (47)
PQ4
C FDV301N_NL_SOT23-3~D C
G
2
100K_0402_1%~D
2

PR12
PR11

1 2 +5VALW
10K_0402_1%~D
1
2

C
2 PQ5
B PMBT3904_SOT23
15K_0402_1%~D
2

E
3
PR13

@
1

PD4
PESD24VS2UT_SOT23-3~D
1

@ PR26
+3VALW 0_0402_5%~D
2 1
VIN
2

1
@ PR17 VL

1000P_0402_50V7K~D
PD6 Item9_X01_power 0_0402_5%~D PR16

1000P_0402_50V7K~D
RLS4148_LL34-2 (47) Dyn_Turbo_Sel 2 1 10K_0402_1%~D

1
@ PR24

PC23
1

1
PD7 0_0402_5%~D

PC8
2
BATT+ RLS4148_LL34-2 PR19 PR29 (53) EMC_THERM# 2 1
2 1 0_0402_5%~D PU1A @ 0_0402_5%~D

2
1

8
PR18 68_1206_5% 1 2 PR25 LM393DR_SO8 PR21

1
0_0402_5%~D D
3 2 1

P
Pre_V 68_1206_5% (47,59) VR_HOT# 2 1 2 1
+ ADP_I (47,53)
PQ6 CA@ PQ7 G 0
2 2 1
- AC_SEL (47)

G
TP0610K-T1-E3_SOT23-3 TP0610K-T1-E3_SOT23-3 S PQ12
2

1000P_0402_50V7K~D
SSM3K7002FU_SC70-3 PR20

1
Pre_V 3 1 3 1 VS 0_0402_5%~D
1

PC7
0.22U_0603_25V7K~D

B B
37.1 CA@PR46
CA@ PR46

2
1

100K_0402_5%~D @
1

PR22 PC10
PC9

100K_0402_5%~D
2

0.1U_0603_25V7K~D
2

PR23
2

22K_0402_5%~D
51ON# 1 2 CA@
(46) 51ON#
PR47
22K_0402_5%~D
51ON# 1 2

@ PR28 @ PU2 "US California Energy Efficiency"

0_0603_5% +CHGRTC G920AT24U_SOT89-3
@
PR27 (Reserve 130mW for no battery mode)
1 2 3 2 1 2
+3VLP
1U_0603_25V6-K~D

OUT IN
4.7U_0603_6.3V6K~D

200_0805_5%
1

GND
1

PC12

Item20_X03_power 1
PC11

2
2

@
@

A Item4_X01_power JRTC1
A

1 +RTCBATT +RTCBATT
1
2
2
MOLEX_53261-0271~D
SP020009Z0L
CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/31 Deciphered Date 2012/01/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-DCIN / Vin Detector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8381P
Date: Thursday, January 12, 2012 Sheet 52 of 63
5 4 3 2 1
 A B C D

Iada=0~7.693A(150W/19.5V=7.693A)

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D
ADP_I = 19.9*Iadapter*Rsense
CP = 90%*Iada ; CP = 6.92A
PL102
Item18_X03_power
Item18_X03_power

1
PC126

PC128

PC129
1.2UH_1231AS-H-1R2N=P3_2.9A_30%
PQ101 P2 PQ102 B+ 1 2 CHG_B+ PQ103
P3 PR101

2
FDS6679AZ-G_SO8~D FDS6679AZ-G_SO8~D 0.01_2512_1% @ @ PJP101 FDS6679AZ-G_SO8~D
VIN 8 1 1 8 1 4 2 2 1 1 1 8
7 2 2 7 2 7
6 3 3 6 2 3 JUMP_43X118 CSIN 3 6
5 5 5

2200P_0402_50V7K~D
4.7U_0805_25V6K~D

4.7U_0805_25V6K~D

0.1U_0603_25V7K~D
EMC_SENSE-

5600P_0402_25V7K~D
Item18_X03_power CSIP PR103

4
1

1
PC102

PC103
1 1
47K_0402_1%~D
VIN PreCHG VIN

PC104

PC105
Item20_X03_power 1 2

PC101
EMC_SENSE+ PR102 @ @ PR104

2
1

3
1 2 1 2

1
1

2
6251VDD
PR105 0_0402_5%~D 0_0402_5%~D @ PD101

0.1U_0603_25V7K~D
200K_0402_1% PR108 1 2 ACOFF
Item17_X02_power

2
2 PR106 ACSETIN PR107 10K_0402_1%~D

PC106

2.2U_0603_6.3V6K~D
200K_0402_1% PD102 191K_0402_1% 1SS355_SOD323-2
2

RB751VM-40TE-17_SOD323-2~D @ PR109

1 1

BAT_DIS_G
1000P_0402_50V7K~D
PC107
ACSETIN 200K_0402_1%

1
1 2 VIN

1 1

15K_0402_1%~D
PD103
1

1
10_1206_5%

PC108
V1 2 PQ104 1SS355_SOD323

PR110

PR111
DTA144EUA_SC70-3 1 2 PQ106 @ PD104
DTC115EUA_SC70-3 2 1 2

2200P_0402_50V7K~D
PQ105 PR112

2
DTC115EUA_SC70-3 10K_0402_5%~D 1SS355_SOD323-2
3

1
2 1 PU101 PC111
(47) FSTCHG

PC109

0.1U_0603_25V7K~D
0.1U_0603_25V7K~D

1
D

SSM3K7002FU_SC70-3
1 2 1 24 DCIN 2 1

2
VDD DCIN
1

1
100K_0402_1%~D

PC112
PR114 @ 0_0402_5%~D PC110 2 PACIN

PQ110
6251VDD 1 2 0.1U_0402_16V7K~D @ G

PR115
PR113 2 23 ACPRN S @ PQ107
ACPRN (54)

3
ACSET ACPRN

1
150K_0402_1%~D PR116 PR117 D @ SSM3K7002FU_SC70-3
6

D 20_0402_5% 100K_0402_1%~D 2
2

2
2 Item20_X03_power 6251_EN 3 22 1 2 CSON V1 2 1 G
EN CSON

2
G PQ108A PC113 S

3
5
6
7
8
DMN66D0LDW-7_SOT363-6~D 0.047U_0603_16V7K~D @
S 4 21 1 2 CSOP
1

1
CELLS CSOP PR118 ACPRN
PC114 6800P_0402_25V7K~D 20_0402_5% PQ111
1 2 5 20 2 1 AO4466L_SO8
ICOMP CSIN
3

2
2 D PR119 4 2

5 PC116 20_0402_5%
G PQ108B 1 2 1 PR120 2 10K_0402_1%~D 6 19 0.1U_0603_25V7K~D
1 2

1
PR122 DMN66D0LDW-7_SOT363-6~D PR123 VCOMP CSIP PR121 PL101 PR124
47K_0402_1%~D S PC115 1 2 100_0402_1%~D 2_0402_5% 10UH_PCMB104T-100MS_6A_20% 0.02_1206_1% BATT+
4

3
2
1
PACIN 1 2 0.01U_0402_25V7K~D PC117 1 2 7 18 LX_CHG 1 2 CHG 1 4
ICM PHASE

4.7_1206_5%
@ 100P_0402_50V8J~D

5
6
7
8

1
(47,52) ADP_I 6251VREF 2 3

PR125
PC118 6251VREF 8 17 DH_CHG
PR126 VREF UGATE PR127 PC119
1 2

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D
147K_0402_1% 2.2_0603_5%~D 0.1U_0603_25V7K~D
2 1 0.1U_0402_16V7K~D 9 16 BST_CHG 1 2 2 1 PQ112

2
(47) IREF CHLIM BOOT

1
0.01U_0402_25V7K~D

4 AO4466L_SO8
1

1
PC124

PC121

PC125

PC122
PQ113 PD105 Item17_X02_power

680P_0402_50V7K~D
PC120

DTC115EUA_SC70-3 PR128 6251aclim 10 15 6251VDDP RB751VM-40TE-17_SOD323-2~D

ACLIM VDDP

PC123
100K_0402_1%~D PR129
2

2
6251VREF 1 2 1 2 6251VDD

3
2
1

2
ACOFF 2 +3VALW 11 14 DL_CHG
2

(47,52) ACOFF VADJ LGATE

2
11.5K_0402_1% PR130
1
10K_0402_1%~D

4.7_0603_5%
2

PR131 12 13 PC127

1
GND PGND
PR143

1 2 6.98K_0402_1% 4.7U_0603_6.3V6K~D
3

@ PR142
4.53K_0402_1% ISL6251AHAZ-T_QSOP24
2
1

@ D
1

2 PQ115
G SSM3K7002FU_SC70-3
0.1U_0402_16V7K~D

S @ PR132
(47) CP_SEL
3
2
PC133

25.5K_0402_1%
(47) CHGVADJ 1 2
1

@
2

3 del 01/25 3

PR133 customer assent

43.2K_0402_1%
1

6251VDD

PR136 @ PU102

2
10K_0402_1%~D EMC1701-2-AIZL-TR_MSOP10
1

1 2

N/C
ACIN (22,46,47,48)
PR134 EMC_SENSE- 3 1
CP mode 47K_0402_1%~D PR135 SENSE- SMCLK EC_SMB_CK2 (15,22,23,41,43,46,47)
10K_0402_1%~D EMC_SENSE+
Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05) PACIN
4
SENSE+ SMDATA
10
EC_SMB_DA2 (15,22,23,41,43,46,47)
2

1 2

Vaclim=2.39*((6.98K//152K)/((11.5K//152K)+(6.98K//152K))) +5VS 5 9 1 2 EMC_ALERT# (47)

ADDR_SEL
VDD ALERT# @ PR141

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D
PQ114 8 0_0402_5%~D EMC_THERM# (52)
THERM#

2
PC131

PC132
DTC115EUA_SC70-3

GND

1
10K_0402_1%~D

10K_0402_1%~D
ACPRN 2
CC=3.3A

1
1

PR139

PR140
@ @

7
PR137
14.3K_0402_1%
IREF=1*Icharge @ @
3

2
1

20K_0402_1%~D
2

PR138
IREF=0.25V~3.3V
CHGVADJ CV mode
@

2
+3VS

4
0V 3.99V per cell 4

slave address : 0101101

BATT Type Charging Voltage CV mode please placemnet near R-sense
1.93V 4.2V per cell
(0x15)

Normal 4S LI-ON Cells

3.3V 4.35V per cell
14800mV 14.80V Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/01/31 Deciphered Date 2012/01/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8381P
Date: Thursday, January 12, 2012 Sheet 53 of 63
A B C D
 5 4 3 2 1

3.3VALWP
TDC 11.09A 5VALWP
Peak Current 15.84A TDC 8.43A
OCP current 20.3A 2VREF_RT8205L Peak Current 12.05A
H/S RDS(on) 12.2m ohm(typ),15m ohm(max) OCP current 15.6A
L/S RDS(on) 3.6m ohm(typ),4.5m ohm(max) H/S RDS(on) 12.2m ohm(typ),15m ohm(max)

1U_0603_10V6K~D
L/S RDS(on) 3.6m ohm(typ),4.5m ohm(max)

1
D D

PC201

2
PC225
100P_0402_25V8K
1 2
Co-Lay
PL708 Item15_X02_power PR201 PR202
1 2 13K_0402_1% 30K_0402_1%
HCB2012KF-121T50_0805 1 2 1 2
PL709

Item12_X01_power 1 2 PR203 PR204

HCB2012KF-121T50_0805 RT8205L_B+ 20K_0402_1%~D 20K_0402_1%~D
1 2 1 2 RT8205L_B+
Typ: 175mA Item8_X01_power
Item8_X01_power
B+ +3VLP

ENTRIP2

ENTRIP1
2200P_0402_50V7K~D

2200P_0402_50V7K~D
10U_0805_25V6K~D

0.1U_0603_25V7K~D

4.7U_0805_25V6K~D

4.7U_0805_25V6K~D

4.7U_0805_25V6K~D

4.7U_0805_25V6K~D

0.1U_0603_25V7K~D
PR205 PR206
1
680P_0402_50V7K~D

PJP205 75K_0402_1%~D 52.3K_0402_1%~D

PC202

PC203

PC210
4.7U_0805_10V6K
2 2 1 1 1 2 1 2
1

1
PC222

PC204

PC205

PC206

PC207

PC208

PC209
SIR472DP-T1-GE3_POWERPAK8-5~D

SIR472DP-T1-GE3_POWERPAK8-5~D
2

JUMP_43X118

5
@ @
2

2
PQ201

PQ202
PC211
@

ENTRIP2

FB2

TONSEL

FB1

ENTRIP1
REF
1
25 P PAD

2
4 4
7 24
C VOUT2 VOUT1 SPOK (60) C
8 23 PR208 PC213
PR207 VREG3 PGOOD 2.2_0603_5%~D
0.1U_0402_16V7K~D
1
2
3

3
2
1
1 2 1 2 BST_3V 9 BOOT2 BOOT1 22 BST_5V 1 2 1 2
2.2_0603_5%~D
PL202 PC212 UG_3V 10
VFB=2.0V 21 UG_5V PL205
2.2UH_FDVE1040-2R2M=P3_14.2A_20%~D 0.1U_0402_16V7K~D UGATE2 UGATE1 2.2UH_FDVE1040-2R2M=P3_14.2A_20%~D
1 2 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP PHASE2 PHASE1
1

1
4.7_1206_5%

4.7_1206_5%
LG_3V LG_5V
SI7170DP-T1-GE3_POWERPAK8-5~D

12 19
LGATE2 LGATE1

5
PQ203
PR209

PR210
SI7170DP-T1-GE3_POWERPAK8-5~D
SKIPSEL

PQ204
VREG5

SECFB
MAINPWON 1 2

GND

VIN
PU201

EN
1 1
2

2
4 PR211 @ PR221 RT8205LZQW(2)_WQFN24_4X4
+ PC214 @ 499K_0402_1% 0_0402_5%~D 4 + PC217

13

14

15

16

17

18
1

1
680P_0402_50V7K~D

680P_0402_50V7K~D
330U_D3L_6.3VM_R18M~D 1 2 330U_D3L_6.3VM_R18M~D
B+
PC215

PC216
2 PR212 2
2

1
2
3

2
499K_0402_1%

3
2
1
1 2
VS
1

100K_0402_1%~D

1U_0603_10V6K~D
1 2
VL

1
PC218
PR215

1
0_0402_5%~D
PR213

PC219
4.7U_0805_10V6K
@ 499K_0402_1% PR214 Typ: 175mA

2
1 2 @ 0_0402_5%~D
Pre_V

PR222
PJP201
2

2
2 2 1 1 Item11_X01_power Item11_X01_power
ENTRIP1 ENTRIP2
@ JUMP_43X118 @ PJP203

1
DMN66D0LDW-7_SOT363-6~D

RT8205L_B+ 2 1
2 1

0.1U_0603_25V7K~D
PJP202
6

D D
DMN66D0LDW-7_SOT363-6~D

+3VALWP 2 1 +3VALW Item20_X03_power @ JUMP_43X118

2
2 1
PQ205A

PQ205B

PC220
B PJP204 B
2 5
@ JUMP_43X118 G G 2VREF_RT8205L 2 2
+5VALWP 1 1 +5VALW
1

@ PC226
680P_0402_50V7K~D S S @ JUMP_43X118
1

1
@ PC227
@PC227
2

680P_0402_50V7K~D

2
2 1
VL PR216
100K_0402_1%~D
PR217
1

@
MAINPWON 1 2
(43,60) MAINPWON
Item20_X03_power 0_0402_5%~D
2
PR1134
EC_ON 1 2
PQ206
1

2.2K_0402_5%~D DTC115EUA_SC70-3
3

PR1135
@ 0_0402_5%~D
2

1 2
VS PR218
40.2K_0402_1%~D

2.2U_0603_10V6K~D

100K_0402_1%~D
1

D
1
PR220

PC221

(53) ACPRN 1 2 2
G
1

PR219 S
3

A 200K_0402_1% A
2

(46,47) EC_ON 2
PQ207
SSM3K7002FU_SC70-3

PQ208
Security Classification Compal Secret Data Compal Electronics, Inc.
3

DTC115EUA_SC70-3
Issued Date 2011/01/31 Deciphered Date 2012/01/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3VALWP/5VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8381P
Date: Thursday, January 12, 2012 Sheet 54 of 63
5 4 3 2 1
 5 4 3 2 1

+1.5VP
PL301
B+ 1.2UH_1231AS-H-1R2N=P3_2.9A_30%
PR301
1 2 1.5V_B+ 1 2 BOOT_1.5V
2.2_0603_5%~D

1
@ PC310 PJP301
680P_0402_50V7K~D 1 2 DH_1.5V
+0.75VSP

4.7U_0805_25V6K~D

4.7U_0805_25V6K~D

0.1U_0402_25V6K~D

2200P_0402_50V7K~D

0.22U_0603_16V7K~D
2

10U_0805_6.3V6M~D

10U_0805_6.3V6M~D
1

1
PAD-OPEN 4x4m SW_1.5V

PC305
@

PC301

PC302

PC303

PC304

1
0.75Volt +/- 5%

8
7
6
5

1
DL_1.5V

PC311

PC312
16

17

18

19

20
PU301 TDC 0.7 A

VLDOIN
BOOT

VTT
PHASE

UGATE

2
D
PAD
21 Peak Current 1 A D

4 Item14_X01_power 15 1
LGATE VTTGND

PQ305 PR302 14 2 +3VALW

PL302 SI4172DY-T1-GE3_SO8 8.06K_0402_1%~D PGND VTTSNS

1
2
3
1UH_PCMB062D-1R0MS_9A_20% 1 2 CS_1.5V
1 2 13 3
+1.5VP CS GND

2
PC306 RT8207MZQW_WQFN20_3X3

8
7
6
5
1U_0603_10V6K~D PC313 PR310

4.7_1206_5%~D
PR303 0.033U_0402_16V7K~D

PR304
12 4 1.2K_0402_1%~D
5.1_0603_5%~D VDDP VTTREF
1 1
220U_D2_2VY_R15M

220U_D2_2VY_R15M

+5VALW

1
+ + VDD_1.5V
PC318

PC324

1 2 11 5

2
VDD VDDQ

PGOOD
4
PC307

SNUB_1.5V

TON

2
2 2

FB
S5

S3
PQ306 1U_0603_10V6K~D PR311
SI4634DY-T1-E3_SO8 +1.5VP 1K_0402_1%~D

680P_0603_50V7K~D

1
2
3

10

2
+5VALW PR331

10K_0402_1%~D

1
0.1U_0402_16V7K~D
1

Item13_X01_power PC308 1K_0402_1%~D

2
PC319

PR312
2

1
@

2
PR306

1
1M_0402_1%~D PR332 PQ307

3
E
Item11_X01_power PR307 1.5V_B+ 1 2 10K_0402_1%~D
0_0402_5%~D +3VALW 2 1 2
B
PMST3906_SOT323-3~D
1 2 S5_1.5V PR314 PR333
(32,47) SYSON 150K_0402_1%~D 1K_0402_1%~D
C

1
1

1
PR308 1 2 2 1
PC309 0_0402_5%~D PR316
1.5VP @ 0.1U_0402_16V7K~D SUSP# 1 2 S3_1.5V 10K_0402_5%~D
2

6
TDC 8.4A

1
+3VALW

DMN66D0LDW-7_SOT363-6~D
PQ301A

PC320
C Item18_X03_power C

10K_0402_1%~D
2

1000P_0402_50V7K~D
Peak Current 12A

1
@ PR318

PR313
2
OCP current 15.6A

2
1
10K_0402_5%~D
H/S RDS(on) 12.2m ohm(typ),15m ohm(max)

10K_0402_5%~D

1
0.01U_0402_25V7K~D
DMN66D0LDW-7_SOT363-6~D
@

2
3

1
L/S RDS(on) 5.5m ohm(typ),6.7m ohm(max)

1
PR319 PQ301B

PC314

75K_0402_1%~D
(6,17) 1.5VDDR_VID0

2
10K_0402_5%~D

PR317
(2A,80mils ,Via NO.= 4)

PR315
1 2 5

2
PJP302

2
1
2 1

2
0.01U_0402_25V7K~D
2 1

1
PR320

PC315
10K_0402_5%~D
@ JUMP_43X118
@

2
PJP303 PJP305 @
+1.5V +0.75VS

2
+1.5VP 2
2 1
1 +0.75VSP 1 2

@ JUMP_43X118
PAD-OPEN 3x3m
1

@ PC323 +3VALW
1

@ PC321 680P_0402_50V7K~D
680P_0402_50V7K~D
2
2

DMN66D0LDW-7_SOT363-6~D
PR321

6
+3VALW 10K_0402_5%~D
Item18_X03_power PQ302A

2
1
@ PR323 2
10K_0402_5%~D

DMN66D0LDW-7_SOT363-6~D

1
3
DDR GPIO Output Voltage Selection
PR329 PQ302B

10K_0402_5%~D
(6,17) 1.5VDDR_VID1

0.01U_0402_25V7K~D
10K_0402_5%~D

1
bit2 = 1.5DDR_VID0 bit1 = 1.5DDR_VID1 DDR Vout 1 2 5

1
PR322

PC316
0.01U_0402_25V7K~D

4
1
B B
0 0 1.65V

2
1
@ PR325 @

PC317

2
10K_0402_5%~D
PJP307
0 1 1.6V

2
+1.5VSP 1 2 +1.5VS

2
1 2
1 0 1.55V @
JUMP_43X79

1
1 1 1.5V (Default) @ PC322
680P_0402_50V7K~D

2
Item11_X01_power PL303

4
@ PJP306 1UH_PH041H-1R0MS_3.8A_20%
2 1 1.5VS_PIN 10 2 LX_1.5VS 1 2
+3VALW

PG
2 1 PVIN LX +1.5VSP
22U_0805_6.3V6M~D

2
JUMP_43X79 9 3
PVIN LX PR324
1

4.7_1206_5%
8
SVIN +1.5VSP
PC330

6 Imax= 0.7 A

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D
2

2 1
FB 1.5VS_SNB
5
EN Ipeak=1 A

1
NC

NC
TP
PC331

PC332

PC333
680P_0603_50V7K~D Iocp(minimum)=4.5 A
11

2
1 2 EN_1.5VS
(19,32,47,56) SUSP#
PR330 1.5VS_FB 1 2
1U_0402_6.3V6K~D
2

0_0402_5%~D @
PC334
1

PR326 PR327

1
1M_0402_1%~D PU303 15.8K_0402_1%
@ SYN470DBC_DFN10_3X3 2 1
2

A PR328 A
1

10.5K_0402_1% PC335
68P_0402_50V8J~D
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/31 Deciphered Date 2012/01/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5VP/+0.75VSP/+1.5VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8381P
Date: Thursday, January 12, 2012 Sheet 55 of 63
5 4 3 2 1
 5 4 3 2 1

Due to remove VENTURA fun,

so delete PR401.
VCCPP
TDC 14.14A @ PL401
Peak Current 20.20A HCB2012KF-121T50_0805
VCCP_B+ 1 2
OCP current 15.6A B+
PJP401
H/S RDS(on) 12.2m ohm(typ),15m ohm(max)

2200P_0402_50V7K~D

0.1U_0603_25V7K~D

4.7U_0805_25V6K~D

4.7U_0805_25V6K~D

4.7U_0805_25V6K~D

1
2 1 @ PC401
2 1
L/S RDS(on) 2.7m ohm(typ),3.3m ohm(max) 680P_0402_50V7K~D

1
@ JUMP_43X118

PC404

PC405

PC406

2
PC402

PC403
CPU_IN_B+

2
PR417 @

SIR472DP-T1-GE3_POWERPAK8-5~D
D
1 2 +3VS D

10K_0402_1%~D
(57) VTTPWRGOOD

5
@ PR426 PQ401
PR420 1 2 +3VALW
10K_0402_1%~D
@ 10K_0402_1%~D

1
4

PR404 PC408
PU401 2.2_0603_5%~D 0.1U_0603_25V7K~D PL402

3
2
1
1 10 BST_VCCP 1 2BST_VCCP-1 1 2 0.42UH_FDUE0640-R42M_20.2A_20%~D
PGOOD VBST
2 1 +VCCPP
PR403 1 2 2 9 DH_VCCP
0_0402_5%~D PR406 52.3K_0402_1%~D TRIP DRVH

1
SUSP# LX_VCCP PQ402

SIR818DP-T1_POWERPAK-SO8-5~D
1 2 3 8
EN SW
(19,32,47,55) SUSP# +5VALW

1
4 7 1
VFB V5IN

220U_D2_2VY_R15M
@PC407
@ PC407 PR405
0.1U_0402_16V7K~D 4.7_1206_5% +

PC409
5 6

2
RF DRVL @
4

0.1U_0402_10V7K~D
1

2
11
TP

1
PC414 2

PC70
1
+5VS TPS51212DSCR_SON10_3X3 4.7U_0805_10V6K

1
PR428 VFB=0.704V

1
2
3
470K_0402_1% DL_VCCP

2
2

PC411

2
PR409 680P_0402_50V7K~D
@ 10K_0402_5%~D
PC55 PR59
@ @
@ PR410 PR411 2 1 2 1
1

(10) VCCP_PWRCTRL 1 2 2 1
10K_0402_5%~D
1000P_0402_50V7K~D 1.2K_0402_1%~D
2
G

0_0402_5%~D @ PR414 PR415

100K_0402_5%~D

0.01U_0402_16V7K~D

162K_0402_1%~D 4.99K_0402_1%
PR413
1

PJP402
PC417

C 3 1 1 2 1 2 C
S

Item11_X01_power 2 1
@ PR419 @ 2 1
2

1
@ @ @ PQ403 0_0402_5%~D @ JUMP_43X118
2 1 VCCIO_SENSE (10)
2

SSM3K7002FU_SC70-3 PR416 +VCCPP PJP403 +VCCP

10K_0402_1%~D 2 1
2 1
2 2 1
VSSIO_SENSE (10) @ JUMP_43X118
0_0402_5%~D PJP406 +1.05VS
PR427 @ 2 1
2 1
1

PR412 Item20_X03_power @ JUMP_43X118

0_0402_5%~D
@

1
@ PC410
2

680P_0402_50V7K~D

2
PU402
SYN470DBC_DFN10_3X3
PL403

4
@ PJP404 1UH_PH041H-1R0MS_3.8A_20%
2 1 1.8VS_PIN 10 2 LX_1.8VS 1 2
+3VALW

PG
2 1 PVIN LX +1.8VSP
22U_0805_6.3V6M~D

2
JUMP_43X79 9 3
PVIN LX PR421
1

8 4.7_1206_5%
SVIN
PC419

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D
6
2

2 1
FB 1.8VS_SNB
5
EN

1
NC

NC
TP
B B
PC421

PC422

PC423
680P_0603_50V7K~D

11

2
SUSP# 1 2 EN_1.8VS

PR422 1.8VS_FB
Item11_X01_power
1 2

1U_0402_6.3V6K~D
2

0_0402_5%~D @

PC424
1
PR424 PR423

1
1M_0402_1%~D 28.7K_0402_1% PJP405
@ 2 1 +1.8VSP 2 1 +1.8VS
2

PR425 2 1
1

14.3K_0402_1% PC425 @ JUMP_43X118

68P_0402_50V8J~D

2
@

1
@ PC412
680P_0402_50V7K~D

2
1.8VSP
TDC 1.08 A
Peak Current 1.55 A
OCP current 4.5 A

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/31 Deciphered Date 2012/01/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR+VCCPP/+1.8VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8381P
Date: Thursday, January 12, 2012 Sheet 56 of 63
5 4 3 2 1
 5 4 3 2 1

+3VS
The 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that
PR503 VCCSA VID is 00 prior to VCCIO stability.

100K_0402_5%~D
1K_0402_5%~D

1
2 1

PR502
H_VCCSA_VID1 (10)

2 +VCCSA_PWRGD
D D
+VCCSAP PJP502 +VCCSA
H_VCCSA_VID0 (10) 2 1
2 1
@ JUMP_43X118

1
PR504 PC1325
(47) +VCCSA_PWRGD 1K_0402_5%~D @ 680P_0402_50V7K~D
2 1

2
H_VCCSA_VID0
H_VCCSA_VID1
+5VALW

+VCCSA_PWRGD
1U_0603_10V6K~D
2

PC506
PR501 PR505
10_0402_1%~D 0_0402_5%~D
VTTPWRGOOD (56)

1
2 1 +VCCSA_EN 1 2
PC505
2.2U_0603_10V7K~D
+VCCSAP
1 2 TDC 4.2 A
Peak Current 6.0 A

18

17

16

15

14

13
PU501 OCP current 7.8 A
PR506 PC507

VID1

VID0
PGOOD

EN
V5FILT
V5DRV
2.2_0603_5%~D 0.1U_0603_16V7K
12 +VCCSA_BT 1 2+VCCSA_BT_1 1 2
BST PL505
19
PGND 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
SW
11 +VCCSA_PHASE 1 2 +VCCSAP
20
PGND

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

0.1U_0402_10V7K~D
1
10

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D
2200P_0402_50V7K~D
SW PR507 @ @ @ @
2200P_0402_50V7K~D

21
PGND

2
0.1U_0603_25V7K~D

10U_0805_6.3V6M~D

10U_0805_6.3V6M~D

4.7_1206_5%

PC511

PC512

PC514

PC515

PC533

PC544
TPS51461RGER_QFN24_4X4
Item21_X03_power

PC513

PC532
9
SW
22
PC502

1 2 2

1
VIN
2

C C
PC501

PC503

PC504

8
SW
23
1

VIN

1
2 1 1 PC510
PAD-OPEN 43X118 7 1000P_0603_50V7K
+3VALW 2 1 +VCCSA_PWR_SRC +VCCSA_PWR_SRC 24
SW

2
VIN
25

COMP

MODE
TP

SLEW

VOUT
VREF
PJP501

GND
1

6
@ PR508 Item11_X01_power
2 1

33K_0402_5%
PR510
100_0402_5%~D
PC509 2 1
2 1

0.22U_0402_10V6K
PR509
@ PR511
2 1 1 2 0_0402_5%~D
2 1

0.01U_0402_25V7K~D
PC508 5.1K_0402_1%~D

2
3300P_0402_50V7K VCCSA_SENSE (10)

PC139
Item20_X03_power

1
PR529 @ PL503
10K_0402_5%~D HCB2012KF-121T50_0805
1 2 +3VS 1.35V_B+ 1 2
GPU_IN_B+
PJP503
2

1
2 1 @ PC516

2200P_0402_50V7K~D

0.1U_0603_25V7K~D

4.7U_0805_25V6K~D

4.7U_0805_25V6K~D

4.7U_0805_25V6K~D
PR530 2 1 680P_0402_50V7K~D
0_0402_5%~D @ JUMP_43X79

2
1

1
5
6
7
8
B B

PC517

PC518

PC519

PC520

PC521
1

2
SI4172DY-T1-GE3_SO8
@

PQ505
4
(17,18,31,35) DGPU_PWROK

Item21_X03_power

3
2
1
Item15_X01_power PR520 PC522 PL504
PU502 2.2_0603_5%~D 0.1U_0603_25V7K~D 1UH_ETQP3W1R0WFN_11.8A_20%
1
PGOOD VBST
10 BST_1.35V 1 2BST_1.35V-1 1 2 1 2 +1.5VSDGPUP
1 2 2 9 DH_1.35V
PR522 88.7K_0402_1%~D TRIP DRVH
3 8 LX_1.35V 1 1 PJP504

10U_0805_6.3V6M~D
0.1U_0402_16V7K~D
EN SW

220U_D2_2VY_R15M

220U_D2_2VY_R15M
2 1
2 1
5
6
7
8

1
PR521 + +
+5VALW

PC527

PC525

PC526
Item2_X01_power 4 7
VFB V5IN

SI4634DY-T1-E3_SO8
4.7_1206_5% @ JUMP_43X118

PC524
5 6

2
RF DRVL
1

2 2 PJP505

PQ506

2
PC523 11 +1.5VSDGPUP 2 1 +1.5VSDGPU
TP 2 1
1

(58) VGA_PWROK 0.1U_0402_16V7K~D 4

2

TPS51212DSCR_SON10_3X3 PC528 @ JUMP_43X118

1
4.7U_0805_10V6K PC529 @
2

PR429 680P_0402_50V7K~D
470K_0402_1% DL_1.35V
3
2
1

2
2

1.5VSDGPUP (for VRAM)

TDC 11.32 A
VFB=0.75V
PR524
Peak Current 16.16 A
1 2 OCP current 21 A
A
11.3K_0402_1%~D
H/S RDS(on) 12.2m ohm(typ),15m ohm(max) A
Item11_X01_power
1

L/S RDS(on) 5.5m ohm(typ),6.7m ohm(max)

PR525
10K_0402_1%~D
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/31 Deciphered Date 2012/01/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-+VCCSAP/+1.5VSDGPUP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8381P
Date: Thursday, January 12, 2012 Sheet 57 of 63
5 4 3 2 1
 8 7 6 5 4 3 2 1

N13P-GT
+3VS
Initial voltage is 1.1V Co-Lay
PR660 PR659 Item15_X02_power
2.2K_0402_5%~D 2.2K_0402_5%~D EDP-TDC = 42 A PL714
GPU_VID_0 1 2 @ 1 @ 2
PR661 1 2 PR658 EDP-Peak = 60 A HCB2012KF-121T50_0805
2.2K_0402_5%~D 2.2K_0402_5%~D
H GPU_VID_1 1 2 @ OCP= 73.5 A PL715
H
PR662 1 2 PR657 1 @ 2 Due to remove VENTURA fun,
GPU_VID_2
2.2K_0402_5%~D
1
2.2K_0402_5%~D
2 @
H/S RDS(on) 12.2m ohm(typ),15m ohm(max) HCB2012KF-121T50_0805
so delete PR601.
PR663 1
2.2K_0402_5%~D
2 PR656
2.2K_0402_5%~D
L/S*2 RDS(on) 2.7m ohm(typ),3.3m ohm(max)
GPU_VID_3 1 2 @
Item4_X01_power PR664 1 2 PR655 GPU_B+
2.2K_0402_5%~D 2.2K_0402_5%~D B+

2200P_0402_50V7K~D

4.7U_0805_25V6K~D

4.7U_0805_25V6K~D

4.7U_0805_25V6K~D

4.7U_0805_25V6K~D
GPU_VID_4 1 2 @
PR665 1 2 PR654 PAD-OPEN 43X118

SIR472DP-T1-GE3_POWERPAK8-5~D

1
2.2K_0402_5%~D 2.2K_0402_5%~D

PC601

PC602

PC603

PC604

PC605
2 1
GPU_VID_5 1 2
Item1_X01_power 1 2 @

2
5
PQ601 PJP1101 GPU_IN_B+
Item2_X01_power H_DPRSLPVR 1 2 PR653 @
2.2K_0402_5%~D
Item6_X01_power PR650 @
1 2 GPIO10_FBCREF_PSI# 1 2 PR652 @
(31) DGPU_CORE_EN
G 10K_0402_5%~D 2.2K_0402_5%~D 4 G

PR602 PC616
2.2_0603_5%~D 0.22U_0603_10V7K~D

3
2
1
1 2 BOOT2_VGA 2 1 BOOT2_2_VGA 1 2
PC641 0.1U_0402_25V6K~D
PR648 UGATE2_VGA PL602
2.2K_0402_5%~D 0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
1 2 H_DPRSLPVR PHASE2_VGA 2 1 +VGA_CORE
PR651
2.2K_0402_5%~D V2P_VGA V2N_VGA
(22) H_DPRSLPVR

5
PQ602 PQ603

SIR818DP-T1_POWERPAK-SO8-5~D

SIR818DP-T1_POWERPAK-SO8-5~D
1 2

3.65K_0402_1%

10K_0402_5%~D
1

2 PR607 1
+3VS

1_0402_5%
4.7_1206_5%
1
PR646

PR603

PR604

PR605
1 1

10K_0402_5%~D

10K_0402_5%~D

470U_D2_2VM_R4.5M~D

470U_D2_2VM_R4.5M~D
1

2 PR1128 1
1.91K_0402_1% GPU_VID_5 (22)
CLK_ENABLE#_VGA + +

PC642

PC643
PR1127
1 2
LGATE2_VGA 4 4

2
1

GPU_VID_4 (22)

2
F 2 2 F

2
680P_0603_50V7K~D
1
PR644 VSUM+_VGA VSUM-_VGA

PC617
GPU_VID_3 (22)

1
2
3

1
2
3
PR669 0_0402_5%~D 10K_0402_5%~D
2

1 2 ISEN2_VGA
(57) VGA_PWROK

2
ISEN3_VGA
GPU_VID_2 (22)

Item2_X01_power
GPU_VID6

ISEN1_VGA
GPIO10_FBCREF_PSI#
GPU_VID_1 (22) Item11_X01_power
+3VS

SIR472DP-T1-GE3_POWERPAK8-5~D
PR642 GPU_B+
GPU_VID_0 (22)
47K_0402_1%~D
2 1

2200P_0402_50V7K~D

4.7U_0805_25V6K~D

4.7U_0805_25V6K~D

4.7U_0805_25V6K~D

4.7U_0805_25V6K~D
5
PQ607
1

PR641 68_0402_5%~D PC639 +5VS

1
PR668 1U_0603_10V6K~D

PC606

PC607

PC608

PC609

PC610
40
39
38
37
36
35
34
33
32
31

+VCCP 1 2
2.2K_0402_5%~D PU601 1 2
CLK_EN#

VID6
VID5
VID4
VID3
VID2
VID1
VID0
DPRSLPVR
VR_ON

1U_0603_10V6K~D

2
E E
4
2

1
PR608 PC618

PC640
30
27.4K_0402_1% @ PR667 BOOT2 PU602 2.2_0603_5%~D 0.22U_0603_10V7K~D
29
UGATE2 BOOT3 2
2 @ 1 0_0402_5%~D 1 28 5 1 1 BOOT3_31 2

2
PR639 PGOOD PHASE2 VCC BOOT
2 1 2 27

3
2
1
PSI# VSSP2 @ PR647 0_0402_5%~D UGATE3_VGA PL604
3 26 6 8
@ PR638 VR_TT# RBIAS LGATE2 FCCM UGATE 0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
4 25 1 2 +5VS
VR_TT# VCCP PHASE3_VGA PHASE3_VGA
1 2 2 1 5 24 1 2 2 7 2 1 +VGA_CORE
4.02K_0402_1%~D NTC PWM3 PR631 0_0402_5%~D@ PWM PHASE
6 23
@ PH602 VW LGATE1 LGATE3_VGA V3P_VGA V3N_VGA

SIR818DP-T1_POWERPAK-SO8-5~D
7 22 3 4
COMP VSSP1 GND LGATE

5
470KB_0402_5%_ERTJ0EV474J PQ608 PQ609

SIR818DP-T1_POWERPAK-SO8-5~D
8 21 Item20_X03_power

3.65K_0402_1%

10K_0402_5%~D
FB PHASE1

1
1 2 9 ISL6208CRZ-T_QFN8~D

4.7_1206_5%
ISEN3

1
UGATE1

PR609

PR610
10
BOOT1

1 1

10K_0402_5%~D

10K_0402_5%~D
ISUM+

ISEN2
1

2 PR1130 1

470U_D2_2VM_R4.5M~D

470U_D2_2VM_R4.5M~D
ISEN1

ISUM-
VSEN

IMON

@ PC637 PC638

PR611

PR613
1_0402_5%
VDD
8.06K_0402_1%~D

RTN
1000P_0402_50V7K~D

VIN

22P_0402_50V8J~D 1U_0603_10V6K~D + +

PC644

PC645
PR1129
41 Item14_X02_power
249K_0402_1%

AGND
2

PC636

4 4
2

2
ISL62883CHRTZ-T_TQFN40_5X5
@ PR637

PR636

11
12
13
14
15
16
17
18
19
20

2
PR634 2 2
2

2
D 499_0402_1%~D PC635 D

680P_0603_50V7K~D
1
VSUM+_VGA

PC619
1 2 1 2
1

1
2
3

1
2
3
VSUM-_VGA
470P_0402_50V7K~D ISEN3_VGA

2
PR635 ISEN2_VGA
PC633 3.57K_0402_1%~D @ PR1126 0_0402_5%~D
1 2 1 2 1 2 +5VS ISEN1_VGA
68P_0402_50V8J~D
ISEN3_VGA Item11_X01_power
ISEN2_VGA @ PR629 0_0402_5%~D
1 2 1 2 1 2 GPU_B+
ISEN1_VGA
PC648 PR632 PR630
150P_0402_50V8J~D324K_0402_1%~D 1 2 GPU_B+
+5VS
0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z
1

SIR472DP-T1-GE3_POWERPAK8-5~D
PC632

PC631

PC630

Item5_X01_power
0.22U_0603_25V7K~D

1_0402_5%
1U_0603_10V6K~D
1

1
PC624

PC623
2

BOOT1_VGA

Item20_X03_power

2200P_0402_50V7K~D

4.7U_0805_25V6K~D

4.7U_0805_25V6K~D

4.7U_0805_25V6K~D

4.7U_0805_25V6K~D
5
PQ604
2

C C

1
PC611

PC612

PC613

PC614

PC615
2

2
VSUM+_VGA UGATE1_VGA 4
VSUM-_VGA
1 2
82.5_0402_5%

+VGA_CORE
PR614 PC620
1

PR625 @ 2.2_0603_5%~D 0.22U_0603_10V7K~D

PR624

3
2
1
1

100_0402_5%~D 2 1 BOOT1_1_VGA 1 2
2.61K_0402_1%~D
PR620

@ PR626 @ PL603
1 2 0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
(23) VCCSENSE_VGA
2

PHASE1_VGA 2 1 +VGA_CORE
0.01U_0402_25V7K

0_0402_5%~D
0.22U_0603_10V7K~D
1

V1P_VGA V1N_VGA
PC627
1

5
PC629 1 PC625 PQ605 PQ606

SIR818DP-T1_POWERPAK-SO8-5~D

SIR818DP-T1_POWERPAK-SO8-5~D
1

1
330P_0402_50V7K~D
PC626

3.65K_0402_1%

10K_0402_5%~D
2

1
4.7U_0603_10V6K~D

PR616
Item20_X03_power 1 1

4.7_1206_5%

10K_0402_5%~D

10K_0402_5%~D
2

2 PR1132 1

470U_D2_2VM_R4.5M~D

470U_D2_2VM_R4.5M~D
B @ B

PR615

PR619
1_0402_5%
2

2 + +

PR617

PC646

PC647
PR1131
LGATE1_VGA 4 4

2
1

1
11K_0402_1%

2
1

PC628 PH601 2 2
PR621

2
@ PR627 1000P_0402_50V7K~D 10K_0402_5%_ERTJ0ER103J
0_0402_5%~D

680P_0603_50V7K~D
2

1
2
3

1
2
3

1
VSUM+_VGA VSUM-_VGA

PC621
1 2
(23) VSSSENSE_VGA
2

ISEN3_VGA

2
PR628 @ ISEN1_VGA
Item20_X03_power 100_0402_5%~D
PR623
1 2 1 2 ISEN2_VGA
VSUM-_VGA Item11_X01_power
698_0402_1%
1

A
PC622 A
0.1U_0402_16V7K~D
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2009/12/01 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C LA-XXXX 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, January 12, 2012 Sheet 58 of 63
8 7 6 5 4 3 2 1
 5 4 3 2 1

CPU_IN_B+
PR701 CPU_IN_B+ GFX_B+ CPU_B+

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D
1 2
1 PH701 NTCG

680P_0402_50V7K~D

680P_0402_50V7K~D
2 1 2

1
PC703

PC702
3.83K_0402_1% PC767
470KB_0402_5%_ERTJ0EV474J PR767 470P_0402_50V7K~D PL710 1 2 PL711 1 2

1
PC704

PC705

PC706

PC707
2K_0402_1%~D Item15_X02_power HCB2012KF-121T50_0805 HCB2012KF-121T50_0805

2
VSUMG+ 1 2 revise 9/21
2

PR703 PL712 1 2 PL713 1 2 @ @

2
PR711 27.4K_0603_1%~D HCB2012KF-121T50_0805 HCB2012KF-121T50_0805
PR713
2.61K_0402_1%~D PC711
Co-Lay Co-Lay

1
PC710 1 2 1 2
UGATEG

330P_0402_50V7K~D
330P_0402_50V7K~D 2 Item15_X02_power
1

1
47P_0402_50V8J~D PQ717 PL702

0.15U_0402_10V6K~D
2 1
3.48K_0402_1%~D PR706 CSD87351Q5D_SON8~D 0.22UH_FDUE0640-H-R22M=P3_25A_20%~D
(10) VCC_AXG_SENSE PR710 PR712
1

1
169K_0402_1%

11K_0402_1%
1 1 PC712 PC716 7 2 1

PR715

PC719

PC713
PH702 PC714 1 2 1 2 1 2 1 2 PHASEG PC709 3 6 +VCC_GFXCORE_AXG
10K_0402_5%_ERTJ0ER103J PC721 (10) VSS_AXG_SENSE 1 2 499_0402_1%~D 267K_0402_1%~D PR705 0.1U_0603_25V7K~D 5

2
0.033U_0402_16V7K~D 470P_0402_50V7K~D 150P_0402_50V8J~D BOOTG 2 1 2 1 4

1
2 2

1_0402_5%
0.01U_0402_16V7K~D 2.2_0603_5%~D
2

PR709

PR708
4.7_1206_5%

3.65K_0603_1%
1

2
D D

680P_0402_50V7K~D
PR723

PR776
10K_0603_1%
8
VSUMG- 2 1 LGATEG

2
+5VS

PR707
1

21

2
PC717

10K_0402_1%~D
PC715

1
357_0402_1%

PR779
0.1U_0402_16V7K~D

1U_0603_10V6K~D
1
VSUMG+ VSUMG-
2

2
1
0_0603_5%

PC718
PR716

1
PR719 ISEN1G ISEN2G

SIR472DP-T1-GE3_POWERPAK8-5~D

SIR472DP-T1-GE3_POWERPAK8-5~D
+VCCP PWMG2 2 1
@ 2.2_0603_5%~D

Item20_X03_power

2
CPU_B+

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D
1
UGATEG
PHASEG
LGATEG
0.1U_0402_16V7K~D

COMPG

BOOTG
2

5
54.9_0402_1%
130_0402_1%~D

PU702 PC722 PQ705 PQ706

FBG
PR722

PR720

5 1 0.1U_0603_25V7K~D

2
VCC BOOT

1
PC724

PC725

PC726

PC727

PC728
1

VSUMG- PC223 2 1 6 8
FCCM UGATE
2

2
@ 0.22U_0402_6.3V6K~D 2 7 4 4 @
PC228 2 PWM PHASE
1

40
39
38
37
36
35
34
33
32
31

1
0_0603_5%
PU701 3 4
(10) VR_SVID_DAT GND LGATE

PR725
0.22U_0402_6.3V6K~D

ISUMNG
RTNG
FBG
COMPG
PGOODG
PWM2G
LGATE1G
PHASE1G
UGATE1G
BOOT1G
9 PL703

3
2
1

3
2
1
(10) VR_SVID_ALRT# @ PR736 0_0402_5%~D PGND 0.36UH_ETQP4LR36AFC_28A_20%~D
1 2 @ ISL6208CRZ-T_QFN8~D 4 1
+5VS +VCC_CORE

2
(10) VR_SVID_CLK BOOT2 @ PR729
1 30
ISUMPG BOOT2

4.7_1206_5%
Alert# PU resister need close CPU, ISEN1G 2 29 UGATE2 0_0603_5%~D +5VS PQ707 PQ708 3 2 PR726

SIR818DP-T1_POWERPAK-SO8-5~D

SIR818DP-T1_POWERPAK-SO8-5~D
ISEN1G UGATE2

1
so the PU resister in HW schematic. ISEN2G 3 28 PHASE2 1 2 PR728 2 1 ISEN1
ISEN2G PHASE2

PR727
NTCG 4 27 LGATE2 PR730 @ ISEN3 1 2 10K_0402_1%~D
but DAT and CLK need close PWM-IC,

Item20_X03_power
VR_SVID_CLK NTCG LGATE2

680P_0402_50V7K~D
5 26 1 2 10K_0603_1%
so the PU resister in POWER schematic. VR_SVID_ALRT# SCLK VCCP
6 ALERT# VDD 25
VR_SVID_DAT 7 24 0_0603_5% PR721 +5VALW 4 4 PR731

1 2
SDA PWM3 LGATE1
8 23 2 1 PR732 2 1 ISEN2
VR_HOT# LGATE1

PC729
1 PR733 2 9 22 PHASE1 VSUM+ 1 2 10K_0402_1%~D
(47) VR_ON VR_ON PHASE1
1

7,52) VR_HOT# UGATE1 1_0603_5% @ 3.65K_0603_1%

1U_0603_10V6K~D
10 21
NTC UGATE1

ISEN3/FB2

1U_0603_10V6K~D
PC735 0_0402_5%~D

1
2
3

1
2
3

2
PC731
43P_0603_50V8 PR738 PR724 +5VS PR735

PGOOD
BOOT1
ISUMN
2

ISUMP

COMP
ISEN2
ISEN1
@ PR737 1 2 1 2 41 2 1 VSUM-
2 1

RTN
TP

PC732
C 1 2 PH703 1_0402_5% C

FB
+VCCP
499_0402_1%~D 3.83K_0402_1% 1_0603_5%

SIR472DP-T1-GE3_POWERPAK8-5~D

SIR472DP-T1-GE3_POWERPAK8-5~D
470KB_0402_5%_ERTJ0EV474J ISL95836HRTZ-T_TQFN40_5X5~D

11
12
13
14
15
16
17
18
19
20

2
2 1 Item21_X03_power
PR739 CPU_B+

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D
27.4K_0402_1%

5
GFX_B+ BOOT1 PQ709 PQ710 add 10/26
10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D

1 1 1
VGATE (6,16)

100U_25V_M

100U_25V_M

100U_25V_M
design change

1
+ + +

PC737

PC738

PC739

PC740

PC733

PC734

PC766
@ @
PR734
1

1
PC198

PC224

PC200

PC194

1.91K_0402_1%

2
PQ718 UGATE2 @ 2 2 2
2 1 +3VS 4 4
CSD87351Q5D_SON8~D
2

2
1

UGATE2G 2
PL704

3
2
1

3
2
1
PL706 0.36UH_ETQP4LR36AFC_28A_20%~D
7 0.22UH_FDUE0640-H-R22M=P3_25A_20%~D PHASE2 4 1
+VCC_GFXCORE_AXG +VCC_CORE
1 2 4.7_1206_5%

PHASE2G 3 6 2 1
1

4.7_1206_5%
5 PC742 3 2

SIR818DP-T1_POWERPAK-SO8-5~D

SIR818DP-T1_POWERPAK-SO8-5~D
5

1
680P_0402_50V7K~DPR1133

LGATE2G 4 PR743
0.1U_0603_25V7K~D PQ711 PQ712

PR744
3.65K_0603_1%

COMP BOOT2 2 1 2 1
1

FB
10K_0402_1%~D

680P_0402_50V7K~D
2.2_0603_5%~D
1

2
10K_0603_1%

PR783
1

PR780

PR781

1_0402_5% PR746 PR747

8

1 2
PC1324

PR782

LGATE2 4 4 ISEN2 1 2 2 1 ISEN1

PC744
PC768 PR768 10K_0603_1% 10K_0402_1%~D
2

VSUMG+ VSUMG- 680P_0402_50V7K~D 2K_0402_1%~D PC748 PR750

2

1 2 1 2 1 2 2 1
2

2
ISEN2G ISEN1G PR748 PR749

1
2
3

1
2
3
47P_0402_50V8J~D 5.76K_0402_1% VSUM+
1 2 2 1 ISEN3
@ PR740
@PR740 0_0402_5%~D PC749 PR754 3.65K_0603_1% 10K_0402_1%~D
+5VS 1 2 1 2 1 2 1 2 1 2 PR752
+5VS PR751 PC752 VSUM-
1U_0603_10V6K~D

2 1

SIR472DP-T1-GE3_POWERPAK8-5~D

SIR472DP-T1-GE3_POWERPAK8-5~D
@ PC743 499_0402_1%~D470P_0402_50V7K~D 267K_0402_1%~D150P_0402_50V8J~D 1_0402_5%
1

10P_0402_25V8J 1 2 CPU_B+
1
0_0603_5%

PC153

COMP PR755

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D
2 1 2 1

5
PR179

PR230 3.74K_0603_1%~D PQ713 PQ714

2

2.2_0603_5%~D
ISEN2
ISEN1
ISEN3

1
B B

PC756

PC757

PC758

@ PC759
1

@ PC745
Item20_X03_power

330P_0402_50V7K~D

PU703 PC177 2 1

2
5 1 0.1U_0603_25V7K~D 0.22U_0402_6.3V6K~D PC760 UGATE1 4 4
2

VCC BOOT
1

PC761

PC750 1 2
6 8 UGATE2G VSUM- 2 1 330P_0402_50V7K~D
FCCM UGATE 0.22U_0402_6.3V6K~D VCCSENSE (10) DCR:0.82mOHM
2

2 7 PHASE2G PC751 @ 1 2 PL705

3
2
1

3
2
1
PWM PHASE PC762 VSSSENSE (10) 0.36UH_ETQP4LR36AFC_28A_20%~D
2 1
3 4 LGATE2G 0.22U_0402_6.3V6K~D 0.01U_0402_16V7K~D PHASE1 4 1
GND LGATE +VCC_CORE

4.7_1206_5%
9 PC764 3 2

SIR818DP-T1_POWERPAK-SO8-5~D

SIR818DP-T1_POWERPAK-SO8-5~D
PGND
1

1
0_0603_5%

PR760 0.1U_0603_25V7K~D PQ715 PQ716

PR229

PR761
ISL6208CRZ-T_QFN8~D BOOT1 2 1 2 1
VSUM+

680P_0402_50V7K~D
2.2_0603_5%~D
1

@ PR762 PR763

1 2
2

LGATE1 4