1/8/2020

VLSI DESIGN FLOW

Verilog Refresher

Sneh Saurabh

Syntax and Semantics: Lexical Rules

Lexical Example
 Lexical convention of Verilog similar to C
 Case Sensitive // This is a comment
 All keywords in lower case
 White space can contain the characters /*
for blanks, tabs, newlines, and form This is a block comment
feeds: ignored except in string and */
separators for tokens
 Single line comment: //
 Multiple line comments: /* … */

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Syntax and Semantics: Identifiers

Identifiers Example
 Names used to give an object, such as a register or a
function or a module
Module_top
 Rules Register_123
 Must begin with an alphabetic character or Function_foo
underscore (a-z A-Z _)
 Can contain alphanumeric character, _, $ (a-z A-Z \1st_module
0-9 _, $)
 Length < 1024
 Any character can be used in an identifier by
“escaping” the identifier
 “Escaping” : preceding the identifier with a
backslash “\”
 “Escaped” identifier ends with a white space

VLSI Design Flow: S. Saurabh RTL: Verilog 3

Syntax and Semantics: Numbers (1)

Numbers Verilog Internal Representation

 Can be specified in decimal, hexadecimal, 1 0000 0000 0000 0000 0000
octal or binary format 0000 0000 0001
 Integers: 1’b1 1
-<size>’<radix><value> 8’ha1 1010 0001
 - for negative sign 6’o71 111 001
 if size not specified, size=32 assumed
 <radix> can be ‘b’, ‘o’, ‘d’, ‘h’ for binary,
octal, decimal, hexadecimal
respectively
 radix and hex digits (a, b, c, d, e, f) are
case insensitive
 spaces are allowed between the
<size>, <radix> and <value>

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Syntax and Semantics: Numbers (2)

Numbers
Verilog Internal
 Integers:
Representation
-<size>’<radix><value>
 When <size> is smaller than <value> 6’h88 00 1000
then leftmost bits are truncated
 When <size> is greater than <value>
then leftmost bits are filled with 8’b1 0000 0001
 ‘0’ if leftmost bit in <value> is 0/1
8’bz zzzz zzzz
 ‘Z’ if leftmost bit in <value> is ‘Z’
 ‘X’ if leftmost bit in <value> is ‘X’ 8’b100z00?1 100z 00z1
 ‘Z’ represents high impedance
8’b1010_1010 1010 1010
 ‘X’ represents “don’t care” or “unknown”
 ‘?’ is an alternative for ‘z’
 ‘_’ can be used in the middle of number
to enhance readability
VLSI Design Flow: S. Saurabh RTL: Verilog 5

Syntax and Semantics: Numbers (3)

Numbers
 Real Numbers:
 Can be represented in decimal or scientific notation:
 <>.<>
 <mantissa>E<exponent>
 Real numbers cannot contain ‘Z’ or ‘X’
 Real numbers are assigned to nearest integer, when assigning to an integer

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Syntax and Semantics: Modules

Modules
 Modules are building blocks of a Verilog design
 Modules are instantiated inside another modules to create a design hierarchy
 Instantiation of a module means using that module in another higher-level module
 module starts a module description, endmodule ends a module description

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Modules: Example

Problem 11:

Write Verilog code to represent the following hierarchy of a design. The names shown in the figure
are the names of the module. Take arbitrary names for name of Instances.

module Top; module Bottom_1;

Mid m1; endmodule
Bottom_2 b2;
endmodule
module Bottom_2;
module Mid; endmodule
Bottom_1 b1;
endmodule

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Syntax and Semantics: Ports (1)

Ports module top(clock, reset, test_port, data,

counter_out);
 Allow communication between the module
and the environment input clock;
 Ports can be input, output or inout input reset;
 Syntax: inout test_port;
input [3:0]data;
 input [left_range:right_range] output [3:0]counter_out;
<list_of_identifiers>;
 output [left_range:right_range] endmodule
<list_of_identifiers>;
 inout [left_range:right_range]
<list_of_identifiers>;
 Port-names are specified in the module
declaration

VLSI Design Flow: S. Saurabh RTL: Verilog 9

Syntax and Semantics: Ports (2)

Ports in a module can be connected in the module mid(clock, d_in, d_out);
instantiation in two ways: input clock;
input d_in;
 By order (implicit connection) output d_out;
 Ports connected automatically in the endmodule
instantiation based on order specified in the
module declaration module top(c, p_in, p_out);
 Difficult to debug …
mid m1(c, p_in, p_out);
 By name (explicit connection) endmodule By order
 Ports connected by explicitly giving names
 Order not important module top(c, p_in, p_out);
…
mid m1(.clock(c), .d_in(p_in),
.d_out(p_out));
endmodule
By name

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Syntax and Semantics: Block of statement

begin
 A group of statements within begin and end …
forms a block end

 A name can be given to a block

begin : my_block_name
 A block can be disabled using disable …
end

begin : my_while_block
…
while (enable) begin
….
disable my_while_block
end
end

VLSI Design Flow: S. Saurabh RTL: Verilog 11

Syntax and Semantics: Data types (1)

Two primary data types: module mid(c, d_in, d_out);
input c;
 Nets input d_in;
output d_out;
 Registers endmodule

module top(c, p_in, p_out);

…
Nets wire w1;
 Represent structural connections reg p_out;
 Cannot store value mid m1(.c(c), .d_in(p_in), .d_out(w1));
 wire, supply0, supply1, wand, wor mid m2(.c(c), .d_in(p_in), .d_out(w2));
 Signals that are not declared but are used in always @ (posedge c)
connections are of type wire begin
p_out <= w1; Implicit
end
endmodule wire

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Syntax and Semantics: Data types (2)

Registers module top(c, p_in, p_out);

…
 Represent variables that store value
 reg reg p_out;
 Registers store last value assigned, until it is
changed by another assignment always @ (posedge c)
begin
 If a signal is assigned within a procedural p_out <= p_in;
block, then it must be of type register end
 Array of registers can be created to model
memory endmodule

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Syntax and Semantics: primitive gates

 Verilog primitive gates available for Example:

modelling logic gates
 and, nand, or, nor, xor, xnor module mygates(a, b, en, y1, y2, y3);
 First terminal is output and rest are inputs input a;
input b;
input en;
 Transmission gates available for output y1;
modelling different types of output y2;
buffers/inverters/tri-states output y3;
 buf, not, bufif0, bufif1, notif0, notif1
and a1(y1, a, b);
 Models combinational logic and a2(y2, a, b, en);
bufif0 b1(y3, a, en);

endmodule

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Syntax and Semantics: Strength and value

Rule 1: If two drivers of a net have the same
strength priority and value, then the net result will
have the same value and strength priority (no
conflict)

Rule 2: If two or more drivers drive a signal then

 Signals have two attributes: strength &
value:
 Examples: weak0, weak1, strong0,
strong1, pull0, supply1, etc..
Resolution: Signal strength priority used
to resolve which value should appear on
a net or gate output, in case of conflict
it will have the value of the driver with highest
strength priority
Rule 3: If two drivers of a net have the same
strength priority but different values then signal
value will be unknown and it will have the same
strength priority as both drivers

VLSI Design Flow: S. Saurabh RTL: Verilog 15

Strength priority and levels: Resolution

Signal Signal Strength Verilog
Strength Description Keyword
Priority
7 Supply Drive supply0,
Problem 12:
supply1
6 Strong Pull strong0, Find the value & strength at Z.
strong1
A B Z
5 Pull Drive pull0, pull1
pull0 pull0 pull0
4 Large capacitance large
supply0 pull0 supply0
3 Weak drive weak0, weak1
2 Medium medium supply0 weak1 supply0
capacitance
pull0 pull1 Value=x,
1 Small capacitance small strength same
0 High Impedance highz0, highz1 as pull0/pull1

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Syntax and Semantics: Operators

Example
 Arithmetic (+, -, * / etc.), Logical (!, &&, ||)
and Relational (<, >, == etc.) operators input [3:0] A;
similar to “C” output Y;
reg Y;
 &, ~&, |, ~|, ^, ~^: Reduction operator reg [7:0]my_reg;
perform a bit-wise operation on a single reg [3:0]part_my_reg;
operand to produce a single bit result. reg [11:0]concat_reg;
reg [19:0]rep_reg;
 []: Bit-select or part-select
Y=&A;
 {}: Concatenation operator, combines
(concatenates) the bits of two or more data part_my_reg = my_reg[6:3];
objects
concat_reg = {part_my_reg, my_reg};
 {N{}}: Replication operator (Multiple
concatenations performed N times) rep_reg = {5{part_my_reg}};

VLSI Design Flow: S. Saurabh RTL: Verilog 17

Syntax and Semantics: Control Statements

Example 1:
 Statements such as if-else, for, case,
while, repeat similar to “C” if (sel == 1’b0) begin
y = a;
end
 casez: treats ‘z’ as don’t cares
else begin
y = b;
 casex: treats ‘x’ and ‘z’ as don’t cares end
 for loop:
Example 2:
 No ++, -- operator
 The number of loop must be inferable
at time of synthesis: amount of input [1:0]sel;
hardware is known case (sel)
0: y = a;
 if-else, case: all cases must be 1: y =b;
covered for inferring combinational 2: y = c;
logic default: y = d;
endcase
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Syntax and Semantics: Delay Specification

 Delay specifies a time in which assigned values propagate through nets or from input pins to
output pins of a gate

 Delay is used in simulation and ignored in synthesis

 One delay value can be specified as:

 #d
 #(d)
 When only one delay value is specified then for all transitions the same delay ‘d’ is taken

 Two delay values can be specified as:

 #(d1, d2) : rise and fall delay

 Three delay values can be specified as:

 #(d1, d2, d3) : rise, fall and turn-off delay

VLSI Design Flow: S. Saurabh RTL: Verilog 19

Syntax and Semantics: Initial block

Example:
 Block starting with initial
initial begin
 Initial block is executed once at the x = 0;
beginning of the simulation y = 1;
reset = 0;
 If there are multiple Initial blocks, all of end
them are executed at the beginning of
the simulation time
 Initial blocks are useful in writing test-
benches

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Syntax and Semantics: Always block

 Block starting with always Example:
 Always block executes throughout reg y; Register
simulation reg q;
Sensitivity
always @(a or b or sel)
 Always block has a sensitivity list that begin list
specifies when to execute that block y = 0;
1. Level sensitive : combinational if (sel == 0) begin
element or latch y = a;
end else begin
2. Edge sensitive : flip-flop
y = b;
end
 Whatever is specified after @ (at) denotes end
the triggering condition for the Always Sensitivity
block always @(posedge clk)
begin list
 In an Always block only reg or integer data q <= d;
type signals can be assigned end
VLSI Design Flow: S. Saurabh RTL: Verilog 21

Syntax and Semantics: posedge/negedge

Posedge Negedge
 Transition from 0, x, and z to 1  Transition from 1, x, and z to 0
 Transition from 0 to x or z.  Transition from 1 to x or z.

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Syntax and Semantics: Multiple Always/Initial block

Example:  If there are multiple Always block and Initial block in
the same module, then all these blocks start executing
reg y; at the start of the simulation and all these blocks
reg q; execute concurrently

initial begin  All three blocks execute concurrently in the example

y = 0; shown
q = 0;
end

always @(posedge clk)

begin
y <= d;
end

always @(posedge clk)

begin
q <= d;
end
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Syntax and Semantics: assign statement

Example:
 assign statement used to continuously
drive a net module myand2(a, b, y);
input a;
 No sensitivity list input b;
output y;
 Models combinational logic
assign y = a&b;

endmodule

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Syntax and Semantics: blocking and non-blocking

assignment (1)

Blocking Non-blocking
Assignment Assignment
Symbol = <=

Execution Execution of next Execution of next

statement blocked statement not
until the current blocked until the
statement is current statement
executed is executed

Multiple Executes Executes

statement sequentially parallelly

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Syntax and Semantics: functions and tasks (1)

functions tasks
 functions and tasks can be
used to model repeated code
Input / Can have one or Can have zero or
 function, endfunction, task, Output multiple inputs, but multiple inputs,
endtask only one output outputs, inouts
Timing Cannot have delays Can have delays
Delay modelled by posedge, modelled by posedge,
negedge, # negedge, #
Model Only combinational Both combinational
circuit and sequential circuits
Call Can call another Can call other task or
function but cannot function
call other task

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Syntax and Semantics: functions and tasks (2)

Example function: Example task:
module mymodule (data_in, data_out);
module mymodule(d1, d2, d3, o1); input [7:0] data_in; output [3:0]data_out; reg
input d1, d2, d3; [3:0]data_out;
output o1; always @(data_in)
count_zeros(data_in, data_out);
function func;
input a, b, c; task count_zeros;
begin input [7:0] data; output [3:0]count; reg
func = a+b-c; [3:0]count;
end integer i;
endfunction begin
count = 0;
assign o1 = func(d1, d2, d3); for (i = 0; i <= 7; i = i + 1)
if (data[i] == 0) count = count + 1;
endmodule end
endtask
endmodule

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blocking and non-blocking assignment: Exercise

Problem 13:
For the following Verilog code, find the time-instant Answer:
at which each of the assignments take place:
module mymodule();
module mymodule(); reg a, b, c, d, e, f;
reg a, b, c, d, e, f;
initial begin : blocking
initial begin : blocking a = #10 1'b1; // time = 10
a = #10 1'b1; b = #20 1'b0; // time = 30
b = #20 1'b0; c = #30 1'b1; // time = 60
c = #30 1'b1; end
end
initial begin : nonblocking
initial begin : nonblocking d <= #10 1'b1; // time = 10
d <= #10 1'b1; e <= #20 1'b0; // time = 20
e <= #20 1'b0; f <= #30 1'b1; // time = 30
f <= #30 1'b1; end
end
endmodule
endmodule
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Syntax and Semantics: System Tasks and Functions

 Name of system tasks and functions start with $

 Used for generating input and output during simulation
 Example: $display, $probe, $monitor, $stop, $finish, $reset, $random, $time etc..
 These functions are ignored by synthesis tools

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References

 http://www.asic-world.com/
 Verilog Language Reference Manual: IEEE Std 1364-2001
 Application-Specific Integrated Circuits, Michael Smith, Addison-Wesley Professional;
1 edition (June 20, 1997)
 Verilog HDL synthesis : a practical primer, J. Bhaskar

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