Comput

erOr
gani
zat
ion

LAQS

UNI
T1

1)Di
scussaboutdi
ff
erentt
ypesofaddr
essi
ngmodes.
ANS:-Thet erm addressingmodesr eferstothewayi nwhi cht heoperandofani nstr
uct
ioni
s
speci
fied.Theaddr essingmodespeci fi
esar uleforinterpr
etingormodi f
yingt headdressfi
eld
oftheinst ructi
onbef or
et heoperandisactuall
yexecut ed.
Addressi ngmodesusedby8086mi cr
oprocessoraredi scussedbelow:
1.I mpl i
edmode: :
Ini mpl
iedaddressi
ngt heoper andisspecifi
edi nt
hei nstructi
onit
sel
f.In
thismodet hedat ais8bit
sor16bi tslonganddat aisthepartofinstruction.
Zero
addr essinstr
uctionaredesignedwithimpl i
edaddr essingmode.

Exampl
e:CLC(
usedt
oresetCar
ryf
lagt
o0)

2.Immediateaddressingmode( symbol#)
:I
nthismodedataispresenti
naddressfiel
dof
i
nstruct
ion.Desi
gnedlikeoneaddressi
nstr
ucti
onformat
.
Note:Li
mitati
oni
nt heimmediatemodeisthatther
angeofconstantsar
erestr
ict
edby
sizeofaddressf
iel
d.

Exampl
e:MOVAL,
35H(
mov
ethedat
a35Hi
ntoALr
egi
ster
)

3.Registermode:Inregist
eraddressingtheoperandisplacedi
noneof8bitor16bit
generalpurposeregi
sters.Thedatai si
ntheregi
stert
hatisspeci
fi
edbyt
heinstr
ucti
on.
Hereoner egist
erref
erenceisrequiredtoaccessthedata.
Exampl
e:MOVAX, CX(mov ethecontentsofCXr egistertoAXr egister)
4.RegisterI
ndir
ectmode: I
nthisaddressi
ngt heoper and’soffsetisplacedinanyoneof
theregist
ersBX,BP,SI,
DIasspecifi
edinthei nstr
uction.Theef f
ectiv
eaddr essoft
hedata
i
sint hebaseregisteroranindexregist
erthatisspeci f
iedbyt heinstruct
ion.
Heret woregi
sterrefer
enceisrequir
edt oaccesst hedat a.

The8086CPUsl etyouaccessmemor
yindi
rect
lyt
hrougharegi
sterusi
ngther
egist
er
indir
ectaddressi
ngmodes.
MOVAX, [BX](
mov ethecontent
sofmemoryl
ocati
onsaddressedbyt
heregist
erBXtothe
r
egi
sterAX)

5.Aut oIndexed( incrementmode) :Eff

ecti
veaddr essoftheoperandisthecontent
sofa
regi
sterspecifi
edi ntheinstruct
ion.Aft
eraccessi ngt
heoperand,thecontent
softhis
regi
sterar eautomat i
cal
lyincrementedtopoi nttothenextconsecut
ivememor y
l
ocation.(R1)+.
Hereoner egi
sterrefer
ence,onememor yref
er enceandoneALUoper ati
onisrequir
edto
accesst hedata.
Exampl e:
AddR1, (R2)+/ /OR
R1=R1+M[ R2]
R2=R2+d
Useful
forsteppi ngthr
oughar raysinal oop.R2–st artofarrayd–sizeofanelement

6.Aut oindexed(decr ementmode) :Effecti

veaddressoftheoperandisthecontent
sofa
regi
sterspecifi
edi nthei nst
ructi
on.Bef or
eaccessingtheoperand,
thecontentsofthi
s
regi
sterareautomat i
callydecrementedt opointtothepr
evi
ousconsecutivememor y
l
ocation.–(R1)
Hereoner egisterrefer
ence,onememor yref
erenceandoneALUoper ati
onisrequi
redto
accesst hedata.
Exampl e:
AddR1, -(R2) // OR
R2=R2- d
R1=R1+M[ R2]
Autodecrementmodei ssameasaut oincr
ementmode.Bot hcanalsobeusedt oimplementa
st
ackaspushandpop.Aut oi ncrementandAut odecrementmodesar eusefulf
or
i
mpl ementi
ng“ Last-
In-
Fi r
st-
Out ”datastruct
ur es.

7.Di
rectaddressi
ng/Absolut
eaddressi
ngMode( symbol[])
:Theoperand’soff
seti
s
gi
venintheinstr
ucti
onasan8bitor16bitdispl
acementel
ement.I
nt hisaddr
essi
ng
modethe16bi teff
ecti
veaddr
essofthedataisthepar
tofthei
nstr
uct i
on.
 Her
eonl
yonememor
yref
erenceoper
ati
oni
srequi
redt
oaccesst
hedat
a.

Exampl
e:ADDAL,
[
0301]/
/addt
hecont
ent
sofof
fsetaddr
ess0301t
oAL

8.Indi
rectaddr essingMode( sy mbol@ or( )):
Inthismodeaddr essfiel
dofinstr
uct
ion
containst headdr essofef fect iveaddr ess. Heretwor eferencesarerequi
red.
1streferencet ogetef fectiveaddr ess.
2ndr eferencet oaccesst hedat a.
 Basedont heav ail
abil
ityofEf fectiveaddr ess,Indirectmodeisoft wokind:
a)Regi sterIndirect:
Int hi smodeef fect i
veaddr essi si
ntheregist
er,and
cor r
espondi ngregist ernamewi llbemai ntainedi ntheaddressfi
eldofan
instruct i
on.
Her eoner egisterref erence,onememor yreferenceisrequi
redtoaccessthedat
a.
b)Memor yIndirect:
Int hi smodeef fect i
veaddr essisinthememor y
,and
cor r
espondi ngmemor yaddr esswi l
lbemai ntainedintheaddressfiel
dofan
instruct i
on.
Her etwomemor yr ef erencei srequi r
edt oaccesst hedata.

9.I
ndexedaddr essi
ngmode: Theoper
and’
soffseti
sthesum oft
hecont
entofani
ndex
regi
sterSIorDIandan8bi tor16bi
tdi
spl
acement.
Example:MOVAX, [SI+05]

2)Def
ineani
nst
ruct
ionf
ormat
?Expl
aindi
ff
erentt
ypesofi
nst
ruct
ionf
ormat
sin
det
ail
.
ANS:-Aninstr
uct i
onincomput ercomprisesofgroupscal
ledf i
elds.Thesefiel
dcontains
di
ff
erentinf
ormat i
onasf orcomput er
sev er
ythi
ngi si
n0and1soeachf i
eldhasdiff
erent
si
gni
ficanceont hebasisofwhi chaCPUdeci dewhattoper f
orm.
Themostcommonf iel
dsare:
 Oper ationfi
eldwhichspecifi
estheoperati
ontobeper f
ormedl i
keaddit
ion.
 Addr essf i
eldwhichcontai
nthelocati
onofoper and,i
.e.,r
egist
erormemor yl
ocat
ion.

Zer
oAddr
essI
nst
ruct
ions–
Astackbasedcomputerdonotuseaddressfi
eldi
ninst
ruct
ion.
Toev
aluat
eaexpr
essi
onf
ir
sti
t
i
sconv er
tedtor
ever
ePol i
shNotat
ioni
.e.Postf
ixNotat
ion.
Expr
ession:X=(A+B)*(
C+D)
Postf
ixed:X=AB+CD+*
TOPmeanst opofstack
M[X]i
sanymemor ylocati
on
PUSH A TOP=A

PUSH B TOP=B

ADD TOP=A+B

PUSH C TOP=C

PUSH D TOP=D

ADD TOP=C+D

MUL TOP=(
C+D)
*(A+B)

POP X M[
X]=TOP

OneAddr essInstr
ucti
ons–
Thisuseai mpli
edACCUMULATORr egist
erf
ordatamanipul
ati
on.
Oneoperandi
sin
accumulatorandotherisi
nregi
sterormemor yl
ocat
ion.
Impl
iedmeanst
hattheCPUal
ready
knowthatoneoper andisi
naccumul at
orsother
eisnoneedtospeci
fyi
t.

Expr
essi
on:X=( A+B)
*(C+D)
ACisaccumul
ator
M[
]isanymemorylocat
ion
M[
T]istempor
aryl
ocati
on
LOAD A AC=M[
A]

ADD B AC=AC+M[
B]

STORE T M[
T]=AC

LOAD C AC=M[
C]

ADD D AC=AC+M[
D]

MUL T AC=AC*M[
T]

STORE X M[
X]=AC
TwoAddr essInstr
uctions–
Thisi
scommoni ncommer cialcomput ers.Heretwoaddresscanbespeci
fiedintheinst
ruct
ion.
Unli
keearli
erinoneaddr essinstructi
onther esul
twasstoredinaccumul
atorhereresul
tcanbe
stor
edatdiffer
entlocati
onr atherthanjustaccumulat
or,butrequi
remorenumberofbi tt
o
repr
esentaddress.

Heredesti
nati
onaddresscanal
socontai
noperand.
Expr
ession:X=(A+B)*(C+D) R1,
R2ar er
egister
s
M[]i
sanymemor ylocation
MOV R1,
A R1=M[
A]

ADD R1,
B R1=R1+M[
B]

MOV R2,
C R2=C

ADD R2,
D R2=R2+D

MUL R1,
R2 R1=R1*R2

MOV X,
R1 M[
X]=R1

ThreeAddressInstructi
ons–
Thishasthreeaddressf i
eldtospeci
fyar egist
eroramemor ylocati
on.Progr am cr
eatedar
e
muchshor tinsi
zebutnumberofbi t
speri nstr
ucti
onincr
ease.Theseinstructionsmake
creat
ionofprogram mucheasi erbutitdoesnotmeant hatprogram wil
lrunmuchf ast
er
becausenowi nstr
uctiononlycontai
nmor einf
ormati
onbuteachmi crooper ation(
changi
ng
cont
entofr
egi
ster
,loadi
ngaddr
essi
naddr
essbuset
c.)wi
l
lbeper
for
medi
nonecy
cleonl
y.

Expressi
on:X=( A+B)*(
C+D)
R1,R2areregi
sters
M[]i
sanymemor ylocat
ion
ADD R1,
A,B R1=M[
A]+M[
B]

ADD R2,
C,D R2=M[
C]+M[
D]

MUL X,
R1,
R2 M[
X]=R1*R2
3)Expl
ain
i
. I mpli
edmode
ii
. I mmediat
emode
i
ii
. Regi st
ermode
i
v. Regi st
eri
ndirectmode
v. Di r
ectaddressingmodewi
thexampl
es

 ANS:
-
i
. I
mpliedmode:Ini
mpliedaddressi
ngtheoperandi
sspeci
fi
edintheinst
ruct
ion
i
tsel
f.I
nthi
smodet hedatais8bitsor16bit
slonganddat
aisthepartof
i
nstr
ucti
on.Zer
oaddressinstr
ucti
onaredesi
gnedwithi
mpli
edaddressi
ngmode.

Exampl
e:CLC(
usedt
oresetCar
ryf
lagt
o0)

i
i. I
mmedi at
eaddr essingmode( symbol#):
Inthismodedat aispresenti
naddr
ess
f
iel
dofi nstr
uction.Designedl
ikeoneaddressinstr
uctionf
ormat.
Note:
Limitati
oni ntheimmediatemodeist hattherangeofconstantsar
e
r
estri
ctedbysi zeofaddr essf
iel
d.
 Exampl
e:MOVAL,
35H(
mov
ethedat
a35Hi
ntoALr
egi
ster
)

i
ii
. Registermode:I nregi
steraddressi
ngtheoperandisplacedi
noneof8bitor16
bi
tgener alpurposeregist
ers.Thedataisi
ntheregist
erthati
sspeci
fi
edbythe
i
nstructi
on.
Hereoner egisterr
eferenceisrequi
redtoaccessthedata.

Exampl
e:MOVAX,
CX(
mov
ethecont
ent
sofCXr
egi
stert
oAXr
egi
ster
)
i
v. Regist
erIndi r
ectMode:
I
nr egi
sterindirectaddressingmode,t
headdressofoper
andisplacedinanyone
oftheregisters.Theinstructi
onspeci
fi
esaregist
ert
hatcont
ainstheaddressof
theoperand.
 Exampl
e:
ADDR1,
(R2)

v
. Dir
ectaddressi
ng/Absoluteaddr
essingMode( symbol[]):Theoperand’sof
fset
i
sgiv enint
heinst
ruct
ionasan8bi tor16bitdisplacementelement.I
nt hi
s
addressi
ngmodet he16biteff
ect
iveaddressoft hedataisthepartofthe
i
nstructi
on.
Hereonlyonememor yref
erenceoperat
ionisrequiredtoaccessthedata.

Exampl
e:ADDAL,
[
0301]/
/addt
hecont
ent
sofof
fsetaddr
ess0301t
oAL

4)I
ll
ust
rat
eoneaddr
essandzer
oaddr
essi
nst
ruct
ionf
ormat
swi
thexampl
es.
Zer
oAddr
essI
nst
ruct
ions–
Ast ackbasedcomput erdonotuseaddressf
ieldini
nstr
uct
ion.Toev
aluat
eaexpr
essi
on
fi
rstitisconver
tedtor everePol
i
shNot
ationi
.e.Postf
ixNot
ation.
Expression:X=( A+B)*(C+D)
Post f
ixed:X=AB+CD+*
TOPmeanst opofst ack
M[X]isanymemor ylocation

PUSH A TOP=A

PUSH B TOP=B

ADD TOP=A+B

PUSH C TOP=C

PUSH D TOP=D

ADD TOP=C+D

MUL TOP=(
C+D)
*(A+B)

POP X M[
X]=TOP

OneAddr essInstr
ucti
ons–
Thisuseai mpli
edACCUMULATORr egist
erf
ordatamanipul
ati
on.
Oneoperandi
sin
accumulatorandotherisi
nregi
sterormemorylocat
ion.
Impl
iedmeansthatt
heCPU
al
readyknowt hatoneoperandi
si naccumul
atorsother
eisnoneedtospeci
fyi
t.

Expr
essi
on:X=( A+B)
*(C+D)
ACisaccumul
ator
 M[
]isanymemorylocat
ion
M[
T]istempor
aryl
ocati
on

LOAD A AC=M[
A]

ADD B AC=AC+M[
B]

STORE T M[
T]=AC

LOAD C AC=M[
C]

ADD D AC=AC+M[
D]

MUL T AC=AC*M[
T]

STORE X M[
X]=AC

5)Discussabouti
nstruct
ioncy
cleindet
ail
.
ANS:
- Aprogr
am r
esi
dingi
nthememoryuni
tofacomput
erconsi
stsofasequenceof
i
nstr
ucti
ons.Theseinst
ructi
onsar
eexecutedbytheprocessorbygoi
ngt hr
oughacy
clef
or
eachi
nstr
ucti
on.
Inabasi
ccomput er
,eachinstr
uct
ioncy
cleconsi
stsofthefoll
owingphases:

 Fetchi
nstr
uct i
onfrom memory
.
 Decodetheinstruct
ion.
 Readtheeffecti
veaddressf
rom memor
y.
 Execut
ethei nst
ructi
on.
 6)Expl
ainmemor
yref
erencei
nst
ruct
ionsi
ndet
ail
.
ANS:-Memor yRef er
ence–Thesei nst
ructi
onsr efert
omemor yaddr
essasanoperand.The
otheroperandisalwaysaccumul
ator.Speci
fies12- bi
taddress,
3-bi
topcode(
othert
han111)
and1-bitaddressi
ngmodef ordi
rectandindi
r ectaddressi
ng.

Example–
I
Rr egi
stercont
ains=0001XXXXXXXXXXXX,
i.
e.ADDaft
erf
etchi
nganddecodi
ngofi
nst
ruct
ion
wef i
ndoutthati
tisamemor yr
efer
encei
nst
ruct
ionf
orADDoperat
ion.
Hence,DR← M[ AR]
AC← AC+DR, SC← 0

7)Expl
ainr
egi
sterr
efer
encei
nst
ruct
ion.
ANS:
-Regist
erReference–Theseinst
ruct
ionsper f
orm operat
ionsonregi
stersrathert
han
memoryaddr
esses.TheIR(14–12)is111(dif
ferenti
atesi
tfrom memor yr
eference)andIR(15)
i
s0(di
ffer
ent
iat
esitfrom i
nput
/out
putinst
ruct
ions).Therest12bitsspeci
fyregist
eroperat
ion.
Example–
I
Rr egi
stercontains=0111001000000000,i
.e.CMAafterf
etchanddecodecy
clewef
indout
thati
tisaregisterref
erencei
nst
ructi
onforcomplementaccumulat
or.
Hence,AC← ~AC

8)Expl
aini
nputandout
puti
nst
ruct
ions.
ANS:-Input
/ Output–Theseinst
ruct
ionsareforcommuni cat
ionbet
weencomputerandoutsi
de
envi
ronment .TheIR(14–12)is111(dif
fer
enti
atesitfr
om memor yr
efer
ence)andI
R(15)is1
(di
ff
erenti
atesitfrom r
egi
sterr
efer
enceinst
ructi
ons).Therest12bi
tsspeci
fyI
/Ooperat
ion.

Exampl e–
I
Rr egist
ercontai
ns=1111100000000000,i
.e.I
NPaf t
erfet
chanddecodecy
clewef
indoutthat
i
tisani nput
/outputi
nst
ruct
ionf
orinput
ingcharact
er.Hence,
INPUTchar
act
erfr
om per
ipher
al
device.

9)Expl
ainstackorgani
zat
ioni
ndet
ail
.
ANS:
-St
ackOrganizat
ion

 Ausef ul f
eat uret hati sincl
udedi ntheCPUofmostcomput ersisast ackorl ast-i
n,fi
rst-
out(UFO)l i
st.Ast acki sast oragedev icet hatst oresinfor mationinsuchamannert hat
theitem st oredl astist hefirstitem retrieved.
 Thest acki ndi gitalcomput ersisessent iall
yamemor yuni twithanaddr essr egisterthat
cancountonl y(af t
erani ni
tialvalueisl oadedi ntoit)
.
 Ther egisterthathol dst headdr essf ort hest acki scalledast ackpointer(SP)because
i
tsv aluealway spoi ntsatt het opi t
em i nt hest ack.
 Thet wooper ationsofast ackar et heinser ti
onanddel etionofi t
ems.Howev er,
not hi
ng
i
spushedorpoppedi nacomput erstack.Theseoper at i
onsar esi
mul atedby
i
ncrement i
ngordecr ement i
ngt hest ackpoi nterr egi
ster.
 RegisterSt ackAst ackcanbepl acedi napor tionofal argememor yori tcanbe
organizedasacol l
ect ionofaf initenumberofmemor ywor dsorregisters.Figure3
showst heor gani zationofa64- wor dr egisterst ack.Thest ackpointerregisterSP
 containsabinar
ynumberwhosev al
ueisequaltotheaddressofthewordt
hati
s
currentl
yontopofthest
ack.Threei
temsareplacedinthestack:
A, B,
andC,i
nthat
order.It
em Cisontopofthest
acksothatthecontentofSPisnow3.

Toremovethetopi
tem,thestacki
spoppedbyr
eadi
ngt
hememor
ywor
dataddr
ess3and
decr
ementi
ngthecontentofSP.

 Item Bisnowont opoft hestacksi nceSPhol dsaddr ess2.Toi nsertanewi tem,the

stackispushedbyi ncrement ingSPandwr it
ingawor dint henext-hi
gherlocati
oninthe
stack.Not ethatit
em Chasbeenr eadoutbutnotphy si
callyremov ed.
 Thisdoesnotmat t
erbecausewhent hest acki spushed, anewi t
em iswritt
eninit
s
place.Ina64- wordst ack,thest ackpoi ntercont ai
ns6bi t
sbecause26 =64.
 SinceSPhasonl ysi xbit
s, i
tcannotexceedanumbergr eaterthan63( 111111inbinary)
.
When63i sincrement edby1, ther esultis0si nce111111+1=1000000i nbinary,
butSP
canaccommodat eonl ythesi xl eastsignificantbits.

Simi l
arl
y,when000000i sdecr ement edby1, theresultis111111.Theone- bi
tregi
ster
FULLi ssett o1whent hest acki sful
l,andt heone- bitregisterEMTYi ssetto1whent he
stackisempt yofit
ems.DRi st hedat ar egisterthatholdst hebinarydatatobewr i
t t
en
i
nt oorreadoutoft hestack.
 Init
ial
ly,
SPi sclearedt o0, EMTYi ssett o1, andFULLi sclearedto0, sothatSPpoi nt
sto
thewor dataddr ess0andt hest acki smar kedempt yandnotf ull
.Ifthestackisnotfull
(ifFULL=0) ,
anewi tem isinser tedwi thapushoper at i
on.

Thepushoper
ati
oni
simpl
ement
edwi
tht
hef
oll
owi
ngsequenceofmi
crooper
ati
ons;
SP← SP+1I ncrementstackpoi
nter
M[SP]← DR Writ
eitem ontopoft
hest ack
I
f(SP=0)then(FULL←1)Checki fstackisful
l
EMTY← 0 Mar kthestacknotempty

 Thest ackpointeri sincrement edsot hatitpointstotheaddressoft henext -

higherwor d.
Amemor ywr i
teoper ati
oni nsertsthewor df r
om DRi nt
othetopoft hest ack.Not ethat
SPhol dstheaddr essoft het opoft hestackandt hatM[SP]denotest hememor yword
specif
iedbyt headdr esspr esent l
yavail
ableinSP.
 Thef i
rstit
em st oredi nthest ackisataddr essLThel asti
tem isstoredataddr ess0.
 IfSPreaches0, thest ackisf ul
l ofit
ems, soFULLi ssettoLThiscondi ti
oni sreachedi f
thetopi t
em priort othel astpushwasi nlocation63and,aft
erincrement ingSP, thelast
i
tem isstoredinl ocat i
on0.
 Onceani t
em isst oredi nlocation0, t
herear enomor eemptyregistersint hestack.Ifan
i
tem iswr i
ttenint hest ack,obv i
ouslythest ackcannotbeempt y,soEMTYi sclearedto0.

Anewi t
em i
sdelet
edfr
om t
hestackift
hestackisnotempt
y(i
fEMTY=0)
.Thepopoper
ati
on
consi
stsoft
hefoll
owi
ngsequenceofmicr
ooperati
ons:

DR← M[SP]Readit
em f
rom thet
opofst ack
SP← SP-1Decrementstackpoi
nter
I
f(SP=0)then(
EMTY← 1)Checki fstackisempt
y
FULL← 0 Markthest
acknotful
l

 Thet opitem isr eadfrom t hest ackintoDR.Thest ackpoi nteri

sthendecremented.If
i
tsv aluereacheszer o, thest ackisempt y,soEMTYi ssett o1.
 Thiscondi ti
oni sreachedi ftheitem readwasi nlocat ion1.Oncet hisi
tem isreadout,
SPi sdecrement edandr eachest hev al
ue0, whichi st heinit
ialv
alueofSP.Not ethati
fa
popoper ationr eadsthei tem f r
om locat i
on0andt henSPi sdecremented,SPchanges
to111111, whichi sequi valenttodecimal 63.
 I
nt hisconf i
gurat i
on,thewor dinaddr ess0r eceiv
est helastitem i
nthestack.Notealso
thataner roneousoper ationwi l
l r
esultifthest ackispushedwhenFULL=1orpopped
whenEMTY=1.
UNI
T2

1)Cl
assi
fyf
lagr
egi
steri
n8086andexpl
ainf
lagi
nst
ruct
ionset
.
ANS:-TheFl
agregi
sterisaSpeci
alPurposeRegi
ster
.Dependinguponthevalueofr
esul
taf
ter
anyar
it
hmeti
candlogicaloper
ati
onthefl
agbit
sbecomeset( 1)orreset(
0).
 2)Di
sti
ngui
shbet
weenmi
nmodeandmaxmodeof8086.
ANS:
-
3)Expl
ainthefunct
ionalbl
ockdi
agr
am of8086andwr
it
eaboutt
hef
unct
ionof
eachblock.
ANS:-
Busi
nter
faceuni
t-
 4)Descr
ibeandexpl
aint
hemi ni
mum modeconf
igur
ati
onof8086wi
thr
eadand
wri
tecycl
esofti
mingdiagr
am.
ANS:
-Thet
imi
ngdi
agr
am f
orr
eadoper
ati
oni
nmi
nimum modei
sshowni
nfi
gbel
ow:

Thesear
eexpl
ainedi
nst
eps.
 I. Whenpr ocessori sreadyt oinitiatet hebuscy cle,itappliesapul set oALEdur ingT1.
Beforethef all
ingedgeofALE, theaddr ess, BHE, M/ I
O, DENandDT/ Rmustbest ablei
.e.
DEN=hi ghandDT/ R=0f orinputorDT/ R=1f orout put.
I
I. Att het raili
ngedgeofALE, ICs74LS373or8282l atchest headdr ess.
II
I. Dur ingT2t headdr esssi gnal sar edi sabledandS3- S7al eav ail
ableonAD16/ S3-AD19/ S6
andBHE/ S7.Al soDENi sl ower edt oenabl et ranscei ver.
I
V. I ncaseofi nputoper ation, RDi sact ivateddur i
ngT2andAD°t oAD15goi nhigh
i
mpedancepr eparingf ori nput .
V. I fmemor yorI /Oi nterfacecanper for mt het ransf erimmedi at
ely;therearenowai tstat
es
anddat ai sout putont hebusdur ingT3.
VI. Af terthedat aisaccept edbyt hepr ocessor ,
RDi sr ai
sedhi ghatt hebegi nningofT4.
VII. Upondet ectingt histransi tiondur i
ngT. 4,thememor yorI /Odev i
cewi lldisableitsdat a
signals.
VII
I. Foranout putoper ati
on, processorappl iesWR=0andt hent hedat aont hedat abus
duringT2.
I
X. I nT4, WRi sraisedhi ghanddat asi gnalsar edi sabl ed.
X. Forei theri nputorout putoper ation, DENi sraiseddur ing14t odisabl ethet r
anscei ver.
AlsoM/ I0i ssetaccor di ngt ot henextt ransferatt histimeordur ingnextT1st ate.Thus
l
engt hofbuscy cl
ein8086i sfourcl ockcy cl
e.I fthebusi st obei nactiveaf t
er
compl etionofbuscy cle, thent hegapbet weent hesuccessi vecy clesisfill
edbyi deal
stateclockcy cles.
Whent hememor yorI /Odev i
cei snotabl et or espondqui cklydur ingtransf er
,wai tstates( Tw)
areinsertedbet weenT3andT4bydi sabl ingt heREADYi nputoft he8086.Thebusact i
vity
duri
ngwai tstatei ssameasdur ingT3.

5)Descr
ibepi
ndi
agr
am of8086andexpl
aineachpi
n.
ANS:
-
 AD0-AD15:Addr ess/Databus.Thesear eloworderaddr essbus.Theyar emulti
plexed
wit
hdata.WhenADl inesareusedt otransmitmemor yaddr essthesy mbol Aisused
i
nsteadofAD, forexampleA0- A15.Whendat aaret r
ansmi t
tedov erADl inest
hesy mbol
DisusedinplaceofAD, f
orexampl eD0- D7,D8-
D15orD0- D15.
 A16-A19:Highor deraddressbus.Thesear emultiplexedwi thstatussignals.
 S2,S1,S0:Statuspins.Thesepi nsareactiv
eduringT4, T1andT2st atesandi s
ret
urnedtopassivestate(1,1,1dur
ingT3orTw( whenr eadyisinacti
v e)
.Thesear eused
bythe8288buscont r
oll
erforgenerati
ngal l
thememor yandI /Ooperation)access
contr
olsi
gnals.Anychangei nS2,S1,S0dur i
ngT4i ndicatest hebeginningofabuscy cle.

S2 S1 S0 CHARACTERI
STI
CS

0 0 0 I
nter
ruptacknowl
edge

0 0 1 ReadI
/Opor
t

0 1 0 Wr
it
eI/
Opor
t

0 1 1 Hal
t

1 0 0 Codeaccess

1 0 1 Readmemor
y

1 1 0 Wr
it
ememor
y
S2 S1 S0 CHARACTERI
STI
CS

1 1 1 Passi
vest
ate

 A16/S3,A17/S4,
A18/S5,A19/
S6:Thespeci
fi
edaddr
essl
i
nesar
emul
ti
plexedwi
th
cor
respondi
ngstatussi
gnal
s.

A17/
S4 A16/
S3 FUNCTI
ON

0 0 Ext
rasegmentaccess

0 1 St
acksegmentaccess

1 0 Codesegmentaccess

1 1 Dat
asegmentaccess

 BHE’ /S7:BusHi ghEnabl e/ Status.Dur ingT1i tisl ow.I tisusedt oenabl edat aont ot he
mostsi gnificanthal fofdat abus, D8- D15.8- bitdev iceconnect edt oupperhal foft he
databususeBHE( Act iveLow)si gnal .Itismul tipl exedwi thstat ussi gnal S7.S7si gnal i
s
availabledur i
ngT2, T3andT4.
 RD’:Thi si susedf orr eadoper ation.I ti sanout putsi gnal .Itisact ivewhenl ow.
 READY:Thi sist heacknowl edgementf rom t hememor yorsl owdev icethatt heyhav e
compl etedt hedat at ransf er.Thesi gnal madeav ai l
abl ebyt hedev icesi ssy nchroni zed
bythe8284Acl ockgener at ort opr ovider eadyi nputt ot hemi cr opr ocessor .Thesi gnalis
acti
v ehi gh( 1).
 INTR:I nterruptRequest .Thi si st rigger edinput .Thi si ssampl eddur ingt hel astclock
cyclesofeachi nst r
uct ionf ordet er mi ningt heav ailabi l
ityoft her equest .Ifanyi nterrupt
requesti sf oundpendi ng, thepr ocessorent er st hei nter ruptacknowl edgecy cle.Thi scan
beint ernallymaskedaf terr esultingt hei nterruptenabl ef lag.Thi ssi gnal isact i
vehi gh(1)
andhasbeensy nchr onizedi nter nal l
y.
 NMI:Nonmaskabl ei nterrupt .Thi sisanedget rigger edi nputwhi chr esultsinat ypeI I
i
nterr upt.Asubr outinei st henv ect or edt hroughani nter ruptv ectorl ookupt ablewhi chis
l
ocat edi nt hesy stem memor y.NMIi snon- maskabl ei nternallybysof tware.At r
ansi ti
on
madef r
om l ow( 0)tohi gh( 1)i nitiatest heint erruptatt heendoft hecur r
entinst r
uct i
on.
Thisi nputhasbeensy nchr oni zedi nternally.
 INTA:I nterruptacknowl edge.I tisact ivelow( 0)dur ingT2, T3andTwofeachi nterrupt
acknowl edgecy cle.
 MN/ MX’ :Mi ni
mum/ Maxi mum.Thi spi nsi gnal indi cat eswhatmodet hepr ocessorwi ll
operat ein.
 RQ’/GT1′ ,RQ’ /
GT0′ :Request /Gr ant .Thesepi nsar eusedbyl ocal busmast ersusedt o
forct hemi croprocessort or el
easet hel ocal busatt heendoft hemi croprocessor ’s
currentbuscy cle.Eachoft hepi ni sbi -directional .RQ’ /GT0′ hav ehi gherpr i
oritythan
RQ’/GT1′ .
 LOCK’ :Itsanact ivelowpi n.I tindi cat est hatot hersy stem busmast ershav enotbeen
all
owedt ogai ncont rol oft hesy st em buswhi leLOCK’ i
sact ivel ow( 0) .TheLOCKsi gnal
 wil
lbeact iveuntilthecompl eti
onoft henexti nstructi
on.
 TEST’ :Thisexami nedbya‘ WAIT’ i
nst ructi
on.IftheTESTpi ngoesl ow(0),executi
onwi l
l
conti
nue, el
set hepr ocessorr emai nsi nani dlestate.Theinputi
sinternall
ysy nchr
onized
duri
ngeachoft hecl ockcy cleonl eadi ngedgeoft heclock.
 CLK:Cl ockI nput.Thecl ocki nputpr ovidest hebasi ct
imingforprocessingoper at
ion
andbuscont rolact i
v i
ty.I
tsanasy mmet r
icsquarewav ewitha33%dut ycycle.
 RESET:Thi spinr equi r
est hemi cropr ocessort oterminateitspr
esentact i
vit
y
i
mmedi atel
y.Thesi gnal mustbeact i
vehi gh(1)foratleastfourcl
ockcy cles.
 Vcc:PowerSuppl y (+5VD. C.)
 GND:Gr ound
 QS1,QS0:QueueSt atus.Thesesi gnal sindicatethestatusoftheinternal8086
i
nstructionqueueaccor dingt othet ableshownbel ow

QS1 QS0 STATUS

0 0 Nooper
ati
on

0 1 Fi
rstby
teofopcodef
rom queue

1 0 Empt
ythequeue

1 1 Subsequentby
tef
rom queue

 DT/R:Dat aTr ansmi t

/Recei v
e.Thi spini srequir
edinmi nimum systems, thatwantt o
usean8286or8287dat abust ransceiver.Thedirect
ionofdat afl
owi scont r
oll
ed
thr
ought het ransceiver.
 DEN:Dat aenabl e.Thispi nispr ovidedasanout putenableforthe8286/ 8287i na
minimum sy stem whichusest ransceiv er
.DENi sactivelow(0)duri
ngeachmemor yand
i
nput-outputaccessandf orINTAcy cl
es.
 HOLD/ HOLDA:HOLDi ndicatest hatanot hermasterhasbeenr equest i
ngal ocalbus
.Thisisanact iv
ehi gh(1).Themi croprocessorreceivi
ngt heHOLDr equestwi ll
issue
HLDA( hi
gh)asanacknowl edgementi nthemi ddleofaT4orT1cl ockcy cle.
 ALE:Addr essLat chEnabl e.ALEi sprov i
dedbyt hemi cr
oprocessort ol
atcht headdress
i
ntothe8282or8283addr essl atch.Itisanact i
vehigh(1)pulseduringT1ofanybus
cycl
e.ALEsi gnal i
snev erfloated, i
salway si
nteger.

6)Expl
ainar
chi
tect
ureof8086i
ndet
ail
.
Ans:
-(Laq3)

7)Expl
ainsegmentr
egi
ster
sindet
ail
.
Ans:
-
 8)Expl
ain20bi
tphy
sicaladdr
essgener
ati
oni
n8086.
Ans:-:For mat i
onofaphy si
caladdress:-Segmentregist
erscarr
y16bi tdata,whichi salso
knownasbaseaddr ess.BIU att
aches0asLSBoft hebaseaddr ess.Sonow t hi
saddr ess
becomes20- bi
taddress.Anybase/ poi
nterorindexr
egist
ercarr
y16bi toff
set
.Offsetaddressis
addedinto20- bi
tbaseaddr esswhichfinal
lyforms20bitphysi
caladdressofmemor ylocati
on.
Exampl e:-AssumeDS=2632H, SI
=4567H
DS: 26320H……. .
.0addedbyBI U(orHardwired0)
+SI: 4567H
--
--
--
--
---
---
---
--
--
--
--
--
-
2A887H

9)Expl
ainmi
nimum modepi
nsof8086.
Ans:-Pindef i
niti
onsf r
om 24t o31ar edi f
fer
entf ormi nimum modeandmaxi mum mode.By
usingthesepi nst he8086i tselfgener at esallbuscont rol signalsint heMi ni
mum Mode
Configurat i
onof8086.Thesesi gnal sar e:
PinDef i
ni ti
ons( 24t o31)i nMi nimum Mode:
 I NTA( I
nter ruptAcknowl edge)Out put: Thi sindicat esr ecogniti
onofani nterr uptr equest.
Itconsi stsoft wonegat i
vegoi ngpul sesi nt woconsecut i
vebuscy cl
es.Thef ir
stpul se
i
nf ormst hei nterfacet hati tsrequesthasbeenr ecogni zedanduponr eceiptoft he
secondpul se, theint er
facei st osendt hei nterruptt ypet othepr ocessorov ert hedat a
bus.
 ALE( Addr essLat chEnabl e)out put: Thissi gnal ispr ov i
dedby8086t odemul t
iplexthe
AD0- AD15i ntoA0- A15andD0- D15usi ngext ernal l
at ches.
 DEN( Dat aEnabl e)out put:Thi ssignal informst het ransceiversthattheCPUi sreadyt o
sendorr ecei v edat a.
 DT/ R( Datat ransmi t/Recei ve)out put:Thi ssi gnal isusedt ocont r
oldat aflowdi rection.
Hi ghont hi spi nindi catest hatt he8086i st r
ansmi tti
ngt hedat aandl owi ndi catest hat
the8086i sr eceivingt hedat a.
 M/ I
Oout put:I tisusedt odi stinguishmemor ydat at ransfer,
(M/ I0=HI GH)andI /Odat a
transfer( M/ I0=LOW) .
 WR: Wr iteout put: WRi slowwhenev ert he8086i swr i
ti
ngdat aintomemor yoranI /O
 device.
 HOLDi nput,HLDAoutput:AHIGHonHOLDpi ni
ndicat
est hatanothermast er(DMA)is
requesti
ngtotakeoverthesy
stem bus.Onr ecei
vi
ngHOLDsi gnalprocessorout put
s
HLDAsi gnalHIGHasanacknowl edgment.Atthesamet i
me, processortri
statesthe
system bus.AlowonHOLDgi vest hesy
stem buscontrolbacktot heprocessor.
Processorthenout
putslowsignalonHLDA.

10) Expl
ainmaxi
mum modepi
nsof8086.
Ans:
-Maxi
mum modepi
nsof8086
UNI
T3

1) Di
scussbrief
lyaboutt wopassassembl er.
Ans:-Assembl
erisaprogr
am forconv
er t
ingi
nst
ruct
ionswr i
tteninl
ow-l
evel
assembl
ycodei
nto
rel
ocatabl
emachinecodeandgenerat
ingalongi
nfor
mat i
onf orthel
oader
.

 Anassembl erisatranslatorthattranslatesanassembl erprogram int

oaconv enti
onal
machinelanguagepr ogram.Basi call
y,theassembl ergoesthr oughtheprogr am onel i
ne
atatime,andgener atesmachi necodef orthatinst
ruct
ion.Thent heassembl er
procedestothenex tinstr
uction.Inthisway ,theenti
remachi necodepr ogram i screat
ed.
Formostinstructi
onst hi
spr ocesswor ksf i
ne, f
orexamplefori nst
ruct
ionst hatonly
refer
enceregister
s,theassembl ercancomput ethemachinecodeeasi ly,sincet he
assemblerknowswher ether egi
stersar e.

Consi
deranassembl
eri
nst
ruct
ionl
i
ket
hef
oll
owi
ng
JMPLATER
.
..
.
..
LATER:

 Thisisknownasaf or wardr efer ence.I ft heassembl eri spr ocessi ngt hef i
leonel i
neata
ti
me, theni tdoesn' tknowwher eLATERi swheni tfir
stencount ersthej umpi nstruction.
So,itdoesn' tknowi ft hejumpi sashor tj ump, anearj umporaf arjump.Ther eisal arge
diff
erenceamongstt hesei nstruct ions.Theyar e2, 3,and5by teslongr espect ivel
y .The
assembl erwoul dhav et oguesshowf arawayt heinstruct i
oni sinor dert ogener at ethe
correctinst ruction.Ift heassembl erguesseswr ong, t
hent headdr essesf oral lother
l
abel slateri nthepr ogr am woul dsbewr ong,andt hecodewoul dhav etober egener ated.
Or,theassembl ercoul dal waychooset hewor stcase.Butt hiswoul dmeangener ati
ng
i
nef f
iciencyi nt hepr ogr am, si
nceal ljumpswoul dbeconsi der edfarj umpsandwoul dbe
5by tesl ong, wher eact uall
ymostj umpsar eshor tjumps, whi char eonl y2by teslong.
 So,whati st obedonet oal l
owt heassembl ertogener atet hecor rectinstruction?
Answer :scant hecodet wice.Thef irstt ime, j
ustcounthowl ongt hemachi necode
i
nstruct i
onswi llbe, justt ofindoutt headdr essesofal l t
hel abel s.Also, createat abl e
thathasal istofal l theaddr essesandwher etheywi llbei nt hepr ogr am.Thi st ableis
knownast hesy mbol t
able.Ont hesecondscan, gener atethemachi necode, anduset he
symbol tablet odet er mi nehowf arawayj umpl abelsar e,andt ogener atethemost
effi
cienti nstruction.
 Thisisknownasat wo- passassembl er .Eachpassscanst hepr ogram, t
hef i
r stpass
gener atest hesy mbol tableandt hesecondpassgener atest hemachi necode.Ihav e
createdal i
st i
ngofanassembl erpr ogr am t hathast hemachi necodel isted,andt he
 sy
mbol
tabl
eli
sted.

2) Descr
ibethesetofrulesoftheassemblelanguage.
Ans:-Someofthecommonrulesofassembl
ylev
ell
anguagear
easf
oll
ows:

o Inassemblylanguagethelabelfi
eldcanbeeitheremptyormayspecif
yasymbol
i
c
addr
ess.
I
nstr
ucti
onfieldscanspecif
ypseudoormachi neinstr
ucti
ons.
o Commentf i
eldscanbel ef
tempt yorcanbecomment edwi t
h.
o Upto4charact er
sareonlyall
owedi nthecaseofsymboli
caddresses.
o Thesymboli
caddr essesfi
eldareterminat
edbyacommawher easthecommentf
iel
d
begi
nswithaf orwardsl
ash.

3) Br
ief
lyexpl
aint
heAssembl
eLanguage
i
nstr
ucti
ons(ADD,SUB,
LOAD,
STORE).
4) Br
ief
lyexpl
aintheAssembl
eLanguagei
nst
ruct
ions(
MOV,
CMP,
JUMP)
.

5) Def
inecont
rolmemor
y.Expl
ainmi
cropr
ogr
ammedcont
rolor
gani
zat
ion.

6) Ex plai
noper ationofcont r
oluni tofbasi ccomput erwithdiagram.
Ans: -Cont r
olUni tisthepar tofthecomput er’
scent r
alprocessi
ngunit(
CPU) ,whi
ch
di
rectstheoper at
ionoft hepr ocessor.
Itisther esponsibili
tyoft heControlUnittot el
l t
hecomput er’
smemor y,ari
thmeti
c/l
ogi
c
unitandinputandout putdev i
ceshowt or espondt ot heinst
ructi
onsthathavebeensenttothe
processor.Itfetchesinternal i
nstruct
ionsoft heprogr amsf r
om themai nmemor ytothe
processorinstructi
onr egister,andbasedont hi
sr egistercontent
s,thecontr
olunitgener
atesa
controlsi
gnal thatsuperv i
sest heexecut i
onoft hesei nstr
ucti
ons.

Acontroluni
twor ksbyr eceiv
inginputi nformat i
ontowhichitconver
tsintocont
rolsi
gnals,
whicharethensentt ot hecent r
alpr ocessor .Thecomputer’
sprocessorthentel
lst
heattached
hardwarewhatoper ati
onst operform.Thef unctionst
hatacontroluni
tperfor
msaredependent
onthetypeofCPUbecauset hear chit
ect ureofCPUv ari
esfr
om manuf actur
ertomanufacturer
.
Examplesofdevicest hatr equir
eaCUar e:
a)Cont rol ProcessingUni ts(CPUs)
b)Gr aphicsPr ocessi
ngUni ts(GPUs)
Funct
ionsoft heCont r
olUni t–
a)I tcoor dinatest hesequenceofdat amov ementsinto,outof,andbetweenapr ocessor
’s
manysub- units.
b)I ti
nt erpretsinst ruct
ions.
c) Itcont rolsdat af l
owi nsi
det heprocessor
.
d)I treceiv esext ernali
nst r
uctionsorcommandst owhi chitconvertstosequenceof
cont rolsignals.
e) Itcont rolsmanyexecut i
onuni ts(
i.
e.ALU,dat
abuf f
ersandr egist
ers)cont
ainedwithi
na
CPU.
f)I talsohandl esmul t
ipletasks,suchasfetchi
ng,decoding,executi
onhandli
ngand
storingr esults.

7) Drawandexpl aint hemi cro-i

nstructionf ormat.
Ans:-Themi croi
nstructionf ormatf orthecontrolmemor yisshowni nfi
gure.The20bi tsoft
he
microinstr
ucti
onar ediv i
dedi ntofourfunctionalpar
tsasf ollows:
1.Thet hr
eefiel
dsF1, F2, andF3speci fymicrooperationsforthecomput er.Themi cro
operationsaresubdividedi ntothreef i
eldsofthreebitseach.Thet hreebit
sineachf iel
dare
encodedt ospecifysev endi sti
nctmi crooperati
ons.Thi sgivesatotalof21mi crooperati
ons.
2.TheCDf iel
dselect
sst atusbitcondi t
ions.
3.TheBRf i
eldspecif
iest het ypeofbr ancht obeused.
4.TheADf iel
dcontainsabr anchaddr ess.Theaddr essf i
eldissevenbitswide,sincethe
controlmemor yhas128=2^ 7wor ds.
  Asanexampl
e,ami
croi
nst
ruct
ioncanspeci
fyt
wosi
mul
taneousmi
crooper
ati
onsf
rom
F2andF3andnonef r
om F1.
DR M[AR]withF2=100
PC PC+1wi thF3=101
Theninebitsofthemicrooper
ationf
iel
dswil
lthenbe000100101.
TheCD( conditi
on)fi
eldconsi
stsoft
wobitswhichareencodedt
ospeci
fyf
ourst
atusbi
t
condi
ti
onsaslistedinTabl
e.

 TheBR(
branch)f
iel
dconsi
stsoft
wobi
ts.I
tisused,
inconj
unct
ionwi
tht
headdr
ess
f
iel
dAD,
tochooset
headdr
essoft
henextmi
croi
nst
ruct
ionshowni
nTabl
e.

8) Explai
ntheorganizati
onofhar dwi r
edcontroli
ndetai
l.
Ans:-TheHardwiredContr
olor
ganizat
ioninv
olvesthecont
rol
logi
ctobeimpl
ement
edwi
th
gat
es,fl
ip-
fl
ops,decoder
s,andotherdi
git
alci
rcuit
s.

Thef
oll
owi
ngi
mageshowst
hebl
ockdi
agr
am ofaHar
dwi
redCont
rol
organi
zat
ion.
  AHard-wiredCont r
ol consi
stsoftwodecoder s,asequencecount er,andanumberof
l
ogicgates.
 Aninst
ructionfetchedf r
om thememor yunitisplacedi ntheinstructi
onregi
ster(I
R).
 Thecomponentofani nst
ructi
onregisterincl
udes;Ibi t
,theoper ati
oncode,andbits0
thr
ough11.
 Theoperationcodei nbits12through14ar ecodedwi t
ha3x8decoder .
 Theoutputsoft hedecoderar edesignatedbyt hesymbol sD0t hroughD7.
 Theoperationcodeatbi t15istransferredtoaf l
ip-
flopdesi gnatedbyt hesymbolI.
 Theoperationcodesf rom Bit
s0t hrough11ar eappliedtothecont roll
ogicgates.
 TheSequencecount er(SC)cancounti nbinaryfrom 0t hrough15.

9) Li
stt
hedi
ff
erencesbet
weenhar
dwi
redcont
rolandmi
cropr
ogr
ammed
cont
rol
.

HARDWI
REDCONTROLUNI
T MI
CROPROGRAMMEDCONTROLUNI
T

Hardwir
edcontr
oluni
tgeneratesthecont
rol Micr
programmedcont r
oluni
tgener
ates
si
gnalsneededf
ortheprocessorusingl
ogic t
hecontrolsi
gnalswit
hthehelpofmicr
o
ci
rcui
ts i
nstr
ucti
onsstoredincont
rolmemory
HARDWI
REDCONTROLUNI
T MI
CROPROGRAMMEDCONTROLUNI
T

Hardwi
redcontr
ol unitisf ast
erwhen
comparedtomicropr ogrammedcont rol
unit Thi
sisslowert
hantheotherasmicr
o
asther
equiredcont r
ol signal
saregenerat
ed i
nstr
ucti
onsareusedforgener
ati
ng
wit
hthehelpofhar dwar es si
gnalsher
e

Dif
fi
cul
ttomodif
yasthecontr
olsignal
sthat Easyt
omodifyast
hemodi
ficati
onneed
needtobegener
atedar
ehardwired tobedoneonl
yatt
hei
nst
ructionlev
el

Lesscostli
erthanhardwi
redcont
rol
as
Morecost
li
erasevery
thi
nghast
ober
eal
i
zed onlymicroinstr
uct
ionsareusedf
or
i
ntermsoflogi
cgates gener
atingcontrol
signal
s

Itcannothandl
ecomplexi
nst
ruct
ionsast
he
cir
cuitdesi
gnfori
tbecomescomplex I
tcanhandl
ecompl
exi
nst
ruct
ions

Onl
yli
mit
ednumberofi
nst
ruct
ionsareused Cont
rolsi
gnalsformanyi
nst
ruct
ions
duet
othehar
dwarei
mplement
ation canbegenerated

Usedi
ncomput erthatmakesuseof
Usedincomput
erthatmakesuseofReduced Compl
exInstr
uctionSet
I
nstr
ucti
onSetComputer
s(RI
SC) Computer
s(CI
SC)

10) Expl
aintheorgani zati
onofmi croprogrammedcont rolunitindetail
.
Ans:-TheMi croprogrammedCont rolorgani
zationi
simplementedbyusi
ngt heprogr
ammi ng
approach.
InMicroprogrammedCont r
ol,themi cr
o-operati
onsareperf
ormedbyexecuti
ngapr ogram
consist
ingofmi cr
o-i
nstr
uct
ions.
Thefoll
owingimageshowst hebl ockdiagram ofaMicroprogr
ammedCont rolorgani
zati
on.

 TheCont
rolmemor yaddressr
egisterspeci
fiest
headdressofthemicr
o-i
nstr
ucti
on.
 TheCont
rolmemor yisassumedtobeaROM, wit
hinwhichal
lcont
roli
nfor
mationis
per
manentl
ystored.
 Thecont
rol
registerhol
dsthemicroinst
ruct
ionfet
chedfrom t
hememor y.
  Themi cro-
inst r
ucti
oncont ai
nsacont r
ol wordthatspeci
fi
esoneormor emi cro-
operati
onsf orthedat aprocessor
.
 Whilethemi cro-operati
onsarebeingexecut ed,
thenextaddressiscomputedi nthenext
addressgener atorci
rcuitandthentransferr
edintothecontr
oladdressr
egistertoread
thenextmi croinst
ructi
on.
 Thenextaddr essgeneratorisoft
enreferredtoasami cr
o-progr
am sequencer,asit
determinestheaddr esssequencet hatisreadfrom cont
rolmemor y.

Expl
11) aint
hef
oll
owi
ngr
elat
edt
oaddr
esssequenci
ng
a)Condi
ti
onalbr
anchi
ng
b)Mappi
ngofinstr
uct
ion
Ans:
-Conditi
onal Br anching:
 Conditional br anchingisobt ainedbyusi ngpar toft hemi cr oinstructiont oselecta
specif
icst atusbi tinordert odet erminei tscondition.
 Thes t
at uscondi tionsar especi albitsint hesystem t hatpr ov i
depar amet erinf
ormation
suchast hecar ry-
outofanadder , t
hesi gnbitofanumber ,themodebi tsofan
i
nstruction, andi /ost atuscondi ti
ons.
 Thes t
at usbi ts,t
oget herwitht hef i
eldint hemi croinstructiont hatspeci f
iesabr anch
address, cont rolthebr anchl ogic.
 Thebr anchl ogict eststhecondi t
ion,ifmett henbr anches, otherwi se,increment sthe
CAR.I fther ear e8st atusbi tcondi ti
ons, t
hen3bi tsint hemi cr
oinst ructionareusedto
specif
yt hecondi ti
onandpr ovidet hesel ecti
onv ariablesf orthemul tiplexer.
 Forunc ondi tional branching,fixthev alueofonest at
usbi tt obeonel oadt hebranch
addressf rom cont rolmemor yint otheCAR.

Mappi
ngofI
nst
ruct
ion:
 Aspeci
alt
ypeofbr
anchexi
stswhenami
croi
nst
ruct
ionspeci
fi
esabr
ancht
othef
ir
st
wordincontr
olmemorywher eami cropr
ogram r
outi
neislocated.
 Thes tat
usbi
tsf
orthi
stypeofbr ancharethebit
sintheopcode.
 Assumeanopcodeoff ourbit
sandacont rolmemoryof128l ocat
ions.Themappi
ng
processconv
ert
sthe4-bitopcodetoa7-bitaddr
essforcontrolmemor yshowni
nbel
ow
fi
gure.

 Mappi
ngconsi
stsofpl
aci
nga0i
nthemostsi
gni
fi
cantbi
toft
headdr
ess,
transf
err
ing
thefouroper at
ioncodebi
ts,
andcleari
ngthet
woleastsi
gni
fi
cantbit
softhecont
rol
addressregister.
 Thisprovidesforeachcomputeri
nstr
ucti
onamicr
oprogr
am rout
inewit
hacapacit
yof
fourmicroinstr
uctions
UNI
T4

1) Di
sti
ngui
shbet
weenI
/Obusandi
nter
facemodul
es.
 2) Di
sti
ngui
shbet
weeni
sol
atedv
ersesmemor
ymappedi
nter
face.
Ans:
-
I
SOLATEDI
/O MEMORYMAPPEDI
/O

Memor yandI
/Ohav
esepar
ateaddr
ess
space Bot
hhav
esameaddr
essspace

Duet
oadditi
onofI/Oaddr
essabl
e
Al
laddr
esscanbeusedbyt
hememor
y memorybecomelessformemory

Separ
atei
nstr
ucti
oncontr
olr
eadand Samei
nst
ructi
onscancont
rol
bot
hI/
O
wri
teoper
ati
oninI/OandMemory andMemory

I
nthi
sI/
Oaddr
essar
ecal
l
edpor
ts. Nor
mal
memor
yaddr
essar
eforbot
h

Mor
eef
fi
cientduet
osepar
atebuses Lesseref
fi
cient

Lar
geri
nsi
zeduet
omor
ebuses Smal
l
eri
nsi
ze

I
tiscompl
exduet
oseparatesepar
ate Simplerl
ogi
cisusedasI/
Oisal
so
l
ogici
susedt
ocontr
olboth. tr
eatedasmemor yonl
y.

3) Expl
ainasy nchronousdatatr
ansfer.
Ans:
-Inmostcomputerasynchronousmodeofdat
atransf
eri
susedi
nwhi
cht
wocomponent
hav eadif
ferentclock.Datatransfercanoccurbetweendat aint woway sser i
alandpar al
lel
.In
caseofpar al
lelmul t
ipl
eli
nesar eusedt osendasinglebitwher easinserialtr
ansfereachbi tis
sendoneatat i
me.Tot el
lotherdev i
ceswhent hecharact
er/datawi l
lbegi venaconceptof
startandendbi tisused.Ast artbiti
sdenotedby0andst opbi tisdetectedwhenl inereturnto1
-stateatl
eastonet ime,here1-statemeanst hatt
hereisnotdat atransferisoccurri
ng.
Whenachar acterisnotbeingsentt henli
neiskeptinstate1.St ar
tofchar act
erisdetected
whena0i ssent .Thecharacterbitalwayscomeafter0bit.Afterlastbi
tissentt hestateofline
tobecome1.
Thedi agr
am bel owshowst hisconcept :
Hereearl
ierst
ateofl
i
newas1whenachar
act
erhast
obesenda0i
ssendandchar
act
erbi
tar
e
t
ransfer
red.

4) Di scussI /Oi nter facei ndet ailwi thexampl e.

Ans:-Themet hodt hatisusedt ot ransf erinformat ionbet weeni nter
nal storageandext ernalI
/O
devi
cesisknownasI /
Oi nt
erface.TheCPUi si nterfacedusingspeci alcommuni cationl i
nksby
theperi
pheralsconnect edtoanycomput ersy stem.
 The secommuni cat
ionl inksar eusedt or esolvethedi f
ferencesbet weenCPUand
peri
pher al.Thereex i
st sspeci alhar dwar ecomponent sbet weenCPUandper ipher al
sto
superviseandsy nchroni zeal l t
hei nputandout puttr
ansferst hatar ecal
ledint erface
unit
s.
ModeofTr ansf er:
Thebinaryinformat ionthatisr ecei vedf rom anext ernaldeviceisusual lystoredinthememor y
unit
.Theinformat i
onthatist ransf erredf rom theCPUt otheext ernaldev i
cei sori
ginat edf r
om
thememor yuni t.CPUmer elypr ocessest heinf ormat i
onbutt hesour ceandt ar
getisal way sthe
memor yunit.Dat atransferbet weenCPUandt heI /
Odev i
cesmaybedonei ndif
fer
entmodes.
Datatr
ansfert oandf r
om theper ipher alsmaybedonei nanyoft het hreepossibleway s
i. Pr ogrammedI /O.
i
i. I nterr
upt-init
iatedI /O.
ii
i. Di rectmemor yaccess(DMA) .

--
ProgrammedI /
O:I ti
sduet ot
heresul
toftheI/
Oinst
ructi
onsthatarewri
tt
eni
nthecomputer
progr
am.Eachdat aitem t
ransf
eri
sinit
iat
edbyaninst
ructi
onintheprogr
am.Usual
lythe
tr
ansferisf
rom aCPUr egist
erandmemor y.I
nthi
scaseitrequi
resconst
antmoni
tori
ngbyt
he
CPUoft heper
ipheraldevi
ces.

ExampleofPr ogrammedI /O:Inthi

scase, theI/Odev i
cedoesnothav edir
ectaccesstot he
memor yunit
.At r
ansf erfrom I/Odev icetomemor yrequi
restheexecut i
onofseveral
i
nstr
uctionsbytheCPU, includingani nputi nst
ructi
ont ot
ransfert
hedat afrom devicetothe
CPUandst oreinstr
uct i
ont otransfert hedat afr
om CPUt omemor y.InprogrammedI /O,the
CPUstay si
nthepr ogram l oopunt i
ltheI /
Ouni tindicat
esthatiti
sreadyf ordatatr
ansfer.This
i
sat i
meconsumi ngpr ocesssi nceitneedl essl
ykeepst heCPUbusy .Thissit
uati
oncanbe
avoi
dedbyusi ngani nterruptfacil
it
y.Thi sisdiscussedbelow.

--
Inter
rupt-ini
ti
atedI/O:Sinceintheabovecasewesawt heCPUi skeptbusyunnecessar
il
y.
Thissituati
oncanv erywellbeav oi
dedbyusingani nter
ruptdr
ivenmet hodfordat
at r
ansf
er.By
usinginterr
uptfaci
li
tyandspeci alcommandst oinfor
mt heint
erfacetoissueaninter
rupt
requestsignalwhenev erdatai
sav ail
abl
efrom anydev i
ce.I
nthemeant imetheCPUcan
proceedf oranyotherprogram executi
on.Theinter
facemeanwhi l
ekeepsmoni tor
ingthedevi
ce.
Whenev eriti
sdeterminedthatthedev i
ceisreadyfordatatr
ansferiti
nit
iatesaninter
rupt
requestsignalt
othecomput er.Upondet ect
ionofanexternali
nterr
uptsignaltheCPUst ops
moment aril
ythetaskthatitwasalreadyperfor
ming,branchestotheserviceprogram to
processtheI/Otransf
er,andthenreturntothetaskitwasor i
ginal
l
yper f
orming.

Not e:Bot hthemethodspr ogrammedI/OandI nterr

upt-
dri
venI/Orequi
retheact iv
eintervent
ion
oft he
processort ot
ransferdatabetweenmemor yandt heI/Omodule,andanydat atransfermust
transv erse
apat hthroughtheprocessor.Thusbot
ht heseformsofI /
Osufferfr
om twoi nherentdrawbacks.
TheI /Otransf
errateisli
mitedbythespeedwi t
hwhi chthepr
ocessorcant estandser vi
cea
dev ice.
Thepr ocessoristi
edupi nmanaginganI/Ot r
ansfer;anumberofinstr
ucti
onsmustbe
execut ed
foreachI /Otr
ansfer.

--
Di r
ectMemor yAccess:Thedatatransferbetweenaf astst
oragemedi asuchasmagnet ic
diskandmemor yuniti
sli
mi t
edbythespeedoft heCPU.Thuswecanal l
owt heperi
pheral
s
directl
ycommuni cat
ewi t
heachotherusingt hememor ybuses,removingtheint
ervent
ionofthe
CPU.Thi stypeofdatatr
ansfert
echniquei sknownasDMAordi rectmemor yaccess.Duri
ng
DMAt heCPUi sidl
eandithasnocont r
ol overthememor ybuses.TheDMAcont r
oll
ertakes
overt hebusestomanaget hetr
ansferdi
rectlybetweentheI/Odev i
cesandthememor yuni
t.

5)Di
scussDMAt
ransf
ert
echni
quei
ndet
ail
wit
hbl
ockdi
agr
am.
Ans:-
 DMAcont
rol
l
erhast
oshar
ethebuswi
tht
hepr
ocessort
omaket
hedat
atr
ansf
er.The
dev i
cethatholdsthebusatagi ventimei scal
ledbusmast er.Whenat r ansferfr
om I /
O
dev i
cetothememor yorv iceversehast obemade, theprocessorstopst heexecutionof
thecurrentprogram, i
ncrement stheprogram counter ,
mov esdataov erst ackthensends
aDMAsel ectsignaltoDMAcont roll
erovertheaddr essbus.
 IftheDMAcont rol
leri
sf r
ee, i
trequeststhecontrolofbusf rom t
hepr ocessorbyr ai
sing
thebusr equestsignal.Processorgrantsthebust ot hecontrol
l
erbyr aisingthebus
grantsi
gnal,nowDMAcont r
oll
eristhebusmast er.Thepr ocessoriniti
at estheDMA
control
l
erbysendi ngt hememor yaddresses,numberofbl ocksofdat at obet ransferr
ed
 anddirecti
onofdatatransfer.Aft
erassigni
ngthedatatr
ansfertasktot
heDMA
contr
oller
,inst
eadofwaitingideall
yti
llcomplet
ionofdatatr
ansfer,
thepr
ocessor
resumest heexecut
ionoft heprogram aft
erret
ri
evi
nginstr
ucti
onsfrom t
hestack.

Tr
ansf
erOfDat
ainComput
erByDMACont
rol
l
er

 DMAcont
rol
l
ernowhast
hef
ull
cont
rol
ofbusesandcani
nter
actdi
rect
lywi
thmemor
y
andI/ Odev icesi ndependentofCPU.I tmakest hedat atransf eraccor dingt ot hecont rol
inst
ructionsr ecei v
edbyt heprocessor .Af t
ercompl etionofdat atransfer,itdisablesthe
busr equestsi gnal andCPUdi sablest hebusgr antsignal therebymov i
ngcont rolof
busest ot heCPU.
 Whe nanI /Odev icewant st oiniti
atethet ransf ertheni tsendsaDMAr equestsi gnalto
theDMAcont roller,forwhi cht hecont roll
eracknowl edgesi fitisfree.Thent hecont roller
requestst hepr ocessorf orthebus, r
aisingt hebusr equestsi gnal.Afterrecei vingthe
busgr antsignal i
ttransf ersthedat afrom t hedev i
ce.Fornchannel edDMAcont r
oll
ern
numberofext er nal dev icescanbeconnect ed.
a)Bur stMode: I
nt hismodeDMAhandov erthebusest oCPUonl yaf tercompl et
ionofwhol e
dat atr
ansfer.Meanwhi l
e, i
ft heCPUr equirest hebusi thast ost ayi dealandwai tfordat a
transfer.
b)Cy cleStealingMode: Int hismode, DMAgi vescont rolofbusest oCPUaf tertransferofev ery
by t
e.Itconti
nuousl yi ssuesar equestf orbuscont rol,
makest het ransf erofoneby t
eand
returnsthebus.Byt hisCPUdoesn’ thav etowai tforal ongt i
mei fitneedsabusf orhi gher
priori
tytask.
c)Tr ansparentMode:Her e,DMAt ransf er
sdat aonl ywhenCPUi sexecut ingt heinstruct i
on
whi chdoesnotr equi r
et heuseofbuses.

6)Di
sti
ngui
shbet
weenpr
ogr
ammedI
/Oandi
nter
rupti
nit
iat
edI
/Owi
thexampl
e.

PROGRAMMEDI
/O I
NTERRUPTI
NITI
ATEDI
/O

Dat
atr
ansf
eri
sini
ti
atedbyt
hemeansof TheI
/Ot
ransf
eri
sini
ti
atedbyt
he
 PROGRAMMEDI
/O I
NTERRUPTI
NITI
ATEDI
/O

i
nst
ruct
ionsst
oredi
nthecomput erprogram.
Whenev
erther
eisarequestforI
/Otransfert
he
i
nst
ruct
ionsar
eexecut
edf r
om theprogram. i
nter
ruptcommandi
ssuedt
otheCPU.

ThereisnoneedfortheCPUtostayi
n
TheCPUst aysintheloopt
oknowifthedev
icei
s theloopasthei
nter
ruptcommand
readyf
ortransferandhast
ocont
inuousl
ymonit
or i
nterrupt
stheCPUwhent hedev
iceis
theper
ipheraldevi
ce. readyfordat
atr
ansfer.

Thisleadstot
hewast ageofCPUcycl
esasCPU
remainsbusyneedlessl
yandthust
heeff
ici
encyof TheCPUcyclesar
enotwast
edasCPU
system get
sreduced. andhencet
hismethodi
smoreef
fi
cient
.

CPUcannotdoanywor kunt
ilt
het r
ansferi
s CPUcandoanyotherworkuntil
itis
completeasithastostayi
ntheloopt o i
nter
rupt
edbythecommandi ndicati
ng
cont
inuousl
ymoni t
ortheperi
pheraldevi
ce. ther
eadi
nessofdevi
cefordatatransfer

I
tsmodul
eisf
ast
ert
hanpr
ogr
ammed
I
tsmodul
eist
reat
edasasl
owmodul
e. I
/Omodul
e.

I
tcanbet r
ickyandcompl
icatedto
under
standifoneusesl
owl evel
I
tisqui
teeasyt
opr
ogr
am andunder
stand. l
anguage.

Theperf
ormanceoft
hesy
stem i
ssev
erel
y Theperfor
manceofthesyst
em i
s
degr
aded. enhancedtosomeextent
.

7)Explai
nbrief
lyaboutDMAcont r
oll
erwit
hbl ockdiagram.
Ans:-Thet
erm DMAstandsf
ordi
rectmemor
yaccess.Thehardwaredev
iceusedf
ordi
rect
memoryaccessi scall
edt heDMAcont r
oll
er.DMAcont roll
erisacont roluni
t,partofI/O
dev
ice’
sinterf
acecircuit
,whi chcantransferblocksofdat abetweenI /
Odev icesandmai n
memorywi thminimalinterventi
onfr
om t heprocessor .
 DMAc ontrol
l
erpr ovidesaninterfacebet weenthebusandt heinput-
outputdev i
ces.
Althoughittr
ansf ersdatawithoutinterventi
onofpr ocessor,i
tiscontroll
edbyt he
processor.Thepr ocessorini
tiatestheDMAcont r oll
erbysendingt hestarti
ngaddress,
Numberofwor dsint hedat
abl ockanddi rect
ionoft r
ansferofdata.i.
e.from I/Odevi
ces
tothememor yorf rom mainmemor ytoI /Odevices.Mor ethanoneext ernaldevi
cecan
beconnect edtot heDMAcont roll
er.
 DMAi nComput erArchitectur
e
DMAcont roll
ercont
ainsanaddr essunit,f
orgeneratingaddr essesandselecti
ngI/Odevi
cefor
tr
ansf
er.Italsocontai
nst hecont r
olunitanddat acountforkeepi ngcountsofthenumberof
bl
ockstransferr
edandi ndicat
ingt hedi
recti
onoft ransferofdat a.Whenthetransf
eri
s
compl
eted, DMAi nf
ormst hepr ocessorbyr ai
singani nt
er r
upt.Thetypi
calblockdi
agram oft
he
DMAcont roll
eri
sshowni nthef i
gurebelow.

Ty
pical
BlockDi
agr
am ofDMACont
rol
l
er

8)Explai
nbr i
efl
yDaisy
-Chai
ningPrior
ityi
npr i
ori
tyint
errupt.
Ans:-Thedai
sy-
chai
ningmet
hodi
nvol
vesconnect
ingal
lthedevi
cesthatcanr
equestan
i
nter
rupti
naseri
almanner.Thisconfi
gurationisgover
nedbyt
heprior
ityofthedevices.The
devi
cewit
hthehi
ghestpri
orit
yisplacedfirstfol
lowedbyt
hesecondhighestpri
ori
tydev i
ceand
soon.Thegi
venfi
gur
edepi ct
sthisarrangement .
WORKI NG:
 The rei sani nterruptr equestl inewhi chi scommont oal lthedev i
cesandgoesi ntot he
CPU.
 Whe nnoi nter r
upt sar ependi ng,thel i
nei sinHI GHst ate.Buti fanyoft hedev i
cesr aises
ani nter rupt ,itplacest hei nterr
uptr equestl inei ntheLOW st at e.
 TheCPUa cknowl edgest hisinterruptr equestf rom thel ineandt henenabl esthe
i
nter r
uptacknowl edgel ineinr esponset ot her equest .
 Thi ssi gnal i
sr ecei vedatt hePI (Prior i
tyin)i nputofdev ice1.
 I fthedev icehasnotr equest edt hei nt errupt,itpassest hissi gnal tothenextdev i
ce
throughi t sPO( priorit
yout )output .( PI=1&PO=1)
 Howe v er, ifthedev icehadr equest edt hei nterrupt,(PI=1&PO=0)
 Thede v iceconsumest heacknowl edgesi gnal andbl ocki tsf ur therusebypl aci
ng0at
i
tsPO( pr ior i
tyout )out put .
 Thede v icet henpr oceedst opl acei tsi nterr
uptv ect
oraddr ess( VAD)i ntot hedatabusof
CPU.
 Thede v iceput si tsinter ruptrequestsi gnal i
nHI GHst atet oi ndi cateitsinterr
upthas
beent akencar eof .
NOTE:VADi st headdr essoft heser vi
cer out inewhi chser vi
cest hatdev ice.
I
fadev i
ceget s0ati tsPIi nput ,itgener ates0att hePOout putt ot el
l ot herdev i
cesthat
acknowl edgesi gnal hasbeenbl ocked.( PI=0&PO=0)
Hence, thedev icehav ingPI=1andPO=0i st hehi ghestpr ioritydev icet hatisrequestingan
i
nterrupt.Ther efor e, bydai sychai nar r
angementwehav eensur edt hatt hehi ghestpr i
orit
y
i
nterruptget sser vicedf irstandhav eest abl i
shedahi erarchy .Thef art heradev i
ceisfrom t he
fi
rstdev i
ce, thel oweri tspr i
or i
ty.

9)DiscussCPU-I
OPcommuni cati
onindet ai
l.
Ans:-Thereisacommuni cat i
onchannelbetweenIOPandCPUt operf
ormt askwhi
chcome
undercomputerar
chi
tect
ur e.Thischannelexpl
ainsthecommandsexecutedbyIOPandCPU
whil
eperfor
mingdomepr ogr ams.TheCPUdonotex ecutest
hei
nstr
ucti
onsbutitassi
gnst
he
taskofi
nit
iat
ingoperat
ions,
theinst
ructi
onsareexecut
edbyI
OP.I
/Ot
ransf
eri
sinst
ruct
edby
CPU.TheIOPasksf orCPUthroughinter
rupt
.

 Thi
schannel
star
tsbyCPU,
bygi
vi
ng“
testI
OPpat
h”i
nst
ruct
iont
oIOPandt
hent
he
communi
cat
ionbegi
nsasshowni
ndi
agr
am:
 Whenev
erCPUget
sint
err
uptf
rom I
OPt
oaccessmemor
y,i
tsendst
estpat
hinst
ruct
ion
toIOP.IOPexecut esandcheckf orstatus,i
fthestat
usgiventoCPUi sOK, t
henCPU
givesstarti
nstructi
ontoIOPandgi vesitsomecont r
olandgetbackt osomeanot her(or
same)pr ogram, aft
erthatIOPisabl etoaccessmemor yf ori
tsprogram.
 NowI OPst artcontrol
l
ingI/Ot r
ansferusingDMAandcr eateanotherstatusrepor
tas
well.ASsoonast hi
sI/Ot r
ansfercompl etesIOPonceagai nsendinterr
upttoCPU, CPU
againrequestforstatusofI OP,I
OPcheckst atuswordfrom memor ylocati
onandgi ves
i
ttoCPU.NowCPUcheckt hecor r
ectnessofst at
usandcont i
nueswi t
ht hesame
process.

Fi
gur
e–Communi
cat
ionchannel
bet
weenI
OPandCPU

10) Expl
ainmappi
ngt
echni
quesi
ncachememor
y.
Ans:-Therear
ethreedif
fer
enttypesofmappi
ngusedf
ort
hepur
poseofcachememor
ywhi
ch
ar
easf ol
lows:
 Directmapping,
 As soci
ati
vemapping,and
  Set-
Associat
ivemappi
ng.
Thesear
eexplai
nedbelow:

DirectMappi ng–
Thesi mplesttechni que,knownasdi rectmapping, mapseachbl ockofmai nmemor yintoonly
onepossi blecachel i
ne.or
InDirectmappi ng, assigneeachmemor yblocktoaspeci fi
cl i
nei nt hecache.I falinei s
previouslytakenupbyamemor yblockwhenanewbl ockneedst obel oaded, theoldbl ockis
trashed.Anaddr essspacei sspl i
tintotwopar t
sindexf i
eldandat agf iel
d.Thecachei susedt o
storethet agfieldwher easther estisstoredinthemai nmemor y .Di r
ectmappi ng`s
performancei sdi r
ectlyproporti
onal totheHitratio.
i=jmodul om
wher e
i
=cachel i
nenumber
j
=mai nmemor ybl ocknumber
m=numberofl inesinthecache
Forpur posesofcacheaccess, eachmai nmemor yaddr esscanbev i
ewedasconsi st i
ngoft hree
fi
elds.Thel eastsignifi
cantwbi tsident i
fyauniquewor dorby t
ewi thi
nabl ockofmai nmemor y.
Inmostcont empor arymachi nes, t
headdr essisatt heby televel.Ther emai ni
ngsbi tsspeci f
y
oneoft he2sbl ocksofmai nmemor y.Thecachel ogicinterpretst hesesbi tsasatagofs- rbits
(mostsi gnif
icantpor ti
on)andal i
nef iel
dofrbits.Thislatterfieldi dentifi
esoneoft he
m=2rl i
nesoft hecache.
AssociativeMapping–
I
nt hi
sty peofmappi ng,theassociati
vememor yi
susedt ost
orecont
entandaddressesoft he
memor ywor d.Anybl ockcangoi ntoanyli
neofthecache.Thi
smeansthatthewordidbi tsar
e
usedtoi dent
if
ywhi chwor dintheblockisneeded,butt
hetagbecomesallofther
emai ningbi
ts.
Thisenablestheplacementofanywor datanypl
aceinthecachememory.Iti
sconsideredtobe
thefastestandthemostf l
exi
blemappi ngform.
Set-associ
ati
veMappi ng–
Thisform ofmappingi sanenhancedform ofdirectmappi ngwher ethedrawbacksofdi r
ect
mappi ngareremoved.Setassociati
veaddressest hepr oblem ofpossiblethrashinginthedir
ect
mappi ngmethod.Itdoest hi
sbysayingthatinst
eadofhav i
ngexact l
yonel i
net hatablockcan
mapt ointhecache,wewi l
lgroupafewlinestoget hercreat ngaset
i .Thenabl ockinmemor y
canmapt oanyoneoft hel i
nesofaspecifi
cset.
.Set -associati
vemappi ngall
owst hateach
wordt hati
spresentinthecachecanhav et woormor ewor dsinthemai nmemor yforthesame
i
ndexaddr ess.Setassociati
vecachemappi ngcombi nesthebestofdi rectandassoci ati
ve
cachemappi ngtechniques.
Inthiscase,t
hecacheconsi stsofanumberofset s,eachofwhi chconsistsofanumberof
l
ines.Ther el
ati
onshi
psar e
m =v*k
i
=jmodv

where
i
=cachesetnumber
j
=mainmemor yblocknumber
v=numberofsets
m=numberoflinesint
hecachenumberofset
s
k=numberofli
nesineachset
 11) Expl
ainAssoci
ati
vememor yandit
smat chlogic.
Ans:
-Associ
ati
vememoryisal
soknownascont
entaddr
essabl
ememor
y(CAM)or
associativestorageorassoci ativear r
ay .Itisaspeci al typeofmemor yt hatisoptimizedf or
performingsear chest hroughdat a,asopposedt opr ov i
dingasi mpl edir ectaccesst othedat a
basedont headdr ess.
Associ ati
vememor yofconv ent i
onal semi conduct ormemor y(usual l
yRAM)wi t
hadded
compar i
soncircuitythatenabl esasear choper ationt ocompl etei nasi ngleclockcy cl
e.Itisa
hardwar esearchengi ne, aspeci altypeofcomput ermemor yusedi ncer tainver
yhi ghsear chi
ng
applicati
ons.
 Thek eyr egisterhol dsamaskt hatallowssear chingbasedonpar tofargument .Ifabit
inthekeyr egist eris1, thent hecor r
espondi ngbi tinthear gumentandeachmemor y
wor dmustbet hesamet obeconsi deredamat ch.Ifabi tinthekeyr egi
steris0,thent he
correspondingbi tisconsi deredamat chwhet herornott hear gumentandmemor ywor d
areequal f
ort hatbit .Thi sallowssear chesf orwor dswher eanysubsetoft hebi t
smat ch
theargumentr egister.
 Thema tchr egister,M, i
sm bi tswi de( couldbehuge) ,andwi l
lcont aina1f oreachwor d
thatmat chest hemaskedar gument ,anda0f oreachwor dthatdoesnot .
 Howwi dear et hear gument , key ,andmat chr egi ster
sina1megx8associ ati
vememor y?
 Si ncethekeybel owi s0101, wor dsi nthememor yareconsi deredamat cht othe
argumenti fbi t0i s1andbi t2i s0.Anot herwayofl ookingati tist hatbi
ts1and3ar e
don'tcares,sot hear gumentweneedt omat chi sx0x1.
Argument 1001 Mat
ch
Key 0101

wor
d0 1100 0
wor
d1 0011 1
wor
d2 0100 0
 word3 0010 0
.
..
wordm-
1 0001 1

12) Descr
ibeI
ntel8089I
OP.

•WhenI/
Oi shandledbyIOP,micr
oprocessorcanperf
orm someot
herf
unct
ionatt
he
ti
meofI/
Ot ransf
er.Thi
sincr
easesthesystem speed.
•Example:
8089

Featuresof8089
•AnI OPcanf et chandexecut eit
sowni nstructions.
•Inst r
ucti
onsar especi al
lydesignedforI/
Opr ocessi ng.
•Inaddi ti
ont odat atransf er,
8089canper form ar i
thmet icandl ogicoperations,
branches, searchingandt ransl
ati
on.
•IOPdoesal l
wor ki
nv olvedinvol
vedinI/Ot ransfertr ansferi
ncludingincludingdev i
ce
setup, pr
ogrammedI /
OandDMAoper ati
on.
•IOPcant r
ansf erdataf r
om an8- bi
tsourcet o16- bitdest i
nati
onandv i
ce-ver sa.
•Communi cationbetweenI OPandCPUi sthr oughmemor ybasedcont r
ol blocks.CPU
definestasksi nt hecont r
ol bl
ockstolocateapr ogram sequence, cal
ledachannel
program.

I
nter
nal
BlockDi
agr
am of8089:
Pi
nDi
agr
am:

Regi
ster
sof8089:

•GA-Pointstosour ce
•GB-Pointstodestinati
on
•GC-Usedasbaseaddr essofa256by
tet
ransl
ati
ont
abl
e.
•TP-
Taskpoi nter
•PP-Paramet erpoint
er
•I
X–I ndexregister
•BC
•MC-containst hei
tpatter
ntobecompar
edandamaskinbi
ts15t
hrough8
 •CC-
channelcont
rol
•PSW-Pr
ogram st
atusr
egi
ster

UNI
T5

1) Di scussSI MDar chi tect

urei ndet ailwithit
sv ari
ants.
Ans:
-SI
MDAr chitecture(Singl
ei nst r
ucti
onMul tipl
eDat a)
 Singl
einst ructi
onisappl i
edt oamul t
ipledat ait
em toproducethesameoutput
.
 Masterinst ructi
onwor konv ectorofoper and
 Noofpr ocessor srunningt hesamei nstructi
ononecl ockcycl
ebyt hest
ri
ctl
ock
approach
 I
tistypeofI nstr
ucti
onl evel paral
lel
i
sm
 Communi cat i
onnetworkal lowpar all
elsy nchronouscommuni cat
ionbet
weensever
al
ProcessingEl ement/Memor ymodul es.

Fi
g(a)SI
MDPr
ocessorAr
chi
tect
ure
  Fol
lowingtwoSI MDar chi
tect
uresdepi
ctfundamentall
ydiff
erentappr
oachestothe
par
all
el pr
ocessing
 Dat
aCommuni cat i
onbasedonmessagepassi ngparadigm:
 Herethememor yi spartofPEandthusitcommunicatesthroughtheint
erconnect
ion
net
wor kforpassingthedata.

Sharedmemor ybet
weenprocessors:
Herememor i
esarenotl
ocalandthedatai
sreadandal
i
gnedbyt
heal
i
gnmentnet
wor
kthat
al
ignsthedat
abetweenPEsandMemor ymodul
es

SI
MDPar al
lelProcess:
Dur
ingt
heexecut i
onofprogr
am,i
tisoft
enrequi
redt
omaskofaPEfrom doi
ngpr
ocessi
ng,
whi
chisequival
enttohavi
ngsomeautonomouscont
rol
wit
hinaPE.
PEhasamaskbi twhichcanbemaskeddur ingprocessi
ngofaninst
r uct
ion.
Whenamaski nPEi sseti
trecei
vesi
nstruct
ionfrom Contr
olUni
tasNooper ati
on.
Executesinst
ruct
ionwhenmaskbi ti
sreset.
EachPEhasoneormor ei
ndexregi
ster
saddedt oglobaladdr
essessuppliedbyt heCU
Inst
ructi
on.
Thearithmeti
clogicuni
thasfewgeneralpurposeregi
ster
sandpointerregist
erst osuppor
tdat
a
andaddr essmanipul
ati
on.

SIMDmeshconnect edarchi t
ectur
e:
Herewear edeal
ingwitht hemeshConnect edarchit
ecturewhichhasbeenbui ltusi
ngthemesh
connect
edarchit
ecture
Eachnodeofsuchmachi newi ll
havefourports-Toppor t
,lef
tport
,r
ightportandbot t
om port
.
Theinst
ructi
onsetbelongst oCUwi t
hPEsexecut ingsomeofi nst
ructi
onst hatarepref
ixedwit
h
Ptoindi
catethattheseshal lbeexecutedonPEsi npar al
l
el.
EachPEalsohasf ourbidirecti
onalportsf
orcommuni cat
iontofourneighbors.

2) Di scussMI MDar chitecturei

ndetailwit
hit
sv ar i
ants.
Ans:-MIMDst andsf or'Mul t
ipleInstr
uct i
onandMulti
pleDat
aSt ream'.
 Inthi
sor ganizati
on, allprocessorsinapar
all
elcomputercanexecutedi
ffer
ent
i
nst
ructionsandoper ateonv ariousdat
aatthesametime.
 InMIMD, eachpr ocessorhasasepar at
eprogr
am andani nstr
ucti
onstr
eam isgener
ated
f
rom eachpr ogram.

Where,
M =Memor yModul
e,PE=Processi
ngEl
ement
,andCU=Cont
rol
Uni
t
Exampl
es:
CrayT90,Cr
ayT3E,I
BM-SP2

3) Explai
nbrief
lyint
erconnectionstr
ucturesofmultiprocessor
ssyst
ems.
Ans:-Thecomponentsthatf
orm amult
ipr
ocessorsy
stem ar
eCPUs,I
OPs
connect
edtoinput
outputdev
ices,
andamemor yunit
.
 Thei nterconnect ionbet weent hecomponentscanhav edi f
ferentphysical
confi
gurations, dependi ngont henumberoft r
ansferpathsthatar eavai
lableo
Betweent hepr ocessor sandmemor yinasharedmemor ysystem oAmongt he
processi
ngel ement si nal ooselycoupledsyst
em
Ther earesev er
al physicalformsav ail
abl
eforestabl
ishingani nter
connecti
on
network.
oTi me- sharedcommonbus
oMul tiportmemor y
oCr ossbarswi tch
oMul tistageswi t
chingnet work
oHy per cubesy stem

4) Di
ff
erent
iat
emul
ti
processorsy
stemsandmul
ti
progr
ammi
ngsy
stems.
Ans:
-

5) Bri
eflyexpl ai
nt hechar acteristi
csofmul t
iprocessor s.
Ans:-Characteri
sticsofmul t
iprocessor s
1.Amul t
iprocessorsy st
em isani nterconnecti
onoft woormor eCPUswi th
memor yandi nput-
outputequipment .
2.Theterm“ processor”inmul t
iprocessorcanmeanei theracentr
alprocessi
ng
uni
t(CPU)orani nput-
outputprocessor( IOP).
3.Multi
processorsar eclassi
fi
edasmul t
ipl
einstruct
ionstream,mult
ipledata
 stream ( MI MD)sy stems
4.Thesi mi lari
t yanddi stinct i
onbet weenmul ti
pr ocessorandmul t
icomput erare
``Si milarity
o Bot hsuppor tconcur rentoper at i
ons
Distinction
o Thenet wor kconsi stsofsev er al autonomouscomput ersthatmayormay
notcommuni catewi theachot her .
o Amul t
iprocessorsy stem iscont roll
edbyoneoper ati
ngsy st em t hat
prov idesi nteractionbet weenpr ocessor sandal lthecomponent soft he
syst em cooper at ei nthesol ut ionofapr obl em.
5.Mul tiprocessi ngi mpr ov est hereliabi lityoft hesy st em.
6.Thebenef i
tder ivedf rom amul ti
pr ocessoror gani zat i
onisani mpr ov ed
system per formance.
Mul ti
plei ndependentj obscanbemadet ooper at einpar al
lel.
Asi nglej obcanbepar t
iti
onedi nt omul tiplepar al l
eltasks.
7.Mul tiprocessi ngcani mpr oveper for mancebydecomposi ngapr ogr am i nto
par
allelexecut ablet asks.
oTheusercanexpl icitlydeclaret hatcer t
ai nt asksoft hepr ogr am be
execut edi npar all
el.
o Thi smustbedonepr iortoloadi ngt hepr ogr am byspeci f
yingt hepar al
lel
execut abl esegment s.
o Theot heri st opr ov ideacompi lerwi thmul tipr ocessorsof twar et hatcan
automat i
callydet ectpar all
elism i nauser ’
spr ogram.
8.Mul tiprocessorar ecl assi fi
edbyt hewayt hei rmemor yisor ganized.
o Amul t
iprocessorsy stem withcommonshar edmemor yiscl assi fi
edasa
shar ed- memor yort ightlycoupl edmul tipr ocessor .
o Tol er ateahi gherdegr eeofint eract i
onbet weent asks.
o Eachpr ocessorel ementwi thi tsownpr iv atel ocal memor yiscl assi f
iedas
adi stributed- memor yorl oosel ycoupl edsy stem.
o Ar emostef fici
entwhent heint eractionbet weent asksi smi nimal

6) De scri
bei ndet
ailaboutf
lynn’
scl
assi
fi
cat
ion.
Ans:
-Fl
ynn’sclassif
icat
ion–

i
. Single-
instruct
ion, si
ngle-
dat a(
SISD)sy stems–
AnSI SDcomput i
ngsy stem isauniprocessormachinewhi chiscapableofexecutinga
singl
einst r
ucti
on, operati
ngonasi ngledat astr
eam.InSISD,machineinstructi
onsar e
processedi nasequent ialmannerandcomput ersadopti
ngthismodel ar
epopul arly
call
edsequent ialcomput ers.Mostconv enti
onalcomputershaveSISDar chit
ectur
e.All
theinstructi
onsanddat atobepr ocessedhav etobestoredinpri
mar ymemor y
.
Thespeedoftheprocessi
ngel
ementint
heSI
SDmodelisl
imit
ed(dependent)bytherat
eat
whichthecomputercantr
ansf
eri
nfor
mati
oni
nter
nal
l
y.Dominantrepr
esentati
veSISDsyst
ems
areIBM PC,wor
kstat
ions.

i
i
. Single-i
nstruction,mult
ipl
e-dat a(SI
MD)sy st
ems–
AnSI MDsy stem isamul t
iprocessormachinecapabl eofexecutingthesamei nst
ruct
ion
onal lt
heCPUsbutoper ati
ngondi f
fer
entdat
ast r
eams.Machi nesbasedonanSI MD
model arewel l
suitedtoscientif
iccomputi
ngsincet heyinvol
velotsofv ect
orandmat ri
x
operations.Sot hattheinf
or mationcanbepassedt oalltheprocessingelements(PEs)
organizeddat aelement sofv ector
scanbedividedintomul ti
plesets(N-
setsforNPE
systems)andeachPEcanpr ocessonedataset.

Domi
nantr
epr
esent
ati
veSI
MDsy
stemsi
sCr
ay’
svect
orpr
ocessi
ngmachi
ne.

i
i
i. Mul
tiple-i
nst
ruct
ion,si
ngle-
data(
MISD)systems–
AnMI SDcomputingsy st
em i
samulti
processormachi
necapabl
eofexecuti
ngdi
ff
erent
i
nst
ruct i
onsondiff
erentPEsbutal
loft
hem operat
ingonthesamedataset.
ExampleZ=si n(x)+cos(x)+tan(
x)
Thesystem perf
ormsdi fferentoper
ati
onsont hesamedat
aset.Machi
nesbuil
tusi
ngtheMISD
modelarenotusef ulinmostoft heappli
cat
ion,afewmachi
nesarebui
lt
,butnoneoft
hem ar
e
avai
l
ablecommer cial
ly.

i
v. Multiple-i
nstr
uct i
on,multiple-data(MIMD)sy stems–
AnMI MDsy stem isamul tiprocessormachinewhi chiscapabl
eofexecuti
ngmult
ipl
e
i
nstruct i
onsonmul ti
pledataset s.EachPEint heMI MDmodel hassepar
atei
nst
ruct
ion
anddat ast r
eams; theref
oremachi nesbui
ltusingthismodelarecapabl
etoanyki
ndof
appli
cat i
on.UnlikeSIMDandMI SDmachines,PEsi nMIMDmachi neswork
asynchr onously
.

MI MDmachi nesarebroadlycategoriz
edintoshar ed-
memor yMIMDanddi stri
buted-memor y
MI MDbasedont hewayPEsar ecoupledtothemai nmemor y.
Inthesharedmemor yMIMDmodel (t
ight
lycoupledmultiprocessorsystems) ,allthePEsare
connectedtoasi ngl
eglobal memor yandtheyallhaveaccesst oit.Thecommuni cati
on
betweenPEsi nthismodel takesplacethr
ought hesharedmemor y,modi f
icationoft hedata
storedintheglobalmemor ybyonePEi svisi
bletoallot
herPEs.Domi nantr epresentat
ive
sharedmemor yMIMDsy stemsar eSili
conGraphicsmachi nesandSun/ I
BM’ sSMP( Symmet ri
c
Mul t
i-
Processi
ng).

I
nDi st
ri
but
edmemor yMI
MDmachines(l
oosel
ycoupl
edmul
ti
processorsy
stems)al
lPEshav
e
alocalmemor
y.Thecommuni
cat
ionbet
weenPEsinthi
smodelt
akesplacethr
oughthe
i
nterconnectionnetwor k(t
hei nterpr ocesscommuni cati
onchannel ,orIPC) .Thenet work
connecti
ngPEscanbeconf i
gur edt otree,meshori naccor dancewi thther equir
ement .
Theshar ed-memor yMI MDar chitecturei seasiertopr ogram butislesst oleranttofail
uresand
hardertoextendwi threspectt ot hedistri
butedmemor yMIMDmodel .Failuresinashar ed-
memor yMI MDaf fecttheentiresy st
em, wher east hi
si snott hecaseoft hedi st
ri
butedmodel ,i
n
whicheachoft hePEscanbeeasi l
yisolated.Mor eover,sharedmemor yMI MDar chit
ecturesar
e
l
essl i
kel
yt oscalebecauset headdi ti
onofmor ePEsl eadst omemor ycont enti
on.Thisisa
si
tuati
ont hatdoesnothappeni nt hecaseofdi st
ributedmemor y,i
nwhi cheachPEhasi t
sown
memor y.Asar esultofpractical outcomesanduser ’srequirement, distri
butedmemor yMI MD
archi
tectureissuperiortotheot herexi sti
ngmodel s.

7) Expl
ainmul
ti
stageswi
tchi
ngnet
wor
k.
Ans:
-
8) Expl
ainomeganet
wor
k.

9) Explai
nt i
meshar edcommonbusi nter
connectionstructure.
Ans:
-Time-Shar
edCommonBus
Acommon- busmulti
processorsyst
em consistsofanumberofprocessorsconnectedthr
ough
acommonpat htoamemor yunit
.Atime-sharedcommonbusf orfi
veprocessorsisshownin
Fi
g.1.Onl
yonepr ocessorcancommuni catewiththememoryoranotherprocessoratany
gi
venti
me.

 Transferoperati
onsar econduct edbyt hepr ocessorthatisincontr
olofthebusatt he
ti
me.
 Anyotherpr ocessorwishingtoi niti
ateat r
ansf ermustfi
rstdeter
minetheav ai
labil
ity
stat
usoft hebus, andonlyaf t
ert hebusbecomesav ail
ablecantheprocessoraddr ess
thedestinati
onunitt oi
nit
iatethet ransfer.
 Acommandi sissuedtoinformt hedest i
nationunitwhatoperati
onistobeper formed.
 Therecei v
ingunitrecogni
zesi tsaddr essint hebusandr espondstothecontrol si
gnals
from t
hesender ,afterwhi
cht het ransferisinit
iated.
 Thesy stem mayexhi bi
ttr
ansf erconf l
ictssinceonecommonbusi ssharedbyal l
 processor s.Theseconf l
ictsmustber esolvedbyi ncor porati
ngabuscont roll
erthat
establishespr i
or i
tiesamongt her equest i
nguni ts.
 Asi nglecommon- bussy stem i sr estrictedtoonet r
ansf eratat ime.
 Thismeanst hatwhenonepr ocessori scommuni catingwi tht hememor y, al
lother
processor sar eeitherbusywi t
hi nternal operat ionsormustbei dl
ewaitingf orthebus.
 Asaconsequence, thetotal ov erall t
ransferr atewi thinthesy stem isli
mi tedbyt he
speedoft hesi nglepat h.
 Thepr ocessor si nt hesyst em canbekeptbusymor eof tent hrought heimpl ement ati
on
oftwoormor ei ndependentbusest oper mitmul t
iplesi multaneousbust ransfers.
Howev er,t
hisincr easest hesy stem costandcompl exity.
 Herewehav eanumberofl ocal buseseachconnect edt oitsownl ocalmemor yandt o
oneormor epr ocessor s.Eachl ocal busmaybeconnect edtoaCPU, anI OP, orany
combi nationofpr ocessor s.
 Asy stem buscont roll
erlinkseachl ocal bust oacommonsy st em bus.TheI /Odevices
connect edt othel ocal I
OP, aswel l ast helocal memor y,areav ai l
abl
etot hel ocal
processor .
 Thememor yconnect edtot hecommonsy stem busi ssharedbyal l
processor s.Ifan
IOPi sconnect eddi rect
lyt ot hesy stem bus, theI /Odev i
cesat tachedtoi tmaybemade
availabletoal lprocessor s.
 Onlyonepr ocessorcancommuni cat ewi t
ht heshar edmemor yandot hercommon
resourcest hrought hesy stem busatanygi vent ime.
 Theot herpr ocessor sarekeptbusycommuni cat i
ngwi ththei rlocalmemor yandI /O
devices.Par toft hel ocal memor ymaybedesi gnedasacachememor yat t
achedt othe
CPU.
 Inthisway ,
theav erageaccesst i
meoft helocal memor ycanbemadet oappr oacht he
cyclet i
meoft heCPUt owhi chi tisat tached.

10)Expl
aincrossbarswi tchint
erconnecti
onstruct
ure.
Ans:
-Acr ossbarswi
tchisaswitchconnecti
ngmulti
plei
nput
st omult
ipl
eout
put
sinamat
ri
x
manner.
Ar
chit
ectureofauni-
dir
ecti
onalcrossbarswi
tch:
  Thecrossbarswi t
chcanswi tchinputs(
yell
owcol orsquar
es)tot heoutput
s(cyancol
or
squar
es)-imagi neeachboxi saCPUoramemor ymodul e.
 Thesetti
ngoft heswitchingfabri
cisunderthecont r
olofaswit
chi nglogi
ccir
cuit
 Thesources(inputs)f
irstsendrequestsi
gnalstot heswit
chi
ngl ogiccir
cui
t.
 Theswitchi
ngl ogi
ccircuitwil
lsettheswit
chingfabrict
oroutether equest
sfrom t
he
i
nputtotheirdesti
nati
ons.

Example:
CPU0want st
oaccessmemorymodule3(needstosendaddr
essv
aluet
omemor ymodul
e3)
CPU1want st
oaccessmemorymodule1(needstosendaddr
essv
aluet
omemor ymodul
e1)
CPU2want st
oaccessmemorymodule0(needstosendaddr
essv
aluet
omemor ymodul
e0)
CPU3want st
oaccessmemorymodule2(needstosendaddr
essv
aluet
omemor ymodul
e2)
Setti
ngoftheswi
tchi
ngcont
rolt
oenablet
hetransmissi
onoft
hememoryaddr
essesf
rom CPU
tothememor ymodules: