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Faculty of Engineering
Department of Electrical & Electronics Engineering
When the button is pressed, it forces the capacitor to discharge to 0 volts, and then it
starts recharging. The output remains at 5V until the voltage of the capacitor reaches a
certain value. When the value of the capacitor exceeds a certain value, the output remains
at 0. If the button is not pressed, the output will be 0 until it is pushed again.
So, we can write output as:
𝑅1
5𝑉, 𝑣𝑐 < 𝑉𝑐𝑐
𝑅1 + 𝑅2
𝑂𝑢𝑡𝑝𝑢𝑡 =
𝑅1
0, 𝑣𝑐 > 𝑉𝑐𝑐
{ 𝑅1 + 𝑅2
Pulse Duration
From the time that button is pressed to critical voltage time (I am neglecting the discharge
time since it happens so quickly.) can be calculated as:
𝑅1 𝑡
−
𝑉𝑐𝑐 = 𝑉𝑐𝑐 −𝑉𝑐𝑐 𝑒 𝑅𝑐 𝐶 , 𝑣𝑐 (0) = 0
𝑅1 + 𝑅2
It can be observed that 𝑉𝑐𝑐 voltage is not affecting the pulse duration!
𝑅1 𝑡
−
= 1 − 𝑒 𝑅𝑐 𝐶
𝑅1 + 𝑅2
𝑅1 𝑡
−
1− =𝑒 𝐶
𝑅𝑐
𝑅1 + 𝑅2
𝑅1 𝑡
ln (1 − )=−
𝑅1 + 𝑅2 𝑅𝑐 𝐶
Rearranging yields;
𝑅1 + 𝑅2
𝑡𝑝𝑢𝑙𝑠𝑒 = 𝑡 = 𝑅𝑐 𝐶. 𝑙𝑛 ( )
𝑅2
So we can say:
In this version, due to positive feedback output will be always saturated. Output has
two states which is +Vsat and -Vsat, two threshold levels can be calculated as:
𝑅2
𝑉𝑈𝑇 = 𝑉𝑐𝑐
𝑅1 + 𝑅2
𝑉𝐿𝑇 = 0 ∵ −𝑣𝑠 = 0
This implementation also prevents noise effects (if amplitude of the noise smaller than
𝑉𝑇𝐻 − 𝑉𝑇𝐻 − ). Also, it whould be better to set −𝑣𝑠 a bit higher than zero to make sure
+
when button is pressed inverting input can be lower than non-inverting input.
Pulse Duration
After pressing the button, opamp will saturate to -Vsat and until the capacitor’s
voltage reaches the upper threshold level it will keep its state. (I am neglecting the
discharge time since it happens quickly.)
𝑅2 𝑡
𝑉𝑐𝑐 = 𝑉𝑐𝑐 −𝑉𝑐𝑐 𝑒 −𝑅𝐶 , 𝑣𝑐 (0) = 0
𝑅1 + 𝑅2
𝑅2 𝑡
= 1 − 𝑒 −𝑅𝐶
𝑅1 + 𝑅2
𝑅1 𝑡
= 𝑒 −𝑅𝐶
𝑅1 + 𝑅2
𝑅1 𝑡
ln ( )=−
𝑅1 + 𝑅2 𝑅𝐶
Rearranging yields
𝑅1 + 𝑅2
𝑡 = 𝑅𝐶 ln ( )
𝑅1
Simulation Graph
For the values given below;
For the first design (not gate version), the duration time was closer to the calculated
values than the second model but output voltage vas lower than we expect it to be. For the
second design (hysteresis version), voltage levels of output was close to our expectations
but pulse duration time has bigger error that the first design.