American International University- Bangladesh (AIUB)

Faculty of Engineering

Course Name: VLSI Circuit Design Course Code: EEE 4217

Semester: Spring 2023-24 Term: Final
Total Marks: 20 Submission Date: 4-05-2024
Instructor Name: Nigar Sultana Assignment: 04
Course Outcome Mapping with Questions
Obtained
Item COs POIs K P A Marks
Marks
A4 CO4 P.b.2.C4 K2 20
Total: 20

Student Information:
Student Name: Student ID:

Section: Department:

Marking Rubrics (to be filled by Faculty):

Excellent Proficient Good Acceptable Unacceptable No Response
[10] [8-9] [6-7] [4-5] [1-3] [0]
Detailed unique
No
response Response with no Partial problem is Unable to clarify
Response shows Response/(Copie Secured
Problem # explaining the apparent errors solved; response the understanding
understanding of d/identical Marks
concept properly and the answer is indicates part of of the problem and
the problem, but submissions will
and answer is correct, but the problem was method of the
the final answer be graded as 0
correct with all explanation is not not understood problem solving
may not be correct for all parties
works clearly adequate/unique. clearly. was not correct
concerned)
shown.
1

Comments Total marks (20)

1. Prepare the physical layout of a 3-input NAND gate.

(i) Show the schematic and the physical layout. Label drain and source terminals on both the diagrams.
(ii) Compute the area of the active area (in terms of λ), considering minimum length/width of polysilicon,
diffusion and metal layers are 2λ/2λ, 4λ/3λ and 3λ/3λ.

N-Diffusion P-Diffusion Polysilicon Metal1 Metal2 Via

(NMOS drain/source) (PMOS drain/source)

Consider A, B, C as inputs and Y as output.

Assuming 1λ spacing is needed between polysilicon and metal layers as well as metal1 and metal2 layers.

Note that lengths are horizontal dimension and widths are vertical dimension. [20]