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9th International Conference On Robotic Vision Signal Processing and Power Applications Empowering Research and Innovation 1st Edition Haidi Ibrahim
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Lecture Notes in Electrical Engineering 398
Haidi Ibrahim
Shahid Iqbal
Soo Siang Teoh
Mohd Tafir Mustaffa
Editors
9th International
Conference on
Robotic, Vision,
Signal Processing and
Power Applications
Empowering Research and Innovation
Lecture Notes in Electrical Engineering
Volume 398
123
Editors
Haidi Ibrahim Soo Siang Teoh
School of Electrical and Electronic School of Electrical and Electronic
Engineering Engineering
Universiti Sains Malaysia Universiti Sains Malaysia
Nibong Tebal, Penang Nibong Tebal, Penang
Malaysia Malaysia
The 9th International Conference on Robotic, Vision, Signal Processing and Power
Applications (RoViSP 2016) was held in Penang, Malaysia, from 2nd to 3rd
February 2016. This conference hosted an electronic paper submission process for
areas that include, but not limited to:
• Electronic Design and Applications
• Numerical Computations and Optimizations
• Artificial Intelligence and Computer Applications
• Vision, Image and Signal Processing
• Robotics, Control, Mechatronics and Automation
• Telecommunications, RF, Antenna and Applications
• Sensors and Sensing Techniques
• Biomedical, BioEngineering and Applications
• Power Systems, High Voltage Engineering and Renewable Energy
• Electrical Machines, Drives and Power Electronics
RoViSP 2016 is the latest conference held by the School of Electrical and
Electronic Engineering, Universiti Sains Malaysia (USM), following its series of
successful conferences. In this version, more than 90 papers were accepted for the
inclusion in this publication. This proceeding gives a picture of the latest scientific
and practical activities carried out in the field of Robotic, Vision, Signal Processing
and Power Applications with theme of “Empowering Research and Innovation”.
The Editors acknowledge the time and effort of all reviewers and technical
committee members in ensuring high-quality technical papers for RoViSP 2016.
The committee would also like to express our gratitude to Springer for the technical
supports.
v
Organization
Organizing Secretary
Technical Chairs
Technical Reviewers
vii
viii Organization
xiii
xiv Contents
Abstract The need to have fast transient response of the voltage regulator is driven
by the increasing current slew rate of the mobile microprocessor. Hence, optimizing
the switching frequency of the voltage regulator becomes an important step to
achieve a balance between preserving the efficiency of the voltage regulator and
improving the transient response. Besides, output capacitor solution with multilayer
ceramic capacitor has also become more popular due to its small size and cheap cost.
A fast transient voltage regulator with all ceramic output capacitors for mobile
microprocessor is proposed in this study. The outcome of the study shows that the
voltage regulator designed is stable with the proposed type and number of
multi-layer ceramic capacitors. More importantly, the actual transient results cor-
relate well with the simulation results in which minimal transient droop and over-
shoot are observed with a dynamic current load step with a slew rate of 10.5 A/1 µs.
1 Introduction
more challenging [1]. The industry is trying to catch up with the high current slew
rate of the processor current load by developing voltage regulator with high
switching frequency.
However, the switching frequency range for voltage regulator is limited in order
to preserve the efficiency and stability. The other design solution to address the high
current slew rate is to design with extra number of output capacitors. Unfortunately,
design with too many output capacitors will increase the product cost and consume
huge amount of board area. This is not a favorable solution for mobile segment. As
a result, this situation poses a great challenge to the voltage regulator designer.
Secondly, size of the voltage regulator has always been too huge driven by
increasing power demand of the mobile processor. This renders the overall mobile
computing product to be heavy, bulky, costly, and unattractive. With AVP
(adaptive voltage positioning) [2] feature introduced, now the voltage regulator
designer has the option to design with all ceramic output capacitors in order to
present an area and cost effective solution. However, design with all ceramic output
capacitors requires thorough analysis and engineering judgment so that the solution
presented is stable and meets the design specifications.
For the case of voltage regulator residing in a mobile computer system, the
switching frequency ranges from 200 kHz to 1 MHz [3]. High switching frequency
is good for transient performance and reducing size of the passive components such
as inductor and capacitors of the voltage regulator. However, too high of a
switching frequency will degrade the efficiency of the voltage regulator and
increase the risk of control loop instability. Hence, voltage regulator designer faces
a great challenge to find the suitable switching frequency in order to meet both the
efficiency and transient performance targets [4].
During transient event, output capacitor plays an important role to contain the
droop and overshoot at the output of the voltage regulator. Besides, output capacitor
is also used to stabilize the control loop of the voltage regulator and to reduce
output voltage ripple. Usually, the amount of output capacitor needed is capped by
the transient requirement of the design.
As the mobile computer market is trending towards cheaper, lighter, and thinner
computing products, multilayer ceramic capacitors (MLCC) emerges as the popular
choice of output capacitors for voltage regulator. The reason is because MLCC is
very cheap and small in size. Apart from this, MLCC has the lowest equivalent
series resistance (ESR) and equivalent series inductance (ESL) among the surface
mounted capacitors available in the market. In other words, MLCC has the least
undesired parasitic components. Besides, MLCC has a reputation for good relia-
bility and least safety hazard. Leakage current in MLCC is also one of the lowest
among the capacitors.
However, designing with MLCC has its fair share of challenges as well such as
lower capacitance, DC biasing effect, and acoustic noise. Proper analysis is needed
to design a voltage regulator with all ceramic output capacitors.
A Fast Transient Voltage Regulator Design … 5
2 Methodology
The design flow of this voltage regulator follows the steps outlined by the flow
chart shown in Fig. 1 below. Firstly, the design specifications are determined based
on the latest electrical specifications shown in Table 1. Once the design specifi-
cations are determined, the first step in designing the voltage regulator is to
determine the switching frequency. In order to reduce the iterations in hardware
measurement, it is imperative to propose a power loss model and develop an
efficiency calculator to estimate the efficiency of the proposed design for different
switching frequencies. For this step, an excel spreadsheet based power loss is
designed for this purpose.
Once a correlation between the measured efficiency and the calculated efficiency
is obtained, then the decision to set the switching frequency of the voltage regulator
can be made. If correlation is poor, then efforts have to be made to improve the
power loss calculator.
Fig. 1 Flow chart to design a fast transient response voltage regulator with all-MLCC output
capacitors
6 C.H. Lee and N.S. Ahmad
The next step is to design the current sensing network to generate an accurate
current feedback information across the desired temperature range. Again, an excel
based calculator spreadsheet is used to design the DCR (direct current resistance)
sensing circuitry of the output inductor. The outcome of the current sensing net-
work must show an accurate AVP load line from 0 to 85 °C.
There are many different types of MLCC available in the market. Fort this study,
three different types of MLCC are compared and analyzed. The MLCC used in the
design has to provide the smallest board area while meeting the transient response
as listed below.
• 22 μF, 6.3 V, 0603 size, 1.00 mm height
• 47 μF, 6.3 V, 0805 size, 1.45 mm height
• 100 μF, 6.3 V, 1210 size, 2.70 mm height
The total output capacitance needed to ensure the output impedance is lower
than the load line of 5.9 mΩ up to 1 MHz is determined using the formula given in
Equation
1
Cout = ð1Þ
2π × RLL × Fco
The final step is to implement the design of the voltage regulator on the test
board and measure the transient response of the voltage regulator.
The power loss calculator estimated that 495 kHz is the highest switching fre-
quency that can still maintain optimal efficiency. In order to ensure the calculated
efficiency is accurate, the simulated 495 kHz efficiency curve is compared with the
measured 495 kHz efficiency curve. The difference between the measured and
calculated curves is small (less than 3 %), thus it shows that the power loss cal-
culator has a good degree of accuracy.
With the switching frequency locked down, now the amount of MLCC needed
for each type can be calculated based on Eq. 1. With the first-cut number ready,
parametric analysis can be run in LTSpice to determine the number of MLCC
needed for each type. At the end, the simulation results show that the voltage
regulator needs 40 pieces of 22 µF MLCC, or 23 pieces of 47 µF of MLCC, or 7
pieces of 100 µF MLCC. Based on the number of MLCC needed, designing with 7
pieces of 100 µF MLCC is the most area effective solution (83.2 mm2) as compared
to 84 mm2 required by 40 pieces of 22 µF MLCC and 90 mm2 required by 23
pieces of 47 µF of MLCC.
Figure 2 shows the measured transient response of the voltage regulator with
original switching frequency of 385 kHz with 2 pieces of 330 µF tantalum polymer
capacitor and 6 pieces of 22 µF 0805 size MLCCs. Figure 3 shows the transient
response of the proposed solution which has the voltage regulator set to operate at
495 kHz and has 7 pieces of 100 µF 1210 size MLCCs. During both load step and
release events, no significant undershoot or overshoot is observed at the output of
the voltage regulator. In fact, the transient response of the proposed voltage regu-
lator has a more critically damped response compared to the original design.
Fig. 2 Transient response of the voltage regulator with original decoupling solutions (2 pieces of
330 µF tantalum polymer capacitor and 6 pieces of 22 µF (0805) MLCCs
8 C.H. Lee and N.S. Ahmad
Fig. 3 Transient response of the voltage regulator with seven pieces of 100 µF (1210) MLCCs
4 Conclusions
In conclusion, a fast transient voltage regulator has been designed using only
multilayer ceramic output capacitors. An optimized switching frequency of
495 kHz is used for the voltage regulator in order to achieve the highest bandwidth
as well as to preserve the efficiency. In fact, the voltage regulator presented in this
study shows significant improvement in terms of the size, cost, and transient per-
formance compared to the original reference design.
References
1. López T, Elferich R, Alarcón E (2010) Voltage regulators for next generation microprocessors.
Springer Science and Business Media
2. Hsiao S-F, Ting W-Y, Liang T-J, Huang J-R, Chen W-W, Chen J-F (2013) Improved transient
response using high-frequency feedback control circuit of the constant current ripple constant
on-time with native adaptive voltage positioning design for voltage regulators. IET Power
Electron 6(9):1948–1955
3. Jovanović M (2007) Power supply technology–past, present, and future. In: Power conversion
and intelligent motion China conference (PCIM China), pp 3–15
4. Bag S, Mukhopadhyay S, Samanta S, Sheehan R, Roy T (2014) Frequency compensation and
power stage design for buck converters to meet load transient specifications. In: 2014 IEEE
applied power electronics conference and exposition—APEC 2014, pp 1024–1031
Autonomous Agent for Universal
Verification Methodology Testbench
of Hard Memory Controller
1 Introduction
The UVM describes high level testbench architecture to verify a DUT. The
architecture is made of multiple individual components that are designed to perform
specific tasks. Figure 1 shows the testbench architecture described by UVM. This
architecture will be reused and improved to perform automated agent approach with
sideband DDR protocol awareness and to reduce the test writer’s burden. The Test
is a standard UVM class that will encapsulate the verification environment and will
instantiate sequences to be parsed to the environment. The Environment is a top
level verification component that wraps around and connects the other verification
components. The Agent typically contains, a driver, a sequencer, a monitor and
configuration objects. Most of the architectural changes to build an automated agent
approach will take place within this level.
The Agent can be configured to be active or passive through the Environment’s
configuration object. While the driver, sequencer and monitor can be reused
independently, UVM’s guidelines recommend using an agent as a container for
these components. The Sequencer is an advanced stimulus generator that will
generate streams of transactions to be consumed by the driver. The Driver is an
active component that consumes the transactions from the sequencer and translates
the transaction into actual pin wiggle to the DUT. This is the UVM component that
actively interacts with the DUT and it merely acts as a translator between object
oriented programming (OOP) to actual pin activity.
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