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NOTES For Ece StudentsEngin
NOTES For Ece StudentsEngin
Process
– Analog/mixed signal Physical Design
Design
source drain
transistors /
chip channel length
power /
transistor supply voltage
ref: Kuo and Lou, Low-Voltage CMOS VLSI Circuits, Fig. 1.3, p. 3
low power/transistor is critical for future ICs
ECE 410, Prof. F. Salem Lecture Notes Page 2.8
Moore’s Law
• In 1965, Gordon Moore realized there 2 Billion
was a striking trend; each new
generation of memory chip contained
roughly twice as much capacity as its
predecessor, and each chip was
released within 18-24 months of the
previous chip. He reasoned, computing
power would rise exponentially over
relatively brief periods of time. 10µm 1µm 0.35µm 45 nm
Feature Size
(ref: http://www.intel.com/intel/museum/25anniv/hof/moore.htm)
• Moore's observation, now known as
Moore's Law, described a trend that Power Supply Tends
has continued and is still remarkably Digital Core Voltage Projections
accurate. In 26 years the number of 1.8 V from the 2000 ITRS*
transistors on a chip has increased 1.5 V
more than 3,200 times, from 2,300 on 1.2 V
the 4004 in 1971 to 7.5 million on the 0.9 V
Pentium¨ II processor. 0.6 V 0.6 V
Process
– Analog/mixed signal Physical Design
Design
source drain
VDD VDD +
nMOS Vgs=Vtn Passes a good low
on when gate 0V VDD - Max high is VDD-Vtn
is ‘high’
Vy = 0 V Vy =
VDD-Vtn
0V 0V -
pMOS Vsg=|Vtp| Passes a good high
on when gate VDD 0V + Min low is |Vtp|
is ‘low’
Vy = VDD Vy = |Vtp|
Rule to Remember
‘source’ is at lowest potential (nMOS) and highest potential (pMOS)
NOR
Remember This??
a=1 ⇒ SW1 closed, SW2 open ⇒ y=0 = a
a • b = a + b, a + b = a • b
DeMorgan relations a=0 ⇒ SW1 open, SW2 closed ⇒ y=1 = a
pMOS
nMOS
VSS = ground
– y = x • A, i.e. y = x iff A = 1
– series = AND
– parallel = OR
• assert-low switch
– y = x • A, i.e. y = x if A = 0 =x
– series = NOR a b
– parallel = NAND
0 1
=VDD
Vin=VDD
1 0
c = ab
c = a+b
y 0 1 g(x,y) = x • y • 1 + x • 0 + y • 0
x
0 1 0 • construct Sum of Products equation with all terms
• each term represents a MOSFET path to the
1 0 0 output
• ‘1’ terms are connected to VDD via pMOS
• ‘0’ terms are connected to ground via nMOS
• Important Points
– series-parallel arrangement
• when nMOS in series, pMOS in parallel, and visa versa
• true for all CMOS logic gates
• allows us to construct more complex logic functions
x y
x y z
g(x,y) = x y z
z
• note shared gate inputs
y • is input order important?
x xyz • in series, parallel, both?
x y
z
• schematic resembles how the
circuit will look in physical layout
x x
y
g(x,y) = x + y g(x,y) = x y
y
x x
• assert-low OR
• bubbles = inversions
• creates NAND function
– Series-connected pMOS
– NOR-AND rule a+b=a•b
x x x y
x x
equivalent y
to y
y y x y
x+y
g(x,y) = x y = x + y
to implement pMOS this way, must push all bubbles • assert-low AND
to the inputs and remove all NAND/NOR output bubbles • creates NOR function
ECE 410, Prof. F. Salem Lecture Notes Page 2.34
Rules for Constructing CMOS Gates
The Mathematical Method
• Given a logic function
F = f(a, b, c)
• Reduce (using DeMorgan) to eliminate inverted operations
– inverted variables are OK, but not operations (NAND, NOR)
• Form pMOS network by complementing the inputs
Fp = f(a, b, c)
• Form the nMOS network by complementing the output
Fn = f(a, b, c) = F
• Construct Fn and Fp using AND/OR series/parallel
MOSFET structures x
– series = AND, parallel = OR
EXAMPLE: g(x,y) = x y
F = ab ⇒ y
x
Fp = a b = a+b; OR/parallel
Fn = ab = ab; AND/series
ECE 410, Prof. F. Salem Lecture Notes Page 2.35
CMOS Combinational Logic Example
• Construct a CMOS logic gate to implement the function:
F = a • (b + c) a 14 transistors (cascaded gates)
F
b
c
• pMOS • nMOS
– Apply DeMorgan expansions – Invert output for nMOS
F = a + (b + c) Fn = a • (b + c)
6 transistors
F=a+(b•c) (CMOS) – Apply DeMorgan
– Invert inputs for pMOS none needed
Fp = a + (b • c) a b
– Resulting Schematic
– Resulting Schematic c
F=a(b+c)
F=a(b+c) a
a b
a
b c
b c
c
F=a(b+c)
eX
bX
Complete CMOS
AOI/OAI circuits
• pMOS
– Group 2: c & d in series
– Group 1: b parallel to G2
– Group 3: a in series with G1/G2
• pMOS • nMOS
– Apply DeMorgan expansions – Invert output for nMOS
none needed Fn = a • (b + c)
– Invert inputs for pMOS – Apply DeMorgan
Fp = a • (b + c) Fn = a + (b+c )
– Resulting Schematic ? Fn = a + (b • c)
– Resulting Schematic ?
• nMOS a b
– Invert Output
c
• Fn = a • b • (a + c) = a • b + (a + c)
– Eliminate NANDs and NORs
F=a b (a+c)
a
• Fn = a • b + ( a • c)
– Reduce Function
• Fn = a • (b + c) b c
– Resulting Schematic ?
– Complement operations for pMOS
• Fp = a + (b • c)
• Exclusive-NOR
– a⊕b=a•b+a•b
– inverse of XOR
a
b b
a a
–XOR: a ⊕ b = a • b + a • b
–XNOR: a ⊕ b = a • b + a • b
ECE 410, Prof. F. Salem Lecture Notes Page 2.45
CMOS Transmission Gates
recall: pMOS passes a good ‘1’
• Function and nMOS passes a good ‘0’
schematic symbol
= a b, b = 1 = a b, b = 1
a⊕b=a•b+a•b
= a, a = 1