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Heuring Chap-2
Heuring Chap-2
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-2 Chapter 2 - Machines, Machine Languages, and Digital Logic
Chapter 2 Topics
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-3 Chapter 2 - Machines, Machine Languages, and Digital Logic
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-4 Chapter 2 - Machines, Machine Languages, and Digital Logic
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-5 Chapter 2 - Machines, Machine Languages, and Digital Logic
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-6 Chapter 2 - Machines, Machine Languages, and Digital Logic
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-7 Chapter 2 - Machines, Machine Languages, and Digital Logic
li $3, 455 Load the 32-bit integer 455 into Reg. 3 R3000
mov R4, dout Move 16 bits from R4 to port dout DEC DP11
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-8 Chapter 2 - Machines, Machine Languages, and Digital Logic
ori $2, $1, 255 Store logical OR of reg 1 with 255 into reg 2 R3000
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-9 Chapter 2 - Machines, Machine Languages, and Digital Logic
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-10 Chapter 2 - Machines, Machine Languages, and Digital Logic
Processor State
C N V Z
Program Counter Condition Codes
•
•
•
Branch Targets
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-11 Chapter 2 - Machines, Machine Languages, and Digital Logic
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-12 Chapter 2 - Machines, Machine Languages, and Digital Logic
Push Pop
Top
Second
• • •
• • •
• • •
•
•
•
Op1Addr: Op1
Op2Addr: Op2
ResAddr: Res
NextiAddr: Nexti
Instruction format
Bits: 8 24 24 24 24
add ResAddr Op1Addr Op2Addr NextiAddr
Which Where to Where to find
operation put result Where to find operands next instruction
Op1Addr: Op1
Op2Addr: Op2
ResAddr: Res
Program
NextiAddr: Nexti 24
counter
Where to find
next instruction
Instruction format
Bits: 8 24 24 24
add ResAddr Op1Addr Op2Addr
Which Where to
operation put result Where to find operands
Op1Addr: Op1
Op2Addr: Op2,Res
Program
NextiAddr: Nexti counter 24
Where to find
next instruction
Instruction format
Bits: 8 24 24
add Op2Addr Op1Addr
Which Where to find operands
operation
Where to
put result
• Result overwrites Operand 2
• Needs only 2 addresses in instruction but less choice in
placing data
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-17 Chapter 2 - Machines, Machine Languages, and Digital Logic
Op1Addr: Op1
Where to find
operand2, and
where to put result
Accumulator
Program
NextiAddr: Nexti counter 24
Where to find
next instruction
Instruction format
Need instructions to load
Bits: 8 24
and store operands:
LDA OpAddr add Op1Addr
STA OpAddr Which Where to find
operation operand1
• Special CPU register, the accumulator,
supplies 1 operand and stores result
• One memory address used for other operand
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-18 Chapter 2 - Machines, Machine Languages, and Digital Logic
Bits: 8 24
Op1Addr: Op1
Format push Op1Addr
TOS
Operation Result
SOS
etc.
add (TOS ← TOS + SOS)
Bits: 8
Stack
Program Format add
NextiAddr: Nexti 24
counter Which operation
Where to find Where to find operands,
next instruction and where to put result
(on the stack)
Evaluat e a = (b+c)*d - e
3 -a d d re s s 2 -a d d re s s 1 -a d d re s s St a c k
add a, b, c load a, b load b push b
mpy a, a, d add a, c add c push c
sub a, a, e mpy a, d mpy d add
sub a, e sub e push d
store a mpy
push e
sub
pop a
• # of instructions & # of addresses both vary
• Discuss as examples: size of code in each case
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-20 Chapter 2 - Machines, Machine Languages, and Digital Logic
R4
add R2, R4, R6 (R2 ← R4 + R6)
add R2 R4 R6
R2
Nexti Program
counter
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-22 Chapter 2 - Machines, Machine Languages, and Digital Logic
Trade-Offs
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-23 Chapter 2 - Machines, Machine Languages, and Digital Logic
Addressing Modes
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-24 Chapter 2 - Machines, Machine Languages, and Digital Logic
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-25 Chapter 2 - Machines, Machine Languages, and Digital Logic
Memory Memory
Instr Op'n R2 4 Instr Op'n 4
+ + Operand
Operand
R2 PC
LOAD 4[R2], ... Operand Addr. LOADRel 4[PC], ... Operand Addr.
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-26 Chapter 2 - Machines, Machine Languages, and Digital Logic
31 0 7 0
R0 32 32-bit 0
general 32
2
purpose bytes
registers of
R31 main R[7] means contents
memory of register 7
PC
M[32] means contents
IR 232 – 1 of memory location 32
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-27 Chapter 2 - Machines, Machine Languages, and Digital Logic
SRC Characteristics
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-28 Chapter 2 - Machines, Machine Languages, and Digital Logic
31 27 26 22 21 0
op ra c1 Type 1
31 27 26 22 21 17 16 0
op ra rb c2 Type 2
31 27 26 22 21 17 16 12 11 0
op ra rb rc c3 Type 3
• Details of formats:
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-29 Chapter 2 - Machines, Machine Languages, and Digital Logic
Total of 7 31 2726 22 21 0
Idr r5, 8 (R[5] = M[PC + 8])
2. Idr, str, lar Op ra
Detailed c1 Iar r6, 45 (R[6] = PC + 45)
Formats 31 27 26 22 21 17 16 0
3. neg, not Op ra rc unused neg r7, r9 (R[7] = – R[9])
unused
31 27 26 22 21 17 16 12 11 2 0
brzr r4, r0
4. br Op rb rc (c3) unused Cond (branch to R[4] if R[0] == 0)
unused
31 27 26 22 21 17 16 12 11 2 0
brlnz r6, r4, r0
5. brl Op ra rb rc (c3) unused Cond (R[6] = PC; branch to R[4] if R[0] ≠ 0)
31 27 26 22 21 17 16 12 11 0
6. add, sub,
Op ra rb rc unused add r0, r2, r4 (R[0] = R[2] + R[4])
and, or
31 27 26 22 21 17 4 2 0
shr r0, r1, #4
7a Op ra rb (c3)
(c3) unused Count (R[0] = R[1] shifted right by 4 bits
7. shr, shra
shl, shic 31 27 26 22 21 17 16 12 4 0
shl r2, r4, r6
7b Op ra rb rc (c3)
(c3) unused 00000 (R[2] = R[4] shifted left by count in R[6])
31 27 26 0
8. nop, stop Op unused stop
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-30 Chapter 2 - Machines, Machine Languages, and Digital Logic
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-31 Chapter 2 - Machines, Machine Languages, and Digital Logic
• It is c3<2..0>, the 3 lsbs of c3, that governs what the branch condition is:
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-34 Chapter 2 - Machines, Machine Languages, and Digital Logic
Branch Instructions—Example
C: goto Label3
SRC:
lar r0, Label3 ; put branch target address into tgt
reg.
br r0 ; and branch
• • •
Label3 •••
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-35 Chapter 2 - Machines, Machine Languages, and Digital Logic
in SRC:
.org 1000 ;next word will be loaded at address
100010
X: .dw 1 ;reserve 1 word for variable X
.org 5000 ;program will be loaded at location
500010
lar r0, Over ;load address of “false” jump location
ld r1, X ;load value of X into r1
brpl r0, r1 ≥0
;branch to Else if r1≥
neg r1, r1 ;negate value
Over: • • • ;continue
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-36 Chapter 2 - Machines, Machine Languages, and Digital Logic
SRC Simulator
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-37 Chapter 2 - Machines, Machine Languages, and Digital Logic
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-38 Chapter 2 - Machines, Machine Languages, and Digital Logic
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-39 Chapter 2 - Machines, Machine Languages, and Digital Logic
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-40 Chapter 2 - Machines, Machine Languages, and Digital Logic
Static Properties
• Specifying registers
• IR〈〈31..0〉〉 specifies a register named “IR” having 32 bits
numbered 31 to 0
• “Naming” using the := naming operator:
• op〈〈4..0〉〉 := IR〈〈31..27〉〉 specifies that the 5 msbs of IR be
called op, with bits 4..0.
• Notice that this does not create a new register, it just
generates another name, or “alias” for an already existing
register or part of a register.
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-41 Chapter 2 - Machines, Machine Languages, and Digital Logic
Dynamic Properties
• Conditional expressions:
(op=12) → R[ra] ← R[rb] + R[rc]: ; defines the add instruction
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-42 Chapter 2 - Machines, Machine Languages, and Digital Logic
Processor state
PC〈〈31..0〉〉: program counter
(memory addr. of next inst.)
IR〈〈31..0〉〉: instruction register
Run: one bit run/halt indicator
Strt: start signal
R[0..31]〈〈31..0〉〉: general purpose registers
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-43 Chapter 2 - Machines, Machine Languages, and Digital Logic
R[0..31]〈〈31..0〉〉:
Colon separates
Name of statements with
registers no ordering
Register # msb #
in square
brackets lsb# Bit # in
.. specifies angle
a range of brackets
indices
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-44 Chapter 2 - Machines, Machine Languages, and Digital Logic
Memory Declaration:
RTN Naming Operator
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-45 Chapter 2 - Machines, Machine Languages, and Digital Logic
Instruction formats
op〈〈4..0〉〉 := IR〈〈31..27〉〉: operation code field
ra〈〈4..0〉〉 := IR〈〈26..22〉〉: target register field
rb〈〈4..0〉〉 := IR〈〈21..17〉〉: operand, address index, or
branch target register
rc〈〈4..0〉〉 := IR〈〈16..12〉〉: second operand, conditional
test, or shift count register
c1〈〈21..0〉〉 := IR〈〈21..0〉〉: long displacement field
c2〈〈16..0〉〉 := IR〈〈16..0〉〉: short displacement or
immediate field
c3〈〈11..0〉〉 := IR〈〈11..0〉〉: count or modifier field
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-46 Chapter 2 - Machines, Machine Languages, and Digital Logic
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-48 Chapter 2 - Machines, Machine Languages, and Digital Logic
Logical NOT
Logical AND
instruction_interpretation := (
¬Run∧ ∧Strt → Run ← 1:
Run → (IR ← M[PC]: PC ← PC + 4; instruction_execution) );
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-49 Chapter 2 - Machines, Machine Languages, and Digital Logic
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-50 Chapter 2 - Machines, Machine Languages, and Digital Logic
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-51 Chapter 2 - Machines, Machine Languages, and Digital Logic
Individual Instructions
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-52 Chapter 2 - Machines, Machine Languages, and Digital Logic
instruction_execution := (
ld (:= op= 1) → R[ra] ← M[disp]: load register
ldr (:= op= 2) → R[ra] ← M[rel]: load register relative
st (:= op= 3) → M[disp] ← R[ra]: store register
str (:= op= 4) → M[rel] ← R[ra]: store register relative
la (:= op= 5 ) → R[ra] ← disp: load displacement address
lar (:= op= 6) → R[ra] ← rel: load relative address
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-53 Chapter 2 - Machines, Machine Languages, and Digital Logic
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-54 Chapter 2 - Machines, Machine Languages, and Digital Logic
• An example:
• If IR = 00001 00101 00011 00000000000001011
• then ld → R[5] ← M[ R[3] + 11 ]:
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-55 Chapter 2 - Machines, Machine Languages, and Digital Logic
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-56 Chapter 2 - Machines, Machine Languages, and Digital Logic
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-57 Chapter 2 - Machines, Machine Languages, and Digital Logic
(c3〈〈4..0〉〉=0) → R[rc]〈〈4..0〉〉:
n := (
(c3〈〈4..0〉〉≠0) → c3〈〈4..0〉〉 ):
shr (:= op=26) → R[ra]〈〈31..0〉〉 ← (n @ 0) # R[rb]〈〈31..n〉〉:
shra (:= op=27) → R[ra]〈〈31..0〉〉 ← (n @ R[rb]〈〈31〉〉) # R[rb]〈〈31..n〉〉:
shl (:= op=28) → R[ra]〈〈31..0〉〉 ← R[rb]〈〈31-n..0〉〉 # (n @ 0):
shc (:= op=29) → R[ra]〈〈31..0〉〉 ← R[rb]〈〈31-n..0〉〉 # R[rb]〈〈31..32-n〉〉:
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-58 Chapter 2 - Machines, Machine Languages, and Digital Logic
13@R[2]〈〈31〉〉 # R[2]〈〈31..13〉〉
R[1]= 1111 1111 1111 1 100 1011 1111 0101 0111
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-59 Chapter 2 - Machines, Machine Languages, and Digital Logic
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-60 Chapter 2 - Machines, Machine Languages, and Digital Logic
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-61 Chapter 2 - Machines, Machine Languages, and Digital Logic
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-62 Chapter 2 - Machines, Machine Languages, and Digital Logic
RTN compiler
Generated processor
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-63 Chapter 2 - Machines, Machine Languages, and Digital Logic
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-65 Chapter 2 - Machines, Machine Languages, and Digital Logic
B
LOAD
CLK
A
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-66 Chapter 2 - Machines, Machine Languages, and Digital Logic
Abbreviated notation
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-67 Chapter 2 - Machines, Machine Languages, and Digital Logic
data gate→data
gate→0
gate
data 1
Data gate
data 2 data1(2),
provided
data2(1)
data 1 is zero
data control→data data 2
Controlled complement
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-68 Chapter 2 - Machines, Machine Languages, and Digital Logic
x
m
x m
Gx
x y
m
y m
Gy
y
Time
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-69 Chapter 2 - Machines, Machine Languages, and Digital Logic
m m
D1 m
G1 m
m
Dn–1
m k
Dn–1
Gn–1 Select
m
x 0
m
x y
m
Gx
Time
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-71 Chapter 2 - Machines, Machine Languages, and Digital Logic
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-72 Chapter 2 - Machines, Machine Languages, and Digital Logic
+V
Inputs Output
0v 0v Open (Out = +V) Out
+V
0v +V Open (Out = +V) o.c.
+V
+V 0v Open (Out = +V)
+V +V Closed (Out = 0v)
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-73 Chapter 2 - Machines, Machine Languages, and Digital Logic
Out
a b
o.c. o.c.
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-74 Chapter 2 - Machines, Machine Languages, and Digital Logic
+V
D0 D1 Dn–1
o.c. o.c. o.c.
G0 G1 Gn–1
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-75 Chapter 2 - Machines, Machine Languages, and Digital Logic
Tri-
Data Out Data Out
state
Enable
Enable
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-76 Chapter 2 - Machines, Machine Languages, and Digital Logic
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-77 Chapter 2 - Machines, Machine Languages, and Digital Logic
Control Sequence
R[2]out, Yin;
R[1]out, Zin;
Zout, R[3]in;
Notice that what could be described in one step in the abstract RTN took
three steps on this particular hardware
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-78 Chapter 2 - Machines, Machine Languages, and Digital Logic
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-79 Chapter 2 - Machines, Machine Languages, and Digital Logic
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar
2-80 Chapter 2 - Machines, Machine Languages, and Digital Logic
Chapter 2 Summary
Computer Systems Design and Architecture by V. Heuring and H. © 1997 V. Heuring and H. Jordan, Updated January, 2001 by David M. Zar