IMPLEMENTATION AND TECHNIQUES FOR ENHANCING SDR

TRANSCEIVER QUALITY ON FPGA

NGUYEN DUC THANG

 1 Outline

1 INTRODUCTION

2 BASELINE MODEL

3 ENHANCING QUALITY TECHNIQUES

4 IMPLEMENTATION ON FPGA
1. INTRODUCTION

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 Digital communication system
In a digital communication system, the formatter/deformater and modulator/demodulator are indispensable
From others
Source

From Information Source Encrypt Channel Spread Multiple

Formatter Multiplexer MODULATOR Transmitter
Source Encoder Encoder Encoder Spectrum Access

Bitstreams Waveform Channel

To Information Source Encrypt Channel Despread Demultiple

Deformatter Demultiplexer DEMODULATOR Receiver
Destination Decoder Decoder Decoder Spectrum Access

To Others
Source

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 Modulation
The digital modulator plays a role in transforming bitstreams into appropriate waveforms for transmission
over the channel. In others word, it shift baseband spectrum into passband spectrum.

1 1 0 0 0 0 1 1
Amplitude

Baseband Passband

fc Frequency
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 Software-Defined Radio
Software-Defined Radio (SDR) is a radio communication
system where components that conventionally have been
implemented in analog hardware (e.g. mixers, filters,
amplifiers, modulators/demodulators, detectors, etc.) are
instead implemented by means of software on a computer
or embedded system [1].

[1] Markus Dillinger; Kambiz Madani; Nancy Alonistioti (2003). Software Defined Radio: Architectures, Systems and Functions. Wiley & Sons.

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 Software-Defined Radio
Advantages:
❖ Flexible with reconfigure ability
❖ Cost efficiency
❖ Easy to upgrade and update
❖ Powerful signal processing ability
❖ Small size

SDR is commonly deployed on General Purpose Processors (GPP),

Graphics Processing Units (GPU), Digital Signal Processors (DSP),
and Field Programmable Gate Arrays (FPGA). Among these, FPGA
stands out for its advantages in processing capacity, offering high
throughput, low latency, and efficient energy utilization.

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2. BASELINE MODEL

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2.1 Modulation scheme
2.2 Demodulation scheme

2.3 Symbol timing

synchronization
2.4 Carrier phase synchronization

2.5 Simulation result

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 2.1 Modulation Scheme
DIGITAL UP CONVERTER
MIXER
BINARY TO PAM RRC HALFBAND CIC
CONVERTER FILTER FILTER FILTER
I CHANNEL
SYMBOL RATE = R fs1 = K x R fs2 = K x 2 x R fs3 = K x 2 x M x R SIN

DDS MODULATED
BITSTREAM
SERIAL WAVEFORM
1 1 0 0 1 TO
PARALLEL

COS
Q CHANNEL
BINARY TO PAM RRC HALFBAND CIC
CONVERTER FILTER FILTER FILTER
MIXER
DIGITAL UP CONVERTER

Fig 2.1: IQ digital modulation scheme for QPSK/16QAM with Pulse shaping

RRC: Root Raised Cosine

CIC : Cascaded Integrator-Comb
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2.1 Modulation Scheme

Fig 2.2: Modulation signal processing progress

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 2.1 Modulation Scheme
Comparing spectrum efficiency between QPSK theory scheme and QPSK pulse shaping at 20 MHz carrier
frequency and 100 Kbps bit rate.

Fig 2.3: Comparing spectrum efficiency

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 2.1 Modulation Scheme
Comparing spectrum efficiency between QPSK theory scheme and QPSK pulse shaping at 20 MHz carrier
frequency and 100 Kbps bit rate.

Fig 2.4: Test modulated QPSK/16QAM signal

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 2.2 Demodulation Scheme
DIGITAL DOWN CONVERTER
MIXER I BASEBAND
I CHANNEL CIC HALFBAND RRC
FILTER FILTER FILTER

SIN DDS PARALLEL

SYMBOL DECODER TO BIT_STREAMS
IF SIGNAL
SERIAL
COS

CIC HALFBAND RRC

Q CHANNEL FILTER FILTER FILTER
MIXER Q BASEBAND
DIGITAL DOWN CONVERTER

Fig 2.5: IQ origin digital demodulation scheme for QPSK/16QAM

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 2.2 Demodulation Scheme
We assume the received signal has form: S ( n ) = m1 (n)sin ( 2 f c n +  ) + m2 (n)cos ( 2 f c n +  )
Note that 𝑚1 , 𝑚2 represent the baseband signals of the I/Q channels, while 𝑓𝑐 and 𝜑 denote the frequency and phase of the
carrier, respectively.
Consider signal after mixer at I channel, we have:

𝐼𝑚𝑖𝑥 𝑛 = 𝑚1 𝑛 sin 2𝜋𝑓𝑐 𝑛 + 𝜑 + 𝑚2 𝑛 cos(2𝜋𝑓𝑐 𝑛 + 𝜑) sin 2𝜋𝑓𝑐 𝑛 + 𝜑LO

𝑚1 𝑛
=− cos 4𝜋𝑓𝑐 𝑛 + 𝜑 + 𝜑LO − cos 𝜑 − 𝜑LO
2
𝑚 𝑛
+ 22 𝑠𝑖𝑛 4𝜋𝑓𝑐 𝑛 + 𝜑 + 𝜑LO + sin(𝜑 − 𝜑LO )

Let 𝜑𝑒 = 𝜑 − 𝜑𝐿𝑂 denote the phase error. After lowpass filtering, the resulting signal is obtained
1
𝐼𝑏𝑎𝑠𝑒𝑏𝑎𝑛𝑑 (𝑛) = 𝑚1 𝑛 𝑐𝑜𝑠𝜑𝑒 − 𝑚2 𝑛 𝑠𝑖𝑛𝜑𝑒
2
Similarly, we have the baseband signal for the Q channel
1
𝑄𝑏𝑎𝑠𝑒𝑏𝑎𝑛𝑑 (𝑛) = 𝑚2 𝑛 𝑐𝑜𝑠𝜑𝑒 + 𝑚1 𝑛 𝑠𝑖𝑛𝜑𝑒
2

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2.2 Demodulation scheme

Fig 2.6: Demodulation signal processing progress 16/49

 Basic issue of demodulation process
For amplitude and phase modulation like QPSK/16QAM, the phase offset significantly affects the demodulation result. A large
phase offset can cause all decoded symbols to be incorrect. Additionally, timing offset also reduces demodulation performance,
especially in pulse shaping communication systems.

Frequency offset Timing offset

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 2.3 Symbol timing synchronization
Conceptually, symbol timing synchronization is the process of estimating a clock signal that is aligned in both phase and frequency
with the clock used to generate the data at the transmitter [2].
Sampling time

Perfect PAM received signal Eye diagram

[2] Michael Rice, Digital Communications – A Discrete Time Approach (2008)

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 2.3 Symbol timing synchronization

Correct timing

Incorrect timing

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 2.3 Symbol timing synchronization

e ( k ) = x ( ( k − 1 / 2 )Ts + ˆ )  x ( ( k − 1)Ts + ˆ ) − x ( kTs + ˆ )

r ( nT ) x ( nT ) x ( kTs + ˆ )
2 samples / symbol 4 samples / symbol
MATCHED INTERPOLATOR
ADC
r (t ) FILTER x ( ( k − 1) Ts + ˆ )
x ( kTs + ˆ )

x ( ( k − 1/ 2 ) Ts + ˆ )
INTERPOLATION
CLOCK CONTROL Ts
T
T= s
N LOOP
FILTER
Ts

TED x ( ( k − 1/ 2 ) Ts + ˆ )
x ( kTs + ˆ )
x ( ( k − 1) Ts + ˆ )

Architecture of symbol timing synchronizer Gardner Timing Error Detector (TED)

[2] Michael Rice, Digital Communications – A Discrete Time Approach (2008). Chapter 8 20/49
 2.3 Symbol timing synchronization
Loop filter Interpolation control
Timing error
K1
r ( nT ) Interpolator x ( nT )
Control signal

 (k )

underflow
K2
Compute
1  (k )
N

Z −1
W (n) Z −1
PI  (n)
1 4 n Control signal Modulo – register
K1 = 
K p K 0 1 + 2 n +  n2
1 4 n2
K2 = 
K p K 0 1 + 2 n +  n2
BnTs
n = 𝑁 :sample/symbol
 1  𝐾𝑝 : Loop gain of TED
N  +
 4  𝐾0 : Loop gain of accumulator in Interpolation control
[2] Michael Rice, Digital Communications – A Discrete Time Approach (2008). Chapter 8 21/49
 2.3 Symbol timing synchronization
There are many interpolation algorithms, and Piecewise Polynomial Interpolation is quite simple to use. It uses polynomials to
approximate new samples from previous ones.
x ( kTI ) = c p ( kTI ) + c p −1 ( kTI ) + c1 ( kTI ) + c0
p p −1
+
kTi = ( m ( k ) +  ( k ) ) T
With 𝑝 = 2 we have
1
x ( ( m(k ) +  (k ) ) T ) =  h2 (i )x ( ( m(k ) − i )T )
i =−2

h2 ( −2 ) =  ( k ) −  ( k )
2

h2 ( −1) = − ( k ) + (1 −  )  ( k )
2

h2 ( 0 ) = − ( k ) − (1 −  )  ( k ) + 1
2

h2 (1) =  ( k ) −  ( k )
2

[2] Michael Rice, Digital Communications – A Discrete Time Approach (2008). Chapter 8 22/49
 2.3 Symbol timing synchronization
Farrow interpolator structures

[2] Michael Rice, Digital Communications – A Discrete Time Approach (2008). Chapter 8 23/49
 2.4 Carrier phase synchronization
Conceptually, carrier phase synchronization is the process of forcing the local oscillators in the detector to oscillate in both phase
and frequency with the carrier oscillator used at the transmitter [2].

I BASEBAND
PHASE ERROR LOOP FILTER
DETECTOR
Q BASEBAND

DDS
SIN

COS

Fig 2.7: Carrier phase synchronizer structure

[2] Michael Rice, Digital Communications – A Discrete Time Approach (2008). Chapter 7 24/49
 Carrier
2.4 phase
Carrier synchronization
phase synchronization

K Q PHASE
I sym ( k ) =  m1 (k )cos e − m2 (k )sin e 
2 Received symbol
K
Qsym ( k ) =  m1 (k )sin e + m2 (k )cos e 
2 Reference symbol

 m1 (k )sin e + m2 (k )cos e  −1  m2 ( k ) 
ˆe = ˆ − 
g (e ) = tan 
−1
 − tan  
m
 1 ( k )cos  e − m2 ( k )sin  e  m1 (k ) 

̂
I PHASE

[2] Michael Rice, Digital Communications – A Discrete Time Approach (2008). Chapter 7 25/49
 Carrier
2.4 phase
Carrier synchronization
phase synchronization

 3
e +  −   e  −
4

 +  −
3
 e  −

 e 2 4 4
  
g (e ) = e −  e 
 4 4
   3
  e −  e 
2 4 4

 −  3
 e  
 e 4

Fig 2.8: S-curve for QPSK constellation using the phase detector

[2] Michael Rice, Digital Communications – A Discrete Time Approach (2008). Chapter 7 26/49
 Carrier
2.4 phase
Carrier synchronization
phase synchronization
ENABLE PHASE ERROR DETECTOR

I SYMBOL

REGISTER
SYMBOL PHASE
ATAN LUT
Q SYMBOL
PHASE ERROR

SUB
450

REGISTER
1350

MUX
REFERENCE PHASE
2250 DDS
3150

ENABLE
ENABLE

REGISTER
SIN

SUM
CAST
32 32 DUAL PORT
FREQ_CTRL
10 SIN ROM
LOOP FILTER COS

SUM

SUM
LEFT SHIFT
256
N1

SUM
PHASE ALIGN

MUX
LEFT SHIFT
0
N2
REGISTER

Fig 2.9: Hardware implementation architecture of carrier phase synchronier

[2] Michael Rice, Digital Communications – A Discrete Time Approach (2008). Chapter 7 27/49
 Demodulation
2.4 Carrier Scheme
phase synchronization

DOWN CONVERTER
MIXER
I CHANNEL CIC HALFBAND RRC I BASEBAND TIMING
FILTER FILTER FILTER SYNCHRONIZATION

SIN DDS I SYMBOL PARALLEL

PHASE CONTROL CARRIER PHASE TO BIT_STREAMS
IF SIGNAL ADC SYNCHRONIZATION SERIAL
Q SYMBOL
COS
I BIT
DOWN CONVERTER
SYMBOL DECODER Q BIT
CIC HALFBAND RRC
FILTER FILTER FILTER Q BASEBAND
Q CHANNEL
MIXER

Fig 2.10: Demodulation scheme with symbol timing and carrier phase synchronizer

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2.5 Simulation Result

Fig 2.11: Symbol timing synchronization progress

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2.5
Simulation
Simulation
Result
Result

Fig 2.12 Carrier phase synchronization progress

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 Problems
The purpose model has some drawbacks:

❖ The symbol timing synchronizer needs desired input signal level to work properly

phase ambiguity with QPSK carrier phase synchronizer

𝜋
❖ 2

❖ Large frequency offset

❖ Multipath fading

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3. ENHANCING QUALITY
TECHNIQUES

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3.1 Differential Coding
3.2 AGC
3.3 Carrier Frequency Offset Estimator
3.4 CMA Equalizer

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 3.1 Differential Encoding
Differential Encoding is a resolution to address phase ambiguity for QPSK system

01 11
Symbol Phase
+ phase
11 0
00 +

01 +
2

10 −
00 10 2

- phase

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 3.1 Differential Encoding
b2k b2 k −1  2 k −2  2 k −1  2k  2 k +1
01 11
0 0 0 0 1 1
+ phase
0 0 0 1 1 0
0 0 1 0 0 1
0 0 1 1 0 0

00 10 0 1 0 0 0 1

- phase
0 1 0 1 0 0
0 1 1 0 1 1
b2k 0 1 1 1 1 0
b2 k +1 Look up  2k 1 0 0 0 0 1
table  2 k +1 1 0 0 1 1 1
1 0 1 0 0 0
1 0 1 1 1 0

D 1 1 0 0 0 0
 2 k −2
1 1 0 1 0 1

 2 k −1 D
1 1 1 0 1 0
1 1 1 1 1 1
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 3.1 Differential Decoding
ˆ2 k ˆ2 k +1 ˆ2 k −2 ˆ2 k −1 bˆ2 k bˆ2 k +1
0 0 0 0 1 1
0 0 0 1 0 1
0 0 1 0 1 0
ˆ2 k 0 0 1 1 0 0

ˆ2 k +1 0 1 0 0 1 0

bˆ2 k 0 1 0 1 1 1

D ˆ Look up 0 1 1 0 0 0
 2 k −2 table 0 1 1 1 0 1

bˆ2 k +1 1 0 0 0 0 1
D 1 0 0 1 0 0
ˆ2 k −1 1 0 1 0 1 1
1 0 1 1 1 0
1 1 0 0 0 0
1 1 0 1 1 0
1 1 1 0 0 1
1 1 1 1 1 1

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 3.1 Differential Decoding
Let consider the example

Transmitted bitstreams Received bitstreams

0011010101000111 1111010101000111

k b2k b2 k −1  2 k −2  2 k −1  2k  2 k +1 k ˆ2 k ˆ2 k +1 ˆ2 k −2 ˆ2 k −1 bˆ2 k bˆ2 k +1

Shift +
0 0 0 0 0 1 1 0 0 0 0 0 1 1
1 1 1 1 1 1 1 1 0 0 0 0 1 1
2 0 1 1 1 0 1 2 1 0 0 0 0 1
3 0 1 0 1 0 0 3 1 1 1 0 0 1
4 0 1 0 0 1 0 4 0 1 1 1 0 1
5 0 0 1 0 0 1 5 1 0 0 1 0 0
6 0 1 0 1 0 0 6 1 1 1 0 0 1
7 1 1 0 0 0 0 7 1 1 1 1 1 1

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 3.2 Automatic Gain Control

DOWN CONVERTER
MIXER I BASEBAND
I CHANNEL CIC HALFBAND RRC I AGC
FILTER FILTER FILTER BASEBAND TIMING
SYNCHRONIZATION
SIN

DDS I SYMBOL
AGC PHASE CONTROL CARRIER PHASE PARALLEL
IF SIGNAL ADC TO
PASSBAND SYNCHRONIZATION BIT_STREAMS
Q SYMBOL SERIAL
COS

I BIT
DOWN CONVERTER
SYMBOL DECODER
CIC HALFBAND RRC Q AGC
BASEBAND Q BIT
Q CHANNEL FILTER FILTER FILTER Q BASEBAND
MIXER

Fig 3.1: Demodulation scheme with additional AGC

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 3.2 Automatic Gain Control

For passband signal For baseband signal

r(n) ra(n) x(n) xa(n)

A(n) Compute
y(n) ya(n)
z-1 Signal
Level
A(n)
α R z-1

𝐴 𝑛 + 1 = 𝐴 𝑛 + 𝛼 𝑅 − 𝑟 𝑛 𝐴𝑟 (𝑛) α R
Compute Signal Level

𝐴𝑀𝐹 𝑛 = 𝑥𝑎2 𝑛 + 𝑦𝑎2 (𝑛)

Fig 3.2: The classical structure of AGC

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 3.2 Automatic Gain Control

16QAM passband signal 16QAM signal level calculated by square method

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 3.2 Automatic Gain Control
𝑁
1
𝐴𝐺 = ෍ max 𝑟𝐺 𝑖
𝑁 𝑖=1→𝑊
𝑖=1
Error A
|e| > Δ ABS
A>B
B
sign Peak

REG
REG
average Reset
MUX 1
REG

0 R
Enable Enable
-1 Window
counter
PEAK DETECTOR Signal out
|e| < Δ
GAIN >0
1
MUX
REG

0
Amplitude

MUX
-1
adding Signal in
LOOP FILTER Adding
factor mul
factor

Fig 3.3: Purpose AGC architecture

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 3.3 Carrier Frequency Offset Estimator
For QPSK, we can estimate the carrier frequency offset using correlation method

𝑀
𝑓𝑠
෢
∆𝑓 = 𝑎𝑟𝑔 ෍ 𝑅(𝑘)
4𝜋(𝑀 + 1)
𝑘=1

𝑅 𝑘 = ෍ 𝑟′𝑖 × 𝑟′𝑖−𝑘
𝑖=𝑘+1

𝑓𝑠 : sampling frequency

𝑁 : number of samples used to calculate autocorrelation

𝑀 : Max lag

𝑟′ = 𝑟 4 , 𝑟 is QPSK baseband signal (Complex form)

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 3.3 Carrier Frequency Offset Estimator
M taps

rk ( . )* D D D D

ACCUMULATOR

 R(k )
LUT

f

[3] Luise, M., and R. Reggiannini. “Carrier Frequency Recovery in All-Digital Modems for Burst-Mode Transmissions.” IEEE® Transactions on
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Communications, Vol. 43, No. 2/3/4, Feb. 1995, pp. 1169–1178.
 3.4 CMA Equalizer
For CMA algorithm
L taps
𝑒 = (𝑅 − 𝑦) × 𝑠𝑖𝑔𝑛(𝑦) input x u1 u2 u3
D D D D
uL
𝑾𝒏𝒆𝒘 = 𝑾𝒄𝒖𝒓𝒓𝒆𝒏𝒕 + 𝑆𝑡𝑒𝑝𝑠𝑖𝑧𝑒 × 𝑼∗ ×𝑒 Adaptive W1 W2 W3 W4 WL
Algorithm

y output

Decision
Device

yd

d
Training
bit
e Error
calculation

Fig 3.4: Linear Equalizer structure

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4. IMPLEMENTATION
ON FPGA

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4.1 Implementation result

4.2 Demo model

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4.1 Implementation result

Table 1: Utilization of Receiver design on FPGA XC7A35T

Resource Utilization Available Utilization
(%)
LUT 2350 20800 11.08
LUTRAM 174 9600 1.81
FF 3560 41600 8.5
BRAM 5.5 50 11
DSP 10 90 11.11

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 4.2 Demo model

Demodulated waveform Testing model with coaxial cable

QPSK SIGNAL TRANSMITTER

DEMODULATION WAVEFORMS

RECEIVER

Carrier frequency: 10 MHz

Bit rate: 1 Mbps

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 4.2 Demo model

20 MHz

PA LNA
-5 dBm 10 dBm
Transmitter Receiver
20TB.FPGA-2021 20TB.FPGA-2021

Wireless testing model with antenna 315 MHz

Carrier frequency: 20 MHz

Bit rate: 1 Mbps

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