Deleonibus Presentation

More MOORE and MORE THAN MOORE MEETING FOR 3D
S.Deleonibus, CEA-LETI, MINATEC Campus, 17 rue des Martyrs , 38054 Grenoble Cedex 09 France.
Tel : 33 (0)4 38 78 59 73 ; Fax: 33 (0)4 38 78 51 83; email: sdeleonibus@cea.fr
INSTITUTE FOR ENERGY EFFICIENCY Santa Barbara, California, December 2, 2011
CEA LETI organization

* Grenoble
Technological Research
1,600 Researchers 1,600 Researchers 3,200 Researchers 3,200 Researchers
Fundamental Research French Nuclear Agency

15,000 Employees 15,000 Employees 3 billion Budget 3 billion Budget
Micro Nano Technology & integration in System

* Saclay
Electronuclear Energy Res.
Software oriented system

* Grenoble
Defense
New technology for Energy & Nanomaterials

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CEA. All rights reserved
S.Deleonibus CEA-LETI December 2011
LETI: Mission and Focus

A single mission : Create innovation & transfer it to industry
A clear focus :
-nanotechnologies, with critical mass in Si Advanced devices for new applications
Mass Production Products Pilot Line Prototypes
Basic Research Publications
Applied Research Patents

|3
LETI in a few numbers - 2010

1 600 researchers
1 000 permanent LETI staff
300 M budget
> 73% from contract ~ 40 M CapEx
200 and 300mm Si capabities 8,000 m clean rooms Continuous operation
350 new patents in 2010 Portfolio > 1,500 patents 32 start-ups

Microelectronics Microsystems Biology & Health Photonics Wireless & Smart devices Energy & Environment S.Deleonibus CEA-LETI December 2011
|4
Since 2005: A complete set of research platforms

CEA LETI (1600 CEA researchers) collaborating in MINATEC campus (>4000 researchers)
MicroTechs for bio 200mm 300mm CMOS new concepts CMOS Integration & Beyond CMOS & adv. modules More Than Moore 200mm Nanoscale Characterization
Incu b ation
Adv anc e 100 d Rese -200 a mm rch
Design
Education interacting daily with R & D platforms worldwide (ST Crolles, IBM Albany, )
|5
Micro/nano-Technologies Micro Nano Technologies
Bio-Technologies
Sciences de base
Nouvelles Technologies pour lEnergie
New Energy Technologies
BioTechnologies Basic research
Budget : 1
Billion
with investment : 150 M 10 000 researchers 10 000 students

> 5 000 publications/year > 500 patents/year
|6
Outline
Introduction : Trends and Hot Topics in Nanoelectronics Nanoelectronics scaling and use of the 3rd dimension to continue Moores law. Interfacing the Multiphysics World (More Than Moore) thanks to functional diversification Building new systems and their packaging with a 3D tool box at a wafer level. Conclusions

|7
Semiconductor Market applications successive waves

Quality of life, Social, Environment, Health, Energy, associated to ICT
Source : Semico Research Corp. May 2004 IPI Report

|8
Ecological Footprint of ICTs

Source: TU reported by Intergovernmental Panel Climate Change(IPCC) Dresden
Currently, 3 % of the world-wide energy is consumed by the ICT infrastructure

which causes about 2 % of the world-wide CO2 emissions comparable to the world-wide CO2 emissions by airplanes or of the worldwide CO2 emissions by cars
ICT: 10% of electrical energy in industrialized nations

900 Bill.. kWh / year = Central and South Americas
The transmitted data volume increases approximately by a factor of 10 every 5 years
For ICTs, keep in mind: Pstat= VddxIoff and Pdyn=CVdd2 f P = Pstat + Pdyn
|9
Scaling: a success storythanks to innovation

Moores law: 2Xdevices/year
1,00E+10
Convergence Digital Camera

2G 4G
Portable Internet
1,00E+09
1 billion
1,00E+08
Number of transistors per chip
1,00E+07
10 millions
VCR Defense Main Frame
64k 16k
1,00E+06
1G 512M ULK(11 lev met) 256M rs Office o 128M polymers ss ) M 64M ce Itanium PC o A r +ALD (10 lev met) DR op Pentium IV es( 16M cr i i or m HiK +metal gate m e Pentium III m 4M ic Cu+H(M)SQ (9 lev met) am 1M Pentium II yn d Cu (7 lev met) Pentium 256k i486
Home PC
FSG(6 lev met)
1,00E+05
80286 8086
1,00E+04
4k
10m
C.T.V.
1,00E+03
1k
8080 4004
STI, salicide contacts plugs (3 lev met)
1m
1,00E+02
0,10m
polycide
1,00E+01
poly gate
1958 1963 1968 1973 1978 1983 1988 1993 1998 2003 2008 2013 2018
10 nm
1,00E+00
Date
Electronic Device Architectures for the Nano-CMOS Era From Ultimate CMOS Scaling to Beyond CMOS Devices Editor: S.Deleonibus, Pan Stanford Publishing, Oct 2008 S.Deleonibus CEA-LETI December 2011
Critical Dimension
| 10
i386
100m
damascene(5 lev met) vias plugs ,CMP(4 lev met)
Nomadic consumer and professional products: largest market share continuously increasing Three major product families
(ITRS aware of CMOS scaling limits)
High Performance (HP)
Connection to power network
t=CV/I
Low Operating Power (LOP)

Intermittent Nomadic Function
Low Stand-by Power (LSTP) Pstat= VddxIoff

Permanent Nomadic Function
Pdyn=CVdd2 f Ptot=Pstat+ Pdyn

| 11
More, More than, Beyond Moore

Tomorrows top added value markets
High growth with More than Moore technologies: they require expertise in all technical domains and inITRS 2009 & 2011 depth knowledge of the targeted markets
| 12
EUV ( = 13.5nm)
from S.A. Campbell, The Science and Engineering of Microelectronic Fabrication, Oxford University Press 2001
Engineering Test Stand (VNL/EUV-LLC)
60% reflectivity for several hundreds of Si / Mo stacks w roughness precision < 3 Placement of mirror and mask Photoresist
>100 M$ 100Wph !!
| 13
System made of 13,000 electron beams working in parallel (MAPPER) (1)

Electron source
Key numbers 22nm node:

HVM
Collimator lens
pre-alpha 110 35 nm 0.3 nA 20 MHz
#beams and data channels Spotsize: Beam current: Datarate/channel
13,000 25 nm 13 nA 3.5 Gbs
Aperture array Condensor lens array
Acceleration voltage
Beam Blanker array Beam Stop array Beam Deflector array Projection lens array
5 kV
5 kV
Nominal dose Throughput @ nominal dose Pixel size @ nominal dose Wafer movement
30 C/cm2 30 C/cm2 10 wph 3.5nm 0.002 wph 2.25 nm
Scanning Static

| 14
System made of 13,000 electron beams working in parallel (MAPPER) (2)
MAPPER single column tool. Upgrade to 13,000 beam for 10WPH
Cluster 100WPH
1m
Interface to track

| 15
Hot Topics in MOSFET technology

Introduction of HiK and metal gate allows continued scaling and relaxes SiO2 gate leakage current related issues - Ig added to SCE, DIBL, subthreshold leakage(LETI IEDM 2002, Intel IEDM 2005) Statistical dopant variability - number of dopants in the active area decreases with scaling - random distribution of channel dopants 12
Poissons law. Standard deviation:
doping =
10
4
N Volume
1 N/N
1000 0.1 100
Nombre d'impurets
Statistical fluctuations of threshold voltage: 150 mV decay for VT=200mV( Lg=25nm) !!
0.01 0.01
10 0.1 Lg (m) 1
Major interest for Low Doped channels

| 16
S.Deleonibus et al. ESSDERC 1999
Outline

| 17
32nm Low Power FDSOI Undoped channels

6T SRAM
300mm wafers
+5 0 -5
Range = 4 !
XUT+/- 5 - SOI thickness deviation
10
SOI Thickness Deviation to target ()
8 nm TSi
10 nm BOx
SOI Thickness Max Mean Min
-5
0.248m2 SNM (1.2V)=140mV 0.179m2 SNM (1.2V)=230mV VDD=1V Ioff=6pA/m

V.Barral et al., IEDM2007
-10 1 9 17 25 33 41 49 57 65 73 81 89 97 105 113 121 129 137
Wafer #
C.Fenouillet Beranger et al., IEDM 2007, VLSI Symp 2010

| 18
Record-high VT matching performance FDSOI Undoped channels vs.FinFET

3
120
Vt=34.5mV
100
FinFETs Planar FDSOI
W =10nm
fin
square : V =50mV
d
2.5
[13]
circle : V =1V
d
A (mV.um)
Vt=24.5mV AVt=0.95mV.m
Count
80 60 40
2
[12]
W =20nm
fin
[13]
W=60nm L=25nm
Vt
1.5 1 UTBSOI LETI [1]

[14] W =15nm
fin
[15] [16] [15] W =20nm

fin
20 0
-6 9 -3 3 5 -8 7 -1 5 -5 1 33 69 15 51 87 0 -1 0 10 5
0.5 10
20
30
40
50
60
Vt shift Vt (mV)
Gate length L (nm)
O.Weber et al., IEDM 2008
Vt =
(Vt=Vt/2 to compare measurements on pairs and on arrays of transistors in the literature)
AVt WL
Best trade-off between VT variations and gate length scaling compared to bulk MOSFETs and FinFETs
| 19
Multi VT solutions for SOC design UTBOX + Back bias ; Gate stack engineering
0,9 0,8 0,7 0,6
HfSiON/TaAlN/TaN HfSiON/TaN/TaAlN HfSiON/Al203+/TiN HfO2/Al203+/TiN HfSiON/TiN10 HfSiON/TiN HfO2/Al203/TiN HfSiON/TiN5 HfO2/TiN
VTN (V)
0,5 0,4 0,3 0,2 0,1 0 0 0,1 0,2 0,3 0,4
0,5
0,6
0,7
0,8
0,9
VTP (V)
BOX = 10nm and VBB/ Ground Plane N and PMOS: VT modulation of 200mV
F.Andrieu et al. , VLSI 2010 Honolulu O.Faynot et al., IEDM 2010 San Francisco, invited talk
VT tuning by gate stack engineering

| 20
Merits of FDSOI
Delay vs. Power x Delay 22% improvement/bulk (20nm) Reachable Scaling rules (TSi, TBOx)
O.Faynot et al, IEDM 2010, invited talk L.Clavelier et al, IEDM 2010, invited talk
| 21
Bulk or thick SOI
Jahan et al. VLSI2005
Gate t source Planar

ThinSOI
Strain global & local
TSi=2.5nm
Barral et al. IEDM2007
3.4 nm
Gate source t
TSi= Lg
Andrieu et al VLSI2006
4.8 nm
Lg=10nm
Double-gate Planar or Finfet
w Gate t
Vinet et al. EDL 2005
Thin Films Devices

Relaxing optimization scaling rule TSi= Lg by architecture
source
Trigate/ nanowire
Bernard et al. VLSI 2008 Dupr et al. IEDM 2008 Ernst et al. IEDM 2008
TSi= 1 to 2 Lg
Gate Source
L
| 22
Stacked Multichannels and MultiNanowires Top-Down approach: device fabrication

Si/Si0.8Ge0.2 superlattice epitaxy on SOI Anisotropic etching of these layers Isotropic etching of SiGe or Si Gate depositions
HfO2 (3nm) TiN (10nm) Poly-Si (200nm)
Gate etching
Gate
SiN SiGe Si SiGe Si SiGe Si BOX BOX BOX
Gate
BOX
BOX
Top view of our device

S/D implantation Spacer formation Activation anneal Salicidation
Standard Back-End of-Line Processes
Nanowires
Source Gate
500 nm
Drain

| 23
Stacked Multichannels and MultiNanowires Tunable width Top-Down approach Design flexibility to tune
6 Conductance (a.u.) Conductance (a.u.) 5 4 3 2 1 0 0
1 nanowire 1 nanowire
the conductance
3 multi W - channels (MC) 3 nanowires Finfet
W v v pitch v
planar
1 2 1 2 Layout width (a.u.) Layout width (a.u.)
1 2 Layout width
See for details: T. Ernst et al, IEDM06,08 SSDM07, ICIDT08 E. Bernard et al. VLSI08, ESSDER07 C. Dupr et al, IEEE SOI Conference 07 S.Deleonibus CEA-LETI December 2011
| 24
Stacked Multichannels and MultiNanowires Top-Down approach
Drain Current I D (A/m)
10-2 10
-4
V =1.2V
D
V =1.2V NWFET
D D
LETI top down approach for Low Power and High performance
-CV/I outperforms Planar in loaded environment -Improved voltage gain (8GHz) wrt Planar -Gate separation possible -Transport properties in small nanowires
LETI: Dupr et al. IEDM 2008, San Francisco(CA) Ernst et al., Invited talk IEDM 2008, San Francisco(CA) Bernard et al, VLSI Symposium 2008 Honolulu K.Tachi et al., IEDM 2010, San Francisco
V =50mV
D
V =50mV I I
ON
10-6 ION=3.3mA/m 10 10
-8
=6.5mA/m =27nA/m
OFF
=0.5nA/m
OFF
-10
SS=65mV/dec DIBL=7mV/V V =-0.62V

T
SS=68mV/dec DIBL=15mV/V V =0.5V

T
C.E.T.=1.8nm
10-12 -2 -1.5 -1 -0.5 0
0.5
G
1.5
Gate Voltage V (V)

| 25
Pervasion of Nanowire technology

Mass detection
Q=870 resonator Gauge width = 80 nm
15 nm oscillator
Poly Si SiO2 Si3N4 SiO2
Zeptogram mass resolution
20nm
Buffer solution at pH<7
Buffer solution at 7<pH<10
Buffer solution at pH>10
n-doped Si
Metal
Passivation
Hole
130
Electron
pH 2 pH 3 pH 5 pH 6 pH 7
0 2000 4000 6000 8000 10000 12000 120 110 100 90 80 70 60
Conductance (nS)
Chemical sensing 3D NAND Flash Memories

T.Ernst et al., IEDM 2008 Hubert et al., IEDM 2009
pH 4
Time (s)

| 26
Tunnel FET Operation principle

Log ID
ideal switch MOSFET
N & P operation modes

A single TFET device can operate either in n or p channel mode N mode : VSD>0 & VGD>0 P mode: VDS<0 & VGS<0
Source N+ VS=0V EFn EC VG < 0
IOFF Vth
TFET
VG<0 VS=0
Gate
P mode VD<0
Drain P+
VG
Source N+
BOx Si
Source N+ VS>0V EFp Drain P+ VD<0 EFn EC
N mode
=0
VG
VG
=0
EFp Drain P+ VD=0
EV
P mode
VG > 0 EV

| 27
SOI TFETs co-integrated with CMOSFETs

Experimental demonstration of Tunnel FET operations: P mode
G S BOx
SOI TFET w. LDDn
SiN protection layer NiSi NiSi
N mode
D
50nm 1st spacer 2nd spacer

NiSi
Gate
Poly HfO2 TiN tSi
NiSi Source HDD
Drain
HDD LDD
LG
P mode: VDS<0 & VGS<0 N mode: VSD>0 & VGD>0

L=100nm; T=300K
F.Mayer et al., IEDM 2008, C.LeRoyer et al., ULIS 2009

| 28
TFET for Ultra Low Power outperforms CMOS Offset/drain reduces Ioff(ambipolar current)
LETI: Mayer et al, IEDM 2008 Intel: U.E. Avci et al, VLSI Tech Symp 2011
Multigate improves Ion

EPFL: K. Boucart & A. M. Ionescu, ESSDERC 2006 TUM: M. Schlosser et al. IEEE TED, Jan. 2009

| 29
3D sequential process
Co-Integrating Heterogeneous orientation or materials
Ge
(100)
eff, hole ( cm /V.s )
(110)
100
pMOS
50
Reference TiN/ HfO2/ Si (100) TiN/HfO2/Si(110) <100>
-4T SRAM 0 0.0 0.2 0.4 0.6 0.8 1.0 - cold end process(bonding). Eeff (MV/cm) Opportunities for other SC(Ge,III-V,...) - improved layout (40% area SRAM cell) -dynamically controlled VT: improved RNM and SNM P.Batude et al., Best student Paper Award, IEDM 2009
First heterogeneous orientation in 3D Si sequential integration Enabled by use of wafer bonding by keeping low thermal budget
| 30
Sequential 3D: towards nanoscale devices

LG~50 nm
Tsi ~10 nm LG~50 nm
TiN THFO2 2.5 nm

P.Batude et al, 2011 VLSI Tech Symp P.Batude et al., IEDM 2011, Invited talk
Tsi 10 nm
First demonstration of 3D sequential structure down to LG 50 nm

| 31
Specific interest of low temperature process

0.03 EOT= 1.15nm Capacitance (F/m2) 0.02 EOT= 1.45nm
HfO2= 2.5nm
Top FET Bottom FET
0.01
BOX
0.00
-2
-1
Gate Voltage VG(V)
The low temp. process (600C) leads to a reduced EOT Explained by a reduction of interfacial oxide growth
P.Batude et al, 2011 VLSI Tech Symp
| 32
Sequential 3D: Potential and Demonstrated Applications

High density logic applications
~ 1 node gain with same design rules for Front end levels
Highly miniaturized CMOS imagers pixels
P. Coudrain et al, IEDM 08,
Heterogeneous integration
pMOS Source pMOS Gate
3D memories
SRAMs FLASH
2m top GeOI pMOS
Nanoelectronics & Photonics applications with Si-Ge Co-integration SRAM on top SOI logic, I/Os, analog on bottom bulk
nMOS Gate nMOS Source
bottom SOI nMOS
Y-H. Son et al, VLSI 07, Jung et al, IEDM 2006 | 33 S.Deleonibus P.Batude et al., IEDM 2009, Best Student Paper Award CEA-LETI December 2011
P. Batude et al,VLSI09
3D-Xbar Memory stacked on Logic: towards NV Logic
Resistive switches
Toshiba, Stanford Univ.: K.Abe et al, ICICDT 2008
proven in 2D with Logic + Stacked NVM: Magnetic Tunnel Junctions, High bandwith, FeRAM Tohoku Univ., Hitachi: Reduced Power consumption, S.Matsunaga et al., Appl.Phys. Express(2008); ROHM Reconfigurability ex: 32 nm node : > 1TB/s per 1mm2
| 34
Advanced Devices and Systems Future Vision

More than Moore
3D stacked Mixed functions: NV Logic +sensors/polymers X bar Fe
Si
III-V/Ge
Heat sink C
3D
Diversified Logic (association to Memory, Passives, Sensors,)
3D stacked devices Memory storing (SRAM, NVM) ZDRAM

3D
3D Nanowires Low stress, HiD
FDSOI
Logic
Std SOI
UTBOX sSOI
16nm
Nanowire Dual channel
HP options More Moore

22nm
xsSOI(N)/ Ge(P)
11nm < 11nm
2015 2012 2009 2013 2014 2010 S.Deleonibus CEA-LETI December 2011 Transfer to Industry Development
2016
| 35
Carbon electronics(CNT,Graphene, Diamond)
3D Sensing/Actuation Bio, Mechanical & Chemical (functionalization, NEMS, Single electronics, RF, opto, )
Beyond CMOS
(e-waves confinement, Spin electronics)
Opportunities for other materials on Silicon

Electronic Device Architectures for the Nano-CMOS Era From Ultimate CMOS Scaling to Beyond CMOS Devices Editor: S.Deleonibus, Pan Stanford Publishing, July 2008
Material n (cm2V-1s-1) p (cm2V-1s-1) sth (W/m/K) Rel. K Eg(eV) vsat(107cm/s) ni(cm-3)
(m*em*h /m2)T3/2 exp(-Eg/2kT)
Si
1400
500 1900 400 300
141 59.9 55 5
11.9 1.12 16 0.66
0,86 0,60 0.72 0.6
2x1010 2x1013 2.1x106 6X1011
Well established high quality material (>40yrs experience) Oxidizable !
Ge Silicon compatible3900 GaAs

Available in all fabs GaAs lattice constant matching
8500
12.9 1.42 13.9 0.74
InGa0.47As0.53 InSb
12 000 77000 2200
Opto/Power RF applications Ge compatible HP N channel
BTBT TFET/W
Poor short channel 850 1.8 16.9 effect immunity 2x1016 0.17 5,0 @77K Highest n but Worst n/p!!
Passive layer combine w BOx (thermal shunt)
C-Diamond sp3 Graphene (CNT) sp2
1800
2000
5.7
5.47
2,7
Highest th
5.7 Semi- 4 metal
High short channel effect immunity

1x1012cm-2 (1x1015)
10-27
104-105
104-105 1000
Most compact logic, Interconnect

| 36
Outline

| 37
NEMS scaling laws. Is it worth scaling?

- resolution increases - sensitivity decreases (SBR,SNR) => arrays, actuation, - figures of merit pressure and vacuum quality dependent
Parameter Scaling rule mass stiffness
noise
m =
DR
M eff Q
10 ( DR / 20 )
1 SNR
k3 k k-1
M eff l w t
eff
Pact
t3 w 3 l
resonant frequency
ML Roukes et. al. APL (2005)
f0
eff
M eff
t l2
mass responsivity
k-4 k3 [rough estimate]
f 0 f0 = = M eff 2 M eff
energy consumption
1 2 EP eff xMax 2 and xMax t

| 38
Nanowire used for mass detection

Q=870 resonator Gauge width = 80 nm
15 nm oscillator
Capacitive actuation & detection
Capacitive actuation & piezo-resistive detection with nanowires
m 0.5 zg / Hz
Thermo-elastic actuation & piezo-resistive detection.
NEMS array
- First 200 mm wafers with 3.5 millions NEMS - Association Nanowire/Resonator ; Cantilever arrays LETI: T.Ernst et al., IEDM 2008, Invited talk CMOS compatible
L. Duraffourg et. al, APL 92, 174106 (2008) E Mille et al, Nanotechnology, 165504, (2010)
| 39
M&NEMS co integrated devices platform for 3D sensing 3-axis accelerometer i R/R<5x10 ( 1g)
-4
Linearity <0.3% ( 0 and 200MPa) S<1mm2 (3 axis)
Area 4 vs SoA
3-axis gyroscope
F0 20.3 kHz Q > 100.000 S=0.8mm / axis
P.Robert et al, 2009 IEEE Sensors D.Ettelt et al, 2011 Transducers
Nanobeams
microphone 3D magnetometer
Resol 20-80 nT/Hz Lin 4.5 mT S=0.25 mm/axis
pressure sensor
| 40
NEMS switch
high speed
rf
from AB. Kaul et al., Nano Letters 6(5) 942-947 (2006)
bistable
memory
from D. Tsamados et al. Solid-State Elec. 52 1374 (2008) from Q.Li et al.,IEEE Nano 6(2) 256-262 (2007)
high on/off
low power logic

| 41
Outline

| 42
System On Wafer: Heterogeneous co-Integrated Systems

(Parallel 3D)
Energy source converter Wafer level packaged MEMS MEMS 80 m diameter TSV imagers packaging
Commercial products - image on board Memories + VGA camera, Stacked

- mixed nodes & modes, Logic, Sensors,, - high density TSV
Cooling option
Si 1m 12m
Cross talks:
-delay, matching, -power dissipation
Stacked ICs l ogy chno ack Embeddedtpassives (global temp. increase, el te spin st (Passives, filters, IC 1 m diameter ab Oxide/Oxide bonding ) Optical Interconnects Vi torque osc,) hot spots, reliability, S + t 3D High AR TSV stacked ICs EM fla ) M Heterogenous Integrationr On Silicon ltra ing(TSV se U Multiphysics k o st is in into Packaging ac takenterp account Chip ilicon New Progress Laws at the 3D wafer level S tive Copper/Copper Ac - application specific bonding | 43
Si
Si Cu Si SiO2
3D Integration: from imagers to advanced 3D ICs

ST LETI collaboration
Mixed Signal Digital/Analog
ST LETI collaboration
Stack structure
170m 30m 120m
400m
TSV~3m
Thin Si~15m
2001
Pitch 120m
80m
TSV~3m Metal1 Thin Si~15m
Pitch 50m
with TSV
2008
3D-IC
Thinned wafer (~100 m)
Die to Die Copper pillars
Memory, Processors, Imagers NEMS with high density TSV, NEMS
VGA cameras (300kpixels)
Diam 60m Thick 120 m
Die to substrate copper pillars
Via Last TSV (Aspect Ratio 2-3)
3D high density
Active Silicon interposer Image-on-Board

| 44
Photonics Integration on Silicon. The building blocks.
Optical modulator
Photodetector
MUX & DEMUX
Waveguide Laser source Grating coupler In-plane coupler
Optical switch LETI: L.Fulbert ESSDERC 2011, Invited talk S.Deleonibus CEA-LETI December 2011
| 45
Application Drivers
E BIL S MO LES E WIR ER UM S ON C
Great focus on packaging & integration

H ALT
HE
ING UT E P OM ORAG C T &S
T AU
E TIV MO
Form Factor
Ultra small TV Tuner , Sharp Computer control using thoughts Quad Core Intel
Cost
Full tranceiver on Chip, Antenna+RF+ Baseband, Leti 128 GB SSD, Toshiba
Performance
Nokia N82, 5Mpixel Video capture, coding, transmission
One Chip SetTopBox (STM)
Intel's Teraflop Chip

| 46
Conclusion :Nanoelectronics CMOS from Devices to Systems Perspectives

Si CMOS: Nanoelectronics Base platform beyond ITRS Durable Low Power solutions:
health, environment, quality of life, energy, IST,
Low Power consumption: major challenge (sub 1V VDD CMOS).

=> Device/ system architecture optimization: Thin Films Gate All Around nanowires, low slopes,layout, 3D => Opportunities for new materials on Silicon (Ge, revised low BG III-V, Carbon,) to co-integrate from LSTP to HP.
Heterogeneous 3D co-Integration on Si, Low Power: Monolithic/Sequential 3rd

dimension in device. New active materials Reconfigurability with NVM ; NV Logic System On Wafer: 2 to 3D heterogeneity functions & chips

| 47
Thank you for your attention Merci de votre attention
Electronic Device Architectures for the Nano-CMOS Era

From Ultimate CMOS Scaling to Beyond CMOS Devices edited by Simon Deleonibus (CEA-LETI, France) Cloth July 2008 978-981-424128-1
Discusses the scaling limits of CMOS, the leverage brought by new materials, processes and device architectures (HiK and metal gate, SOI, GeOI, Multigate transistors, and others), the fundamental physical limits of switching based on electronic devices and new applications based on few electrons operation Weighs the limits of copper interconnects against the challenges of implementation of optical interconnects Reviews different memory architecture opportunities through the strong low-power requirement of mobile nomadic systems, due to the increasing role of these devices in future circuits Discusses new paths added to CMOS architectures based on single-electron transistors, molecular devices, carbon nanotubes, and spin electronic FETs
Available at Amazon.com or any good bookstores.

| 49

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More MOORE and MORE THAN MOORE MEETING FOR 3D

INSTITUTE FOR ENERGY EFFICIENCY Santa Barbara, California, December 2, 2011

CEA LETI organization

Fundamental Research French Nuclear Agency

Micro Nano Technology & integration in System

Electronuclear Energy Res.

Software oriented system

New technology for Energy & Nanomaterials

S.Deleonibus CEA-LETI December 2011

LETI: Mission and Focus

Mass Production Products Pilot Line Prototypes

Basic Research Publications

Applied Research Patents

LETI in a few numbers - 2010

200 and 300mm Si capabities 8,000 m clean rooms Continuous operation

350 new patents in 2010 Portfolio > 1,500 patents 32 start-ups

Since 2005: A complete set of research platforms

Micro/nano-Technologies Micro Nano Technologies

New Energy Technologies

BioTechnologies Basic research

with investment : 150 M 10 000 researchers 10 000 students

S.Deleonibus CEA-LETI December 2011

Semiconductor Market applications successive waves

Source : Semico Research Corp. May 2004 IPI Report

Ecological Footprint of ICTs

Currently, 3 % of the world-wide energy is consumed by the ICT infrastructure

ICT: 10% of electrical energy in industrialized nations

The transmitted data volume increases approximately by a factor of 10 every 5 years

Scaling: a success storythanks to innovation

Convergence Digital Camera

Number of transistors per chip

FSG(6 lev met)

STI, salicide contacts plugs (3 lev met)

damascene(5 lev met) vias plugs ,CMP(4 lev met)

Low Operating Power (LOP)

Low Stand-by Power (LSTP) Pstat= VddxIoff

Pdyn=CVdd2 f Ptot=Pstat+ Pdyn

More, More than, Beyond Moore

Engineering Test Stand (VNL/EUV-LLC)

S.Deleonibus CEA-LETI December 2011

System made of 13,000 electron beams working in parallel (MAPPER) (1)

Key numbers 22nm node:

pre-alpha 110 35 nm 0.3 nA 20 MHz

#beams and data channels Spotsize: Beam current: Datarate/channel

13,000 25 nm 13 nA 3.5 Gbs

Aperture array Condensor lens array

30 C/cm2 30 C/cm2 10 wph 3.5nm 0.002 wph 2.25 nm

S.Deleonibus CEA-LETI December 2011

System made of 13,000 electron beams working in parallel (MAPPER) (2)

MAPPER single column tool. Upgrade to 13,000 beam for 10WPH

S.Deleonibus CEA-LETI December 2011

Hot Topics in MOSFET technology

1000 0.1 100

Statistical fluctuations of threshold voltage: 150 mV decay for VT=200mV( Lg=25nm) !!

Major interest for Low Doped channels

S.Deleonibus et al. ESSDERC 1999

S.Deleonibus CEA-LETI December 2011

S.Deleonibus CEA-LETI December 2011

32nm Low Power FDSOI Undoped channels

SOI Thickness Deviation to target ()

SOI Thickness Max Mean Min

0.248m2 SNM (1.2V)=140mV 0.179m2 SNM (1.2V)=230mV VDD=1V Ioff=6pA/m

-10 1 9 17 25 33 41 49 57 65 73 81 89 97 105 113 121 129 137

C.Fenouillet Beranger et al., IEDM 2007, VLSI Symp 2010

S.Deleonibus CEA-LETI December 2011