Flash Memory

PRESENTED BY:
AMIT RAJ
09EE6406
INSTRUMENTATION ENGG.
 Contents
• Flash Memory Generalities
– Construction & Properties
• History of Flash Memory
• Operation Principles
• NOR & NAND Architectures
• Optimizations
• Standardization
• Applications of Flash
• Future of Flash memory
• Conclusion
• References
 Flash Memory
• A type of EEPROM (Electrically-Erasable
Programmable Read-Only Memory)
• Non-volatile, solid state technology
• Relatively limited lifespan
• Information is stored in an array of memory
cells made from floating-gate (FG) transistors
 Flash Memory
• Packaged inside a memory card:
– Extremely durable
– Can withstand intense pressure
– Immersion in water
• Better kinetic shock resistance than hard disks
• Average power requirements range from 5V-
12V
 History of Flash Memory
• Invented by Fujio Masuoka while he was
working for Toshiba in the early 1980s.
• First introduced at the 1984 International
Electron Devices Meeting in San Francisco.
• Intel Corporation introduced the first
commercial NOR type flash chip in 1988.
• Toshiba announced NAND flash at the
1987 International Electron Devices Meeting
 Operation Principles
• The information is stored in
Flash memory as an array of
floating gate transistors,
called "cells", each of which
traditionally stores one bit of
information.
• Newer flash memory devices,
sometimes referred to as
multi-level cell devices, can
store more than 1 bit per
cell, by varying the number A flash memory cell
of electrons placed on the
floating gate of a cell.
Flash Memory Cell
 Floating-gate transistor

• In flash memory, each

memory cell resembles
a standard MOSFET,
except the transistor
has two gates instead
of one.
 NOR Flash Memory
• Developed to replace read only
memory
• Full address and data buses allow
random access to any memory
location
– Can access any memory cell
– Slow sequential access

NOR Flash array equivalent circuit

NOR flash memory wiring and structure on silicon

Basic Operations in a NOR Flash
Memory

NOR Flash Memory―Erase NOR Flash Memory―Write

NOR Flash Memory―Read

 Some facts about NOR flash
• Reading from NOR flash is similar to reading from random-access
memory, provided the address and data bus are mapped correctly.

• Erasure must happen a block at a time, and resets all the bits in the
erased block back to one. Typical block sizes are 64, 128, or 256
Kilobytes.

• Bad block management is a relatively new feature in NOR chips.

• The specific commands used to lock, unlock, program, or erase NOR

memories differ for each manufacturer.

• For sequential data writes, NOR flash chips typically have slow write
speeds compared with NAND flash.
 NAND Flash Memory
• Developed to replace hard disks
• Sequential-accessed command and data registers
replace the external bus of NOR
– Decreases chip real estate
– Can only access pages
– Faster sequential access

NAND flash memory wiring and structure on silicon

 Some facts about NAND flash
• These memories are accessed much like block devices such as hard disks or
memory cards. Each block consists of a number of pages. The pages are
typically 512 or 2,048 or 4,096 bytes in size.

• While reading and programming is performed on a page basis, erasure can

only be performed on a block basis.

• In NAND flash, data in a block can only be written sequentially.

• NAND devices also require wear levelling, bad block management and Error
correcting code by the device driver software, or by a separate controller chip.

• NAND is best suited to systems requiring high capacity data storage. This type
of flash architecture offers higher densities and larger capacities at lower cost
with faster erase, sequential write, and sequential read speeds, sacrificing the
random-access and execute in place advantage of the NOR architecture.
 USB flash drive

1. USB connector
2. USB mass storage controller
device
3. Test points
4. Flash memory chip
5. Crystal oscillator
6. LED
7. Write-protect switch (Optional)
8. Space for second flash memory
chip

Internals of a typical USB flash drive

 Optimizations
• Wear levelling
– Counting writes & dynamically remapping blocks
• Bad block management
– Write verification and remapping bad sectors
• Multi-Level Cell technology
– Memory cells store more than one bit
 Standardization
• Part of the reason for the success of Flash
memory
• Open NAND Flash Interface Working Group
developed standard low-level interface
– Standard pinout
– Standard command set for reading, writing, and
erasing NAND flash chips
– Mechanism for self-identification
Manufacturers of Flash
 Applications

• Serial flash
• Firmware storage
• As a replacement for hard drives
 Future of Flash Memory
• Continues to be among the most aggressively
scaled electronic technologies
• Memory cell size minimum of 20 nm expected
to be met in 2010
• May be replaced by Phase-Change RAM or
other emerging technologies
• One of the most popular alternatives for
portable device storage
• Aggressive advances are still being made
 Conclusion
• Due to its relatively simple structure and high demand for
higher capacity, NAND flash memory is the most
aggressively scaled technology among electronic devices.
• As the feature size of flash memory cells reach the
minimum limit (currently estimated ~20 nm), further Flash
density increases will be driven by greater levels of MLC,
possibly 3-D stacking of transistors, and process
improvements. Even with these advances, it may be
impossible to economically scale Flash to smaller and
smaller dimensions. Many promising new technologies
(such as FeRAM, MRAM, PMC, PCM, and others) are under
investigation and development as possible more scalable
replacements for Flash.
 References
http://ieeexplore.ieee.org/stamp/stamp.jsp?
arnumber=01199079
http://en.wikipedia.org/wiki/Flash_memory
http://electronics.howstuffworks.com/flash-
memory.htm
http://smithsonianchips.si.edu/ice/cd/MEMORY97/SEC1
0.PDF