EE 382V Spring 2011

VLSI Physical Design Automation

Lecture 1. Introduction

Prof. David Z. Pan

dpan@ece.utexas.edu
Office: ACES 5.434

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 What is this course for?
1. Understandable to everyone
2. Understandable to intended
audience
3. Understandable to experts only, such
as the speaker
4. Understandable to nobody, including
the speaker

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 Intended Audience
VLSI CAD (also known as EDA electronic design
automation) students, in particular for chip
implementation (physical design)
Circuit designers to understand how tools work behind
the scene
Process engineers to tune process that is more
circuit/physical design friendly
Mathematical/Computer Science majors who want to
find tough problems to solve
Lots of VLSI physical design problems can be formulated into
combinatorial optimization or mathematical programming
problems.
Actually, most CAD problems are NP-complete -> heuristics

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 Course Objectives

Obtain a general understanding of IC designs.

Understand the process of VLSI layout design
Study the basic algorithms used in layout
design of VLSI circuits.
Learn about the physical design automation
techniques used in the best-known academic
and commercial layout systems.
Get know recent research topics and
problems.

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 Course Logistics
Lecture Hours: MW 9:30-11am
Location: ENS 116
Instructor: David Pan
Email: dpan@ece.utexas.edu (best way to reach me)
Office: ACES 5.434
Office Hour: MW 1:30-2:30pm, & by appointment.
Class web page
http://www.ece.utexas.edu/~dpan/EE382V_PDA
Prerequisites
Basic understand of algorithms (EE360C)
Basic understand of VLSI (EE360R)
or consent of instructor
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 Course Reader
Recommended books (not required)
S. K. Lim, Practical Problems in VLSI Physical Design
Automation, Springer, 2008
C. J. Alpert, D. P. Mehta, S. S. Sapatnekar, Handbook of
Algorithms for Physical Design Automation, Auerbach
Publications, 2008
S. M. Sait and H. Youssef, VLSI Physical Design
Automation: Theory and Practice, World Scientific, 1999.
Algorithm book (for your reference)
T. H. Cormen, C. E. Leiserson, R. L. Rivest, C. Stein
Introduction to Algorithms, MIT Press, 2009 (3rd edition)
Selected papers from the literature.

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 Grading Policy
Class participation: 10%
Class attendance expected (unless legitimate reasons)
Class interaction welcomed (do ask questions)
Homework: 25%
Several home works to help you master basic concepts and
hone your problem solving ability
Midterm: 25%
March 28 (ISPD week)
Project: 40%
Gain direct experience and in depth study of a PD topic
Very important

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 Course Outline
Introduction
Partitioning
Floorplanning
Placement
Global Routing
Detailed Routing
Clock and Power Routing
Emerging topics

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Physical Design Automation Interlock

Automation Techniques VLSI Physical Design

Graph algorithms Partition

Graph algorithms Placement

mathematical programming
Shortest path Routing
Mathematical programming
Greedy algorithm

The most important thing often is to find the right problem formulation

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 Basic Components In VLSI Circuits
Pad Metal1 Via Metal2

Devices
Transistors
Logic gates and cells Data Path
PLA I/O

Function blocks
Interconnects ROM/

Local signals RAM

Global signals
A/D Random
Clock signals Converter logic

Power/ground nets

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 VLSI Design Cycle

Manual

System Chip
Specification Automation

Large number of devices

Optimization requirements for high performance
Time-to-market competition
Power (and other) constraints

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 VLSI Design Cycle

System Specification

Functional Design

X=(AB*CD)+(A+D)+(A(B+C))

Logic Design Y=(A(B+C))+AC+D+A(BC+D))

Circuit Design

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VLSI Design Cycle (cont.)

Physical Design

Fabrication

Packaging

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 Physical Design

Physical design converts a circuit description

into a geometric description. This description is
used to manufacture a chip. The physical design
cycle consists of
1 Partitioning
2 Floorplanning and Placement
3 Routing
4 Compaction

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 Physical Design Process

Design Steps:
Partition & Clustering
Floorplan & Placement
Pin Assignment a
clk
clk
Global
GlobalRouting
Routing
Detailed Routing clk
a

Methodology: a
Divide-and-Conquer

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Physical Design Cycle
Circuit
Physical Design Design

cutline 1
(a) Partitioning

cutline 2

Floorplanning
(b) &
Placement

(c) Routing

(d) Compaction

Fabrication

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Complexities of Physical Design
More than 100 million transistors
Performance driven designs
Power-constrained designs
Time-to-Market

Design cycle

...

High performance, high cost

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 History 101 of Physical Design
Born in early 60s (board layout)
Passed teenage in 70s (standard cell place and
route)
Entered early adulthood in 80s (over-the-cell routing)
Declared dead in late 80s !!!
Found alive and kicking in 90s
Physical Design (PD) has become a dominant force in
overall design cycle,
thanks to the deep submicron scaling
expand vertically with logic synthesis and interconnect
optimization, analysis. => Design closure!

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 Why Physical Design still Relevant?
Many existing solutions are still very suboptimal
E.g., placement
Interconnect dominates
No physical layout, no accurate interconnect
More new physical and manufacturing effects pop up
Crosstalk noise,
OPC (manufacturability), etc.
More vertical integration needed
Physical design is the KEY linking step between
higher level planning/optimization and lower level
modeling

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 PD Courses in Context
This course is on core physical design (that
covers every major step in details).
Another graduate course Optimization
Issues of VLSI CAD.
The topics may vary each time that I teach,
based on new research needs and results
More vertical integration for design closure
Crosscutting topics, such as DFM,
interconnect, low power, reliability

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 Moores Law

The minimum transistor feature size decreases by

0.7X every three years (Electronics Magazine, Vol.
38, April 1965)
Consequences of smaller transistors:
Faster transistor switching
More transistors per chip
True for 45 years!
More Moore, but facing lots of red brick walls
Need smarter and more powerful CAD tools than ever

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 Technology Trend and Challenges

Source:
ITRS

Interconnect determines the overall performance

In addition: noise, power => Design closure
Furthermore: manufacturability => Manufacturing closure

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 Placement Challenge
Placement, to large extend, determines the overall
interconnect
If it sucks, no matter how well you interconnect
optimization engine works, the design will suck
Placement is a very old problem, but got renewed
interest
Mixed-size (large macro blocks and small standard cells)
Optimality study shows that placement still a bottleneck
Not even to mention performance driven, and coupled with
buffering, interconnect optimizations, and so on (all you
name)

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 Comparison with Optimal
3.00 45000
40000
2.50
35000
2.00 30000
Multiple of Optimal

runtime(s)
25000
1.50
20000
1.00 15000
10000
0.50
5000
0.00 0
0 50000 100000 150000 200000 250000 0 50000 100000 150000 200000 250000
#cells #cells

dragon capo mPL dragon capo mPL

Capo: Based on recursive min-cut (UCLA-UMich)

Dragon: Recursive min-cut + SA refinement at each level (NWU-UCLA)
mPL: multi-level placer (UCLA)
There is significant room for improvement in placement algorithms:
existing algorithms are 50-150% away from optimal!

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FloorPlacer (Mix-mode Placement)
- Many macros
- data paths +
dust logic
- I/O constraint
(area I/O or
wirebond)

(source: IBM)

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Optical Proximity Correction (OPC)

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OPC-Aware Routing

More OPC friendly

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 Class Project
Three types
Literature survey (one person): at most 80% out of 40% for the
total project grade
Implementation/comparison of existing PD algorithms (2-person
team)
Explore new ideas (2-person team)
Project and term paper outline
Introduction and motivation
Problem statement and/or formulation
Previous works (exhaustive search)
Your approach (new ideas)
Experimental results (implement your idea and show it works or
state why if it doesnt work)
Summary, conclusion and future work

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 Class Project
Rough milestones for class project
Proposal by Feb. 16:
Project team and initial proposal on what topic to work on
First report by Mar. 9:
Project proposal with initial literature review
And your ideas, plan of attack, and framework
Second report by April 11
Comprehensive literature review
Initial implementation results or findings
Final project report and presentation
TBD, around the final week
Conference submission deadlines in Spring 2011
ICCAD deadline (around April 18)
ASPDAC deadline (around early July)

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 Class Project
Possible topics
Comprehensive literature survey of a relevant topic and point
out future trends
Implement a placement engine (different groups should share
the same input/output formats => compete)
Mixed size placement (large blocks with lots of dust logics)
Detailed/incremental placement
Routing for manufacturability enhancement
Suggest your own topics
We will talk more later

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 Some Previous Class Projects
A. Rajaram, D. Z. Pan and J. Hu, "Improved Algorithms for Link
Based Non-tree Clock Network for Skew Variability Reduction",
Proc. International Symposium on Physical Design (ISPD), San
Francisco, CA, April 2005.
M. Cho, S. Ahmed and D. Z. Pan, "TACO: Temperature Aware
Clock Optimization", Proc. ACM/IEEE Int'l Conference on
Computer-Aided Design (ICCAD), November, 2005 (covered by
EE Times on June 19, 2006)
Avijit Dutta, Jinkyu Lee and David Z. Pan, Partial Functional
Manipulation Based Wirelength Minimization, Proc. International
Conference on Computer Design (ICCD), Oct. 2006

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 Resources
Please check the web site for a set of reference,
papers and links (will be updated frequently)
EE Times (www.eetimes.com) for recent trend/development
IEEE Explorer
ACM Digital Library
http://citeseer.com/
Google Scholar

MIT OpenCourseWare
If you need to make up some knowledge (e.g., Cormens
algorithm book/class)
http://ocw.mit.edu/index.html

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 VLSI CAD Conferences
DAC: Design Automation Conference
ICCAD: Intl Conference on Computer-Aided Design
ASP-DAC: Asia & South Pacific Design Automation Conference
DATE: Design Automation and Test in Europe
ISPD: Intl Symposium on Physical Design
ISLPED: Intl Symposium on Low Power Electronics and Design
ISQED: Intl Symposium on Quality Electronic Design
ISCAS: Intl Symposium on Circuits and Systems
ICCD: Intl Conference on Computer Design

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 VLSI/CAD Related Journals
IEEE TCAD
IEEE Transactions on CAD of Integrated Circuits and
Systems
IEEE TVLSI
IEEE Transactions on VLSI Systems
ACM TODAES
ACM Transactions on Design Automation of Electronic
Systems
IEEE TCAS (I and II)
IEEE Transactions on Circuits and Systems
Integration, the VLSI Journal

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