Computer Organization

Engr. Sana Elahi

Recommended Textbooks
 Computer Organization and Design by David A Patterson and
John L. Hennessy, (the hardware/software interface) Latest Edition

 Computer System Architecture by M. Morris Mano, 3rd Edition

 Computer Organization and Architecture by William Stallings, 8th

or 9th Edition

THE PROCESSOR 2
Multicycle Approach
Outline of this lecture
 Problem with single cycle datapath
 Analyzing delays in a single cycle datapath
 Clock periods in single cycle and multi-cycle design
 Improving resource utilization
 Add register and multiplexers
Single Cycle Datapath
0

2
S
0
4
PC + 4 (28-31) 1

+
1

+
2
S
rs 21-25
rdad1

PC ad inst
rt 16-20
rdad2
rddata1

ALU
adrs rddata
1
0 rddata2 0
write
IM wrdata
0
RF
rd 00-15
1 wrdata 1
DM

00-15
X
S
Problem with single cycle design
 Slowest instruction pulls down the clock frequency
 Resource utilization is poor
 There are some instructions which are impossible to be
implemented in this manner
Clock Period in Single Cycle Design
Clock Period

t1 tR tA tR
R-Class
Lw t1 tR tA tM tR

Sw t1 tR tA tM

Beq t1 tR tA
t0 t0
t1 t0

j t0
t1
Clock Period in Multi Cycle Design
Clock Period

t1 tR tA tR
R-Class
Lw t1 tR tA tM tR

Sw t1 tR tA tM

Beq t1 tR tA
t0 t0
t1 t0

j t0
t1
Unbalanced Delays
Clock Period

t1 tR tA tR
R-Class
Lw t1 tR tA tM tR
Sw t1 tR tA tM
Beq t1 tR tA
t0 t0
t1 t0

j t0
t1
Improving Resource Utilization
› Can we eliminate two adders ?
› How to share or reuse a resource (say ALU) in different clock
cycles ?
› Store results in registers
› Of course , more multiplexing may be required
› Resource in this design : RF,ALU,MEM.
Single Cycle Datapath
0

2
S
0
4
PC + 4 (28-31) 1

+
1

+
2
S
rs 21-25
rdad1

PC ad inst
rt 16-20
rdad2
rddata1

ALU
adrs rddata
1
0 rddata2 0
write
IM wrdata
0
RF
rd 00-15
1 wrdata 1
DM

00-15
X
S
Merge IM and DM
0

2
S
0
4
PC + 4 (28-31) 1

+
1

+
2
S
rs 21-25
rdad1

PC ad inst
rt 16-20
rdad2
rddata1

ALU
adrs rddata
1
0 rddata2 0
write
IM wrdata
0
RF
rd 00-15
1 wrdata 1
DM

00-15
X
S
Merge IM and DM
0

2
S
0
4
PC + 4 (28-31) 1

+
1

+
2
S
rs 21-25
rdad1

PC ad inst
rt 16-20
rdad2
rddata1

ALU
adrs rddata
1
0 rddata2 0
write
IM wrdata
0
RF
rd 00-15
1 wrdata 1
DM

00-15
X
S
Rearrange Diagram
0

2
S
0
4 1
PC + 4 (28-31)

+
1

+
2
S
rs 21-25
rdad1

PC rt 16-20
rdad2
rddata1

ALU
adrs
rddata 0 rddata2 0
write
wrdata rd 11-15
1 wrdata RF 1
DM

00-15

X
S
Eliminate First Adder
0

2
S
0
4 1
PC + 4 (28-31)

+
1

+
2
S
rs 21-25
rdad1

PC rt 16-20
rdad2
rddata1

ALU
adrs
rddata 0 rddata2 0
write
wrdata rd 11-15 4
1 wrdata RF 1
DM

00-15

X
S
Eliminate Second Adder
0

2
S
0
PC + 4 (28-31)
1
1

+
2
S
rs 21-25
rdad1

PC rt 16-20
rdad2
rddata1

ALU
adrs
rddata 0 rddata2 0
write
wrdata rd 11-15 4
1 wrdata RF 1
DM

00-15

X
S

2
S
Rearrange Diagram
0

2
S
0
PC + 4 (28-31)
1
1

rs 21-25
rdad1

PC rt 16-20
rdad2
rddata1

ALU
adrs
rddata 0 rddata2 0
write
wrdata rd 11-15 4
1 wrdata RF 1
DM

00-15

X
S

2
S
Introduce Adder
0

2
S
0
PC + 4 (28-31)
1
1

rs 21-25
rdad1 A

PC IR
rt 16-20
rdad2
rddata1

ALU
adrs
B
rddata 0 rddata2 0
write
wrdata RES
rd 11-15
1 4
wrdata RF 1
DM

00-15
DR

X
S

2
S
Rearranging PC Input Multiplexer
0

2
S
0
PC + 4 (28-31)
1
1

2
rs 21-25
rdad1 A
1
PC IR
rt 16-20
rdad2
rddata1

ALU
adrs
B
rddata 0 rddata2 0 0
write
wrdata RES
rd 11-15
1 4
wrdata RF 1
DM

00-15
DR

X
S

2
S
Introduce ALU inp1 Multiplexer

2
S
PC + 4 (28-31)

0
2
rs 21-25
rdad1 A
1 1
PC IR
rt 16-20
rdad2
rddata1

ALU
adrs
B
rddata 0 rddata2 0 0
write
wrdata RES
rd 11-15
1 4
wrdata RF 1
DM

00-15
DR

X
S

2
S
Introduce ALU inp2 Multiplexer

2
S
PC + 4 (28-31)

0
2
rs 21-25
rdad1 A
1 1
PC IR
rt 16-20
rdad2
rddata1

ALU
adrs
B 3
rddata 0 rddata2 0
write
wrdata RES
rd 11-15 4 2
1 wrdata RF
DM 1

00-15 0
DR

X
S

2
S
Introduce RF inp Multiplexer

2
S
PC + 4 (28-31)

0
2
rs 21-25
rdad1 A
1 1
PC IR
rt 16-20
rdad2
rddata1

ALU
adrs
B 3
rddata 0 rddata2 0
write
wrdata RES
rd 11-15 4 2
1 wrdata RF
DM 1

00-15 0
DR

X
S

2
S
0
1
Introduce Meminp Multiplexer

2
S
PC + 4 (28-31)

0
2
rs 21-25
rdad1 A
1 1
PC 0 IR
rt 16-20
rdad2
rddata1

ALU
adrs
1 B 3
rddata 0 rddata2 0
write
wrdata RES
rd 11-15 4 2
1 wrdata RF
DM 1

00-15 0
DR

X
S

2
S
0
1
Summary
› Single Cycle Approach to Multi-cycle approach: improve
performance and resource sharing.
› Delays in different cycles should be balanced.
› Single ALU and single memory used.
› Additional registers and multiplexers required.