ECE 3544

Digital Design I
2: CMOS LOGIC
CH A PT E R 1 4 : S E CT I O NS 1 – 3 , 4 , 6 . 3

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What you should know…
The characteristics of the basic logic gates: AND, OR, NOT, NAND, NOR, XOR,
XNOR.

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What you might not know…
How transistors are connected to make gates.
How electrical characteristics affect digital design constraints such as speed
(performance) and power.

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Logic Values and Voltages
Gates deal with logic 0 and 1, but in reality logic values are represented by
voltages.

Lower voltages
these days

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CMOS Logic
The vast majority of modern digital systems are built with Complementary
Metal Oxide Semiconductor (CMOS) circuits
Advantages of CMOS circuits:
◦ High speed.
◦ Fully-restored voltage swings (logic-1 is VDD, logic-0 is ground), which
provides good noise immunity.
◦ Very little power consumed when not switching.

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CMOS Logic
“Complementary” comes from having both n-channel and p-channel MOS
transistors in networks that are duals of each other.

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Transistors in Practice

Source: https://www.electrical4u.com/mosfet-characteristics/

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Transistors in Practice

Source: https://www.electrical4u.com/mosfet-characteristics/

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CMOS Logic: Switch Models
Ideally, the transistors are voltage-controlled switches that are either open
(Z = ∞) or closed (Z = 0).

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CMOS Logic: What’s going on?

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CMOS Logic: The Inverter

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CMOS Logic: Switch Models
Using alternative transistor symbols highlights this “switch model” behavior.

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CMOS Logic: More Gates
We can make other logic gates with CMOS by connecting transistors in
series/parallel combinations.
In general:
◦ The n-transistors provide pathways from logic-0 to the output; the p-
transistors provide pathways from logic-1 to the output.
◦ Transistors in series represent AND branches; transistors in parallel
represent OR branches.
◦ The pathways are duals of each other. (If one is a series connection, then
the other is a parallel connection.)
◦ No static path exists between VDD and ground.

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CMOS Logic: What’s going on?

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CMOS Logic: The NAND gate

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CMOS Logic: The NOR gate

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CMOS Logic: Other Examples

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CMOS Logic: Other Examples
Why not make an AND gate? It takes more transistors!

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CMOS Logic: Other Examples
We can make complex logic functions in a single “gate”:

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CMOS Logic: Other Examples

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CMOS: Electrical Characteristics
In terms of logic functionality, we only have to deal with 0s and 1s. This allows
the consideration of ideal switch models.
When trying to meet major design constraints and implementing systems, we
must consider the circuit’s electrical characteristics.
The major design constraints are speed and power consumption.

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Hey, Wait!
This is Computer Engineering! Why do we care about electrical characteristics?
Speed (performance) is usually the primary design constraint for a digital
circuit.
◦ Understanding the electrical characteristics will help us to build faster
circuits.
◦ We need to know about the delay characteristics in case something goes
wrong in a circuit, e.g., a high load capacitance connected to a signal with
low drive strength.
◦ We’ll use delays later on to model actual circuits in Verilog.
◦ When we synthesize circuits, the tools will provide an estimate of delay for
the Verilog simulations.

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Dynamic Electrical Behavior
The power consumption and speed of CMOS logic gates mainly depend upon
the dynamic characteristics of the circuit – when it is switching.
Power is mainly determined by capacitance, operating voltage, and how often
the circuit switches.
Speed is mainly determined by resistance of the transistors and capacitance of
the load.

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Example CMOS Data Sheet

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CMOS: Power Consumption
Power consumption in CMOS is mainly dynamic power resulting from the
charging and discharging of the load capacitance. In general, this assumes fast
transition times.
Dynamic power = CV2f, where
◦ C is the load capacitance being switched
◦ V is the voltage through which the load is being switched (usually VDD)
◦ f is the switching frequency of the gate.

In recent years, static power consumption has increased due to smaller

transistors. The leakage is small for one transistor, but there are more
transistors per unit area.

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CMOS: Power Consumption
Suppose that a CMOS gate is a component of a clocked system having
frequency fCLK.

Even though we know the system frequency, it might not be the case that the
gate output switches value during every clock period.
◦ Let f = fCLK, where  is the activity factor of the gate.
◦ In effect, the activity factor is the fraction of system clock cycles that the
gate actually switches.
◦  relates the frequency of the system to the switching frequency of the
gate, as mentioned previously.
A clock has  = 1. A gate whose value changes once per cycle has  = 0.5.
Depending on the design of the system, data propagating through gates
results in a “typical”   0.1

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CMOS: Speed
Speed depends on transition time and propagation delay.
◦ Transition time: the time for a signal to change from 0 to 1 or from 1 to 0.
◦ Propagation delay: the time for a change on an input to cause a change on
the output.

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CMOS: Transition Time
Transition time measures the slope of a changing signal.
Ideally, a signal transition occurs in zero time. This gives rise to ideal signals
having the appearance of a square wave.

In practice, the transition time represents the time between “minimum high”
and “maximum low” input values.

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CMOS: Transition Time
Transition time depends mainly on the “on” resistance of the transistor and
the load capacitance.

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CMOS: Transition Time
A similar situation occurs for the rise time.

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CMOS: Propagation Delays
Propagation delays depend upon speed of signal paths. The path could be a
wire connecting gates, or it could be between internal nodes of a complex
gate.
Propagation delays can be specified as a function of the output transition
direction:
◦ tpHL: time between input change and output high-to-low transition.
◦ tpLH: time between input change and output low-to-high transition.

Propagation delays are typically measured at midpoint of transition to factor

out transition times.

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CMOS: Propagation Delays
Propagation delay for an inverter

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Summary
CMOS circuits are the workhorse of the digital design industry.
The advantages of CMOS gates over other alternatives include high speed, low
static power consumption, and good noise margins.
The dynamic power consumed by a CMOS gate is equal (proportional) to CV2f.
The transition time of a gate is the time required for a signal to rise from 0 to 1
or to fall from 1 to 0. Transition times should be short.
The propagation delay of a gate is time required for the output to change with
respect to a change in the input.

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Coming Up Next…
Next topic
Combinational Logic Design
Reading Assignment
Chapter 3

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