Chapter 3

Microprocessor 8085 Architecture

1
 Outline
• Pin out diagrams detail
• Internal architecture of 8085
– Timing and control unit
– Instruction registers and decoder
• Microprocessor communication and bus timing
– Address de-multiplexing
• Timing diagrams
– Instruction cycle, machine cycle and T-state
– Opcode fetch and rd/wr machine cycle
• Generation of control signals
– Memory rd/wr and I/O rd/wr 2
Intel 8085 Pin Configuration

3
 Pin out diagrams & pin details
• The 8085 is an 8-bit general purpose microprocessor
that can address 64K Byte of memory.
• It has 40 pins and uses +5V for power. It can run at a
maximum frequency of 3 MHz.
– The pins on the chip can be grouped into 6 groups:
• Address Bus.
• Data Bus.
• Control & Status Signals.
• Power supply & frequency.
• Externally Initiated Signals.
• Serial I/O ports.
4
 The 8085 pin out & Signals
GND
. X1 1 40 Vcc
Serial 1 2
+5V
40 20
X2 2 39 HOLD I/O X1 X2 Vcc Vss
HLDA SID 4
RESET OUT 3 38 ports A15 28
SOD 4 37 CLK (OUT) SOD 5
High-order
SID 5 RESET IN Address bus
36
TRAP 6 35 READY TRAP 6 A8 21

RST 7.5 7 8085A 34 IO/M RST 7.5 7 AD7 19

8085A
8 P 33 S1 RST 6.5 8 Address/Data
RST 6.5
RD
P
RST 5.5 9 32 Externally RST 5.5 9 bus
INTR 10 31 WR initiated AD0 12
INTR 10
ALE signals
INTA 11 30 READY 35
AD0 12 29 S0 HOLD 39 30 ALE
AD1 13 28 A15 29 S0 Control
RESET IN 36
AD2 14 27 A14 33 S1 &
AD3 15 A13 status
26 34 IO/M
External INTA 11 signals
AD4 16 25 A12 32 RD
signals HLDA 38
AD5 17 24 A11 31 WR
Acknowledg
AD6 18 23 A10 ment
AD7 19 22 A9 3 37
Vss 20 21 A8
RESET OUT CLK (OUT)
5
 The Address & Data Bus Systems
• The address bus has 8 signal lines A8 – A15
which are unidirectional.
• The other 8 address bits are multiplexed (time
shared) with the 8 data bits.
– So, the bits AD0 – AD7 are bi-directional &
serve as A0 – A7 & D0 – D7 at the same time.
• During the execution of the instruction,
these lines carry the address bits during the
early part, then during the late parts of the
execution, they carry the 8 data bits.
6
ALE used to demultiplex address/data bus

7
 The Control & Status Signals
• There are 4 main control and status signals. These are:
1. ALE: Address Latch Enable. This signal is a pulse that become 1
when the AD0 – AD7 lines have an address on them. It becomes
0 after that. This signal can be used to enable a latch to save the
address bits from the AD lines.
– It is a positive going pulse generated every time the 8085 begins an
operation (machine cycle).
– It goes high during the first clock cycle of a m/c & enables the low-order
address to be latched thus generate the A0-A7 address lines.
2. IO/M’(output): This signal specifies whether the operation is a
memory operation (IO/M’=0) or an I/O operation (IO/M’=1).
– when it goes high, the address on the bus is for I/O device –thus it
indicates an I/O operation
– when it goes low, the address on the bus is for the memory
location-thus it indicates a memory operation
3. S1 & S0(output) : Status signals to specify the kind of operation
being performed. Usually not used in small systems
8
4. RD’ & WR’
• RD (output): is a READ control signal (active low).
– when it goes low, the selected memory location or I/P device is read & data is available on the data
bus
• WR (output): it is a Write control signal (active low).
– when it goes low, the data on the data bus is written in to the selected memory location or o/p
device

IO/M’ Operations Operations Status

(machine cycle) Control Signal
0 Memory Operation IO/M S1 S0
1 I/O Operation
Opcode Fetch 0 1 1 RD=0
Table: Memory and I/O operations
Memory Read 0 1 0 RD=0
S1 S0 Operations Memory write 0 0 1 WR=0
0 0 HALT I/O Read 1 1 0 RD=0
0 1 WRITE
1 0 READ I/O Write 1 0 1 WR=0
1 1 FETCH Interrupt Ack 1 1 1 INTA=0
Halt z 0 0 RD, WR=z, INTA=1
Table: status codes for 8085
HOLD z x x RD, WR=z, INTA=1
RESET z x x RD, WR=z, INTA=1
Table: 8085 m/c status and control signals 9
 Power supply & Frequency Control Signals
• There are 3 important pins in the frequency control group.

1. X0 & X1 are the inputs from the crystal or clock

generating circuit.
• The frequency is internally divided by 2.
-So, to run the microprocessor at 3 MHz, a clock
running at 6 MHz should be connected to the X0 & X1 pins
2. CLK (OUT): An output clock pin to drive the clock
of the rest of the system(to other digital Ics).
3. VCC: +5Vdc, and Vss: GND

10
 Externally generated signals
• READY (input): used to synchronize slower peripherals with the MP.
– That is it is used by the MP to sense whether a peripheral is ready to
transfer data or not.
– If high- ready, else MP get into wait state
• HOLD (input): This signal is used to indicate whether a device (e.g. DMA) is
requesting system bus
– HOLD signal is High, the MP relinquishes the bus for the requesting device
using HLDA
• INTR (input): Interrupt request signal.
• INTA’ (output): Interrupt Acknowledge signal. It is active low.
• RST 5.5, RST 6.5, RST 7.5, TRAP (inputs): they are external vectored interrupt
signals.
• RESET IN’ (input): All internal operations are suspended & resets the PC to
0000H. The buses are tri-state and the MP is reset.
– it does not affect any other flag or register except the instruction register (IR).

11
 Serial I/O Port
• The 8085A also provides serial input data (SID) and
serial output data (SOD) lines for simple serial interface.
• SID (Input)
• Serial input data line.The data on this line is loaded into
accumulator bit 7 whenever a RIM instruction is executed.
• SOD (output)
• Serial output data line. The output SOD is set or reset as
specified by the SIM instruction.

12
. INTR INTA RST 5.5 RST 6.5 RST 7.5 TRAP SID SOD

Serial I/O
Interrupt Control Control

8-bit internal data bus

MUX
IR (8)
W (8) Z (8)
Temp.

Reg. select.
ACC (8) B (8) C(8)
Reg (8) Flags (5)

decod
D (8) E (8)
Instruction
H (8) L (8)
Decoder &
M/code SP (16)
ALU encoder PC (16)
(8)
Incrementer/
+5V decrementer
GND Address latch
X1 Timing & Control
X2 Control Status DMA Reset

IO/M
AB(8) ADB (8)
CLK OUT WR ALE HOLD HLDA RESET OUT
READY RD S0 S1 RESET IN
A15-A8 AD7-AD0
13
Fig. The 8085A MP functional block diagram
 Timing & Control Unit
• This unit synchronizes all the MP operations with the
clock & generates the control signals necessary for
communication between the MP & peripherals
– it generates timing & control signals which are
necessary for the execution of instructions.
– it provides status, control & timing signals which are
required for the operation of memory & I/O devices
– it controls the entire operations of the MP and
peripherals connected to it
– CU acts as the brain of the computer system

14
 Instruction Register & Decoder
• IR & the decoder are part of the ALU
• IR holds the instruction fetched from
memory
• The decoder decodes the instruction &
establishes the sequences of events to follow
• IR is not accessible & can not be
programmed through any instruction

15
 Microprocessor communication & Bus timings

Figure : Moving data form memory to MP using instruction

MOV C, A (code machine 4FH = 0100 1111) 16
Microprocessor communication & Bus timings cont’d…

17
 Microprocessor communication & Bus timings cont’d..
• The Fetch Execute Sequence :
1. The μp placed a 16 bit memory address from PC to address bus.
– Figure : At T1
– The high order address, 20H, is placed at A15– A8
– The low order address, 05H, is placed at AD7- AD0 & ALE is
active high.
– Synchronously the IO/M is in active low condition to show it is a
memory operation.
2. At T2 the active low control signal, RD, is activated so as to activate
read operation; it is to indicate that the MP is in fetch mode operation.
3. T3: The active low RD signal enabled the byte instruction, 4FH, to be
placed on AD7 – AD0 & transferred to the MP. While RD high, the
data bus will be in high impedance mode.
4. T4: The machine code, 4FH, will then be decoded in instruction
decoder. The content of accumulator (A) will then copied into C
register at time state, T4.
18
 De-multiplexing the Bus AD7-AD0
• From the above description, it becomes obvious that the AD7–
AD0 lines are serving a dual purpose & that they need to be
demultiplexed to get all the information.
• The high order bits of the address remain on the bus for three
clock periods. However, the low order bits remain for only one
clock period & they would be lost if they are not saved externally.
• To make sure we have the entire address for the full three clock
cycles, we will use an external latch to save the value of AD 7–
AD0 when it is carrying the address bits. We use the ALE signal
to enable this latch.
• Given that ALE operates as a pulse during T1, we will be able to
latch the address. Then when ALE goes low, the address is saved
& the AD7–AD0 lines can be used for their purpose as the bi-
directional data lines
19
 A15 A15

High-order
8085 Address Bus
MP

A8 A8
ALE
G
CLK
AD7 D Q A7
74LS373
Low-order
Octal Latch Address Bus

AD0 OC A0

D7
8-bit
Data Bus
20
D0
 Timing Diagrams
• It is a representation of Various Control signals generated during
Execution of an Instruction
Instruction Cycle : the necessary steps that a CPU carries out to fetch an
opcode from memory & decode it & read necessary data from memory
& execute it & store the result back to memory (if any) constitute an
instruction cycle. i.e. it is defined as the time taken by the processor to
execute an instruction once.
- An instruction cycle consists of a fetch cycle & execute cycle.
Thus the total time required to execute an instruction is given by
IC = FC + EC
Fetch cycle:- constitute the necessary steps which are carried out to fetch
an opcode from the memory.
Execute cycle:- constitute the necessary steps which are carried out to get
(read) data, if any, from the memory & to perform the specific
operation(s) specified in the instruction & stored the result, if any.
After the instruction is decoded , execution begins. 21
In the execute operation: after the instruction is decoded (during fetch
cycle) execution begins.
• If the operand is in GPRs, execution is immediately performed---the
time taken in decoding & executing is one clock cycle.
• If an instruction contains data or operand or address which are still
in memory, the CPU has to perform memory read operations to get
the desired data. After receiving the data it performs execute operation.
i.e., in some instructions an execute cycle may involve one or more
Read or Write cycles or both.
Wait Cycle:- clock cycle(s) for which the MP waits till, incase, a slow
memory sends the opcode. Most of the CPUs have been designed to
introduce WAIT cycles to cope with slow memories.
Machine cycle: constitute necessary steps carried out to perform an
operation such as fetch operation, memory read/write, I/O read/write
operations. i.e. defined as the time required for the processor to
access memory/IO devices.
- an instruction cycle may consist 1 to 5 machine cycles.
T-sate: one clock cycle of the system clock.
One m/c may consist 3 to 6 T-states. 22
 • Most fetch cycles have 4 T-states. Some can be 5 or 6 T-
states.
Opcode Fetch
(M1) • IO/M goes low indicating that the address is for memory
• S1=1, S0=1 for fetch operation.
CLK
T1 T2 T3 T4
• A8-A15 transmits the 8-MSBs of the memory address of
opcode.
A8-A15 • During T1, the 8-LSB of address are sent on AD0-AD7 &
PCH unspecified
are latched during T2, thus AD0-AD7 are made free
OUT IN
PCL for opcode fetching during T2 & T3.
AD0-AD7 Opcode
D0-D7 • RD is asserted low during T2, to enable the memory for
IO/M fetch operation. Now opcode is placed on AD-bus.
Memory operation
• During T3 the opcode is placed in IR , RD goes High &
Fetch
disables the memory.
S1,S0 • The fetch cycle is completed during T3.
• The opcode is decoded during T4.
Note: The MP examines READY signal in T2, & if it is
ALE high, the MP enters into T3, otherwise if it is low the
MP enters a WAIT state between T2 and T3.
RD
Note: if the operands are in GPRs, the decoding of the
opcode & its execution takes only one machine cycle
& 4 T-states. Examples of such instructions include:
MOV r1, r2 ADD r SUB r RAL
Fig. Timing diagram for memory fetch operation
etc.
23
 Cont’d…

• Instructions with 6 clock cycle opcode fetch

1. INX/DCX instructions
2. Push instruction
3. PCHL/SPHL/XTHL instructions
4. Conditional return instruction
5. RST instruction
6. Conditional and unconditional CALL instructions.

24
 . Memory write cycle has 3 T-states.
Memory Write . IO/M goes low indicating that the
T1 T2 T3 address is for memory.
CLK
.S1=0, S0=1 for write operation.
. A8-A15 transmits the 8-MSBs of the
A8-A15 High-order address
memory address of data.
OUT OUT
AD0-AD7 A0-A7 Data . During T1,the 8-LSB of address are sent
D0-D7 on AD0-AD7 & are latched during T2
IO/M thus AD0-AD7 are made free for data
Memory operation
transfer.
S1
Write . Data is placed on AD0-AD7 bus during
S0 T2 by the CPU.
. WR is asserted low during T2, to enable
ALE the memory for Write operation.
WR . During T3 the data enters into memory,
WR goes High & terminates the write
operation
Fig. Timing diagram for memory Write operation
25
 Memory Read . Memory read cycle has 3 T-states.

CLK
T1 T2 T3 . IO/M goes low indicating that the address is
for memory.

A8-A15 High-order address . S1=1, S0=0 for read operation.

OUT IN . A8-A15 transmits the 8-MSBs of the memory
AD0-AD7 A0-A7 Data address of data.
D0-D7 . During T1, the 8-LSB of address are sent on
IO/M
Memory operation AD0-AD7 & are latched during T2 thus
AD0-AD7 are made free for data transfer.
S0
S1
Read . RD is asserted low during T2, to enable the
memory for read operation. Now data is placed
on data bus.
ALE . During T3 the data enters into CPU, RD goes
High & disables the memory.
RD

Fig. Timing diagram for memory read operation

26
 Instruction Cycle

Opcode Fetch (M1) Memory Read (M2)

CLK
T1 T2 T3 T4 T1 T2 T3

A8-A15 PCH unspecified High-order address

OUT IN OUT IN
AD0-AD7 PCL Opcode A0-A7 Data8

D0-D7 D0-D7

Fetch M. Read
IO/M
Status IO/M=0, S1=1,S0=1 IO/M = 0, S1=1,S0=0
S1,S0

ALE

RD

Fig. Timing diagram for execution of the instruction MVI r, data8 27

28
29
30
31
32
33
34
35
Example: Execution of 2-byte instruction:
MVI A, 23H ; Load byte 23H into ACC
3EH, 23H ; binary code
assume the instruction is, the two binary codes are, stored in memory
locations 2000H & 2001H.
a) Illustrate the timing diagram,
b) calculate the time required for IC=FC+EC, if clock frequency =2MHZ.
Answer:
c) Explained the timing diagram on the next slide.
d) Time required to execute the instruction , MVI A, 23H
Given, clock frequency, f=2MHZ.
. T-state= clock period(1/f)=0.5s
. execute time for opcode fetch= 4Tx0.5=2 s
. Execution time for Memory read operation=3Tx0.5=1.5 s
. Execution time for instruction=7Tx0.5=3.5 s
36
 .

Instruction Cycle

Opcode Fetch (M1) Memory Read (M2)

CLK
T1 T2 T3 T4 T1 T2 T3

A8-A15 20H unspecified 20H High-order address

OUT IN OUT IN
AD0-AD7 00H 3EH 01H 23H
Low-order opcode Low-order Data8

Fetch M. Read
IO/M
Status IO/M=0, S1=1,S0=1 IO/M = 0, S1=1,S0=0
S1,S0

ALE

RD

Fig. Timing diagram for execution of the instruction MVI A, 23H 37

Exercises:
1. Repeat for the instruction
STA 2050H ;
32H, 50H, 20H ; binary code
it has fetch m/c, two read m/c, and one write m/c for the data in ACC
to be stored
in 2050H. Thus, 4+3+3+3=13 T-states total.`
a) Illustrate the timing diagram,
b) calculate the time required for IC=FC+EC, if clock frequency =2MHZ.
2. MVI M,45h
3. PUSH H.

38
 Generation of Control Signal
• The following fig. shows how memory & I/O control signals are generated using
RD, WR, & IO/M and logic gates.

IO/M RD WR control signal

74LS32
Quadruple 2-i/p
0 0 1 MEMR OR Gates
0 1 0 MEMW
MEMR
1 0 1 IOR
8085 MP MEMW
1 1 0 IOW
IO/M
IOR
RD

IOW
WR

Fig. Schematic to generate Read/Write Control Signals for memory and I/O 74LS04
Hex converter
- Memory read operation takes place when IO/M & RD both are LOW.
- Memory Write operation takes place when IO/M & WR both are LOW.
- I/O read operation takes place when IO/M is HIGH & RD is LOW.
- I/O write Takes place when IO/M is HIGH and WR is LOW.
39