DIGITAL LOGIC DESIGN (DLD)

Lecturer: Engr. Ali Iqbal

CHAPTER 4: Combinational Logic
 INTRODUCTION
 ANALYSIS PROCEDURE
 DESIGN PROCEDURE
 BINARY ADDER-SUBTRACTOR
 BINARY ADDER
 BINARY SUBTRACTOR
 FOUR BIT ADDER SUBTRACTOR
 DECIMAL ADDER
 BCD ADDER
 DECODERS
 ENCODERS
 PRIORITY ENCODER
 MULTIPLEXERS
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DESIGN PROCEDURE

The procedure involves the following steps:

1 From the specifications of the circuit, determine the required

number of inputs and outputs and assign a symbol to each.

2 Derive the truth table that defines the required relationship

between inputs and outputs.

3 Obtain the simplified Boolean functions for each output as a

function of the input variables.

4 Draw the logic diagram and verify the correctness of the

design (manually or by simulation).

D.R.V.L.B Thambawita Combinational Logic

DESIGN PROCEDURE
Example:An example that converts binary coded decimal (BCD) to
the excess-3 code for the decimal digits.
DESIGN PROCEDURE

Code Conversion Example

D.R.V.L.B Thambawita Combinational Logic

DESIGN PROCEDURE

Code Conversion Example

D.R.V.L.B Thambawita Combinational Logic

DESIGN PROCEDURE

Code Conversion Example

D.R.V.L.B Thambawita Combinational Logic

DESIGN PROCEDURE
Code Conversion Example

D.R.V.L.B Thambawita Combinational Logic

BINARY ADDER-SUBTRACTOR

• A combinational circuit that performs the addition of two bits is called

a half adder.
• One that performs the addition of three bits (two significant bits and
a previous carry) is a full adder.
• A binary adder - subtractor is a combinational circuit that performs
the arithmetic operations of addition and subtraction with binary
numbers.
• We will develop this circuit by means of a hierarchical design. The
half adder design is carried out first, from which we develop the
full adder. Connecting ‘n’ full adders in cascade produces a binary
adder for two n-bit numbers. The subtraction circuit is included in
a complementing circuit.

D.R.V.L.B Thambawita Combinational Logic

BINARY ADDER-SUBTRACTOR

Half Adder
We assign symbols x and y to the two inputs and S(for sum) and
C(for carry) to the outputs

D.R.V.L.B Thambawita Combinational Logic

BINARY ADDER-SUBTRACTOR

Implementation of half adder

D.R.V.L.B Thambawita Combinational Logic

 BINARY ADDER-SUBTRACTOR
Full Adder
• It consists of three inputs and two outputs.
• Two of the input variables, denoted by x and y, represent the
two significant bits to be added. The third input, z, represents
the carry from the previous lower significant position.

D.R.V.L.B Thambawita Combinational Logic

BINARY ADDER-SUBTRACTOR

Full Adder: K-Maps for full adder

D.R.V.L.B Thambawita Combinational Logic

BINARY ADDER-SUBTRACTOR

Full Adder

D.R.V.L.B Thambawita Combinational Logic

BINARY ADDER-SUBTRACTOR

Implementation of full adder in sum-of-products form

D.R.V.L.B Thambawita Combinational Logic

BINARY ADDER-SUBTRACTOR

Implementation of full adder with two half adders and an OR gate

D.R.V.L.B Thambawita Combinational Logic

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