Digital Systems

Lecture 4

Dr.-Ing. Erwin Sitompul

President University
http://zitompul.wordpress.com
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Terms in Digital Logic Design

 Synthesis: the design of a new circuit that implements a desired
function and behavior.
 Analysis: the task of determining the function and behavior of an
existing circuit.

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Example of Synthesis
Given the following truth table, A B Y
design the circuit
0 0 1
0 1 1
1 0 0
1 1 1

From the truth table, we now write the Sum-of-Product:

Y1 = A’B’ + A’B + AB
We can now create A
the logic circuit:

B X

● 1st possibility

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Example of Synthesis
We can simplify the Boolean expression and obtain different
synthesis result:
Y2 = A’B’ + A’B + AB
Y2 = A’(B’ + B) + AB (Distributive)
Y2 = A’ + AB (Complement)
Y2 = A’ + B (Elimination)

A
X
B
● 2nd possibility

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Minimum Cost Realization

 Logic circuits should be implemented by using as few as logic
gates as possible. Optimal implementation will directly affect
speed, resource, and power consumption.
 One formula of how to calculate cost is:
Cost = Σ(gates) + Σ(gate inputs)
 From previous pages,
Cost of Y1 = 6 + 11 = 17
Cost of Y2 = 2 + 3 = 5

A
A

B X X
B

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Minimum Cost Realization

 Neither SoP nor PoS guarantee a minimum cost implementation.
 In stead of these two-level forms, in some cases a multi-level form
is better.
 In practice, any circuit can be implemented only by using NAND
and NOR Gates. NAND and NOR Gates provide higher speed,
require less power, and can be built with less number of
transistors.

 Nevertheless, SoP and PoS are the basis for development of circuit
minimization methods.
 Converting from SoP and PoS to NAND and NOR circuits is
straightforward and easy.

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Minimum Cost Realization

 A formula to calculate cost may include the following factors:
 Number of gates
 Number of gate inputs
 Number of transistors
 Area of the circuit
 Routing / wiring cost
 Critical path delay

 Minimum cost realization can be done by using several methods:

 Boolean algebra simplification
 Karnaugh map
 Quine-McCluskey algorithm
 NAND/NOR equivalent

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Example: Minimum Cost Realization

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Functional Completeness
 A set of Boolean operators is called functionally complete if the set
can be used to express all possible logic functions by combining
members of the set.
 Some sets of logic operators with functional completeness are:
 AND and NOT
 OR and NOT
 NAND
 NOR

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NAND and NOR Gates

● NAND Gates

● NOR Gates

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NAND and NOR Gates: Inverter

X
X

? ● Check the truth table of

the (tied-together 2-input
NAND and NOR Gates

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NAND and NOR Gates: De Morgan’s Theorem

X
X X
Y Y
Y

(X · Y)’ = X’ + Y’
● NAND Gates

X
X X
Y Y
Y

(X + Y)’ = X’ · Y’
● NOR Gates

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Completeness of NAND Gate

 Any Boolean function can be implemented using NAND Gates only.
 NOT Gate  NAND Gate, with 2 inputs tied together.

 AND Gate  NAND Gate, followed by NOT Gate

 OR Gate  NAND Gate, preceded by NOT Gates

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Completeness of NOR Gate

 Any Boolean function can be implemented using NOR Gates only.
 NOT Gate  NOR Gate, with 2 inputs tied together.

 OR Gate  NOR Gate, followed by NOT Gate

 AND Gate  NOR Gate, preceded by NOT Gates

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Using NAND Gates to Implement an SoP

x1
x2
x3
x4
x5

x1
x2
x3
x4
x5

x1
x2
x3
x4
x5
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Using NOR Gates to Implement a PoS

x1
x2
x3
x4
x5

x1
x2
x3
x4
x5

x1
x2
x3
x4
x5
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Example: Realization with NAND Gates

For the following SoP circuit, make a circuit
realization that only uses NAND Gates.
x1
x2 F

x3

x1 x1
x2 F x2 F

x3 x3

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Example: Realization with NOR Gates

For the following PoS circuit, make a circuit
realization that only uses NOR Gates.
x1
x2 F
x3

x1 x1
x2 F x2 F
x3 x3

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Example: Realization with NAND Gates

For the following circuit, make a circuit realization
that only uses NAND Gates.
x1
x2 F
x3

x1
x2 F
x3

x1
x2 F
?
● Redo this example
for the use of NOR
Gates

x3
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Exercise: SoP with NAND Gates

Implement the following SoP function with NAND Gates only.
F = Y’Z + X’YZ
Try the variance where
a) 3-input NAND Gates are allowed
b) only 2-input NAND Gates are allowed

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Exercise: XOR with NAND and NOR Gates

Implement the XOR Gate using NAND Gates only and
NOR Gates only. Hint: Start from the truth table.

A● Be sure to know
the ways

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Homework 4
1.Implement circuit A with NAND
Gates only and NOR Gates only.

Circuit A

2.Implement circuit B with NAND

Gates only and NOR Gates
only.

Circuit B

 Deadline: Tuesday, 4 October 2016.

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