Lec 2 - ds1 - pp03 - Gates

Digital
Fundamentals
11th Global Edition
Floyd
Chapter 3
© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 1

Topics
• Functions of logic gates
• Expressions of logic gates
• Timing diagram
• Propagation delay

3-1 Inverter A X
Function and truth table
The inverter performs the Boolean NOT operation. When the
input is LOW, the output is HIGH; when the input is HIGH,
the output is LOW.
Truth table: a list of the output for each possible input

condition in terms of logic levels (or corresponding bits)

3-1 Inverter A X
Table 3-1 Inverter Truth Table

Input Output
A X
LOW (0) HIGH (1)
HIGH (1) LOW(0)
The NOT operation (complement) is shown with an overbar.

Thus, the Boolean expression for an inverter is X = A.

3-1 Inverter A X
Operation
Operation with pulse input:
In most applications, the inputs to a gate are not stationary

levels; they are voltage waveforms that change between
HIGH and LOW logic levels.
Figure 3-2

3-1 Inverter
Operation A X
Figure 3-3: Timing diagram for Figure 3-2
Operation with waveform inputs:
A
X

3-1 Inverter A X
Application
A group of inverters can be used to form the 1’s

complement of a binary number:
Binary number
1 0 0 0 1 1 0 1
0 1 1 1 0 0 1 0
1’s complement

3-1 Inverter A X
Symbol
Negation Indicator
Represented by a bubble for inversion (or complementation)

3-1 Inverter
Active level A X
Logic level (HIGH (1) or LOW (0)) for indication of a “true” event
The “bubble” (o) present at the end of the NOT gate symbol above
indicates an active-LOW (0) output. That is when input is true
(high), the output is low. This low output indicates a true event at
the input.
This issue is not restricted to the NOT gate only but can be used on
any digital circuit or gate.

3-1 Inverter
TTL Implementation

3-1 Inverter
Buffer
While this may seem like a pointless thing to do, it does have practical
application. Remember that gate circuits are signal amplifiers, regardless
of what logic function they may perform.
A weak signal source (one that is not capable of sourcing or sinking a

large amount of current to a load) may be boosted by means of two
inverters like the pair shown in the previous illustration. The logic level
is unchanged, but the full current-sourcing or -sinking capability of the
final inverter is available to drive a load resistance if needed.

3-1 Inverter
Buffer
For this purpose, a special logic gate called buffer is manufactured to

perform the same function as two-cascaded inverters. Its symbol is
simply a triangle, with no inverting "bubble" on the output terminal:

3-1 Inverter
Buffer
TTL Implementation
Source: http://www.electronics-tutorials.ws/logic/logic_9.html

3-1 Inverter
Buffer
74LS07 Buffer

3-2 AND Gate A X
B
The AND gate produces a HIGH output only when all

inputs are HIGH; otherwise, the output is LOW.
Truth table: a list of the output for each possible input

condition in terms of logic level (or corresponding bit)

3-2 AND Gate
Table 3-2: Truth table for a 2-input AND gate

Inputs Output
A B X
0 0 0
0 1 0
1 0 0
1 1 1
The AND operation is usually shown with a dot between the

variables but it may be implied (no dot). Thus, the AND
operation is written as X = A .B or X = AB.

3-2 AND Gate
Input/output relationship

3-2 AND Gate
Operation with waveform inputs
A
B
X

3-2 AND Gate
Example 3-3: If two waveforms, A and B , are applied to the

inputs of the AND gate in the following figure, determine the
output waveform.
Solution:

3-2 AND Gate
Figure 3-16 An AND gate performing an

enable/inhibit function for a frequency counter.
This enable/disable function is widely used in microprocessor systems.

3-2 AND Gate
Figure 3-17 A simple seat belt alarm circuit using an

AND gate.

3-2 AND Gate A X
B
C
Multiple input AND gate
Given n inputs, the total number of possible conditions of

binary inputs is N=2n
For 2 inputs, N=22 =4 conditions.

Figure 3.15 Boolean expressions
for AND gates with two, three, and
four inputs.
Operation follows the definition.

3-2 AND Gate
Example 3-2: (a) Develop the truth table for a 3-input AND gate.
(b) Determine the total number of possible input conditions
for a 4-input AND gate.
Solution:
(a) Table 3-3
A B C X
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
(b) ?

3-2 AND Gate
Example 3-5: For a 3-input AND gate, determine the output
waveform in relation to the inputs.
Solution:

3-3 OR Gate A X
B
The OR gate produces LOW output only when all inputs are
LOW; the output is HIGH if any input(s) is(are) HIGH.
Table 3-5: Truth table for a 2-input OR gate
Inputs Output
A B X
0 0 0
0 1 1
1 0 1
1 1 1
The OR operation is shown with a plus sign (+) between the

variables. Thus, the OR operation is written as X = A + B.

3-3 OR Gate A X
B
Input/output relationship
Figure 3-19 All possible logic levels for a

2-input OR gate.

3-3 OR Gate
A
B
X

3-3 OR Gate
Figure 3-20 Example of OR gate operation with a timing
diagram showing input and output time relationships.

3-3 OR Gate
Application
The OR operation can be used in computer programming to set

certain bits of a binary number to 1.
Example: ASCII codes of letters have a 1 in the bit 5 position for

lower case letters and a 0 in this position for capitals. (Bit positions
are numbered from right to left starting with 0.) What will be the
result if you OR an ASCII code with the 8-bit mask 00100000?
Solution: The resulting letter will be in lower case.

3-3 OR Gate
Figure 3-25 A simplified intrusion detection

system using an OR gate.

3-3 OR Gate
Multiple input OR gate
Given n inputs, the total number of possible conditions of

binary inputs is N=2n


3-3 OR Gate
Figure 3-24 Boolean expressions for OR

gates with two, three, and four inputs.

3-3 OR Gate A X
B
C
Example 3-9: For a 3-input OR gate, determine the output

waveform in relation to the inputs.
Solution:

3-4 NAND Gate A X
B
The NAND gate produces a LOW output only when all
inputs are HIGH; the output is HIGH for all other
conditions. For a 2-input NAND gate, the truth table is
Inputs Output
A B X
0 0 1
0 1 1
1 0 1
1 1 0
The NAND operation is shown with a dot between the

variables and an overbar covering them. Thus, the NAND
operation is written as X = A .B (Alternatively, X = AB.)
3-4 NAND Gate
A X
Symbol
B
Figure 3-26 Standard NAND gate logic symbols

(ANSI/IEEE Std. 91-1984).

3-4 NAND Gate
A X
Symbol
B
Figure 3-30 Standard symbols representing the two

equivalent operations of a NAND gate.
Use truth table to verify.

3-4 NAND Gate
Figure 3-31 Detection of both 1/4 full or more.

3-4 NAND Gate
Figure 3-32 Detection of either less than ¼ full.

3-4 NAND Gate
A
B
X
The NAND gate is particularly useful because it is a “universal” gate – all

other basic gates can be constructed from NAND gates.
Question: How would you connect a 2-input NAND gate

to form a basic inverter?
Solution:

3-4 NAND Gate
3-input NAND gate:
Figure 3-29

3-4 NAND Gate
Multiple input NAND gate

3-5 NOR Gate A X
B

The NOR gate produces a HIGH output only when all
inputs are LOW; otherwise, the output is LOW output.
For a 2-input NOR gate, the truth table is
Inputs Output
A B X
0 0 1
0 1 0
1 0 0
1 1 0
The NOR operation is shown with a plus sign (+) between

the variables and an overbar covering them. Thus, the NOR
operation is written as X = A + B.
3-5 NOR Gate
A
B
X
The NOR operation will produce a LOW if any input is

HIGH.

3-5 NOR Gate
3-input NOR gate:
Figure 3-37

3-5 NOR Gate
A X
Symbol
B
Figure 3-38 Standard symbols representing the two
equivalent operations of a NOR gate.

3-5 NOR Gate
A X
Application
B
Figure 3-40

3-5 NOR Gate
+5.0 V
Example: When is the LED ON for the circuit 330 W
shown?
A
Solution: The LED will be on when any of B X
C
the four inputs are HIGH. D

3-5 NOR Gate
Multiple input NOR gate:

3-6 XOR Gate A
B
X

The XOR gate produces a HIGH output when both inputs
are at opposite logic levels. The truth table is
Inputs Output
A B X
0 0 0
0 1 1
1 0 1
1 1 0
The XOR operation is written as X = AB + AB.

Alternatively, it can be written with a circled plus sign
between the variables as X = A + B.

3-6 XOR Gate A X
B
A
B
X
Notice that the XOR gate will produce a HIGH only when
exactly one input is HIGH.
Question: If the A and B waveforms are both inverted for the above
waveforms, how is the output affected?
Solution: There is no change in the output.

3-6 XNOR Gate A X
B

The XNOR gate produces a HIGH output when both inputs
are at the same logic level. The truth table is
Inputs Output
A B X
0 0 1
0 1 0
1 0 0
1 1 1
The XNOR operation is shown as X = AB + AB.

Alternatively, the XNOR operation can be shown with a
circled dot between the variables. Thus, it can be shown as X
= A . B.
3-6 XNOR Gate
A
B
X
Notice that the XNOR gate will produce a HIGH when both inputs are the
same. This makes it useful for comparison functions.
Question: If the A waveform is inverted but B remains the same,

how is the output affected?
Solution: The output will be inverted.

Summary
Active Levels
.
(Figure 3-73)

3-8 Fixed Function Logic
TTL and CMOS
Two major fixed function logic families are TTL and CMOS.
A third technology is BiCMOS, which combines the first
two. Packaging for fixed function logic is shown.
0.335 – 0.334 in.
0.740 – 0.770 in. 14 13 12 11 10 9 8
14 13 12 11 10 9 8
0.250 ±0.010 in. 0.228 – 0.244 in.
1 2 3 4 5 6 7
1 2 3 4 5 6 7
Pin no.1 Lead no.1
identifiers identifier
14
1 14
1
DIP package SOIC package

Logic gates
Some common gate configurations are shown.
VCC VCC VCC VCC
14 13 12 11 10 9 8 14 13 12 11 10 9 8 14 13 12 11 10 9 8 14 13 12 11 10 9 8
1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7
GND GND GND GND
'00 ' 02 '04 '08
VCC VCC VCC VCC

14 13 12 11 10 9 8 14 13 12 11 10 9 8 14 13 12 11 10 9 8 14 13 12 11 10 9 8
1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7
GND GND GND GND
'10 '11 '20 '21
VCC VCC VCC VCC

14 13 12 11 10 9 8 14 13 12 11 10 9 8 14 13 12 11 10 9 8 14 13 12 11 10 9 8
1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7
GND GND GND GND
'27 '30 '32 '86

Logic symbol
Logic symbols show the gates and associated pin numbers.
VCC
(14)
(1)
(3)
(2) (1) & (3)
(4) (2)
(6) (4)
(5) (6)
(5)
(9) (9)
(8) (8)
(10) (10)
(12) (12)
(11) (13) (11)
(13)
(7)
GND

Gate level voltage - TTL 74LS00

Noise immunity

Propagation delay
Time delay between a cause (input change) and an effect
(output change), assuming an output load capacitance of 30pF.
Figure 3-52

Propagation delay
74AC00: Advanced CMOS 2-input NAND gate
min typical max

t PHL (ns) 1.5 4.5 6.5
t PLH (ns) 1.5 6.0 8.0

Propagation delay
With the FPGA chips, the internal “gate” propagation

delay is approximately 100ps, which is much faster
than discrete logic circuits.
FPGA programming will be discussed in Digital

Systems 2 in Year 3.

Fan-out
Figure 3-53 The LS series NAND gate output fans out to a
maximum of 20 LS series gate inputs.

3-7 Programmable Logic
PLD
A Programmable Logic Device (PLD) can be programmed to implement logic. There
are various technologies available for PLDs. Many use an internal array of AND gates
to form logic terms. Many PLDs can be programmed multiple times.
A A B B
SRAM SRAM SRAM SRAM

cell cell cell cell
SRAM SRAM SRAM SRAM

cell cell cell cell

3-7 Programmable Logic
PLD
The required logic for a PLD is developed with the aid of a

computer.
The logic can be entered using a Hardware Description
Language (HDL) such as VHDL. A logic can be specified
to the HDL as a text file, a schematic diagram, or a state
diagram.

Supplementary
Tri-state gates
P-channel MOSFET:
on – VGS < 0
off – VGS =0
N-channel MOSFET:
on – VGS > 0
off – VGS =0

Supplementary
Tri-state gates
Calculate Vout for the case A=5V, B=0
P-channel MOSFET is “off” (RDS = 500,000 Ω)

N-channel MOSFET is “off” (RDS = 500,000 Ω)
Vout= 5 x (500,000 / 1,000,000) = 2.5 V
IDS = 5 / 1,000,000 = 5 uA
Here, Vout is effectively disconnected (in the “Hi-Z state”)

when A is high and B is low.
Use an output enable signal to achieve this.

Supplementary
Tri-state gates
Tri-state buffer – disabled
H
L off
Hi-Z
X
off
H L

Supplementary
Tri-state gates
Tri-state buffer – enabled
H
H off
L
L
on
L H

Supplementary
Tri-state gates
Tri-state buffer – enabled
L
H on
H
H
off
L L

Supplementary
Tri-state gates
Tri-state buffer (active-high)

Supplementary
Tri-state gates
Tri-state buffer as a switch (active-high)

Supplementary
Tri-state gates
Motivation - wired two outputs

Supplementary
Tri-state gates
Tri-state buffer can be used to connect multiple devices to a
bus.
At any time, only one device is enabled and allowed to get

connected to the bus. Other devices should be disabled with
outputs put into Hi-Z state.
In this case, the disabled devices do not either supply or

sink current.

Supplementary
Tri-state buffer – Data bus control

Supplementary

Supplementary
Figure: (a) Tristate buffers used to connect several signals to a common

bus; (b) conditions for transmitting B to the bus.

Supplementary
Active-low tri-state buffer
EN A OUT
0 0 0
0 1 1
1 0 Hi-Z
1 1 Hi-Z
Output = Input if enable signal is NOT equal to “1”

Supplementary
Active-low tri-state buffer
74LS126 Quad Tri-state Buffer

Supplementary
Tri-state gates
74LS244 Octal Tri-state Buffer

Selected Key Terms
Inverter A logic circuit that inverts or complements its

input.
Truth table A table showing the inputs and corresponding
output(s) of a logic circuit.
Timing A diagram of waveforms showing the proper time
diagram relationship of all of the waveforms.
Boolean The mathematics of binary variables

algebra
AND gate A logic gate that produces a HIGH output only
when all of its inputs are HIGH.
Floyd, Digital Fundamentals, 11th ed © 2015 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Selected Key Terms
OR gate A logic gate that produces a HIGH output when

one or more inputs are HIGH.
NAND gate A logic gate that produces a LOW output only
when all of its inputs are HIGH.
NOR gate A logic gate that produces a LOW output when one
or more inputs are HIGH.
Exclusive-OR A logic gate that produces a HIGH output only

gate when its two inputs are at opposite levels.
Exclusive-NOR A logic gate that produces a LOW output only
gate when its two inputs are at opposite levels.
Summary
• Functions of NOT, AND, OR, NAND, NOR gates

(memorize)
• Expressions of NOT, AND, OR, NAND, NOR gates
(memorize)
• Timing diagrams of NOT, AND, OR, NAND, NOR
gates (understand)
• Active levels –active-high output, active-low output,
active-high input, active-low input
(understand)
• Tri-state gates (memorize)

Lec 2 - ds1 - pp03 - Gates

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Digital

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 1

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 2

Truth table: a list of the output for each possible input

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 3

Table 3-1 Inverter Truth Table

The NOT operation (complement) is shown with an overbar.

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 4

In most applications, the inputs to a gate are not stationary

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 5

Figure 3-3: Timing diagram for Figure 3-2

Operation with waveform inputs:

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 6

A group of inverters can be used to form the 1’s

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 7

Represented by a bubble for inversion (or complementation)

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 8

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 9

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 10

A weak signal source (one that is not capable of sourcing or sinking a

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 11

For this purpose, a special logic gate called buffer is manufactured to

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 12

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 13

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 14

The AND gate produces a HIGH output only when all

Truth table: a list of the output for each possible input

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 15

Table 3-2: Truth table for a 2-input AND gate

The AND operation is usually shown with a dot between the

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 16

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 17

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 18

Example 3-3: If two waveforms, A and B , are applied to the

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 19

Figure 3-16 An AND gate performing an

This enable/disable function is widely used in microprocessor systems.

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 20

Figure 3-17 A simple seat belt alarm circuit using an

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 21

Given n inputs, the total number of possible conditions of

For 2 inputs, N=22 =4 conditions.

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 22

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 23

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 24

The OR operation is shown with a plus sign (+) between the

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 25

Figure 3-19 All possible logic levels for a

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 26

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 27

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 28

The OR operation can be used in computer programming to set

Example: ASCII codes of letters have a 1 in the bit 5 position for

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 29

Figure 3-25 A simplified intrusion detection

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 30

Given n inputs, the total number of possible conditions of

For 2 inputs, N=22 =4 conditions.

Operation follows the definition.

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 31

Figure 3-24 Boolean expressions for OR

© 2015 Pearson Education. Modified by Q. Cheng. Chapter 3 32

Example 3-9: For a 3-input OR gate, determine the output