DESIGN OF 4-BIT SERIAL

MULTIPLIER

150040010-Y.ADWIT
150040012-A.RISHWANTH ROY
150040015-BALA KOWSHIK.A
Shift/Add Multiplication
Multiplication with right shifts: top-to-bottom accumulation
p(j+1) = (p(j) + xj a 2k) 2–1 withp(0) = 0 and
|–––add–––| p(k) = p = ax + p(0)2–k
|––shift right––|

Multiplication with left shifts: bottom-to-top accumulation

p(j+1) = 2 p(j) + xk–j–1a withp(0) = 0 and
|shift| p(k) = p = ax + p(0)2k
|––––add––––|
 Examples of Basic Multiplication
Right-shift algorithm Left-shift algorithm Examples
======================== ======================= of
a 1 0 1 0a 1 0 1 0
x 1 0 1 1x 1 0 1 1
sequential
======================== ======================= multipli-
p(0) 0 0 0 0 p(0) 0 0 0 0 cation with
+x0a 1 0 1 0 2p(0) 0 0 0 0 0
right and
––––––––––––––––––––––––– +x3a 1 0 1 0
2p (1)
0 1 0 1 0 –––––––––––––––––––––––– left shifts.
p (1)
0 1 0 1 0 p(1) 0 1 0 1 0
+x1a 1 0 1 0 2p(1) 0 1 0 1 0 0
––––––––––––––––––––––––– +x2a 0 0 0 0
2p (2)
0 1 1 1 1 0 ––––––––––––––––––––––––
p(2) 0 1 1 1 1 0 p(2) 0 1 0 1 0 0
+x2a 0 0 0 0 2p(2) 0 1 0 1 0 0 0
––––––––––––––––––––––––– +x1a 1 0 1 0
2p(3) 0 0 1 1 1 1 0 ––––––––––––––––––––––––
p (3)
0 0 1 1 1 1 0 p (3)
0 1 1 0 0 1 0 Check:
+x3a 1 0 1 0 2p (3)
0 1 1 0 0 1 0 0 10  11
––––––––––––––––––––––––– +x0a 1 0 1 0
2p (4)
0 1 1 0 1 1 1 0 –––––––––––––––––––––––– = 110
p (4)
0 1 1 0 1 1 1 0 p(4) 0 1 1 0 1 1 1 0 = 64 + 32 +
======================== ======================= 8+4+2
 Basic Hardware Multipliers

p(j+1) = (p(j) + xj a 2k) 2–1

|–––add–––|
|––shift right––|

Hardware realization of the sequential multiplication

algorithm with additions and right shifts.
 Example of Hardware Multiplication

(11)ten

0 1 1 0 1 1 1 0 (110)ten

(10)ten
1 0 1 0

p(j+1) = (p(j) + xj a 2k) 2–1

|–––add–––|
|––shift right––|
Hardware realization of the sequential multiplication
algorithm with additions and right shifts.
 Bit-Serial Multipliers
Bit-serial adder
FF
(LSB first) …x2 x1 x0 …s2 s1 s0
FA
…y2 y1 y0

Bit-serial multiplier
(Must follow the k-bit
…a a a …p p p
2 1 0
2 1 0
inputs with k 0s;
alternatively, view …x x x
2 1 0
the product as being
only k bits wide)
 A Direct Design for a Bit-Serial Multiplier
p (i–1) ai xi ai a(i - 1)
a
x
t out t in xi x(i - 1)

ai x(i - 1) Already
accumulated
cout ai xi c in into three
a i xi
numbers
(5; 3)-counter
2 1 0 xi a(i - 1)
1
sin s out
0
Mux
p
Already output
Building block for a latency-free (a) Structure of the bit-matrix
bit-serial multiplier.
... ai p(i - 1)
... xi ai xi
ai x(i - 1)
... t out t in LSB xi a(i - 1)
... cout c in 0
Shift right to
2p (i ) obtain p(i )
... sin s out pi

(b) Reduction after each input bit

The cellular structure of the bit-
serial multiplier based on the cell in Bit-serial multiplier design in
dot notation.