Professional Documents
Culture Documents
• Bus arrangements
• Bus components
• Bus protection techniques
• CT Saturation
• Application Considerations:
High impedance bus differential relaying
Low impedance bus differential relaying
Special topics
LBB (or BFR) Protection
Single bus - single breaker
ZONE 1
1 2 3 ---- n-1 n
ZONE 2
ZONE 1
TRANFER BUS
ZONE 2
ZONE 2
ZONE 2
TB1
B1 B2
TB1
L3 L4
BUS 2
ISO 1 ISO 2
CB 1
ISO 3
BYPASS
BUS 1
BUS 2
+
ISOLATOR 1
7B 7A
BUS 1
ISOLATOR 1
+
CB 1
7B 7A
ISO 3
BYPASS
ISOLATOR 1 CLOSED
F1a Contact Input F1a On
F1c Contact Input F1c On
F1b
-
Current Transformers
BUS 1
BUS 2
ISO 1 ISO 2
B LO C K
CTs
50 50 50 50 50
• Blocking signal could be sent
over communications ports
(peer-to-peer)
• This technique is limited to
simple one-incomer
distribution buses
Overcurrent (unrestrained) Differential
• Differential current derived by
summation of all feeder currents
connected to the bus
• CT ratio matching may be required
• On external faults, saturated CTs
51 yield spurious differential current
• Time delay used to cope with CT
saturation
• Instantaneous differential OC
function useful on integrated
microprocessor-based relays
• May maloperate on CT saturation
on external fault
Linear Couplers
59
0V
40 V 10 V 10 V 0V 20 V
External
Fault
If = 8000 A
where,
Iprim – primary current in each circuit
Xm – liner coupler mutual reactance (5V per 1000Amps => 0.005 @ 60Hz )
ZR – relay tap impedance
ZC – sum of all linear coupler self impedances
If = 8000 A Internal Bus
Fault
40 V 59
0V 10 V 10 V 0V 20 V
formed in a number of
ways
• No dedicated CTs needed
• Used for protection of re-
configurable buses possible
I DIF I 1 I 2 ... I n
I RES I 1 I 2 ... I n I RES max I 1 , I 2 , ..., I n
Low Impedance Percent Differential
– Individual currents sampled by protection and summated digitally
• CT ratio matching done internally (no auxiliary CTs)
• Dedicated CTs not necessary
– Additional algorithms improve security of percent differential
characteristic during CT saturation
– Dynamic bus replica allows application to reconfigurable buses
• Done digitally with logic to add/remove current inputs from differential
computation
• Switching of CT secondary circuits not required
– Low secondary burdens
– Additional functionality available
• Digital oscillography and monitoring of each circuit connected to bus zone
• Time-stamped event recording
• Breaker failure protection
Digital Differential Algorithm Goals
– Improve the main differential algorithm operation
• Better filtering
• Faster response
• Better restraint techniques
• Switching transient blocking
– Provide dynamic bus replica for reconfigurable bus bars
– Dependably detect CT saturation in a fast and reliable manner,
especially for external faults
– Implement additional security to the main differential algorithm to
prevent incorrect operation
• External faults with CT saturation
• CT secondary circuit trouble (e.g. short circuits)
Low Impedance Differential (Distributed)
– Data Acquisition Units (DAUs)
installed in bays
52 52 52 – Central Processing Unit (CPU)
processes all data from DAUs
DA U DA U DA U
– Communications between
DAUs and CPU over fiber using
proprietary protocol
– Sampling synchronisation
between DAUs is required
CU – Perceived less reliable (more
hardware needed)
co pp er
fi be r
– Difficult to apply in retrofit
applications
Low Impedance Differential (Centralized)
With DC Offset
• Waveform starts off being
asymmetrical, then
symmetrical in steady state
Ratio Current CT Current
External Fault & Ideal CTs
d iffere ntia l
t1
t0 restraining
– Fault starts at t0
– Steady-state fault conditions occur at t 1
t1
t0 restraining
– Fault starts at t0
– Steady-state fault conditions occur at t 1
t1
t0 restraining
– Fault starts at t0, CT begins to saturate at t1
– CT fully saturated at t2
CB 11 CB 12
Large Bus Applications
87B phase A
87B phase B
87B phase C
Logic relay
(switch status,
optional BF)
Large Bus Applications
For buses with up to 24 circuits
Summing External Currents
Not Recommended for Low-Z 87B relays
CT-1
• Relay becomes combination
of restrained and unrestrained
CT-2
elements
• In order to parallel CTs:
CT-3
– CT performance must be closely
I 1 = Error
matched
• Any errors will appear as
CT-4
I2 = 0
differential currents
– Associated feeders must be
I3 = 0
1
iR i1 i2 i3 ... in “scaled sum of”
n
R eg ion 1
(lo w d iffe re ntia l
c urre nts )
re s tra ining
Bus Differential Adaptive Logic Diagram
DIFL
AND
DIR
OR
87B BIASED OP
OR
SAT
AND
DIFH
Phase Comparison Principle
• Internal Faults: All fault (“large”) currents are approximately in
phase.
Secondary Current of
Faulted Circuit
• No Voltages are required or needed (Severe CT Saturation)
Phase Comparison Principle Continued…
Ip Ip
imag imag
ID I p OP E R AT E ID I p OP E R ATE
B LOC K B L OC K
Ip Ip
ID - Ip real ID - I p real
Ip ID I p ID I p
Ip
B LOC K
B L OC K
OP E R AT E OP E R ATE
CT Saturation
t2
d iffere ntia l
t1
t0 restraining
– Fault starts at t0, CT begins to saturate at t1
– CT fully saturated at t2
CT Saturation Detector State Machine
NORMAL
SAT := 0
The differential
current below the saturation
first slope for condition
certain period of
time EXTERNAL
FAULT
SAT := 1
The differential-
The differential restraining trajectory
characteristic out of the differential
entered characteristic for
certain period of time
EXTERNAL
FAULT & CT
SATURATION
SAT := 1
CT Saturation Detector Operating Principles
• The 87B SAT flag WILL NOT be set during internal faults,
regardless of whether or not any of the CTs saturate.
• The 87B SAT flag WILL be set during external faults,
regardless of whether or not any of the CTs saturate.
• By design, the 87B SAT flag WILL force the relay to use the
additional 87B DIR phase comparison for Region 2
150
100 ~1 ms
50
current, A
0
-50
-100
-150
-200
0.06 0.07 0.08 0.09 0.1 0.11 0.12
time, sec
Despite heavy CT
saturation the
external fault current
The element is seen in the
The
does not opposite direction
directional flag
maloperate
is not set
CT Saturation – Internal Fault Example
The
The element directional
operates in flag is set
10ms
Applying Low-Impedance Differential Relays
for Busbar Protection
Basic Topics
– Configure physical CT Inputs
– Configure Bus Zone and Dynamic Bus Replica
– Calculating Bus Differential Element settings
Advanced Topics
– Isolator switch monitoring for reconfigurable buses
– Differential Zone CT Trouble
– Integrated Breaker Failure protection
Configuring CT Inputs
– For each connected CT circuit enter Primary rating
and select Secondary rating.
– Each 3-phase bank of CT inputs must be assigned
to a Signal Source that is used to define the Bus
Zone and Dynamic Bus Replica
High Set
(Unrestrained)
High Slope
Low Slope
High
Breakpoint
High Set
(Unrestrained)
High Slope
Low Slope
High
Breakpoint
B -1 S -1 S -3 S -5
B -5
CT-1 CT-7
CT-2 B -2 CT-3 B -3 CT-4 B -4 CT-5
B -7
CT-6
CT-8
B -6
S -2 S -4 S -6
S O UTH B US
B -1 S -1 S -3 S -5
B -5
B -7
CT-6
CT-8
B -6
S -2 S -4 S -6
S O UTH B US
B -1 S -1 S -3 S -5
B -5
B -7
CT-6
CT-8
B -6
S -2 S -4 S -6
S O UTH B US
B -1 S -1 S -3 S -5
B -5
CT-1 CT-7
CT-2 B -2 CT-3 B -3 CT-4 B -4 CT-5
B -7
CT-6
CT-8
B -6
S -2 S -4 S -6
S O UTH B US
On Off OPEN No No
Iso
l ato
n r
os itio Pos
itio
o r P n
l at
Iso Phase A AC signals wired
here, bus replica configured
here
FAULT
B C
A
3 4
1 2 5 6
LOAD LOAD
7 8
LOAD
62-1
50BF Breaker Failure
AND Timer
BFI Scheme Output
Timing Chart
50BF
CURRENT
PROTECTIVE
DETECTOR
FAULT CLEARED
RELAY BREAKER MARGIN
TIME INTERRUPT TIME RESET TIME TIME
TIME
AUX
62-1 BREAKER FAILURE TIMER TIME TRIP LOCAL BACKUP BREAKER
BFI RELAY INTERRUPT TIME
TIME
TRANSFER TRIP
TIME
FAULT OCCURS REMOTE BACKUP BREAKER
TOTAL FAULT CLEARING TIME INTERRUPT TIME
Two Components
• Current Detector
• Breaker Failure Timer
Current Detector
• Detects current flow
• Pick up for minimum fault
• If phase current set above load current
• If ground current set above unbalance
• Drop out not delayed by dc offset
• Use 52a only if no current
Timer
• Longer than it takes the breaker to clear a
fault
• Shorter than the Critical Clearing Time plus
some margin.
• Could be longer for Line to Ground Faults than
for Three Phase Faults
Critical clearing Time
• Dictated by Transient Stability limit
• Results from Stability Study
• Typically taken as 100mSec.
Total Clearing Time
The sum of :
BFI pick up + Breaker Failure Timer + Auxiliary
trip relay time + Local back up breaker time +
(Transfer trip time if remote)
Transient Stability time
• Severity of Fault
• Loading on System
• Mass of Generators
• Type of Fault
Circuit Breaker Failure Modes
• Failure to Trip
• Failure to Clear
Failure to Trip
• Contacts do not open after trip circuit
energized.
• Short or open in Trip coil
• Mechanical problem with breaker
Failure to Clear
62-1
50BF Breaker Failure
AND Timer
BFI Scheme Output
62-2
Re-Trip the
Timer
Breaker
50BF
Enables 50BF
Breaker Failure
AND
Scheme Output
62-1
BFI Timer
Addition of Control Timer
Control
timer
50BF
Enabled only after Breaker Failure
62-1 times out AND
Scheme Output
62-1
Enable
BFI Timer
Breaker Failure Seal-In
62-1
50BF Breaker Failure
AND Timer
OR Scheme Output
BFI
Minimum Fault Current
• Use where current magnitude may not be
enough to pick up current detector
• Transformers
• Generators
• Harmonic Filters
Minimum Fault Current
62-1
BFI Breaker Failure
50BF AND Timer
OR Scheme Output
52a
Ring Bus Application
21/ 21/
79 79
Ring Bus
Ring Bus
• Separate Ct inputs into relay
• Careful of current distribution after one
breaker opens in setting current detectors.
• Another Working group (K5) to look into this
issue.
Distributed Breaker Failure
GOOSE
Breaker Failure
Protection
Trip
Fault Point
Design Considerations
• Total Breaker Failure clearing time should be
less than system stability limit.
• Independent of type of failure detected
• Should operate during loss of dc to breaker
Conclusions
• BFP should operate only when desired
• Timer setting should allow adequate margin between
backup breaker clearing and system critical clearing
time.
• Multiple timers can be used for different types of
faults
• Use auxiliary contacts as last resort for BFI.
Conclusions
• Phase current detectors should be set above load to
protect from scheme operating during testing.
• Seal in circuits should be used to insure breaker
failure scheme does not drop out prematurely
• Care should be taken when applying breaker failure
to ring bus and breaker and one half .
THANKS
ABHAY KUMAR
DGM, POWERGRID
abhaykumar@powergridindia.com