Chapter 5

DIGITAL BUILDING BLOCKS Chapter 5
Computer System Architectures

Based on
Digital Design and Computer Architecture,
2nd Edition
David Money Harris and Sarah L. Harris
Chapter 5 <1>
DIGITAL BUILDING BLOCKS Chapter 5 :: Topics
• Introduction
• Arithmetic Circuits
• Number Systems
• Sequential Building Blocks
• Memory Arrays
• Logic Arrays
Chapter 5 <2>
DIGITAL BUILDING BLOCKS Introduction
• Digital building blocks:
– Gates, multiplexers, decoders, registers,
arithmetic circuits, counters, memory arrays,
logic arrays
• Building blocks demonstrate hierarchy,
modularity, and regularity:
– Hierarchy of simpler components
– Well-defined interfaces and functions
– Regular structure easily extends to different
sizes
Chapter 5 <3>
DIGITAL BUILDING BLOCKS 1-Bit Adders
Half Full
Adder Adder
A B A B
Cout Cout Cin

+ +
S S
A B Cout S Cin A B Cout S

0 0 0 0 0
0 1 0 0 1
1 0 0 1 0
1 1 0 1 1
1 0 0
S = 1 0 1
Cout = 1 1 0
1 1 1
S =
Cout =
Chapter 5 <4>
Half Full
Adder Adder
A B A B
Cout Cout Cin

+ +
S S

0 0 0 0 0 0 0 0 0
0 1 0 1 0 0 1 0 1
1 0 0 1 0 1 0 0 1
1 1 1 0 0 1 1 1 0
1 0 0 0 1
S = 1 0 1 1 0
Cout = 1 1 0 1 0
1 1 1 1 1
S =
Cout =
Chapter 5 <5>
Half Full
Adder Adder
A B A B
Cout Cout Cin

+ +
S S

0 0 0 0 0 0 0 0 0
0 1 0 1 0 0 1 0 1
1 0 0 1 0 1 0 0 1
1 1 1 0 0 1 1 1 0
1 0 0 0 1
S =AB 1 0 1 1 0
Cout = AB 1 1 0 1 0
1 1 1 1 1
S = A  B Cin
Cout = AB + ACin + BCin
Chapter 5 <6>
DIGITAL BUILDING BLOCKS Multibit Adders (CPAs)
• Types of carry propagate adders (CPAs):
– Ripple-carry (slow)
– Carry-lookahead (fast)
– Prefix (faster)
• Carry-lookahead and prefix adders faster for large
adders but require more hardware
Symbol
A B
N N
Cout Cin
+
N
S
Chapter 5 <7>
DIGITAL BUILDING BLOCKS Ripple-Carry Adder
• Chain 1-bit adders together
• Carry ripples through entire chain
• Disadvantage: slow
A31 B31 A30 B30 A1 B1 A0 B0
Cout Cin
+ C30 + C29 C1 + C0 +
S31 S30 S1 S0
Chapter 5 <8>
DIGITAL BUILDING BLOCKS Ripple-Carry Adder Delay
tripple = NtFA
where tFA is the delay of a full adder
Chapter 5 <9>
DIGITAL BUILDING BLOCKS Carry-Lookahead Adder
• Compute carry out (Cout) for k-bit blocks using generate and
propagate signals
• Some definitions:
– Column i produces a carry out by either generating a carry out or
propagating a carry in to the carry out
– Generate (Gi) and propagate (Pi) signals for each column:
• Column i will generate a carry out if Ai AND Bi are both 1.
Gi = A i B i
• Column i will propagate a carry in to the carry out if Ai OR Bi is 1.
P i = A i + Bi
• The carry out of column i (Ci) is:
Ci = Ai Bi + (Ai + Bi )Ci-1 = Gi + Pi Ci-1

Chapter 5 <10>
DIGITAL BUILDING BLOCKS Carry-Lookahead Addition
• Step 1: Compute Gi and Pi for all columns
• Step 2: Compute G and P for k-bit blocks
• Step 3: Cin propagates through each k-bit
propagate/generate block
Chapter 5 <11>
DIGITAL BUILDING BLOCKS Carry-Lookahead Adder
• Example: 4-bit blocks (G3:0 and P3:0) :
G3:0 = G3 + P3 (G2 + P2 (G1 + P1G0 )
P3:0 = P3P2 P1P0
• Generally,
Gi:j = Gi + Pi (Gi-1 + Pi-1 (Gi-2 + Pi-2Gj )
Pi:j = PiPi-1 Pi-2Pj
Ci = Gi:j + Pi:j Ci-1
Chapter 5 <12>
DIGITAL BUILDING BLOCKS 32-bit CLA with 4-bit Blocks
B31:28 A31:28 B27:24 A27:24 B7:4 A7:4 B3:0 A3:0
4-bit CLA C27 4-bit CLA C23 C7 4-bit CLA C3 4-bit CLA
Cout Cin
Block Block Block Block
S31:28 S27:24 S7:4 S3:0
B3 A3 B2 A2 B1 A1 B0 A0
C2 C1 C0
Cin
+ + + +
S3 S2 S1 S0
G3:0 G3
P3
G2
P2
G1
P1
G0
P3
Cout P3:0 P2
P1
Cin
P0
Chapter 5 <13>
DIGITAL BUILDING BLOCKS Carry-Lookahead Adder Delay
For N-bit CLA with k-bit blocks:
tCLA = tpg + tpg_block + (N/k – 1)tAND_OR + ktFA
– tpg : delay to generate all Pi, Gi

– tpg_block : delay to generate all Pi:j, Gi:j
– tAND_OR : delay from Cin to Cout of final AND/OR gate in k-bit CLA
block
An N-bit carry-lookahead adder is generally much faster than a

ripple-carry adder for N > 16
Chapter 5 <14>
DIGITAL BUILDING BLOCKS Prefix Adder
• Computes carry in (Ci-1) for each column, then
computes sum:
Si = (Ai Å Bi) Å Ci
• Computes G and P for 1-, 2-, 4-, 8-bit blocks, etc.
until all Gi (carry in) known
• log2N stages
Chapter 5 <15>
• Carry in either generated in a column or propagated from a
previous column.
• Column -1 holds Cin, so
G-1 = Cin, P-1 = 0
• Carry in to column i = carry out of column i-1:
Ci-1 = Gi-1:-1
Gi-1:-1: generate signal spanning columns i-1 to -1
• Sum equation:
Si = (Ai Å Bi) Å Gi-1:-1
• Goal: Quickly compute G0:-1, G1:-1, G2:-1, G3:-1, G4:-1, G5:-1, …
(called prefixes)
Chapter 5 <16>
• Generate and propagate signals for a block spanning bits i:j:
Gi:j = Gi:k + Pi:k Gk-1:j
Pi:j = Pi:kPk-1:j
• In words:
– Generate: block i:j will generate a carry if:
• upper part (i:k) generates a carry or
• upper part propagates a carry generated in lower part
(k-1:j)
– Propagate: block i:j will propagate a carry if both the
upper and lower parts propagate the carry
Chapter 5 <17>
DIGITAL BUILDING BLOCKS Prefix Adder Schematic
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -1
14:13 12:11 10:9 8:7 6:5 4:3 2:1 0:-1
14:11 13:11 10:7 9:7 6:3 5:3 2:-1 1:-1
14:7 13:7 12:7 11:7 6:-1 5:-1 4:-1 3:-1
14:-1 13:-1 12:-1 11:-1 10:-1 9:-1 8:-1 7:-1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Legend i i
i:j
Ai Bi Pi:k Pk-1:jGi:k Gk-1:j Gi-1:-1 Ai Bi
Pi:i Gi:i
Pi:j Gi:j
Si
Chapter 5 <18>
DIGITAL BUILDING BLOCKS Prefix Adder Delay
tPA = tpg + log2N(tpg_prefix ) + tXOR
– tpg: delay to produce Pi Gi (AND or OR gate)

– tpg_prefix: delay of black prefix cell (AND-OR gate)
Chapter 5 <19>
DIGITAL BUILDING BLOCKS Adder Delay Comparisons
Compare delay of: 32-bit ripple-carry, carry-lookahead, and
prefix adders
• CLA has 4-bit blocks
• 2-input gate delay = 100 ps; full adder delay = 300 ps
Chapter 5 <20>
prefix adders
tripple = NtFA = 32(300 ps)
= 9.6 ns
= [100 + 600 + (7)200 + 4(300)] ps
= 3.3 ns
= [100 + log232(200) + 100] ps
= 1.2 ns
Chapter 5 <21>
DIGITAL BUILDING BLOCKS Subtracter
Symbol Implementation
A B
N
A B
N N
N N
-
N +
Y N
Y
Chapter 5 <22>
DIGITAL BUILDING BLOCKS Comparator: Equality
A3
B3
A B A2
4 4 B2
Equal
= A1
B1
Equal
A0
B0
Chapter 5 <23>
DIGITAL BUILDING BLOCKS Comparator: Less Than
A B
N N
-
N
[N-1]
A<B
5-<24>
Copyright © 2007 Elsevier
Chapter 5 <24>
DIGITAL BUILDING BLOCKS Arithmetic Logic Unit (ALU)
F2:0 Function
A B 000 A& B
N N 001 A| B
010 A+ B
ALU 3F 011 not used
N 100 A & ~B
Y 101 A | ~B
110 A- B
111 SLT
5-<25>
Chapter 5 <25>
DIGITAL BUILDING BLOCKS ALU Design
A B
N N F2:0 Function
000 A&B
N
001 A|B
1
0 F2
N 010 A+B
011 not used
Cout +
100 A & ~B
[N-1] S
101 A | ~B
Extend
Zero
110 A-B
N N N N
111 SLT
1
0
3
2 F1:0
N
Y
5-<26>
Chapter 5 <26>
prefix adders
tripple = NtFA = 32(300 ps)
= 9.6 ns
= [100 + 600 + (7)200 + 4(300)] ps
= 3.3 ns
= [100 + log232(200) + 100] ps
= 1.2 ns
Chapter 5 <27>
DIGITAL BUILDING BLOCKS Set Less Than (SLT) Example
A B
N N
• Configure 32-bit ALU for SLT
operation: A = 25 and B = 32
N
1
0
F2
N
Cout +
[N-1] S
Extend
Zero
N N N N
1
0
3
2 F1:0
N
Y
5-<28>
Chapter 5 <28>
DIGITAL BUILDING BLOCKS Set Less Than (SLT) Example
A B
N N
• Configure 32-bit ALU for SLT
operation: A = 25 and B = 32
N
1
– A < B, so Y should be 32-bit
0
F2 representation of 1 (0x00000001)
N
– F2:0 = 111
– F2 = 1 (adder acts as
Cout + subtracter), so 25 - 32 = -7
[N-1] S
– -7 has 1 in the most
Extend
significant bit (S31 = 1)

Zero
N N N N
– F1:0 = 11 multiplexer selects
1
0
3
F1:0
N
2
Y = S31 (zero extended) =
Y 0x00000001.
5-<29>
Chapter 5 <29>
DIGITAL BUILDING BLOCKS Shifters
• Logical shifter: shifts value to left or right and fills empty spaces with 0’s
– Ex: 11001 >> 2 =
– Ex: 11001 << 2 =
• Arithmetic shifter: same as logical shifter, but on right shift, fills empty
spaces with the old most significant bit (msb).
– Ex: 11001 >>> 2 =
– Ex: 11001 <<< 2 =
• Rotator: rotates bits in a circle, such that bits shifted off one end are
shifted into the other end
– Ex: 11001 ROR 2 =
– Ex: 11001 ROL 2 =
5-<30>
Chapter 5 <30>
DIGITAL BUILDING BLOCKS Shifters
• Logical shifter:
– Ex: 11001 >> 2 = 00110
– Ex: 11001 << 2 = 00100
• Arithmetic shifter:
– Ex: 11001 >>> 2 = 11110
– Ex: 11001 <<< 2 = 00100
• Rotator:
– Ex: 11001 ROR 2 = 01110
– Ex: 11001 ROL 2 = 00111
Chapter 5 <31>
DIGITAL BUILDING BLOCKS Shifter Design
A 3 A2 A 1 A 0 shamt1:0
2
00 S1:0
01
10
Y3
shamt1:0 11
2 00
S1:0
01
Y2
A3:0 4 >> 4 Y3:0
10
11
00
S1:0
01
10
Y1
11
00
S1:0
01
10
Y0
11
Chapter 5 <32>
DIGITAL BUILDING BLOCKS Shifters as Multipliers, Dividers
• A << N = A × 2N
– Example: 00001 << 2 = 00100 (1 × 22 = 4)
– Example: 11101 << 2 = 10100 (-3 × 22 = -12)
• A >>> N = A ÷ 2N
– Example: 01000 >>> 2 = 00010 (8 ÷ 22 = 2)
– Example: 10000 >>> 2 = 11100 (-16 ÷ 22 = -4)
Chapter 5 <33>
DIGITAL BUILDING BLOCKS Multipliers
• Partial products formed by multiplying a single
digit of the multiplier with multiplicand
• Shifted partial products summed to form result
Decimal Binary
230 multiplicand 0101
x 42 multiplier x 0111
460 partial 0101
+ 920 products 0101
9660 0101
+ 0000
result 0100011
230 x 42 = 9660 5 x 7 = 35
Chapter 5 <34>
DIGITAL BUILDING BLOCKS 4 x 4 Multiplier
A B
4 4
x
8
P
A3 A2 A1 A0
B0
B1
0
A3 A2 A1 A0 0
x B3 B2 B1 B0 B2
A3B0 A2B0 A1B0 A0B0
A3B1 A2B1 A1B1 A0B1 0
B3
A3B2 A2B2 A1B2 A0B2
+ A3B3 A2B3 A1B3 A0B3
0
P7 P6 P5 P4 P3 P2 P1 P0
P7 P6 P5 P4 P3 P2 P1 P0
Chapter 5 <35>
DIGITAL BUILDING BLOCKS 4 x 4 Divider
0 B3 0 B2 0 B1 A3 B0
Legend
R B
1 R B
Cout Cin Cout Cin
+
Q3 D
D
N R'
A2
0
N
1
R'
Q2 A/B = Q + R/B
A1 Algorithm:
1
R’ = 0
for i = N-1 to 0
Q1
R = {R’ << 1. Ai}
A0
D=R-B
1
if D < 0, Qi=0, R’=R
Q0
R3 R2 R1 R0
else Qi=1, R’=D
R’=R
Chapter 5 <36>
DIGITAL BUILDING BLOCKS Number Systems
• Numbers we can represent using binary
representations
– Positive numbers
• Unsigned binary
– Negative numbers
• Two’s complement
• Sign/magnitude numbers
• What about fractions?
Chapter 5 <37>
DIGITAL BUILDING BLOCKS Numbers with Fractions
• Two common notations:
– Fixed-point: binary point fixed
– Floating-point: binary point floats to the right of the
most significant 1
Chapter 5 <38>
DIGITAL BUILDING BLOCKS Fixed-Point Numbers
• 6.75 using 4 integer bits and 4 fraction bits:
01101100
0110.1100
22 + 21 + 2-1 + 2-2 = 6.75
• Binary point is implied
• The number of integer and fraction bits must be
agreed upon beforehand
Chapter 5 <39>
DIGITAL BUILDING BLOCKS Fixed-Point Number Example
• Represent 7.510 using 4 integer bits and 4
fraction bits.
Chapter 5 <40>
DIGITAL BUILDING BLOCKS Fixed-Point Number Example
• Represent 7.510 using 4 integer bits and 4
fraction bits.
01111000
Chapter 5 <41>
DIGITAL BUILDING BLOCKS Signed Fixed-Point Numbers
• Representations:
– Sign/magnitude
– Two’s complement
• Example: Represent -7.510 using 4 integer and 4 fraction
bits
– Sign/magnitude:
– Two’s complement:
Chapter 5 <42>
DIGITAL BUILDING BLOCKS Signed Fixed-Point Numbers
• Representations:
– Sign/magnitude
– Two’s complement
• Example: Represent -7.510 using 4 integer and 4 fraction
bits
– Sign/magnitude:
11111000
– Two’s complement:
1. +7.5: 01111000
2. Invert bits: 10000111
3. Add 1 to lsb: + 1
10001000
Chapter 5 <43>
DIGITAL BUILDING BLOCKS Floating-Point Numbers
• Binary point floats to the right of the most significant 1
• Similar to decimal scientific notation
• For example, write 27310 in scientific notation:

273 = 2.73 × 102
• In general, a number is written in scientific notation as:
± M × BE
– M = mantissa
– B = base
– E = exponent
– In the example, M = 2.73, B = 10, and E = 2
Chapter 5 <44>
DIGITAL BUILDING BLOCKS Floating-Point Numbers
1 bit 8 bits 23 bits
Sign Exponent Mantissa
• Example: represent the value 22810 using a 32-bit floating

point representation
We show three versions –final version is called the IEEE 754

floating-point standard
Chapter 5 <45>
DIGITAL BUILDING BLOCKS Floating-Point Representation 1
1. Convert decimal to binary (don’t reverse steps 1 & 2!):
22810 = 111001002
2. Write the number in “binary scientific notation”:

111001002 = 1.110012 × 27
3. Fill in each field of the 32-bit floating point number:

– The sign bit is positive (0)
– The 8 exponent bits represent the value 7
– The remaining 23 bits are the mantissa
0 00000111 11 1001 0000 0000 0000 0000
Sign Exponent Mantissa
Chapter 5 <46>
• First bit of the mantissa is always 1:
– 22810 = 111001002 = 1.11001 × 27
• So, no need to store it: implicit leading 1

• Store just fraction bits in 23-bit field

0 00000111 110 0100 0000 0000 0000 0000
Sign Exponent Fraction
Chapter 5 <47>
• Biased exponent: bias = 127 (011111112)
– Biased exponent = bias + exponent
– Exponent of 7 is stored as:
127 + 7 = 134 = 0x100001102
• The IEEE 754 32-bit floating-point representation of 22810

0 10000110 110 0100 0000 0000 0000 0000
Sign Biased Fraction
Exponent
Chapter 5 <48>
DIGITAL BUILDING BLOCKS Floating-Point Example
Write -58.2510 in floating point (IEEE 754)
Chapter 5 <49>
DIGITAL BUILDING BLOCKS Floating-Point Example
Write -58.2510 in floating point (IEEE 754)
1. Convert decimal to binary:
58.2510 = 111010.012
2. Write in binary scientific notation:

1.1101001 × 25
3. Fill in fields:
Sign bit: 1 (negative)
8 exponent bits: (127 + 5) = 132 = 100001002
23 fraction bits: 110 1001 0000 0000 0000 0000
1 100 0010 0 110 1001 0000 0000 0000 0000
in hexadecimal: 0xC2690000
Chapter 5 <50>
DIGITAL BUILDING BLOCKS Floating-Point: Special Cases
Number Sign Exponent Fraction

0 X 00000000 00000000000000000000000
∞ 0 11111111 00000000000000000000000
-∞ 1 11111111 00000000000000000000000
NaN X 11111111 non-zero
Chapter 5 <51>
DIGITAL BUILDING BLOCKS Floating-Point Precision
• Single-Precision:
– 32-bit
– 1 sign bit, 8 exponent bits, 23 fraction bits
– bias = 127
• Double-Precision:
– 64-bit
– 1 sign bit, 11 exponent bits, 52 fraction bits
– bias = 1023
Chapter 5 <52>
DIGITAL BUILDING BLOCKS Floating-Point: Rounding
• Overflow: number too large to be represented
• Underflow: number too small to be represented
• Rounding modes:
– Down
– Up
– Toward zero
– To nearest
• Example: round 1.100101 (1.578125) to only 3 fraction bits
– Down: 1.100
– Up: 1.101
– Toward zero:1.100
– To nearest: 1.101 (1.625 is closer to 1.578125 than 1.5 is)
Chapter 5 <53>
DIGITAL BUILDING BLOCKS Floating-Point Addition
1. Extract exponent and fraction bits
2. Prepend leading 1 to form mantissa
3. Compare exponents
4. Shift smaller mantissa if necessary
5. Add mantissas
6. Normalize mantissa and adjust exponent if necessary
7. Round result
8. Assemble exponent and fraction back into floating-point
format
Chapter 5 <54>
DIGITAL BUILDING BLOCKS Floating-Point Addition Example
Add the following floating-point numbers:
0x3FC00000
0x40500000
Chapter 5 <55>
1. Extract exponent and fraction bits
0 01111111 100 0000 0000 0000 0000 0000
0 10000000 101 0000 0000 0000 0000 0000
For first number (N1): S = 0, E = 127, F = .1

For second number (N2): S = 0, E = 128, F = .101
2. Prepend leading 1 to form mantissa

N1: 1.1
N2: 1.101
Chapter 5 <56>
3. Compare exponents
127 – 128 = -1, so shift N1 right by 1 bit
4. Shift smaller mantissa if necessary

shift N1’s mantissa: 1.1 >> 1 = 0.11 (× 21)
5. Add mantissas
0.11 × 21
+ 1.101 × 21
10.011 × 21
Chapter 5 <57>
DIGITAL BUILDING BLOCKS Floating Point Addition Example
6. Normalize mantissa and adjust exponent if necessary
10.011 × 21 = 1.0011 × 22
7. Round result
No need (fits in 23 bits)
8. Assemble exponent and fraction back into floating-point
format
S = 0, E = 2 + 127 = 129 = 100000012, F = 001100..
0 10000001 001 1000 0000 0000 0000 0000
in hexadecimal: 0x40980000
Chapter 5 <58>
DIGITAL BUILDING BLOCKS Counters
• Increments on each clock edge
• Used to cycle through numbers. For example,
– 000, 001, 010, 011, 100, 101, 110, 111, 000, 001…
• Example uses:
– Digital clock displays
– Program counter: keeps track of current instruction executing
CLK
N CLK
N N
+ Q
Q N N r
1
Reset
Reset
Chapter 5 <59>
DIGITAL BUILDING BLOCKS Shift Registers
• Shift a new bit in on each clock edge
• Shift a bit out on each clock edge
• Serial-to-parallel converter: converts serial input (Sin) to
parallel output (Q0:N-1)
Symbol: Implementation:
CLK
N
Q Sin Sout
Sin Sout
Q0 Q1 Q2 QN-1
Chapter 5 <60>
DIGITAL BUILDING BLOCKS Shift Register with Parallel Load
• When Load = 1, acts as a normal N-bit register
• When Load = 0, acts as a shift register
• Now can act as a serial-to-parallel converter (Sin to Q0:N-1) or
a parallel-to-serial converter (D0:N-1 to Sout)
D0 D1 D2 DN-1
Load
Clk
Sin 0 0 0 0 Sout
1 1 1 1
Q0 Q1 Q2 QN-1
Chapter 5 <61>
DIGITAL BUILDING BLOCKS Memory Arrays
• Efficiently store large amounts of data
• 3 common types:
– Dynamic random access memory (DRAM)
– Static random access memory (SRAM)
– Read only memory (ROM)
• M-bit data value read/ written at each unique N-bit address
N
Address Array
Data
Chapter 5 <62>
• 2-dimensional array of bit cells
• Each bit cell stores one bit
• N address bits and M data bits: Address
N
Array
– 2N rows and M columns
– Depth: number of rows (number of words) M
– Width: number of columns (size of word) Data

– Array size: depth × width = 2N × M
Address Data
11 0 1 0
2
Address Array 10 1 0 0
depth
01 1 1 0
3 00 0 1 1
Data width
Chapter 5 <63>
DIGITAL BUILDING BLOCKS Memory Array Example
• 22 × 3-bit array
• Number of words: 4
• Word size: 3-bits
• For example, the 3-bit word stored at address 10 is 100
Address Data
11 0 1 0
2
Address Array 10 1 0 0
depth
01 1 1 0
3 00 0 1 1
Data width
Chapter 5 <64>
1024-word x
10
Address 32-bit
Array
32
Data
Chapter 5 <65>
DIGITAL BUILDING BLOCKS Memory Array Bit Cells
bitline
wordline
stored
bit
bitline = bitline = Z
wordline = 1 wordline = 0
stored stored
bit = 0 bit = 0
bitline = bitline =
stored stored
bit = 1 bit = 1
(a) (b)
Chapter 5 <66>
DIGITAL BUILDING BLOCKS Memory Array Bit Cells
bitline
wordline
stored
bit
bitline = 0 bitline = Z
stored stored
bit = 0 bit = 0
bitline = 1 bitline = Z
stored stored
bit = 1 bit = 1
(a) (b)
Chapter 5 <67>
DIGITAL BUILDING BLOCKS Memory Array
• Wordline:
– like an enable
– single row in memory array read/written
– corresponds to unique address
– only one wordline HIGH at once
2:4
Decoder bitline2 bitline1 bitline0
wordline3
11
2 stored stored stored
Address bit = 0 bit = 1 bit = 0
wordline2
10
stored stored stored
wordline1 bit = 1 bit = 0 bit = 0
01
bit = 1 bit = 1 bit = 0
wordline0
00
bit = 0 bit = 1 bit = 1
Data2 Data1 Data0

Chapter 5 <68>
DIGITAL BUILDING BLOCKS Types of Memory
• Random access memory (RAM): volatile
• Read only memory (ROM): nonvolatile
Chapter 5 <69>
DIGITAL BUILDING BLOCKS RAM: Random Access Memory
• Volatile: loses its data when power off
• Read and written quickly
• Main memory in your computer is RAM
(DRAM)
Historically called random access memory because any data

word accessed as easily as any other (in contrast to sequential
access memories such as a tape recorder)
Chapter 5 <70>
DIGITAL BUILDING BLOCKS ROM: Read Only Memory
• Nonvolatile: retains data when power off
• Read quickly, but writing is impossible or
slow
• Flash memory in cameras, thumb drives, and
digital cameras are all ROMs
Historically called read only memory because ROMs

were written at manufacturing time or by burning fuses.
Once ROM was configured, it could not be written again.
This is no longer the case for Flash memory and other
types of ROMs.
Chapter 5 <71>
DIGITAL BUILDING BLOCKS Types of RAM
• DRAM (Dynamic random access memory)
• SRAM (Static random access memory)
• Differ in how they store data:
– DRAM uses a capacitor
– SRAM uses cross-coupled inverters
Chapter 5 <72>
DIGITAL BUILDING BLOCKS Robert Dennard, 1932 -
• Invented DRAM in
1966 at IBM
• Others were skeptical
that the idea would
work
• By the mid-1970’s
DRAM in virtually all
computers
Chapter 5 <73>
DIGITAL BUILDING BLOCKS DRAM
• Data bits stored on capacitor
• Dynamic because the value needs to be refreshed
(rewritten) periodically and after read:
– Charge leakage from the capacitor degrades the value
– Reading destroys the stored value
bitline bitline
wordline wordline
stored
bit stored
bit
Chapter 5 <74>
DIGITAL BUILDING BLOCKS DRAM
bitline bitline
wordline wordline
stored + + stored
bit = 1 bit = 0
Chapter 5 <75>
DIGITAL BUILDING BLOCKS SRAM
bitline
wordline
stored
bit
bitline bitline
wordline
Chapter 5 <76>
DIGITAL BUILDING BLOCKS Memory Arrays Review
2:4
wordline3
11
wordline2
10
01
bit = 1 bit = 1 bit = 0
wordline0
00
bit = 0 bit = 1 bit = 1
Data2 Data1 Data0
DRAM bit cell: SRAM bit cell:

bitline bitline bitline
wordline wordline
Chapter 5 <77>
DIGITAL BUILDING BLOCKS ROM: Dot Notation
bitline
2:4
Decoder wordline
11
2
Address
bit cell
10
containing 0
01 bitline
wordline
00
bit cell
Data2 Data1 Data0 containing 1
Chapter 5 <78>
DIGITAL BUILDING BLOCKS Fujio Masuoka, 1944 -
• Developed memories and high
speed circuits at Toshiba, 1971-1994
• Invented Flash memory as an
unauthorized project pursued during
nights and weekends in the late
1970’s
• The process of erasing the memory
reminded him of the flash of a
camera
• Toshiba slow to commercialize the
idea; Intel was first to market in
1988
• Flash has grown into a $25 billion
per year market
Chapter 5 <79>
DIGITAL BUILDING BLOCKS ROM Storage
2:4
Decoder Address Data
11
Address 2 11 0 1 0
10
10 1 0 0
depth
01 01 1 1 0
00 00 0 1 1
Data2 Data1 Data0
width
Chapter 5 <80>
DIGITAL BUILDING BLOCKS ROM Logic
2:4
Decoder
Data2 = A1 Å A0
11
2
Address
10
Data1 = A1 + A0
01
00 Data0 = A1A0
Data2 Data1 Data0
Chapter 5 <81>
DIGITAL BUILDING BLOCKS Example: Logic with ROMs
Implement the following logic functions using a 22 × 3-bit
ROM:
– X = AB 2:4
Decoder
– Y=A+B
11
– Z=AB 2
A, B
10
01
00
X Y Z
Chapter 5 <82>
DIGITAL BUILDING BLOCKS Example: Logic with ROMs
ROM:
– X = AB 2:4
Decoder
– Y=A+B
11
– Z=AB 2
A, B
10
01
00
X Y Z
Chapter 5 <83>
DIGITAL BUILDING BLOCKS Logic with Any Memory Array
2:4
wordline3
11
wordline2
10
01
bit = 1 bit = 1 bit = 0
wordline0
00
bit = 0 bit = 1 bit = 1
Data2 Data1 Data0
Data2 = A1 Å A0
Data1 = A1 + A0
Data0 = A1A0
Chapter 5 <84>
DIGITAL BUILDING BLOCKS Logic with Memory Arrays
memory array:
– X = AB
– Y=A+B
– Z=AB
Chapter 5 <85>
memory array:
– X = AB 2:4
– Y=A+B Decoder bitline2 bitline1 bitline0
wordline3
11
– Z=AB
A, B bit = 1 bit = 1 bit = 0
wordline2
10
01
bit = 0 bit = 1 bit = 0
wordline0
00
bit = 0 bit = 0 bit = 0
X Y Z
Chapter 5 <86>
Called lookup tables (LUTs): look up output at each input
combination (address)
4-word x 1-bit Array
2:4
Decoder bitline
Truth
Table 00
stored
A A1
bit = 0
A B Y 01
B A0
0 0 0 stored
0 1 0 bit = 0
1 0 0 10
1 1 1 stored
bit = 0
11
stored
bit = 1
Chapter 5 <87>
DIGITAL BUILDING BLOCKS Multi-ported Memories
• Port: address/data pair
• 3-ported memory
– 2 read ports (A1/RD1, A2/RD2)
– 1 write port (A3/WD3, WE3 enables writing)
• Register file: small multi-ported memory
CLK
WE3
A1 RD1
N M
A2 RD2
N M
A3 Array
N
WD3
M
Chapter 5 <88>
DIGITAL BUILDING BLOCKS SystemVerilog Memory Arrays
// 256 x 3 memory module with one read/write port
module dmem( input logic clk, we,
input logic[7:0] a
input logic [2:0] wd,
output logic [2:0] rd);
logic [2:0] RAM[255:0];
assign rd = RAM[a];
always @(posedge clk)

if (we)
RAM[a] <= wd;
endmodule
Chapter 5 <89>
DIGITAL BUILDING BLOCKS Logic Arrays
• PLAs (Programmable logic arrays)
– AND array followed by OR array
– Combinational logic only
– Fixed internal connections
• FPGAs (Field programmable gate arrays)
– Array of Logic Elements (LEs)
– Combinational and sequential logic
– Programmable internal connections
Chapter 5 <90>
DIGITAL BUILDING BLOCKS PLAs
• X = ABC + ABC
• Y = AB Inputs
M
AND Implicants OR
ARRAY N ARRAY
P
Outputs
A B C
OR ARRAY
ABC
ABC
AB
AND ARRAY
X Y
Chapter 5 <91>
DIGITAL BUILDING BLOCKS PLAs: Dot Notation
Inputs
M
AND Implicants OR
ARRAY N ARRAY
P
Outputs
A B C
OR ARRAY
ABC
ABC
AB
AND ARRAY
X Y
Chapter 5 <92>
DIGITAL BUILDING BLOCKS FPGA: Field Programmable Gate Array
• Composed of:
– LEs (Logic elements): perform logic
– IOEs (Input/output elements): interface with outside
world
– Programmable interconnection: connect LEs and
IOEs
– Some FPGAs include other building blocks such as
multipliers and RAMs
Chapter 5 <93>
DIGITAL BUILDING BLOCKS General FPGA Layout
Chapter 5 <94>
DIGITAL BUILDING BLOCKS LE: Logic Element
• Composed of:
– LUTs (lookup tables): perform combinational logic
– Flip-flops: perform sequential logic
– Multiplexers: connect LUTs and flip-flops
Chapter 5 <95>
DIGITAL BUILDING BLOCKS Altera Cyclone IV LE
Chapter 5 <96>
DIGITAL BUILDING BLOCKS Altera Cyclone IV LE
• The Spartan CLB has:
– 1 four-input LUT
– 1 registered output
– 1 combinational output
Chapter 5 <97>
DIGITAL BUILDING BLOCKS LE Configuration Example
Show how to configure a Cyclone IV LE to perform the
following functions:
– X = ABC + ABC
– Y = AB
Chapter 5 <98>
DIGITAL BUILDING BLOCKS LE Configuration Example
Show how to configure a Cyclone IV LE to perform the
following functions:
– X = ABC + ABC
– Y = AB
(A) (B) (C) (X)
data 1 data 2 data 3 data 4 LUT output
0 0 0 X 0
0 0 1 X 1
A data 1
0 1 0 X 0
B data 2
0 1 1 X 0 C
data 3 X
1 0 0 X 0
0 data 4
1 0 1 X 0 LUT
1 1 0 X 1
LE 1
1 1 1 X 0
(A) (B) (Y)

data 1 data 2 data 3 data 4 LUT output
0 0 X X 0 A data 1
0 1 X X 0 B data 2
1 0 X X 1 0 data 3 Y
1 1 X X 0 0 data 4 LUT
LE 2
Chapter 5 <99>
DIGITAL BUILDING BLOCKS FPGA Design Flow
Using a CAD tool (such as Altera’s Quartus II)
• Enter the design using schematic entry or an HDL
• Simulate the design
• Synthesize design and map it onto FPGA
• Download the configuration onto the FPGA
• Test the design
Chapter 5 <100>

Chapter 5

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DIGITAL BUILDING BLOCKS Chapter 5

Computer System Architectures

Cout Cout Cin

A B Cout S Cin A B Cout S

Cout Cout Cin

A B Cout S Cin A B Cout S

Cout Cout Cin

A B Cout S Cin A B Cout S

A31 B31 A30 B30 A1 B1 A0 B0

where tFA is the delay of a full adder

Ci = Ai Bi + (Ai + Bi )Ci-1 = Gi + Pi Ci-1

S31:28 S27:24 S7:4 S3:0

– tpg : delay to generate all Pi, Gi

An N-bit carry-lookahead adder is generally much faster than a

14:13 12:11 10:9 8:7 6:5 4:3 2:1 0:-1

14:11 13:11 10:7 9:7 6:3 5:3 2:-1 1:-1

14:7 13:7 12:7 11:7 6:-1 5:-1 4:-1 3:-1

14:-1 13:-1 12:-1 11:-1 10:-1 9:-1 8:-1 7:-1

Ai Bi Pi:k Pk-1:jGi:k Gk-1:j Gi-1:-1 Ai Bi

– tpg: delay to produce Pi Gi (AND or OR gate)

significant bit (S31 = 1)

• What about fractions?

• For example, write 27310 in scientific notation:

Sign Exponent Mantissa

• Example: represent the value 22810 using a 32-bit floating

We show three versions –final version is called the IEEE 754

2. Write the number in “binary scientific notation”:

3. Fill in each field of the 32-bit floating point number:

• So, no need to store it: implicit leading 1

1 bit 8 bits 23 bits

• The IEEE 754 32-bit floating-point representation of 22810

1 bit 8 bits 23 bits

2. Write in binary scientific notation:

Number Sign Exponent Fraction

For first number (N1): S = 0, E = 127, F = .1

2. Prepend leading 1 to form mantissa

4. Shift smaller mantissa if necessary

– Width: number of columns (size of word) Data

Data2 Data1 Data0

Historically called random access memory because any data

Historically called read only memory because ROMs

Data2 Data1 Data0

DRAM bit cell: SRAM bit cell:

Data2 Data1 Data0

logic [2:0] RAM[255:0];

always @(posedge clk)

(A) (B) (Y)

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