COMPILER

CONSTRUCTION
Lecture 3
 SYNTAX TREE goal

x+2-y expr

expr op term

expr op term – <id,y>

term + <number, 2>

<id,x>
2
 ABSTRACT SYNTAX TREES

• The parse tree contains a lot of

unneeded information.
• Compilers often use an abstract
syntax tree (AST).

3
 ABSTRACT SYNTAX TREES

+ <id,y>
<id,x> <number,2>

• This is much more concise

4
 ABSTRACT SYNTAX TREES
–

+ <id,y>
<id,x> <number,2>

• AST summarizes grammatical

structure without the details of
derivation 5
 ABSTRACT SYNTAX TREES
–

+ <id,y>
<id,x> <number,2>

• ASTs are one kind of

intermediate representation (IR)
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 THE BACK END

IR Instruction IR Register IR Instruction machine

selection allocation scheduling code

errors

7
 THE BACK END

• Translate IR into target machine code.

• Choose machine (assembly) instructions to
implement each IR operation

8
 THE BACK END

• Ensure conformance with system

interfaces
• Decide which values to keep in registers

9
 THE BACK END

IR Instruction IR Register IR Instruction machine

selection allocation scheduling code

errors

Instruction Selection:
•Produce fast, compact code.
10
 THE BACK END
IR Instruction IR Register IR Instruction machine
selection allocation scheduling code

errors
Instruction Selection:
• Take advantage of target features such as
addressing modes.
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 THE BACK END
IR Instruction IR Register IR Instruction machine
selection allocation scheduling code

errors
Instruction Selection:
• Usually viewed as a pattern matching
problem – dynamic programming.
12
 THE BACK END

IR Instruction IR Register IR Instruction machine

selection allocation scheduling code

errors

Register Allocation:
•Have each value in a register when
it is used. 13
 THE BACK END

IR Instruction IR Register IR Instruction machine

selection allocation scheduling code

errors

Register Allocation:
•Manage a limited set of resources –
register file. 14
 THE BACK END

IR Instruction IR Register IR Instruction machine

selection allocation scheduling code

errors

Instruction Scheduling:
•Avoid hardware stalls and
interlocks. 15
 THE BACK END

IR Instruction IR Register IR Instruction machine

selection allocation scheduling code

errors

Instruction Scheduling:
•Use all functional units
productively. 16