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Instructor:
Mr. Sheraz Babar
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Lecture 04
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Syntax Tree goal
x+2-y expr
expr op term
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Abstract Syntax Trees
–
+ <id,y>
<id,x> <number,2>
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Abstract Syntax Trees
–
+ <id,y>
<id,x> <number,2>
+ <id,y>
<id,x> <number,2>
errors
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The Back End
Translate IR into target
machine code.
Choose machine (assembly)
instructions to implement each
IR operation
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The Back End
Ensure conformance with
system interfaces
Decide which values to keep
in registers
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The Back End
IR Instruction IR Register IR Instruction machine
selection allocation scheduling code
errors
Instruction Selection:
Produce fast, compact code.
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The Back End
IR Instruction IR Register IR Instruction machine
selection allocation scheduling code
errors
Instruction Selection:
Take advantage of target
features such as addressing
modes.
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The Back End
IR Instruction IR Register IR Instruction machine
selection allocation scheduling code
errors
Instruction Selection:
Usually viewed as a pattern
matching problem – dynamic
programming.
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The Back End
IR Instruction IR Register IR Instruction machine
selection allocation scheduling code
errors
Instruction Selection:
Spurred by PDP-11 to VAX-11
- CISC.
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The Back End
IR Instruction IR Register IR Instruction machine
selection allocation scheduling code
errors
Instruction Selection:
RISC architecture simplified
this problem.
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The Back End
IR Instruction IR Register IR Instruction machine
selection allocation scheduling code
errors
Register Allocation:
Have each value in a register
when it is used.
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The Back End
IR Instruction IR Register IR Instruction machine
selection allocation scheduling code
errors
Register Allocation:
Manage a limited set of
resources – register file.
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The Back End
IR Instruction IR Register IR Instruction machine
selection allocation scheduling code
errors
Register Allocation:
Can change instruction choices
and insert LOADs and STOREs.
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The Back End
IR Instruction IR Register IR Instruction machine
selection allocation scheduling code
errors
Register Allocation:
Optimal register allocation is
NP-Complete.
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The Back End
IR Instruction IR Register IR Instruction machine
selection allocation scheduling code
errors
Instruction Scheduling:
Avoid hardware stalls and
interlocks.
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The Back End
IR Instruction IR Register IR Instruction machine
selection allocation scheduling code
errors
Instruction Scheduling:
Use all functional units
productively.
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The Back End
IR Instruction IR Register IR Instruction machine
selection allocation scheduling code
errors
Instruction Scheduling:
Optimal scheduling is
NP-Complete in nearly all cases.
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The End
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