Eee303 Week05 Alu

EEE 303 – Digital Electronics
EEE ALU Design
303
Lecture 05.1
Dr. Sajid Muhaimin Choudhury, Assistant Professor
Department of Electrical and Electronics Engineering
Bangladesh University of Engineering and Technology
Adder Design

Addition of Unsigned Numbers
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 3

Department of EEE, BUET
Half Adder

Half Adder Circuit Symbol

Full Adder

Full Adder with 2 cascaded half adders
Cascading 2 Half -Adders
Half Adder
𝑆 𝐻𝐴1=𝑥𝑖⨁ 𝑦𝑖
𝐶 𝐻𝐴1=𝑥𝑖 𝑦𝑖
Full Adder
𝑆 𝑖=( 𝑥 𝑖⨁ 𝑦𝑖 ) ⨁ 𝐶𝑖
𝐶 𝑖+1=( 𝑥 𝑖 𝐶 𝑖 )+ ( 𝑦 𝑖 𝐶 𝑖 ) + ( 𝑥 𝑖 𝑦 𝑖 )
+
EEE 303 – Digital Electronics + Dr. Sajid Muhaimin Choudhury 9
Full Adder – Logic Diagram

Half Full
Adder Adder
A B A B
Cout Cout Cin

+ +
S S
A B Cout S Cin A B Cout S

0 0 0 0 0 0 0 0 0
0 1 0 1 0 0 1 0 1
1 0 0 1 0 1 0 0 1
1 1 1 0 0 1 1 1 0
1 0 0 0 1
S =AB 1 0 1 1 0
Cout = AB 1 1 0 1 0
1 1 1 1 1
S = A  B Cin
Cout = AB + ACin + BCin
N-bit Ripple Carry Adder

• Chain 1-bit adders together

• Carry ripples through entire chain
• Disadvantage: slow
tripple = NtFA
where tFA is the delay of a 1-bit full adder

Performance Issue
• Each carry calculation needs 2 cascaded gates.
• Gate delay for each gate Δt
• Final result of the addition will be valid after a delay of nΔt,

Carry Mechanism
Carry Generate:
Only if A and B both are 1
G = A.B
Carry Propagate
Either A or B is 1
P = A+B
The technique can be exploited to predict carry a priori

Performance Issue
• Each carry calculation needs 2 cascaded gates.
• Gate delay for each gate Δt
• Final result of the addition will be valid after a delay of nΔt,

Mitigation: Carry Lookahead Adder
Compute Cout for k-bit blocks using generate and

propagate signals

Carry-Lookahead Adder
Compute Cout for k-bit blocks using generate and propagate signals
Some definitions:
– Column i produces a carry out by either generating a carry out or propagating a carry
in to the carry out
– Generate (Gi) and propagate (Pi) signals for each column:
• Generate: Column i will generate a carry out if Ai and Bi are both 1.
G i = Ai B i
• Propagate: Column i will propagate a carry in to the carry out if Ai or Bi is 1.
Pi = Ai + Bi
• Carry out: The carry out of column i (Ci) is:
Ci = Ai Bi + (Ai + Bi )Ci-1 = Gi + Pi Ci-1

Propagate and Generate Signals
Examples: Column propagate and generate signals:
Column propagate: Pi = Ai + Bi
Column generate: Gi = Ai Bi
Ci = Gi + Pi Ci-1
Block Propagate
Block Propagate and
and Generate Generate
Now use column Propagate and Generate
signals to compute Block Propagate and
Block Generate signals for k-bit blocks, i.e.:
• Compute if a k-bit group will propagate a carry in (of the
block) to the carry out (of the block)
• Compute if a k-bit group will generate a carry out (of the
block)

Block Propagate and Generate Signals
• Example: 4-bit blocks
• Block propagate signal: P3:0 (single-bit signal)
• A carry-in would propagate through all 4 bits of the block:
P3:0 = P3P2 P1P0
• Examples:

P3:0 = P3P2 P1P0
• Block generate signal: G3:0 (single-bit signal)
• A carry is generated:
• in column 3, or
• in column 2 and propagated through column 3, or
• in column 1 and propagated through columns 2 and 3, or
• in column 0 and propagated through columns 1-3
G3:0 = G3 + G2P3 + G1P2P3 + G0P1P2P3

P3:0 = P3P2 P1P0
• in column 3, or
• in column 2 and propagated through column 3, or ...
G3:0 = G3 + G2P3 + G1P2P3 + G0P1P2P3

G3:0 = G3 + P3 [G2 + P2 (G1 + P1G0 )]

Block Generate
Block Generate Signal
Signal Examples Examples
• A carry is: generated in column 3, or generated in column 2 and
propagated through column 3, or ...
G3:0 = G3 + G2P3 + G1P2P3 + G0P1P2P3

P3:0 = P3P2 P1P0
• in column 3, or
• in column 2 and propagated through column 3, or …
G3:0 = G3 + G2P3 + G1P2P3 + G0P1P2P3
G3:0 = G3 + P3 [G2 + P2 (G1 + P1G0 )]
C3 = G3:0 + P3:0 C-1
• Example: Block propagate and generate
signals for 4-bit blocks (P3:0 and G3:0):
P3:0 = P3P2 P1P0
G3:0 = G3 + P3 (G2 + P2 (G1 + P1G0 )
C3 = G3:0 + P3:0 C-1
• Generally,
Pi:j = PiPi-1 Pi-2Pj
Gi:j = Gi + Pi (Gi-1 + Pi-1 (Gi-2 + Pi-2Gj )
Ci = Gi:j + Pi:j Cj-1

32-bit CLA with 4-bit Blocks

Carry-Lookahead Addition
• Step 1: Compute Gi and Pi for all columns
• Step 2: Compute G and P for k-bit blocks
• Step 3: Cin propagates through each k-bit
propagate/generate logic (meanwhile computing sums)
• Step 4: Compute sum for most significant k-bit block

G i = Ai Bi
Pi = Ai + Bi

P3:0 = P3P2 P1P0
G3:0 = G3 + P3 (G2 + P2 (G1 + P1G0 )

propagate/generate logic (meanwhile computing sums
B31:28 A31:28 B27:24 A27:24 B7:4 A7:4 B3:0 A3:0
4-bit CLA C27 4-bit CLA C23 C7 4-bit CLA C3 4-bit CLA
Cout Cin
Block Block Block Block
S31:28 S27:24 S7:4 S3:0

B3 A3 B2 A2 B1 A1 B0 A0
C C C
+ 2 + 1 + 0 + Cin
S3 S2 S1 S0 B3 A3 B2 A2 B1 A1 B0 A0
G3:0 C C C
G3
P3 + 2 + 1 + 0 + Cin B3 A3 B2 A2 B1 A1 B0 A0
G2 S3 S2 S1 S0 C C C
P2
G1 G3:0 G3 + 2 + 1 + 0 + Cin
P1 P3 S3 S2 S1 S0
G0 G2
B3 A3 B2 A2 B1 A1 B0 A0 P2 G3:0 G3
C C C P3:0 P3 G1 P3
+ 2 + 1 + 0 + Cin Cout P2
P1
P1
G0 G2
S3 S2 S1 S0 Cin P0 P2
G1
P3:0 P3 P1
G3:0 G3 Cout P2 G0
P3 Cin P1
G2 P0 P3
P2 Cout P3:0 P2
G1 P
P1 Cin P1
G0 0
P3:0 P3
Cout P2
Cin P1
P0

propagate/generate logic (meanwhile computing sums)
• Step 4: Compute sum for most significant k-bit block
B3 A3 B2 A2 B1 A1 B0 A0
C C C
+ 2 + 1 + 0 + Cin
S3 S2 S1 S0 B3 A3 B2 A2 B1 A1 B0 A0
G3:0 C C C
G3
P3 + 2 + 1 + 0 + Cin B3 A3 B2 A2 B1 A1 B0 A0
G2 S3 S2 S1 S0 C C C
P
G2
1 G3:0 G3 + 2 + 1 + 0 + Cin
P1 P3 S3 S2 S1 S0
G0 G2
B3 A3 B2 A2 B1 A1 B0 A0 P2 G3:0 G3
C C C P3:0 P3 G1 P3
+ 2 + 1 + 0 + Cin Cout P2
P1
P1
G0 G2
S3 S2 S1 S0 Cin P0 P2
G1
P3:0 P3 P1
G3:0 G3 Cout P2 G0
P3 Cin P1
G2 P0 P3
P2 Cout P3:0 P2
G1 P
P1 Cin P1
G0 0
P3:0 P3
Cout P2
Cin P1
P0


Carry-Lookahead Adder Delay
For N-bit CLA with k-bit blocks:
tCLA = tpg + tpg_block + (N/k – 1)tAND_OR + ktFA
– tpg : delay to generate all Pi, Gi

– tpg_block : delay to generate all Pi:j, Gi:j
– tAND_OR : delay from Cin to Cout of final AND/OR gate in k-bit CLA
block
An N-bit carry-lookahead adder is generally much faster than

a ripple-carry adder for N > 16

Adder
Adder Delay Delay Comparisons
Comparisons
Compare delay of: 32-bit ripple-carry, CLA,
• CLA has 4-bit blocks
• 2-input gate delay = 100 ps; full adder delay = 300 ps
tripple = NtFA = 32(300 ps)
= 9.6 ns
tCLA = tpg + tpg_block + (N/k – 1)tAND_OR + ktFA
= [100 + 600 + (7)200 + 4(300)] ps
= 3.3 ns

Budget: Performance vs Cost
• Ripple Carry adder:

Simpler, Lower Number of transistors, Slow Speed
• Fast Adder:
Complex, Higher Number of Transistors, Fast
• As a designer, you need to choose the appropriate

solution! Performance vs Budget

Arithmetic Overflow

Recall: Signed numbers

Arithmetic Overflow
• If n bits are used to represent signed numbers, then the

result must be in the range −2n−1 to 2n−1 − 1.
• If the result does not fit in this range, then we say that
arithmetic overflow has occurred.
• To ensure the correct operation of an arithmetic circuit, it
is important to be able to detect the occurrence of
overflow.

Example of Overflow – 4 bit addition

EEE ALU Design: Verilog
Implementations for
303 Adders, Subtractor
Lecture 05.2
4 Bit Adder – with 7483 / 74283 Integrated Circuit

8 Bit Adder – with 7483 / 74283 Integrated Circuit
A0 A4
A7A6 A5A4A3A2 A1A0
A1 A5
B7B6 B5B4B3B2 B1B0
A2 S0 A6 S4
S8S7S6 S5S4S3S2 S1S0 A3 S1 S5
A7
B0 S2 B4 S6
B1 S3 B5 S7
B2 B6
B3 B7
S8

Verilog Implementation of Full Adder
module fulladd (Cin, x, y, s, Cout);

input Cin, x, y;
output s, Cout;
xor (s, x, y, Cin);
and (z1, x, y);
and (z2, x, Cin);
and (z3, y, Cin);
or (Cout, z1, z2, z3);
endmodule

Verilog Implementation of Full Adder
module fulladd (Cin, x, y, s, Cout);

input Cin, x, y;
output s, Cout;
assign s = x^y^Cin;
assign Cout=(x&y)|(x&Cin)|(y&Cin);
endmodule

Simplified Implementation of Full Adder with
Arithmetic Assignment

4-Bit Adder with Cascading Full Adders
module adder4 (carryin, x3, x2, x1, x0, y3, y2, y1, y0,
s3, s2, s1, s0, carryout);
input carryin, x3, x2, x1, x0, y3, y2, y1, y0;
output s3, s2, s1, s0, carryout;
fulladd stage0 (carryin, x0, y0, s0, c1);
fulladd stage1 (c1, x1, y1, s1, c2);
fulladd stage2 (c2, x2, y2, s2, c3);
fulladd stage3 (c3, x3, y3, s3, carryout);
endmodule

Verilog Implementation of Full Adder with Vectors
module adder4 (carryin, X, Y, S, carryout);
input carryin;
input [3:0] X, Y;
output [3:0] S;
output carryout;
wire [3:1] C;
fulladd stage0 (carryin, X[0], Y[0], S[0], C[1]);
fulladd stage1 (C[1], X[1], Y[1], S[1], C[2]);
fulladd stage2 (C[2], X[2], Y[2], S[2], C[3]);
fulladd stage3 (C[3], X[3], Y[3], S[3], carryout);
endmodule

module addern (carryin, X, Y, S, carryout);
parameter n = 32;
input carryin;
input [n– 1:0] X, Y;
output reg [n –1:0] S;
output reg carryout;
reg [n:0] C;
integer k;
always @(X, Y, carryin) begin
C[0] = carryin;
for(k=0;k< n;k=k+1) begin
S[k] = X[k] Y[k] C[k];
C[k+1] = (X[k] & Y[k]) (X[k] & C[k]) (Y[k] & C[k]);
end
carryout = C[n];
end endmodule
N-bit adder with arithmetic assignment
module addern (carryin, X, Y, S);
parameter n = 32;
input carryin;
input [n –1:0] X, Y;
output reg [n –1:0] S;
always @(X, Y, carryin)
S = X + Y + carryin;
endmodule

The generate Keyword in Verilog
 Generates sub-circuits using a loop

If a for loop is included in the generate block, the loop index
variable has to be declared of type genvar.
 A genvar variable is similar to an integer variable, but
i. it can have only positive values
ii. it can be used only inside generate blocks

N-bit Ripple Carry Adder with generate
module addern (carryin, X, Y, S, carryout);
parameter n = 32;
input carryin;
input [n –1:0] X, Y;
output [n –1:0] S;
output carryout;
wire [n:0] C;
genvar i;
assign C[0] = carryin;
assign carryout = C[n];
generate
for (i = 0; i < = n –1; i = i+1)
begin:addbit
fulladd stage (C[i], X[i], Y[i], S[i], C[i+1]);
end
endgenerate
endmodule
Recall: Overflow Checking

N-bit adder with overflow check
S omits the MSB

N-bit adder with overflow check – Extra Memory
Sum requires extra

memory to implement

Simplified n-bit Adder with Overflow Check

Subtraction

“Taking
Recall: 2’s the Two’s
Complement
• Complement”
Flips the sign of a two’s complement number.
• Method:
1. Invert the bits (1’s Complement)
2. Add 1 (2’s Complement)
• Example: Flip the sign of 310 = 00112
1. 1100
2. + 1
1101 = -310
Add 6 + (-6) using two’s complement numbers

“Taking
Recall: 2’s the Two’s
Complement
• Complement”
Flips the sign of a two’s complement number.
• Method:
1. Invert the bits -> Subtract each digit from 1 (1’s Complement)
2. Add 1 (2’s Complement)
• Example: Flip the sign of 310 = 00112
1. 1100
2. + 1
1101 = -310
Add 6 + (-6) using two’s complement numbers

“Taking the
Radix Complement Two’s
• Complement”
Flips the sign of a N’s complement number in Base-N
• Method:
1. Subtract Each Digit from (N-1) (N-1)’s complement
2. Add 1 N’s complement

“Taking the
10’s Complement Two’s
• Complement”
Flips the sign of a 10’s complement number in Base-10.
• Method:
1. Subtract Each Digit from 9 9’s complement
2. Add 1 10’s complement
• Example: Flip the sign of 8210 in 10’s Complement
1. (9-8) (9-2) = (99-82) = 17 9’s complement
2. + 1
18 10’s complement

2’s complement
• For an n-digit decimal number,

• 2’s complement:
• A-B:

10’s complement
• For an n-digit decimal number,

• A-B:

Understanding 10’s Complement

Cascading
• If A ≥ B, then the operation A + (10n − B) produces a carry-out of 1. This

carry is equivalent to 10n; hence it can be simply ignored.
• If A < B, then the operation
A + (10n − B) produces a carry-out of 0. Let the result obtained be M , so
that A − B = M − 10n
• Or 10n −(B−A)=M, so M is a 10’s complement of (B-A)

N-bit Subtractor with Adder

Subtracter

Comparator: Equality

Comparator: Less Than
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 73 73

Comparator

EEE ALU Design:
ALU, Multiplication,
303 Division, BCD
Lecture 05.3
ALU: Arithmetic Logic Unit
ALU should perform:
• Addition
• Subtraction
• AND
• OR

ALUControl1:0 Function
00 Add
01 Subtract
10 AND
11 OR
Example: Perform A + B
ALUControl = 00
Result = A + B

00 Add
01 Subtract
10 AND
11 OR
Example: Perform A OR B

00 Add
01 Subtract
10 AND
11 OR
Example: Perform A OR B
ALUControl1:0 = 11
Mux selects output of OR gate as Result, so
Result = A OR B

00 Add
01 Subtract
10 AND
11 OR

00 Add
01 Subtract
10 AND
11 OR
ALUControl1:0 = 00
ALUControl0 = 0, so:
Cin to adder = 0
2nd input to adder is B
Mux selects Sum as Result, so
Result = A + B

ALU with Status Flags
Flag Description
N Result is Negative
Z Result is Zero
C Adder produces Carry
out
V Adder oVerflowed


ALU with Status Flags: Negative
N = 1 if:
Result is negative
So, N is connected to
most significant bit of
Result

ALU with Status Flags: Zero
Z = 1 if:
all of the bits of
Result are 0

ALU with Status Flags: Carry
C = 1 if:
Cout of Adder is 1
AND
ALU is adding or
subtracting
(ALUControl is 00 or
01)

ALU with Status Flags: oVerflow
V = 1 if:
The addition of 2
same-signed
numbers produces a
result with the
opposite sign

V = 1 if:
ALU is performing addition or subtraction
(ALUControl1 = 0)

V = 1 if:
(ALUControl1 = 0)
AND
A and Sum have opposite signs

V = 1 if:
(ALUControl1 = 0)
AND
AND
A and B have same signs upon addition
OR
A and B have different signs upon
subtraction

V = 1 if:
(ALUControl1 = 0)
AND
AND
A and B have same signs upon addition
(ALUControl0 = 0)
OR
A and B have different signs upon
subtraction
(ALUControl0 = 1)

Shifters
Logical shifter: shifts value to left or right and fills empty spaces with 0’s
• Ex: 11001 >> 2 =
• Ex: 11001 << 2 =
Arithmetic shifter: same as logical shifter, but on right shift, fills empty spaces with the old
most significant bit (msb)
• Ex: 11001 >>> 2 =
• Ex: 11001 <<< 2 =
Rotator: rotates bits in a circle, such that bits shifted off one end are shifted into the other end
• Ex: 11001 ROR 2 =
• Ex: 11001 ROL 2 =
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 93 93

Shifters
Logical shifter:
• Ex: 11001 >> 2 = 00110
• Ex: 11001 << 2 = 00100
Arithmetic shifter:
• Ex: 11001 >>> 2 = 11110
• Ex: 11001 <<< 2 = 00100
Rotator:
• Ex: 11001 ROR 2 = 01110
• Ex: 11001 ROL 2 = 00111

Shifter Design

Multiplication by 2n
• 11011 x 100 = 1101100
• Multiplying with 4 will just increase the number of zeros in
the LSB. This can be implemented with right shifting the
number 2 bits.
• Multiplying with any 2n number will just shift the number n

bits to left.

Shifters as Multipliers, Dividers
• A << N = A × 2N
• Example: 00001 << 2 = 00100 (1 × 22 = 4)
• Example: 11101 << 2 = 10100 (-3 × 22 = -12)
• A >>> N = A ÷ 2N
• Example: 01000 >>> 2 = 00010 (8 ÷ 22 = 2)
• Example: 10000 >>> 2 = 11100 (-16 ÷ 22 = -4)

Multipliers
• Partial products formed by multiplying a single digit of the
multiplier with multiplicand
• Shifted partial products summed to form result

4 x 4 Multiplier
A B
4 4
x
8
A3 A2 A1 A0
P
B0
B1
0
A3 A2 A1 A0 0
x B3 B2 B1 B0 B2
A3B0 A2B0 A1B0 A0B0
A3B1 A2B1 A1B1 A0B1 0
B3
A3B2 A2B2 A1B2 A0B2
+ A3B3 A2B3 A1B3 A0B3
0
P7 P6 P5 P4 P3 P2 P1 P0
P7 P6 P5 P4 P3 P2 P1 P0

Dividers
A/B = Q + R/B
Decimal Example: 2584/15 = 172 R4
Long-Hand: Long-Hand Revisited:

Dividers
A/B = Q + R/B
Decimal: 2584/15 = 172 R4 Binary: 1101/0010 = 0110 R1

Divider Algorithm
A/B = Q + R/B
Binary: 1101/10 = 0110 R1
R’ = 0
for i = N-1 to 0
R = {R’ << 1, Ai}
D=R-B
if D < 0, Qi= 0; R’= R
else Qi= 1; R’= D
R=R’

4 x 4 Divider
Legend
R B
R B
Cout Cin Cout Cin
+
D
D
N R'
0
N
R'
Division: A/B = Q + R/B
R’ = 0
for i = N-1 to 0
R = {R’ << 1, Ai}
D=R-B
if D < 0, Qi=0, R’=R
else Qi=1, R’=D
Each row computes one iteration of the division algorithm.
R=R’
4 x 4 Divider
Legend
R B
R B
Cout Cin Cout Cin
+
D
D
N R'
0
N
R'
Each row computes one iteration of the division algorithm.

Design a circuit to multiply a number by 3

Design a circuit to multiply a number by 3

Binary Coded Decimal

computation
107

BCD Number conversion
• Convert a Binary Number to BCD:
• Rigorous Method:
– Find Truth Table
– Simplify Logic

BCD Conversion: Truth Table & SOP
Binary Code Decimal BCD Code
Number
A B C D B4 :B3 B2 B1 B0
0 0 0 0 0 0 : 0 0 0 0
0 0 0 1 1 0 : 0 0 0 1
0 0 1 0 2 0 : 0 0 1 0
0 0 1 1 3 0 : 0 0 1 1
0 1 0 0 4 0 : 0 1 0 0
0 1 0 1 5 0 : 0 1 0 1
0 1 1 0 6 0 : 0 1 1 0
0 1 1 1 7 0 : 0 1 1 1
1 0 0 0 8 0 : 1 0 0 0
1 0 0 1 9 0 : 1 0 0 1
1 0 1 0 10 1 : 0 0 0 0
1 0 1 1 11 1 : 0 0 0 1
1 1 0 0 12 1 : 0 0 1 0
1 1 0 1 13 1 : 0 0 1 1
1 1 1 0 14 1 : 0 1 0 0
1 1 1 1 15 1 : 0 1 0 1
https://www.javatpoint.com/binary-to-bcd-conversion-in-digital-electronics
BCD Conversion: Truth Table & SOP

Department of EEE, BUET https://www.javatpoint.com/binary-to-bcd-conversion-in-digital-electronics
BCD Number conversion
Binary Code Decimal BCD Code
• Convert a Binary Number to BCD: A B C D
Number
B4 :B3 B2 B1 B0
• Rigorous Method: 0 0 0 0 0 0 : 0 0 0 0
– Find Truth Table 0 0 0 1 1 0 : 0 0 0 1
– Simplify Logic 0 0 1 0 2 0 : 0 0 1 0
0 0 1 1 3 0 : 0 0 1 1
• Observation: 0 1 0 0 4 0 : 0 1 0 0
0 1 0 1 5 0 : 0 1 0 1
0 1 1 0 6 0 : 0 1 1 0
0 1 1 1 7 0 : 0 1 1 1
1 0 0 0 8 0 : 1 0 0 0
1 0 0 1 9 0 : 1 0 0 1
Add 6 to a 4 bit binary 1 0 1 0 10 1 : 0 0 0 0
number to get its BCD 1010+0110
1 0 1 1 11 1 : 0 0 0 1
1 1 0 0 12 1 : 0 0 1 0
1011+0110
1 1 0 1 13 1 : 0 0 1 1
1 1 1 0 14 1 : 0 1 0 0
1 1 1 1 15 1 : 0 1 0 1

Addition

Schematic

Verilog code for BCD addition

BCD Conversion Compact Circuit

Verilog code for BCD Addition


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EEE 303 – Digital Electronics

EEE ALU Design

Dr. Sajid Muhaimin Choudhury, Assistant Professor

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 3

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 4

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 5

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 7

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 11

Cout Cout Cin

A B Cout S Cin A B Cout S

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 13

• Chain 1-bit adders together

where tFA is the delay of a 1-bit full adder

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 15

The technique can be exploited to predict carry a priori

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 17

Compute Cout for k-bit blocks using generate and

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 18

Ci = Ai Bi + (Ai + Bi )Ci-1 = Gi + Pi Ci-1

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G3:0 = G3 + G2P3 + G1P2P3 + G0P1P2P3

G3:0 = G3 + G2P3 + G1P2P3 + G0P1P2P3

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S31:28 S27:24 S7:4 S3:0

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– tpg : delay to generate all Pi, Gi

An N-bit carry-lookahead adder is generally much faster than

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• Ripple Carry adder:

• As a designer, you need to choose the appropriate

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Dr. Sajid Muhaimin Choudhury, Assistant Professor

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• If n bits are used to represent signed numbers, then the

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303 Adders, Subtractor

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module fulladd (Cin, x, y, s, Cout);

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module fulladd (Cin, x, y, s, Cout);

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 Generates sub-circuits using a loop

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S omits the MSB

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Sum requires extra