COMPUTER ORGANIZATION AND ARCHITECTURE

MOD U LE- 3 PART TWO

- LIPSA SUBHADARSHINI

Subject Code- BC 2007

No. of Credits- 4
BCA 3rd Semester

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 C O N T E N T

• Computer Arithmetic
• Multiplication Algorithms for fixed point numbers
• Division Algorithms for fixed point numbers

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 M U LT I P L I C AT I O N A L G O R I T H M

• Multiplication of two fixed point binary number in signed magnitude representation is done with process
of successive shift and add operation.

• In the multiplication process we are considering successive bits of the multiplier, least significant bit first.
If the multiplier bit is 1, the multiplicand is copied down else 0’s are copied down.
• The numbers copied down in successive lines are shifted one position to the left from the previous number.
Finally numbers are added and their sum form the product.
• The sign of the product is determined from the sign of the multiplicand and multiplier. If they are alike, sign of the
product is positive else negative.
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Hardware Implementation

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 M U LT I P L I C AT I O N A L G O R I T H M

• Registers:
Two Registers B and Q are used to store multiplicand and multiplier respectively.
Register A is used to store partial product during multiplication.
Sequence Counter register (SC) is used to store number of bits in the multiplier.
• Flip Flop:
To store sign bit of registers we require three flip flops (A sign, B sign and Q sign).
Flip flop E is used to store carry bit generated during partial product addition.
• Complement and Parallel adder:
This hardware unit is used in calculating partial product i.e, perform addition required.
Flowchart of Multiplication
• Initially multiplicand is stored in B register and multiplier is stored in Q register.
• Sign of registers B (Bs) and Q (Qs) are compared using XOR functionality (i.e., if both the signs are alike, output
of XOR operation is 0 unless 1) and output stored in As (sign of A register).Note: Initially 0 is assigned to register
A and E flip flop. Sequence counter is initialized with value n, n is the number of bits in the Multiplier.

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 M U LT I P L I C AT I O N A L G O R I T H M

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 M U LT I P L I C AT I O N A L G O R I T H M

• Now least significant bit of multiplier is checked. If it is 1 add the content of register A with Multiplicand (register
B) and result is assigned in A register with carry bit in flip flop E. Content of E A Q is shifted to right by one
position, i.e., content of E is shifted to most significant bit (MSB) of A and least significant bit of A is shifted to
most significant bit of Q.
• If Qn = 0, only shift right operation on content of E A Q is performed in a similar fashion.
• Content of Sequence counter is decremented by 1.
• Check the content of Sequence counter (SC), if it is 0, end the process and the final product is present in register A
and Q, else repeat the process.
Example:
Multiplicand = 10111
Multiplier = 10011

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 M U LT I P L I C AT I O N A L G O R I T H M

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 D I V I S I O N A L G O R I T H M

• The Division of two fixed-point binary numbers in the signed-magnitude representation is done by the cycle of
successive compare, shift, and subtract operations.
• The binary division is easier than the decimal division because the quotient digit is either 0 or 1. Also, there is no
need to estimate how many times the dividend or partial remainders adjust to the divisor.

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 D I V I S I O N A L G O R I T H M

HARDWARE IMPLEMENTATION
• The hardware implementation in the division operation is identical to that required for multiplication and consists of the following
components –
• Here, Registers B is used to store divisor, and the double-length dividend is stored in registers A and Q
• The information for the relative magnitude is given in E.
• A sequence Counter register (SC) is used to store the number of bits in the dividend.

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 D I V I S I O N A L G O R I T H M

FLOWCHART

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 D I V I S I O N A L G O R I T H M

• Initially, the dividend is in A & Q and the divisor is in B.

• The sign of the result is transferred into Q, to be part of the quotient. Then a constant is set into the SC to specify
the number of bits in the quotient.
• Since an operand must be saved with its sign, one bit of the word will be inhabited by the sign, and the magnitude
will be composed of n -1 bits.
• The condition of divide-overflow is checked by subtracting the divisor in B from the half of the bits of the dividend
stored in A. If A ≥ B, DVF is set and the operation is terminated before time. If A < B, no overflow condition occurs
and so the value of the dividend is reinstated by adding B to A.
• The division of the magnitudes starts with the dividend in AQ to left in the high-order bit shifted into E. 
(Note – If shifted a bit into E is equal to 1, and we know that EA > B as EA comprises a 1 followed by n -1 bits
whereas B comprises only n -1 bits). In this case, B must be subtracted from EA, and 1 should insert into Q, for the
quotient bit.
• If the shift-left operation (shl) inserts a 0 into E, the divisor is subtracted by adding its 2’s complement value and
the carry is moved into E. If E = 1, it means that A ≥ B; thus, Q, is set to 1. If E = 0, it means that A < B, and the
original number is reimposed by adding B into A.
• Now, this process is repeated with register A containing the partial remainder.

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 D I V I S I O N A L G O R I T H M

Example of a binary division using digital hardware:

Divisor B = 10001, Dividend A = 0111000000
Final Remainder: 00110
Final Quotient: 11010
Now, what if the divisor is greater than or equal to the
dividend. In this process, division overflow occurs. EA
stores the value of A+B, there is no application of Q here as
if the divisor is equal to dividend then Q might 1 and
remainder is 0, else in every other condition the value of
quotient 1 and remainder equals to the dividend.

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