Understanding and improving

the metastability of D Flip

Flop
Presented by : Kandivalasa Ravi Teja (22ECE2005)
Under the guidance : Dr.Pragati Patel
Contents:

• Setup Time
• Hold Time
• Metastability
• Different Architectures of D flip flop
• Project idea
• Progress
 • The required time duration that the input data MUST be
Setup Time: stable before the triggering-edge of the clock.

Figure 1 : Setup time wave form[2]

 • The minimum amount of time required for the input to a
Hold Time: Flip-Flop to be stable after a clock edge.

Figure 2 : Hold time wave form [2]

Metastability:

• When there is setup and hold

time violations in a flip-flop, it
enters a state in which its output
is unpredictable, this is known as
a metastable state .

Figure 3 : Metastability Condition[3]

Different Architectures of D flipflop:

Sense
Static D Flip Dynamic D
Amplifier D
Flop Flip Flop
Flip Flop
Project Idea:
• Improving metastability by calculating setup and hold time with
different architectures.[1]
Progress: Simulated the D flip flop and calculated Setup time and
Hold Time.

Setup Time: Hold Time:

Figure 4 : simulation results

 References:
• [1] P. Parekh, F. Yuan and Y. Zhou, "Area/Power-Efficient True-Single-
Phase-Clock D-Flipflops with Improved Metastability," 2020 IEEE 63rd
International Midwest Symposium on Circuits and Systems (MWSCAS),
Springfield, MA, USA, 2020, pp. 182-185, doi:
10.1109/MWSCAS48704.2020.9184567.
• [2]
https://www.icdesigntips.com/2
020/10/setup-and-hold-time-ex
plained.html
• [3]
https://toshiba.semicon-storage.
com/kr/semiconductor/knowled
ge/e-learning/cmos-logic-usage-
considerations/usage-11.html