Unit - 2 - Fundamentals of Digital Electronics

Introduction to Electronics
Engineering
Dept. of Electronics and Telecommunication

UNIT-III
FUNDAMENTALS OF DIGITAL ELECTRONICS
Dept. of Electronics and Telecommunication November 29, 202 2

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T4- Modern Digital Electronics, by R. P. Jain, MGH Publication, 4th Edition
Text book /
Points Page no Remark LECTURES
Ref. Book
Introduction T4 2
Digital Signals T4 2,3 Positive & negative logic L20

Basic digital circuits- AND, OR, NOT,
T4 3-14
NAND, NOR, EXOR
Boolean algebra T4 14-20 De Morgans theorem TUT-2(online practice)
Examples of logic IC gates T4 3-14

Standard representation of logic
T4 165-173 SOP & POS form
function
Multiplexers, T4 200 Select line, tree, 8:1 using 4:1
Demultiplexes T4 238 mux, applications TUT-4
Block, truth table. Present state,

Flip Flops: 1-bit memory cell, T4 279-289 L22
next state.Edge &level triggered
iShift Registers T4 312-318
Asynchronous Counters
T4 321-322

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 Digital Electronics
• Digital Electronics represents information (0, 1) with only two discrete values.
• Ideally
“no voltage” (e.g., 0v) represents a 0 and
“full source voltage” (e.g., 5v) represents a 1
• Realistically
“low voltage” (e.g., <1v) represents a 0 and
“high voltage” (e.g., >4v) represents a 1
• We achieve these discrete values by using transistor switches.
• Transistor switches, operate at high speed, electronically and are small in size.

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Binary Logic and Logic Levels
• For example 0V represents Logic 0 and +5V represents Logic 1.
• Positive Logic:-
Logic 0 (Low) = 0V
Logic 1 (High) = +5V
• Negative Logic:-
Logic 0(low) = +5V
Logic 1 (High) = 0V

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 Logic Levels
Positive Logic levels

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 Analog versus Digital
• Analog systems process time-varying signals that can take on any value across a
continuous range of voltages (in electrical/electronics systems).
• Digital systems process time-varying signals that can take on only one of two
discrete values of voltages (in electrical/electronics systems).
– Discrete values are called 1 and 0 (ON and OFF, HIGH and LOW, TRUE and
FALSE, etc.)
• Digital Devices
– Gates
– Flip-Flops
– PLDs
– FPGAs

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 Gates
• It is very basic building block of a digital circuit.
• Function of Gate is to allow or block (gating) the flow of digital information.
• A gate has one or more inputs and produces an output depending on the input(s).
• Three most important gates are: AND, OR, NOT
Logic Gates
Basic Gates Universal Gates Derived Gates
1. NOT 1. NAND 1. EX-OR

2. AND
2. NOR 2. EX-NOR
November 29, 202 8
3. OR 3
 Gates

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3
3
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Boolean Laws
Sr. Name Statement of the law
No.
1. Commutative Law A.B = B.A

A +B = B+A
2. Associative Law (A.B).C = A. (B.C)

(A+B)+C = A+(B+C)
3. Distributive Law A.(B +C) = AB +AC

4. Inversion Law A̿ = A
5. AND Laws A.0 =0
A.1 = A
A.A= A
A.A̅ = 0
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Continued…
Sr. Name Statement of the law
No.
6. OR Laws A +0 = A
A +1 = 1
A + A= A
A + A̅ = 1
7. Other Important Laws A+BC = (A +B) (A +C)
A̅ + AB = A̅ + B
A̅ + AB̅ = A̅ + B̅
A + AB = A
A + A̅B = A+B

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 Logic and Boolean Algebra
George Boole
1815-1864

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DeMorgan’s Theorem #1
A · B = A + B NAND = Bubbled OR
A B AB AB A B A+B

0 0 0 1 1 1 1
0 1 0 1 1 0 1
1 0 0 1 0 1 1
1 1 1 0 0 0 0
EQUAL
A · B = A + B
A
B
=
Invert output of an AND gate Invert the inputs of an OR gate

A + B = A · B NOR = Bubbled AND
A B A+B A+B A B A.B

0 0 0 1 1 1 1
0 1 1 0 1 0 0
1 0 1 0 0 1 0
1 1 1 0 0 0 0
EQUAL
A + B = A · B
A A
B
= B
Invert output of an OR gate Invert the inputs of an AND gate

 NAND & NOR Gate

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Represent Basic Gates Using NAND Gate
1. NOT Gate:-
Input = A = B =A
So Output :-
Y = A. B = A. A = A̅

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Continued…
2. AND Gate
• Y = A. B ……AND Gate
Y = A.B …….Double Inversion

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Continued…
3. OR Gate
Y = A + B …………OR Gate
Y = A + B …........Double Inversion
Y = A̅ . B̅ ………… De Morgan’s Law

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Represent Basic Gates Using NOR Gate
1. NOT Gate
Input = A= B= A
Output :-
Y= A + B = A + A = A̅

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2. AND Gate
Y= A . B = A. B
Y= A̅ + B̅

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3. OR Gate
Y= A + B= A+ B

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 Universal Gates: NAND and NOR

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 Universal Gates: NAND and NOR

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Example
• Square wave is applied as one of the input to a gate. Second
input of the gate is connected to a ground. Draw the output
waveform if the gate is
1. OR
2. NAND
3. EX-OR

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 Combinational Logic Circuit
• Gates are combined into circuits by using the output of one gate as the
input for another
AND
OR
AND
• Because there are three inputs to this circuit, eight rows are required to describe all
possible input combinations
• This same circuit represented using Boolean algebra:
X = (AB + AC)
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 Now let’s go the other way;
let’s take a Boolean expression and draw
• Consider the following Boolean expression: A.(B + C)

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 Now let’s go the other way;
let’s take a Boolean expression and draw
• Consider the following Boolean expression: A(B + C)
• Now compare the final result column in this truth table to the truth table for
the previous example
• They are identical
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Logic Circuits
Sequential Combinational
Circuits Circuits
• Adders
• Flip-flips • Decoder
• Counters • Comparators
• Shift Registers • Multiplexers &
• Demultiplexers
• Digital systems may be divided into two broad categories:
– Combinational Logic
• where the outputs are determined by the current states of the inputs.
• Does not depends on the order or sequence.
– Sequential Logic
• where the outputs are determined by the order or sequence of applying

inputs and the previous inputs.
 Combinational Logic Circuit
• Combinational logic circuits have no feedback, and any changes to the signals being applied to
their inputs will immediately have an effect at the output.
• It has no “memory”, “timing” or “feedback loops”.
• The three main ways of specifying the function of a combinational logic circuit are:
– Boolean Algebra – This forms the algebraic expression showing the operation of the logic circuit for each
input variable either True or False that results in a logic “1” output.
– Truth Table – A truth table defines the function of a logic gate by providing a concise list that shows all the
output states in tabular form for each possible combination of input variable that the gate could encounter.
– Logic Diagram – This is a graphical representation of a logic circuit that shows the wiring and connections of
each individual logic gate, represented by a specific graphical symbol, that implements the logic circuit.

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 Common Terminology
• Literal
– The appearance of a variable or its complement
• Product Term
– One or more literals connected by AND operators
• Sum Term
– One or more literals connected by OR operators

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 Common Terminology (cont.…)

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 Minterms, Maxterms & Truth Table
• There is a close correspondence between the truth table and minterms and maxterms
• A minterm is a product term that is 1 in exactly one row of the truth table
• Similarly (by duality) a maxterm is a sum term that is 0 in exactly one row of the truth
table
• An n-variable minterm can be represented by an n-bit integer. Thus, we can use mi to
denote the minterm corresponding row i of the truth table.
• For maxterm i (Mi), if the bit in the binary representation of i is 1, the corresponding
variable is complemented

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 Minterms, Maxterms & Truth Table
Row No. ABC Minterms Maxterms
0 000 A'B'C' = m0 A + B + C = M0
1 001 A'B'C = m1 A + B + C' = M1
2 010 A'BC' = m2 A + B' + C = M2
3 011 A'BC = m3 A + B' + C' = M3
4 100 AB'C' = m4 A' + B + C = M4
5 101 AB'C = m5 A' + B + C' = M5
6 110 ABC' = m6 A' + B' + C = M6
7 111 ABC = m7 A' + B' + C' = M7

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 EXAMPLE

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Continued…
• f(A,B,C) = + + + + + =
f(A,B,C) = Σ m(0,1,3,4,6,7) = ∏M (2,5)
• f(A,B,C) = Σ m(3,5,7)
Then f(A,B,C) = ∏M ( )

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K-map Representation of Logic Functions

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Representation of SOP on K-Map
43

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3

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Grouping cells for simplification
47
 Half Adder
• A half-adder is an arithmetic circuit block that can be used to add two bits. Such
a circuit thus has two inputs that represent the two bits to be added and two
outputs, with one producing the SUM output and the other producing the
CARRY.
• Adding two single-bit binary values A, B produces a sum S bit and a carry C bit.
A
S
Half C
B
Adder

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 Half Adder Truth Table
Input Output
A B SUM CARRY Sum = S = ?
0 0 0 0
0 1 1 0 Carry = C = ?
1 0 1 0
1 1 0 1

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 Half Adder
Input Output
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

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 Full Adder
• A full adder circuit is an arithmetic circuit block that can be used to add three bits to
produce a SUM and a CARRY output.
• Such a building block is needed in order to add binary numbers with a large number of
bits.
• The full adder circuit overcomes the limitation of the half-adder, which can be used to
add two bits only
S
A
B
Full Cout
Cin Adder

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 Full Adder
Inputs Outputs
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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Full Adder Sum S
A’B’Cin
Bcin
A 00 01 11 10
0 1 3 2 A’BCin’
Full Adder Truth Table 0 1 1

4 5 7 6
1 1 1
Inputs Outputs
AB’Cin’
A B Cin S Cout ABCin
0 0 0 0 0 S = A’B’(Cin) + A’B(Cin)’ + AB(Cin) + AB’(Cin)’
0 0 1 1 0 S = A Å B Å (Cin)
0 1 0 1 0 Carry C-out
0 1 1 0 1 BCin
BCin
1 0 0 1 0 A 00 01 11 10
0 1 3 2
1 0 1 0 1 0 1
1 1 0 0 1 1 4 5 7 6
1 1 1
1 1 1 1 1
ACin AB
S(A,B, Cin) = S (1,2,4,7)
Cout = AB + A(Cin) + B(Cin)
Cout(A, B, Cin) = S (3,5,6,7)
 Full Adder
Inputs Outputs
A B Cin S Cout S = m(1,2,4,7)

0 0 0 0 0
0 0 1 1 0 C = m(3,5,6,7)
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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 Full Adder
Inputs Outputs
A B Cin S Cout S = m(1,2,4,7)

0 0 0 0 0
0 0 1 1 0 C = m(3,5,6,7)
0 1 0 1 0
0 1 1 0 1 Using K-map, simplified SOP form is:
1 0 0 1 0 C = AB + BCin + ACin
S = A‘B‘C in+ A‘BCin'+AB‘C‘in+ABCin
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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 Representation of Full Adder by using Half
Adder
Inputs Outputs
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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 Multiplexers (Data Selectors)
• A multiplexer (MUX) selects one of multiple input signals and passes it to the output.
• The basic two input multiplexer
• The four input multiplexer
• The eight input multiplexer
• And so on….

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Continued…
• Multiplexing is the generic term used to describe the operation
of sending one or more analogue or digital signals over a
common transmission line at different times or speeds and as
such,
• The device we use to do just that is called a Multiplexer.

Continued…
• A combinational logic circuit designed to switch one of several
input lines through to a single common output line by the
application of a control signal.
• Multiplexers operate like very fast acting multiple position

rotary switches connecting or controlling multiple input lines
called “channels” one at a time to the output.
• Many to one circuit

Continued…
• They are used as one method of reducing the number of logic

gates required in a circuit design or when a single data line or data
bus is required to carry two or more different digital signals. For
example, a single 8-channel multiplexer.
• The selection of each input line in a multiplexer is controlled by

an additional set of inputs called control lines and according to the
binary condition of these control inputs, either “HIGH” or “LOW”
the appropriate data input is connected directly to the output.
 Continued…
A multiplexer (MUX) selects
1 out of N input data
sources and transmits the
selected data to a single
output.
• n inputs
m select inputs
One output
• n = 2^m

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 2:1 MUX

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4:1 MUX
Enable Select Input Output

E S1 S0 Y
1 0 0 D0
1 0 1 D1
1 1 0 D2
1 1 1 D3
8:1 MUX
Enable Select Lines Ourput
E S2 S1 S0 Y
1 0 0 0 D0
1 0 0 1 D1
1 0 1 0 D2
1 0 1 1 D3
1 1 0 0 D4
1 1 0 1 D5
1 1 1 0 D6
1 1 1 1 D7
 Typical Application of a MUX
Multiple Selector Single
Sources Destination
MP3 Player
Docking Station
D0
Laptop
MUX
D1
Sound Card Y
D2
D3
Surround Sound System
Digital B A Selected Source

Satellite
0 0 MP3
0 1 Laptop
1 0 Satellite
Digital
1 1 Cable TV
Cable TV
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 What is a Demultiplexer (DEMUX)?
• A DEMUX is a digital switch with a
single input (source) and a multiple Demultiplexer
outputs (destinations). Block Diagram
• The select lines determine which

output the input is connected to. 2m
DEMUX
1
• DEMUX Types Input Outputs
(source) (destinations)
– 1-to-2 (1 select line)
– 1-to-4 (2 select lines) m
– 1-to-8 (3 select lines)
Select
– 1-to-16 (4 select lines) Lines

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1:2 Demultiplexer
Enable Select Output
E S Y1 Y0
0 X 0 0
1 0 0 Din
1 1 Din 0

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 1-to-4 De-Multiplexer (DEMUX)
Enable Data Select Outputs
input inputs
E Din S1 S0 Y3 Y2 Y1 Y0
1 Din 0 0 0 0 0 Din
1 Din 0 1 0 0 Din 0
Ena 1 Din 1 0 0 Din 0 0

ble
E
1 Din 1 1 Din 0 0 0

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1:8 De-Multiplexer (DEMUX)
Enable Data Select inputs Outputs
input
E Din S2 S1 S0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
1 Din 0 0 0 0 0 0 0 0 0 0 Din
1 Din 0 0 1 0 0 0 0 0 0 Din 0
1 Din 0 1 0 0 0 0 0 0 Din 0 0
1 Din 0 1 1 0 0 0 0 Din 0 0 0
1 Din 1 0 0 0 0 0 Din 0 0 0 0
1 Din 1 0 1 0 0 Din 0 0 0 0 0
1 Din 1 1 0 0 Din 0 0 0 0 0 0
1 Din 1 1 1 Din 0 0 0 0 0 0 0
November 29, 202 70

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 Typical Application of a DEMUX
Single Source Selector Multiple
Destinations
B/W Laser
Printer
Fax
Machine
D0
DEMUX
X D1
D2 Color Inkjet
Printer
D3
B A Selected Destination
0 0 B/W Laser Printer Pen
0 1 Fax Machine Plotter
1 0 Color Inkjet Printer

1 1 Pen Plotter

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 Sequential Logic Circuit
• Sequential logic is a type of logic circuit whose output depends not only on the present
value of its input signals but on the sequence of past inputs, the input history.
• Sequential logic is combinational logic with memory.

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 Flip-Flop
• A basic sequential circuit is a flip-flop
• Flip-flop has two stable states of complementary output values
• One Flip Flop can store one bit of data.
• Two output can not be same
Q
Flip-Flop
Clock

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Clock Signal
• It is a timing signal
• It is a rectangular signal with duty cycle equal to 50% that’s
means its on time is equal to off time.

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 SR Flip-Flop
• It is basically S-R latch using NAND gates with an additional enable input.
• It is also called as level triggered SR-FF. For this, circuit change in output will take place
if and only if the enable input (E) is made active.
• In short this circuit will operate as an S-R latch if E = 1 but there is no change in the
output if E = 0.
• Block diagram

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 SR Flip-Flop

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 SR Operation
S.N. Condition Operation
1 S = R = 0 : No change If S = R = 0 then output of NAND gates 3 and 4 are forced to become
1.
Hence R' and S' both will be equal to 1. Since S' and R' are the input
of the basic S-R latch using NAND gates, there will be no change in
the state of outputs.
2 S = 0, R = 1, E = 1 Since S = 0, output of NAND-3 i.e. R' = 1 and E = 1 the output of
NAND-4 i.e. S' = 0.
Hence Qn+1 = 0 and Qn+1 bar = 1. This is reset condition.
3 S = 1, R = 0, E = 1 Output of NAND-3 i.e. R' = 0 and output of NAND-4 i.e. S' = 1.

Hence output of S-R NAND latch is Qn+1 = 1 and Qn+1 bar = 0. This is
the set condition.
4 S = 1, R = 1, E = 1 As S = 1, R = 1 and E = 1, the output of NAND gates 3 and 4 both are

0 i.e. S' = R' = 0.
Hence the Race condition will occur in the basic NAND latch.

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 Delay Flip Flop / D Flip Flop
• Delay Flip Flop or D Flip Flop is the simple gated S-R latch with a NAND inverter connected
between S and R inputs. It has only one input.
• The input data is appearing at the output after some time. Due to this data delay between i/p and
o/p, it is called delay flip flop.

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 Operation of D Flip-Flop
1 E=0 Latch is disabled. Hence no change in output.
2 E = 1 and D = 0 If E = 1 and D = 0 then S = 0 and R = 1. Hence

irrespective of the present state, the next state is Qn+1 =
0 and Qn+1 bar = 1. This is the reset condition.
3 E = 1 and D = 1 If E = 1 and D = 1, then S = 1 and R = 0. This will set the

latch and Qn+1 = 1 and Qn+1 bar = 0 irrespective of the
present state.

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 JK Flip Flop
The JK flip-flop is basically an SR flip flop with feedback.
S = J. Q
R = K. Q

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Truth Table of J-K flip- flop
Data inputs Outputs Input to S-R flip-flop Output
=. =
0 0 0 1 0 0 0
0 0 1 0 0 0 1
= Qn
1 0 0 1 1 0 1
1 0 1 0 0 0 1
0 1 0 1 0 0 0 =1
0 1 1 0 0 1 0
1 1 0 1 1 0 1 =0
1 1 1 0 0 1 0
=

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J-K Flip-Flop Using NAND Gates
Jn Kn
0 0
1 0 1
0 1 0
1 1

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 Toggle Flip Flop / T Flip Flop
• Toggle flip flop is basically a JK flip flop with J and K terminals permanently connected
together.
• It has only input denoted by T

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 Operation of T Flip-Flop
1 T = 0, J = K = 0 The output Q and won't change.
2 T = 1, J = K = 1 Output will toggle corresponding to every leading edge

of clock signal.

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Shift registers
• A shift register is a cascade of flip flops
• In which the output of each flip-flop is connected to the "data" input

of the next flip-flop in the chain, resulting in a circuit that shifts by one
position the "bit array” stored in it,
• Shifting in the data present at its input and shifting out the last bit in the
array, at each transition of the clock input.
• Shift registers can have both parallel and serial inputs and outputs.
Continued…
• It is a temporary data storage device
• Uses 1 FF per bit, e.g.: 4 bit register uses 4 FF and can store 4 bits
• Can be used for Data storage & Data Transfer

 Shift Registers
• Shift Registers are devices that store and move data bits in serial (to the left or the
right),
• ..or in parallel,
• ..or a combination of serial and parallel.

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 Shift Registers
right),

3
 Shift Registers
right),

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 Shift Register Applications
• Shift Registers are an important Flip-Flop configuration with a wide range of
applications, including:
– Computer and Data Communications
– Serial and Parallel Communications
– Multi-bit number storage
– Sequencing
– Basic arithmetic such as scaling (a serial shift to the left or right will change the
value of a binary number a power of 2)
– Logical operations

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 Parallel versus Serial
• Serial communications: provides a binary number as a sequence of binary digits, one after
another, through one data line.
• Parallel communications: provides a binary number as binary digits through multiple data lines
at the same time.

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 Configuration
• In Shift Registers, the binary digit transfers (shifts) from the output of one flip-flop to
the input of the next individual Flip-Flop at every clock edge.
• Once the binary digits are shifted in, the individual Flip-Flops will retain a bit, and the
whole configuration will be stored as a binary number.

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 Construction
• Shift registers are constructed from flip-flops due to their characteristics:
– Edge-triggered devices
– Output state retention
• Each Flip-Flop in a shift register can retain one binary digit.
– For instance, if a 4-bit binary number needs to be stored and shifted, 4 flip-flops are
required.
• Each binary digit transfer operation requires a clock edge.
• Asynchronous inputs are useful in resetting the whole configuration.

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 Shift Register Construction
• Shift registers are comprised of D Flip-Flops that share a common clock input.
D Q D Q D Q

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Data Transfer Methods/ Modes
1. Serial input- Serial output [SISO]
2. Serial input- Parallel output [SIPO]
3. Parallel input- Parallel output [PIPO]
4. Parallel input- Serial output [PISO]

There are also 'bidirectional' shift registers which allow
shifting in both directions: L→R or R→L
 Data Transfer Methods/ Modes
• SISO: Serial In, Serial Out
10110 10110
• SIPO: Serial In, Parallel Out
• PISO: Parallel In, Serial Out
• PIPO: Parallel In, Parallel Out

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10110 10110
• SIPO: Serial In, Parallel Out 10110
10110

3
10110 10110
10110
10110
10110

3
10110 10110
10110
10110
10110
10110
10110
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 Serial-in/Serial out Shift Register
• 5-bit serial in/serial out shift register implemented with D flip-flops.
FF0 FF1 FF2 FF3 FF4

Serial 1 1 1 1 1 1 Serial
data D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 data
input output
C C C C C
CLK
CLK
100
Siso [shift right]
CLK Din= Q3=D2 Q2=D1 Q1=D0 Q0

D3
Initially 0 0 0 0
1st 1 1 0 0 0
2nd 1 1 1 0 0
3rd 1 1 1 1 0
4th 1 1 1 1 1
 SIPO Flip-Flop Shift Register
• a Serial In Parallel Out shift register has a single input and access to all outputs
Output Output Output
Input D Q D Q D Q
Q Q Q

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 Parallel In/Serial Out Shift Registers
• Shift registers can be used to convert parallel data to serial form.
D0 D1 D2 D3
SHIFT/LOAD
G1 G5 G2 G6 G3 G7 G4
Serial data
D D D D
Q0 Q1 Q2 Q3 out
C C C C
FF0 FF1 FF2 FF3

CLK
Dept. of Electronics and Telecommunication 103
 PIPO Flip-Flop Shift Register
• a Parallel In Parallel Out register has the simplest configuration. It represents a memory
device.
Input Input Input
D Q D Q D Q
Q Q Q
Output Output Output

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 Universal Shift Registers
• Universal Shift Registers can be configured to operate in a variety of modes. For
instance, they can be configured to have either Serial or Parallel Input/Output.
• Internally use steering gates to determine: ??

– Serial input/output direction
– Parallel input (load)
– Hold

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Counters
• Sequential circuit
• Counting pulses
• Group of flip-flops with clock signal applied
• Count the number of clocks

types
Counters
Synchronous Asynchronous
All FF receive the external clk External clock signal is applied

pulse to 1FF, & then o/p of preceding
FF is connected to the clk of
next FF
classification
Counters
Up Counters Down Counters Up/Down

Counters
 Counters
• Counters are circuits that cycle through a specified number of states.
• Two types of counters:
– synchronous (parallel) counters
– asynchronous (ripple) counters
• Ripple counters allow some flip-flop outputs to be used as a source of clock for other
flip-flops.
• Synchronous counters apply the same clock to all flip-flops.

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 Asynchronous (Ripple) Counters
• Asynchronous counters: the flip-flops do not change states at exactly the same time as
they do not have a common clock pulse.
• Also known as ripple counters, as the input clock pulse “ripples” through the counter –
cumulative delay is a drawback.
• n flip-flops -> a MOD (modulus) 2n counter.
– (Note: A MOD-x counter cycles through x states.)
• Output of the last flip-flop (MSB) divides the input clock frequency by the MOD number
of the counter, hence a counter is also a frequency divider.

3
 Asynchronous (Ripple) Counters
• Example: 2-bit ripple binary counter.
• Output of one flip-flop is connected to the clock input of the next more-significant flip-
flop.
CLK 1 2 3 4 HIGH
Q0 J Q0 J Q1
CLK C C
Q0
Q0 0 1 0 1 0 K K
FF0 FF1
Q1 0 0 1 1 0
Timing diagram
00  01  10  11  00 ...

3
 Asynchronous Down Counters
• Example: A 2-bit binary (MOD-4) down counter.

3
 Ring Counter
• A ring counter takes the serial output of the last Flip-Flop of a shift register and provides it to
the serial input of the first Flip-Flop.
• Ring Counters are also known as re-circulating shift registers.
• The display characteristics will be familiar…

3
 Ring Counter

3
 Ring Counter
 A common pattern for a ring counter is to load it with a single 1 or a single 0. The waveforms
shown here are for an 8-bit ring counter with a single 1.
CLK 1 2 3 4 5 6 7 8 9 10
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
115
Thank You…
Q&A

3
Few problems based on Boolean expressions to be
covered in the class or give for practice
Think and Share group activity on

• designing of SISO/PISO
• or digital IC design
• Or ripple counters design..etc
• Additional links
• Lecture series on Digital Circuits & Systems by
Prof.S.Srinivasan, Department of Electrical
Engineering, IIT Madras.For more details on NPTEL
visit http://nptel.ac.in
3

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Introduction to Electronics

Dept. of Electronics and Telecommunication

FUNDAMENTALS OF DIGITAL ELECTRONICS

Dept. of Electronics and Telecommunication November 29, 202 2

Digital Signals T4 2,3 Positive & negative logic L20

Boolean algebra T4 14-20 De Morgans theorem TUT-2(online practice)

Examples of logic IC gates T4 3-14

Block, truth table. Present state,

iShift Registers T4 312-318

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Basic Gates Universal Gates Derived Gates

1. NOT 1. NAND 1. EX-OR

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1. Commutative Law A.B = B.A

2. Associative Law (A.B).C = A. (B.C)

3. Distributive Law A.(B +C) = AB +AC

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Dept. of Electronics and Telecommunication November 29, 202 15

A B AB AB A B A+B

Invert output of an AND gate Invert the inputs of an OR gate

A B A+B A+B A B A.B

Invert output of an OR gate Invert the inputs of an AND gate

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• Does not depends on the order or sequence.

• where the outputs are determined by the order or sequence of applying

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Full Adder Truth Table 0 1 1

A B Cin S Cout S = m(1,2,4,7)

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A B Cin S Cout S = m(1,2,4,7)

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• The device we use to do just that is called a Multiplexer.