CLOCK TREE SYNTHESIS

Presented by:
Apoorva Jinal

Yesha Susmita
 CTS

❑ Clock Tree Synthesis is a process which makes sure that the clock gets
distributed evenly to all sequential elements in a design.
❑ CTS is the process of insertion of buffers or inverters along the clock
paths of ASIC design in order to achieve minimum skew or balanced
skew.
❑ In ICs, clock consumes around half of the total power consumption.

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 CTS

❑ CTS is the process of connecting the clocks to all clock pin of sequential
circuits by using inverters/buffers in order to balance the skew and to
minimize the insertion delay.
❑ All the clock pins are driven by a single clock source.

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 CTS Goals
– Max. Transition
– Max. Capacitance
– Max. Fanout
– Minimal skew
– Minimum insertion delay

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 Input files required in CTS

❑ Technology file(.tf)
❑ Netlist
❑ SDC
❑ TLU+ file
❑ Library files(.lib & .lef)
❑ Placement DEF file
❑ Clock specification file
❑ Buffer or inverters for building the clock tree
❑ The source of clock and all the sinks where the clock is going to feed

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 Clock tree SDC content
❑ SDC is a format used to specify the design intent, including the timing,
power and area constraints for a design.
Design Rule Constraint set_max_capacitance
set_min_capacitance
set_max_fanout
set_max_transition

Timing Constraint creat_clock

creat_generated_clock
set_clock_latency
set_clock_uncertainty

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 Crosstalk noise
❏ Noise refers to undesired or unintentional effect between two or more
signals that are going to affect the proper functionality of the chip.
❏ Glitch:
❏ When one net is switching and another net is constant then switching
signal may cause spikes on the other net because of coupling
capacitance.

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 Crosstalk delay
❏ When both nets are switching or in transition state then switching
signal at the victim may have some delay or advancement in the
transition due to coupling capacitance.
❏ It depends on switching direction of aggressor and victim nets.

❏ Types of crosstalk:
1. Positive crosstalk
2. Negative crosstalk

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 Positive crosstalk
❏ In this case, aggressor net has a rising transition and at the same time
victim net has a falling transition.
❏ Here switching is in opposite direction, so it increases the delay of the
victim.

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 Negative crosstalk
❏ In this case both the aggressor and victim nets have rising transition.
❏ Here switching is in same direction so it decreases the delay of the
victim.

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 Checklist before CTS
❑ Check power stripes, standard cell rails and verify PG connections
❑ High fanout nets such as scan enable, reset are synthesized with
buffers.
❑ The clock source is identified with the create_clock or
create_generated_clock commands.
❑ The placement of standard cells and optimization is done
❑ Congestion- acceptable
❑ Timing – acceptable
❑ Estimated max tran/cap – no violations

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 CTS flow

❏ Check macro locations

❏ Read CTS SDC
❏ Generate CTS specification file
❏ Compile CTS using CTS specification file
❏ Place clock tree
❏ Route clock tree (Optional)

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 Clock buffers and Normal buffers
❏ Clock buffers are designed with special properties such as equal rise and
fall time.
❏ In clock buffer, the size of PMOS is greater than NMOS.
❏ Normal buffers have not equal rise and fall time. Here size of PMOS/
NMOS don’t need to be in the ratio of 2:1.
❏ Normal buffers are smaller in size compared to clock buffers.
❏ Clock buffer ckt uses two inverters
connected back to back.

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 Clock Tree Optimization
❏ Buffer and Gate Sizing
❏ Buffer and Gate Relocation
❏ Level Adjustment
❏ Reconfiguration
❏ Delay Insertion
❏ Dummy Load Insertion

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 Buffer and Gate Sizing
❏ Sizes up or down buffers and gates to improve skew and insertion delay.

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 Buffer and Gate Relocation
❏ Physical location of the gate or buffer is moved to reduce skew and
insertion delay.

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 Level Adjustment
❏ Adjust the level of the clock pins to a higher or lower part of the clock
tree hierarchy.

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 Reconfiguration
❏ Clustering of sequential logic.
❏ After that buffer placement is performed.

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 Delay Insertion
❏ Delay is inserted for shortest paths.
❏ By adding new buffers to the clock path the clock tree hierarchy is
changed.

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 Dummy Load Insertion
❏ Uses load balancing to fine tune the clock skew by increasing the
shortest path delay.

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 Clock Tree Routing Algorithms
❑ H Tree
❑ X Tree
❑ Method of Mean and Median
❑ Recursive Geometric Matching Algorithms
❑ Pi Configuration

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 H-Tree
❏ This approach is based on the equalization of wire length.
❏ The distance from the clock source point to each of the clock sink points are
always same.
❏ As shown in figure, all the terminal points are exactly 7 units from the
reference point Po.

❏ Advantages:
● Exact zero skew in terms of distance due to
the symmetry of the H tree.
❏ Disadvantages:
● Blockages can spoil the symmetry of H tree.
● Non-uniform sink location complicates the design of the H tree.
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 X-tree
❏ In the X-tree based approach connections are not rectilinear.
❏ Due to close proximity of wires, it may cause crosstalk.

❏ Advantages:
● Better than H-tree algorithm
❏ Disadvantages:
● Crosstalk due to adjacent wires
● Clock routing is not rectilinear

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 Method of mean and median(MMM)
❏ Can handle sink location anywhere.
❏ It continuously partitions the set of terminals into two subsets of equal
parts.
❏ Then it connects center of mass of whole set to the center of masses of
the partitioned subsets.
❏ This algorithm ignores blockages and produces a non-rectilinear tree.

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Recursive geometric matching algorithm(RGM)
❏ The physical locations of sub-modules are not symmetric. Developing H-tree among
these sub-modules is practically not possible. At first two sub-modules are grouped
together and those trees are named as X-1, X-2, X-3 and X-4 (fig-4(B)). Then two
two-point trees are joined together to form a H like structure. The resultant H-trees
are named as X-12 and X-34 (fig-4(C)).
❏ As shown in fig-4(D), the tap points of both

the H structure cannot be connected by using

rectilinear nets and the resultant will be as
shown in fig-4(E).

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 Pi Configuration
❑ In Pi-config ,total number of buffers inserted along the clock path is
multiple of previous level.
❑ This type of structure uses the same number of buffers and geometrical
wires and relies on matching the delay components at each level of the
clock. Pi structure is considered to be balanced.
❑ Advantage: No crosstalk and min skew

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 Checklist after CTS
❑ Skew report
❑ Power and Area report
❑ Timing report for setup and hold
❑ clock tree report

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 Output of CTS

❑ Timing QoR report

❑ Congestion report
❑ Skew report
❑ Clock structure report
❑ CTS DEF file

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THANK YOU

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