Professor Dept. of Computer Science and Engineering Khulna University of Engineering & Technology (KUET) 1 Khulna 9203, Bangladesh Sequential Logic
Latches and Flip-Flops
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Sequential Logic Circuits
The output of sequential logic circuits
depends on the past history of the state of the outputs. Therefore, it incorporate a memory element (circuits must remember the past states of their outputs). Main characteristic of these circuits feedback An output logic level is treated just like another input to the circuit.
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Sequential Logic Circuits
Latches Flip-flops
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The S-R (SET-RESET) Latch
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The S-R (SET-RESET) Latch
Negative-OR equivalent of the NAND gate
\S-\R latch
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The S-R (SET-RESET) Latch
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The S-R (SET-RESET) Latch
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The S-R (SET-RESET) Latch
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An Application of Latch
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The Gated S-R Latch
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The Gated S-R Latch
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The Gated D Latch
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The Gated D Latch
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Flip-Flops
Flip-flops are synchronous bistable devices.
Synchronous means that the output changes state only at a specified point on the triggering input called the clock (CLK). Changes in the output occur in synchronization with the clock.
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Edge-Triggered FFs
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Edged-Triggered S-R FF
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Edged-Triggered S-R FF
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Edged-Triggered S-R FF
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Edge-Triggered D FF
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Edge-Triggered D FF
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Edge-Triggered JK-FF
JK-FF is versatile and is a widely used type
of flip-flop. The functioning of the JK-FF is identical to that of the SR-FF in the SET, RESET, and NC. The difference is that the JK-FF has NO invalid state as does the SR-FF.
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Edge-Triggered JK-FF
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Edge-Triggered JK-FF
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Edge-Triggered JK-FF
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Asynchronous Preset and Clear Inputs Most IC flip-flops have asynchronous inputs. These are inputs that affect the state of the FF independent of the clock. Preset (PRE) or direct set (SD) Clear (CLR) or direct reset (RD)
Logic symbol for a J-K flip-flop
active-LOW preset and clear inputs.
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Edge-triggered JK-FF with PRE and CLR Toggle mode example