Combinational Logic: Digital Integrated Circuits © Prentice Hall 1995

COMBINATIONAL LOGIC
Digital Integrated Circuits
Combinational Logic
Prentice Hall 1995
Overview
Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino np-CMOS
Combinational Logic
Prentice Hall 1995
Combinational vs. Sequential Logic

Logic In Circuit Out In Logic Circuit Out
State
(a) Combinational Output = f(In)

(b) Sequential Output = f(In, Previous In)
Combinational Logic
Prentice Hall 1995
Static CMOS Circuit

At every point in time (except during the switching transients) each gate output is connected to either VDD or Vss via a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.
Digital Integrated Circuits Combinational Logic Prentice Hall 1995
Static CMOS
VDD In1 In2 In3 PUN
PMOS Only
F=G
In1 In2 In3
PDN
NMOS Only
VSS
PUN and PDN are Dual Networks

NMOS Transistors in Series/Parallel Connection

Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high
A X A B Y Y = X if A and B
Y = X if A OR B
NMOS Transistors pass a strong 0 but a weak 1

PMOS Transistors in Series/Parallel Connection

PMOS switch closes when switch control input is low
A X A B Y = X if A AND B = A + B
Y = X if A OR B = AB
PMOS Transistors pass a strong 1 but a weak 0

Complementary CMOS Logic Style Construction (cont.)
Combinational Logic
Prentice Hall 1995
Example Gate: NAND
Combinational Logic
Prentice Hall 1995
Example Gate: NOR
Combinational Logic
Prentice Hall 1995
Example Gate: COMPLEX CMOS GATE

VDD B A C D
OUT = D + A(B+C)
A D B C
Combinational Logic
Prentice Hall 1995
4-input NAND Gate

Vdd
VDD In1 In2 In1 In2 In3 In4 Out
Out
In3 In4
GND
In1 In2 In3 In4
Standard Cell Layout Methodology
metal1
VDD Well
VSS Routing Channel signals polysilicon
Combinational Logic
Prentice Hall 1995
Two Versions of (a+b).c

VDD VDD
x GND GND a b c
(a) Input order {a c b}
(b) Input order {a b c}
Combinational Logic
Prentice Hall 1995
Logic Graph
VDD b j a x b c a i GND b j a PDN c x c i VDD x PUN
Combinational Logic
Prentice Hall 1995
Consistent Euler Path

x
c x i VDD
GND
{ a b c}
Example: x = ab+cd
x b x a GND (a) Logic graphs for (ab+cd) d c V DD x a GND (b) Euler Paths {a b c d} V DD d b x c V DD
x GND a b c d (c) stick diagram for ordering {a b c d}

Properties of Complementary CMOS Gates
High noise margins: VOH and VOL are at VDD and GND, respectively. No static power consumption: There never exists a direct path between VDD and VSS (GND) in steady-state mode. Comparable rise and fall times: (under the appropriate scaling conditions)
Combinational Logic
Prentice Hall 1995
Properties of Complementary CMOS Gates

High noise margins: VOH and VOL are at VDD and GND, respectively. No static power consumption: There never exists a direct path between VDD and VSS (GND) in steady-state mode. Comparable rise and fall times: (under the appropriate scaling conditions)
Combinational Logic
Prentice Hall 1995
Transistor Sizing
for symmetrical response (dc, ac) for performance
V DD B A 6 C D 6 F A D 1 B 2 C 2 2 12 12
Input Dependent Focus on worst-case
Combinational Logic
Prentice Hall 1995
Propagation Delay Analysis - The Switch Model

=
VDD Rp A A F Rn CL A Rn B Rn A (a) Inverter (b) 2-input NAND Rn A Rp B F CL A F Rn B CL Rp B Rp
RON
V DD
VDD Rp
(c) 2-input NOR
tp = 0.69 Ron CL (assuming that CL dominates!)
Combinational Logic
Prentice Hall 1995
What is the Value of Ron?
Combinational Logic
Prentice Hall 1995
Numerical Examples of Resistances for 1.2m CMOS
Combinational Logic
Prentice Hall 1995
Analysis of Propagation Delay

VDD Rp A Rn B Rn A 2-input NAND B F CL Rp
1. Assume Rn =Rp = resistance of minimum sized NMOS inverter 2. Determine Worst Case Input transition (Delay depends on input values) 3. Example: tpLH for 2input NAND - Worst case when only ONE PMOS Pulls up the output node - For 2 PMOS devices in parallel, the resistance is lower t pLH = 0.69Rp CL 4. Example: tpHL for 2input NAND - Worst case : TWO NMOS in series t pHL = 0.69(2R n)CL
Combinational Logic
Prentice Hall 1995
Design for Worst Case

V DD
V DD
1
A B
1
A
F CL
B 2 C D 2
4 4
2
B
2
A
A D 1 B
2 2C 2
Here it is assumed that Rp = Rn

Influence of Fan-In and Fan-Out on Delay

VDD A B C D Fan-Out: Number of Gates Connected 2 Gate Capacitances per Fan-Out
A B C D FanIn: Quadratic Term due to: 1. Resistance Increasing 2. Capacitance Increasing (tpHL )
tp = a1 FI + a2 FI 2 + a3 FO
tp as a function of Fan-In
4.0 3.0 tp (nsec) 2.0 1.0
linear
tpHL
quadratic
tp
tpLH 9
0.0
5 fan-in
AVOID LARGE FAN-IN GATES! (Typically not more than FI < 4)

Fast Complex Gate - Design Techniques

Transistor Sizing:
As long as Fan-out Capacitance dominates
Progressive Sizing:
Out InN MN CL M1 > M2 > M3 > MN In3 In2 In1 M3 M2 M1 C3 Distributed RC-line C2 C1
Can Reduce Delay with more than 30%!

Combinational Logic Prentice Hall 1995
Fast Complex Gate - Design Techniques (2)

Transistor Ordering
critical path CL critical path CL
In3
M3
In1
M1
In2
M2
C2
In2
M2
C2
In1
M1
C1 (a)
In3
M3
C3 (b)
Combinational Logic
Prentice Hall 1995

Improved Logic Design
Combinational Logic
Prentice Hall 1995

Buffering: Isolate Fan-in from Fan-out
CL
CL
Combinational Logic
Prentice Hall 1995
Example: Full Adder

V DD VDD Ci A B Ci A Ci X Ci A Ci A B B VDD A Co B Ci A B S B VDD B A A B
Co = AB + Ci(A+B) 28 transistors
A Revised Adder Circuit

V DD VDD A "0"-Propagate Ci "1"-Propagate A B A Generate B A B Ci A B B B Kill A Co Ci S Ci A B V DD Ci A B
24 transistors
Combinational Logic
Prentice Hall 1995
Ratioed Logic
VDD Resistive Load RL F In1 In2 In3 PDN VSS (a) resistive load In1 In2 In3 PDN VSS (b) depletion load NMOS Depletion Load VDD VT < 0 F In1 In2 In3 PDN VSS (c) pseudo-NMOS PMOS Load VSS F VDD
Goal: to reduce the number of devices over complementary CMOS

Ratioed Logic
VDD N transistors + Load Resistive Load RL VOH = V DD VOL = F In1 In2 In3 RPN RPN + RL Assymetrical response PDN Static power consumption tpL = 0.69 RL CL
VSS
Active Loads
VDD Depletion Load PMOS Load VSS F In1 In2 In3 PDN In1 In2 In3 PDN F VDD
VT < 0
VSS depletion load NMOS
VSS pseudo-NMOS
Combinational Logic
Prentice Hall 1995
Load Lines of Ratioed Gates

1
Current source
IL(Normalized)
0.75
0.5
Pseudo-NMOS
Depletion load 0.25 Resistive load 0 0.0
1.0
2.0
3.0 Vout (V)
4.0
5.0
Combinational Logic
Prentice Hall 1995
Pseudo-NMOS
VDD
F CL
VOH = VDD (similar to complementary CMOS)

2 VOL k p 2 k n ( VDD VTn )VOL ------------- = ------ ( V DD VTp ) 2 2 kp V ) 1 1 ------ (assuming that V = V = (V = V ) OL DD T T Tn Tp k n
SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!

Pseudo-NMOS NAND Gate

VDD
GND
Combinational Logic
Prentice Hall 1995
Improved Loads
V DD
Enable
M1
M2
M1 >> M2
F A B C D CL
Adaptive Load
Improved Loads (2)

VDD VDD
M1
M2
Out A A B B
Out
PDN1
PDN2
VSS
VSS
Dual Cascode Voltage Switch Logic (DCVSL)

Example
Out Out
XOR-NXOR gate
Pass-Transistor Logic
B Inputs Switch Network B Out A Out B
N transistors No static consumption
Combinational Logic
Prentice Hall 1995
NMOS-only switch
C=5V A=5V B CL A=5V Mn M1 C=5V M2 B
VB does not pull up to 5V, but 5V - VTN Threshold voltage loss causes static power consumption
Solution 1: Transmission Gate

C A
C B A C B
C
C=5V A=5V B CL C=0V
Resistance of Transmission Gate
30000.0 Rn (W/L)p =(W/L)n = 20000.0 R (Ohm) Rp 1.8/1.2
10000.0
Req
0.0 0.0
1.0
2.0 Vout
3.0
4.0
5.0
Combinational Logic
Prentice Hall 1995
Pass-Transistor Based Multiplexer

S VDD
S V DD
M2 S M1 F
GND In1
In2
Prentice Hall 1995
Combinational Logic
Transmission Gate XOR

B
B M2 A M1 B B A F M3/M4
Combinational Logic
Prentice Hall 1995
Delay in Transmission Gate Networks

5 In 0 V1 Vi-1 C 0 (a) Req In V1 C Req Req Vn-1 C Req 5 Vi C 5 Vi+1 0 C Vn-1 C 5 Vn 0 C
Vi C
Vi+1 C
Vn C
(b) m Req In C CC C C CC C Req Req Req Req Req
(c)
Combinational Logic
Prentice Hall 1995
Elmore Delay (Chapter 8)

Vin R1 1 R2 2 Ri-1 Ci-1 i-1 Ri Ci i RN CN N
C1
C2
Assume All internal nodes are precharged to VDD and a step voltage is applied at the input Vin N N = N N i
Ri Cj = C i R j i=1 j=i i=1 j=1
Combinational Logic
Prentice Hall 1995
Delay Optimization
Combinational Logic
Prentice Hall 1995
Transmission Gate Full Adder

P VDD A A B VDD Ci Ci A Setup A P A P B Ci P Ci P A P Ci P Co Carry Generation VDD S Sum Generation
VDD
Combinational Logic
Prentice Hall 1995
(2) NMOS Only Logic: Level Restoring Transistor

VDD Level Restorer Mr B A Mn X M1 M2 Out VDD
Advantage: Full Swing Disadvantage: More Complex, Larger Capacitance Other approaches: reduced threshold NMOS
Level Restoring Transistor
5.0 Vout (V) without 3.0 1.0 -1.00
5.0 with VB 3.0 1.0 4 6 -1.00 2 t (nsec) 4
with without
VX
t (nsec)
(a) Output node
(b) Intermediate node X
Combinational Logic
Prentice Hall 1995
Solution 3: Single Transistor Pass Gate with VT=0

VDD 0V VDD 5V
VDD
0V
Out
5V
WATCH OUT FOR LEAKAGE CURRENTS

Complimentary Pass Transistor Logic

A A B B Pass-Transistor Network F
(a)
A A B B Inverse Pass-Transistor Network F
A B A B AND/NAND F=AB F=AB
A B A B OR/NOR F=A+B F=A+B
A A A A EXOR/NEXOR F=A F=A
(b)
Combinational Logic
Prentice Hall 1995
4 Input NAND in CPL
Combinational Logic
Prentice Hall 1995
Dynamic Logic
V DD Mp Out In1 In2 In3 CL PDN In1 In2 In3 PUN Out Me n network Mp p network CL V DD Me
2 phase operation:
Precharge Evaluation
Example
V DD Mp Out Ratioless No Static Power Consumption A C B Noise Margins small (NML ) Requires Clock
N + 1 Transistors
Me
Combinational Logic
Prentice Hall 1995
Transient Response
6.0 Vout
4.0 Vout (Volt)
EVALUATION
PRECHARGE
2.0
0.0 0.00e+00
2.00e-09
t (nsec)
4.00e-09
6.00e-09
Prentice Hall 1995
Combinational Logic
Dynamic 4 Input NAND Gate

VDD
Out
In1 In2 In3 In4
GND
Combinational Logic
Prentice Hall 1995
Reliability Problems Charge Leakage

VDD Mp Out (1) A (2) Vout CL precharge evaluate t
Me t (b) Effect on waveforms
(a) Leakage sources
Minimum Clock Frequency: > 1 MHz

Charge Sharing (redistribution)

VDD Mp Out CL A Ma X Ca
case 1) if V out < VTn

C V = C V t + C (V V ( V )) L DD L out ( ) a DD Tn X or Ca V out = Vout ( t ) V DD = ------- ( V DD V Tn ( V X )) CL
B=0
Mb
case 2) if V out > VTn

C a Vout = V DD ---------------------- Ca + CL
Me
Cb
Combinational Logic
Prentice Hall 1995
Charge Redistribution - Solutions

VDD Mp Mbl Out A Ma Mb A Ma Mb VDD Mp Mbl
Out
Me
Me
(a) Static bleeder

(b) Precharge of internal nodes

Clock Feedthrough
VDD Mp Out CL A Ma X Ca
could potentially forward bias the diode 5V
Mb
overshoot out
Me
Cb
Combinational Logic
Prentice Hall 1995
Clock Feedthrough and Charge Sharing

output without redistribution (Ma off) feedthrough 6
out 4 V (Volt) internal node in PDN 2
1 t (nsec)
Combinational Logic
Prentice Hall 1995
Cascading Dynamic Gates

VDD VDD V In Out2 Out1 In Out2 Me (a) Me (b) VTn V t
Mp Out1
Mp
Only 0 1 Transitions allowed at inputs!

Domino Logic
VDD Mp Out1 VDD VDD Mp Mr Out2 In1 In2 In3 Me Me PDN In4 PDN Static Inverter with Level Restorer
Combinational Logic
Prentice Hall 1995
Domino Logic - Characteristics

Only non-inverting logic Very fast - Only 1->0 transitions at input of inverter move VM upwards by increasing PMOS Adding level restorer reduces leakage and charge redistribution problems Optimize inverter for fan-out
Combinational Logic
Prentice Hall 1995
np-CMOS
VDD Mp VDD Out1 Me
In1 In2 In3
PDN
In4
PUN Out2
Me
Mp
Only 1 0 transitions allowed at inputs of PUN

np CMOS Adder
VDD A1 VDD A0 A0 C i0 Carry Path
V DD B1 A1 Ci2
V DD A1 C i1 A1 B1 VDD V DD Ci1 A0 B0 C i0
V DD S1
B1
B1
Ci1
B0 A0 C i0
B0
B0
S0
Manchester Carry Chain Adder

V DD P0 M0 3 C i,0 3.5 G0 3 M1 P1 2.5 G1 3.5 M2 2.5 P2 2 G2 2 M3 P3 1.5 G3 2.5 M4 1.5 P4 1 G4 1 C o,4 0.5 Total Area: 225 m 48.6 m
1.5
Combinational Logic
Prentice Hall 1995
CMOS Circuit Styles - Summary
Combinational Logic
Prentice Hall 1995

Combinational Logic: Digital Integrated Circuits © Prentice Hall 1995

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COMBINATIONAL LOGIC

Digital Integrated Circuits

Prentice Hall 1995

Digital Integrated Circuits

Prentice Hall 1995

Combinational vs. Sequential Logic

(a) Combinational Output = f(In)

(b) Sequential Output = f(In, Previous In)

Prentice Hall 1995

Static CMOS Circuit

In1 In2 In3

PUN and PDN are Dual Networks

NMOS Transistors in Series/Parallel Connection

NMOS Transistors pass a strong 0 but a weak 1

PMOS Transistors in Series/Parallel Connection

PMOS Transistors pass a strong 1 but a weak 0

Complementary CMOS Logic Style Construction (cont.)

Digital Integrated Circuits

Prentice Hall 1995

Example Gate: NAND

Digital Integrated Circuits

Prentice Hall 1995

Example Gate: NOR

Digital Integrated Circuits

Prentice Hall 1995

Example Gate: COMPLEX CMOS GATE

Digital Integrated Circuits

Prentice Hall 1995

4-input NAND Gate

VDD In1 In2 In1 In2 In3 In4 Out

Standard Cell Layout Methodology

VSS Routing Channel signals polysilicon

Digital Integrated Circuits

Prentice Hall 1995

Two Versions of (a+b).c

(a) Input order {a c b}

(b) Input order {a b c}

Digital Integrated Circuits

Prentice Hall 1995

Digital Integrated Circuits

Prentice Hall 1995

Consistent Euler Path

x GND a b c d (c) stick diagram for ordering {a b c d}

Properties of Complementary CMOS Gates

Digital Integrated Circuits

Prentice Hall 1995

Properties of Complementary CMOS Gates

Digital Integrated Circuits

Prentice Hall 1995

Input Dependent Focus on worst-case

Digital Integrated Circuits

Prentice Hall 1995

Propagation Delay Analysis - The Switch Model

(c) 2-input NOR

tp = 0.69 Ron CL (assuming that CL dominates!)

Digital Integrated Circuits

Prentice Hall 1995

What is the Value of Ron?

Digital Integrated Circuits

Prentice Hall 1995

Numerical Examples of Resistances for 1.2m CMOS

Digital Integrated Circuits

Prentice Hall 1995