United International University (UIU)

Dept. of Electrical and Electronic Engineering (EEE) Course Code: EEE 442, Title: VLSI Design Lab Summer 2012

Experiment # 6: Layout design for a 1- bit binary / 4 - bit binary Full Adder
Full Adder: A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 CIN 0 1 0 1 0 1 0 1 CO 0 0 0 1 0 1 1 1 SUM 0 1 1 0 1 0 0 1 CO = AB SUM = A B + AB

Procedures: 01. Draw a 1-bit Full Adder using Half Adders and Logic Gates. 02. Draw the layout of this Full Adder (A sample layout of Full Adder in Figure 1). Use layout of the Half Adder from Experiment 3. Open the Half Adder Layout HA_1bit.MSK and save it as FA_1bit.MSK. 03. Simulate this layout and verify the results.

Figure 1: Layout of 1-bit Full Adder 04. Save the layout. We will use this layout to build a 4-bit Full Adder. 05. Open the 1-bit Full Adder Layout if it is not already opened and save it as FA_4bit.MSK. 06. Draw the layout of a 4-bit Full Adder (A sample layout of Full Adder in Figure 1). Use the 1bit Full Adder Layout to draw the 4-bit Full Adder layout. 07. Simulate this layout and verify the results.

Figure 2: Layout of 4-bit Full Adder