1

3 March 2009 1
Gate
Source
Drain
Ids
Operation Mode: nMOS
VGS < Vtn
Gate
Source
Drain
Ids
VGS > Vtn
VGD > Vtn
Gate
Source
Drain
Ids
VGS > Vtn
VGD < Vtn
Cutoff
Linear
Saturation
(

=
2
) (
2
DS
DS T GS n DS
V
V V V k I
2
) (
2
T GS
n DS
V V
k I

= 0 =
DS
I
3 March 2009 2
Gate
Source
Drain
Ids
Operation Mode: pMOS
VGS < Vtp
VGD < Vtp
Gate
Source
Drain
Ids
VGS < Vtp
VGD > Vtp
Gate
Source
Drain
Ids
VGS > Vtp
Cutoff
Linear
Saturation
(

=
2
) (
2
DS
DS T GS
p
DS
V
V V V k I
2
) (
2
T GS
p DS
V V
k I

= 0 =
DS
I
3 March 2009 3
Gate
Source
Drain
Ids
Operation Region: pMOS
VGS < Vtp
VGD < Vtp
Gate
Source
Drain
Ids
VGS < Vtp
VGD > Vtp
Gate
Source
Drain
Ids
VGS > Vtp
Cutoff
Linear
Saturation
0 =
DS
I
(

=
2
) (
2
DS
DS T GS
p
DS
V
V V V k I
2
) (
2
T GS
p DS
V V
k I

=
3 March 2009 4
CMOS Inverter
First-Order DC Analysis
Vin = 0 Vin = VDD
High noise margin
Ratioless
low output impedance
extremely high input impedance
no static power
Vin Vout
VDD
3 March 2009 5
CMOS Inverter: Transient Response
Vin = VDD 0 Vin = 0 VDD
Low-to-High High-to-Low
To reduce delay:
Reduce CL
Reduce Rp,n
Increase W/L ratio
Output:
CL is composed of the drain diffusion capacitances of the NMOS and PMOS transistors,
the capacitance of connecting wires, and the input capacitance of the fan-out gates
3 March 2009 6
NMOS Load Lines
0 0.5 1 1.5 2 2.5
0
1
2
3
4
5
6
x 10
-4
V
DS
(V)
I D
S
(
A
)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Linear Saturation
V
DS
= V
GS
- V
T
2
3 March 2009 7
PMOS Load Lines
Vin Vout
VDD
3 March 2009 8
CMOS Inverter Load Characteristics
3 March 2009 9
CMOS Inverter VTC
VTC: Voltage-Transfer
Characteristic
3 March 2009 10
CMOS Inverter VTC
Vtn Vin
Vout
VDD
Vin Vout
VDD
S
S
D
D
G
G
3 March 2009 11
CMOS Inverter VTC
Vtn Vin
VDD
Vout
Vout - |Vtp|
Vin Vout
VDD
S
S
D
D
G
G
3 March 2009 12
CMOS Inverter VTC
Set pMOS Linear I
DS
equal to nMOS
Saturation I
DS
( )
|
|

\
|
=
|
|

\
|
2
) (
) )( (
2
2 2
DD out
DD out tp DD in p
tn in
n
V V
V V V V V k
V V
k
( )
0
2
) )( (
2
) (
2 2
=

tn in
p
n
DD out tp DD in
DD out
V V
k
k
V V V V V
V V
( )
2 2
) ( ) ( ) (
tn in
p
n
tp DD in tp DD in DD out
V V
k
k
V V V V V V V V + =
( )
2 2
) ( ) (
tn in
p
n
tp DD in tp in out
V V
k
k
V V V V V V + =
3
3 March 2009 13
CMOS Inverter VTC
Vtn
VDD
Vout
Vout - |Vtp| Vout + Vtn
Vin
Vin Vout
VDD
S
S
D
D
G
G
3 March 2009 14
CMOS Inverter VTC
Vtn
VDD
Vout
Vout - |Vtp| Vout + Vtn
Vtn VDD - |Vtp| Vin
Vin Vout
VDD
S
S
D
D
G
G
3 March 2009 15
CMOS Inverter VTC
Set nMOS Linear I
DS
equal to pMOS
Saturation I
DS
( )
( )
|
|

\
|
=
|
|

\
|
2 2
2
2
out
out tn in n
tp DD in
p
V
V V V k
V V V
k
( )
( )
0
2 2
2
2
=

+
tp DD in
n
p
out tn in
out
V V V
k
k
V V V
V
( ) ( ) ( )
2 2
tp DD in
n
p
tn in tn in out
V V V
k
k
V V V V V =
3 March 2009 16
CMOS Inverter VTC
Vtn
VDD
Vout
Vout - |Vtp| Vout + Vtn
Vtn VDD - |Vtp| Vin
VDD
Vin Vout
VDD
S
S
D
D
G
G
3 March 2009 17
CMOS Inverter VTC
VDD
Vin
Vout
VDD
3 March 2009 18
CMOS Inverter
(assume Vt = Vtn = |Vtp|)
4
3 March 2009 19
Switching Threshold
The point (V
m
) at which the inverter has
both transistors in saturation (V
in
= V
out
)
2 2
) (
2
) (
2
tp DD M
p
tn M
n
V V V
k
V V
k
=
) ( ) (
tp DD M
n
p
tn M
V V V
k
k
V V =
) ( ) 1 (
tp DD tn M
V V r V r V + + = +
r
V V r V
V
tp DD tn
M
+
+ +
=
1
) (
r is the relative driving strengths of the PMOS and NMOS transistors
r
3 March 2009 20
Switching Threshold
When V
tn
= -V
tp
and r = 1,
When V
tn
= -V
tp
and r > 1,
r
V V r V
V
tp DD tn
M
+
+ +
=
1
) (
2
DD
M
V
V =
2
DD
M
V
V >
Stronger PMOS
3 March 2009 21
0
0.5
1
1.5
2
2.5
0 0.5 1 1.5 2 2.5
V
in
(V)
V
o
u
t
(
V
)
Balanced
Strong PMOS
Strong NMOS
Switching Threshold
3 March 2009 22
Noise Margin
A measure of the acceptable noise at a gate
input so that the output is not affected.
Noise margin is closely related to the DC
voltage characteristics
Sources: supply noise, crosstalk,
interference
3 March 2009 23
Noise Margin
VOLmax: Maximum low
output voltage produced
by the driving gate
VILmax: Maximum low input
voltage recognized by the
receiving gate
Low Noise Margin
High Noise Margin
Logical Low Input Voltage
Logical Low Output Voltage
Output
Characteristics
Input
Characteristics
3 March 2009 24
Noise Margins
Voltage Transfer Function
Voltage Transfer Function with Noise
Perturbed voltage is the sum of the nominal
output plus the gain times the noise
Keep the gain less than 1
) (
in out
V f V =
) (
noise in out
V V f V + =
noise
in
out
in out
V
dV
dV
V f V + ) (
5
3 March 2009 25
Noise Margins
VDD
Vin
Vout
VDD
VOH
VOL
Undefined region
VIL
VIH
3 March 2009 26
Static Load Inverter
3 March 2009 27
Static Load Inverter
3 March 2009 28
Static Load Inverter
Linear
Mode
3 March 2009 29
Static Load Inverter
Transistor is in linear region
(

=
2
) (
2
DS
DS T GS n DS
V
V V V k I
(

=
2
) (
2
OUT
OUT T IN n DD OUT
V
V V V Rk V V
0 ) 1 ) ( (
2
2
= + +
DD OUT T IN n OUT
n
V V V V Rk V
Rk
( )
n
DD
n
T IN
n
T IN OUT
Rk
V
Rk
V V
Rk
V V V 2
1 1
) (
2

|
|

\
|
+ + =
3 March 2009 30
Static Load Inverter
6
3 March 2009 31
Static Load Inverter
Transistor is in saturation
) 1 (
2
) (
2
DS
T GS
n DS
V
V V
k I +

=
) 1 (
2
) (
2
OUT
T IN
n DD OUT
V
V V
Rk V V +

=
2
2
) ( 2
) ( 2
T IN n
T IN n DD
OUT
V V Rk
V V Rk V
V
+

=

3 March 2009 32
Static Load Inverter
V
OH
V
OL
Undefined region
3 March 2009 33
Static Load Inverter
Does not go down all the way to 0 due to
the resistance path between V
DD
and
ground when nMOS is on
Static power
Noise margins are tighter
Switching threshold is not centered
To get high gain in the transition region,
bigger resistors are needed