DM74LS194A 4-Bit Bidirectional Universal Shift Register

August 1986 Revised March 2000

DM74LS194A 4-Bit Bidirectional Universal Shift Register
General Description
This bidirectional shift register is designed to incorporate virtually all of the features a system designer may want in a shift register; they feature parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely: Parallel (broadside) load Shift right (in the direction QA toward QD) Shift left (in the direction QD toward QA) Inhibit clock (do nothing) Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, HIGH. The data is loaded into the associated flip-flops and appear at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited. Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is HIGH and S1 is LOW. Serial data for this mode is entered at the shift-right data input. When S0 is LOW and S1 is HIGH, data shifts left synchronously and new data is entered at the shift-left serial input. Clocking of the flip-flop is inhibited when both mode control inputs are LOW.

s Parallel inputs and outputs s Four operating modes: Synchronous parallel load Right shift Left shift Do nothing s Positive edge-triggered clocking s Direct overriding clear

Ordering Code:
Order Number DM74LS194AM DM74LS194AN Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

© 2000 Fairchild Semiconductor Corporation


before the most-recent ↑ transition of the clock. B.DM74LS194A Function Table Inputs Clear L H H H H H H H Mode S1 X X H L L H H L S0 X X H H H L L L Clock X L ↑ ↑ ↑ ↑ ↑ X Serial Left X X X X X H L X Right X X X H L X X X A X X a X X X X X Parallel B X X b X X X X X C X X c X X X X X D X X d X X X X X QA L QA0 a H L QBn QBn QA0 Outputs QB L QB0 b QAn QAn QCn QCn QB0 QC L QC0 c QBn QBn QDn QDn QC0 QD L QD0 d QCn QCn H L QD0 H = HIGH Level (steady state) L = LOW Level (steady state) X = Don’t Care (any input. QBn. d = The level of steady state input at inputs A. Logic Diagram www. C or D. QB0. QC. QCn. QB. QB. respectively. Q D0 = The level of QA. including transitions) ↑ = Transition from LOW-to-HIGH level a. QAn. QA0. c. or QD. before the indicated steady state input conditions were established.fairchildsemi. Q Dn = The level of QA. b. QC. QC0. respectively. 2 .

5 0. TA = 25°C and VCC = 5V. VI = 0. RL = 2 kΩ. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. VI = 2.35 0.DM74LS194A Absolute Maximum Ratings(Note 1) Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 0°C to +70°C −65°C to +150°C 7V 7V Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. and the serial inputs.8 −0.4 8 25 20 Nom 5 Max 5.4 0. II = −18 mA VCC = Min. VI = 7V VCC = Max. CLEAR. inputs A through D grounded.7 3.25 Units V V V mA mA MHz ns ns ns ns °C Note 2: CL = 15 pF. IOL = Max VIL = Max. The “Recommended Operating Conditions” table will define the conditions for actual device operation. and the duration should not exceed one second.4 −100 23 mA µA mA mA mA Min Typ (Note 5) Max −1.7V VCC = Max.4V VCC = Max (Note 6) VCC = Max (Note 7) −20 15 2.5 Units V V V Note 5: All typicals are at VCC = 5V. ICC is tested with momentary ground.75 2 0.5V applied to CLOCK. S1. Note 6: Not more than one output should be shorted at a time. VIH = Min IOL = 4 mA.5V applied to S0. VCC = Min VCC = Max. TA = 25°C. Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL IOS ICC Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current Conditions VCC = Min. and 4. TA = 25°C and VCC = 5V. The device should not be operated at these limits.4 0. Note 7: With all outputs open. Note 3: CL = 50 pF. VIH = Min VCC = Min.fairchildsemi. IOH = Max VIL = Max. 3 www. Recommended Operating Conditions Symbol VCC VIH VIL IOH IOL fCLK tW tSU tH tREL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency (Note 2) Clock Frequency (Note 3) Pulse Width (Note 4) Setup Time (Note 4) Hold Time (Note 4) Clear Release Time (Note 4) Free Air Operating Temperature Clock Clear Mode Data 0 0 20 20 30 20 0 25 0 70 Parameter Min 4.1 20 −0. Note 4: TA = 25°C and VCC = 5V. then .

From (Input) To (Output) Clock to Any Q Clock to Any Q Clear to Any Q CL = 50 pF. and the serial inputs.DM74LS194A Switching Characteristics at VCC = 5V and TA = 25°C Symbol fMAX tPLH tPHL tPHL Parameter Maximum Clock Frequency Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time HIGH-to-LOW Output Note 8: All typicals are at VCC = 5V. then 4. and 4.5V applied to CLOCK. Load. Right-Shift. RL = 2 kΩ Min 20 26 35 38 Max Units MHz ns ns ns Timing Diagram Typical Clear. and the duration should not exceed one second. ICC is tested with momentary ground. TA = 25°C. Note 9: Not more than one output should be shorted at a time. S1. and Clear Sequences 4 . CLEAR. Inhibit. Note 10: With all outputs open. inputs A through D grounded. Left-Shift.fairchildsemi.5V applied to S0.

JEDEC . 0.fairchildsemi.150 Narrow Package Number M16A 5 www.DM74LS194A Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC).

fairchildsemi. Life support devices or systems are devices or systems which.DM74LS194A 4-Bit Bidirectional Universal Shift Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP). As used herein: 1.fairchildsemi. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. www. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system. and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling. or to affect its safety or effectiveness.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described. JEDEC 6 2. no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 0. can be reasonably expected to result in a significant injury to the user. (a) are intended for surgical implant into the body. or (b) support or sustain . www.

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