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Features
s Parallel inputs and outputs s Four operating modes: Synchronous parallel load Right shift Left shift Do nothing s Positive edge-triggered clocking s Direct overriding clear
Ordering Code:
Order Number DM74LS194AM DM74LS194AN Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.
Connection Diagram
DS006407
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DM74LS194A
Function Table
Inputs Clear L H H H H H H H Mode S1 X X H L L H H L S0 X X H H H L L L Clock X L X Serial Left X X X X X H L X Right X X X H L X X X A X X a X X X X X Parallel B X X b X X X X X C X X c X X X X X D X X d X X X X X QA L QA0 a H L QBn QBn QA0 Outputs QB L QB0 b QAn QAn QCn QCn QB0 QC L QC0 c QBn QBn QDn QDn QC0 QD L QD0 d QCn QCn H L QD0
H = HIGH Level (steady state) L = LOW Level (steady state) X = Dont Care (any input, including transitions) = Transition from LOW-to-HIGH level a, b, c, d = The level of steady state input at inputs A, B, C or D, respectively. QA0, QB0, QC0, Q D0 = The level of QA, QB, QC, or QD, respectively, before the indicated steady state input conditions were established. QAn, QBn, QCn, Q Dn = The level of QA, QB, QC, respectively, before the most-recent transition of the clock.
Logic Diagram
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DM74LS194A
Note 2: CL = 15 pF, TA = 25C and VCC = 5V. Note 3: CL = 50 pF, RL = 2 k, TA = 25C and VCC = 5V. Note 4: TA = 25C and VCC = 5V.
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL IOS ICC Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current Conditions VCC = Min, II = 18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 4 mA, VCC = Min VCC = Max, VI = 7V VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max (Note 6) VCC = Max (Note 7) 20 15 2.7 3.4 0.35 0.5 0.4 0.1 20 0.4 100 23 mA A mA mA mA Min Typ (Note 5) Max 1.5 Units V V
Note 5: All typicals are at VCC = 5V, TA = 25C. Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 7: With all outputs open, inputs A through D grounded, and 4.5V applied to S0, S1, CLEAR, and the serial inputs, ICC is tested with momentary ground, then 4.5V applied to CLOCK.
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DM74LS194A
Switching Characteristics
at VCC = 5V and TA = 25C Symbol fMAX tPLH tPHL tPHL Parameter Maximum Clock Frequency Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time HIGH-to-LOW Output
Note 8: All typicals are at VCC = 5V, TA = 25C. Note 9: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 10: With all outputs open, inputs A through D grounded, and 4.5V applied to S0, S1, CLEAR, and the serial inputs, ICC is tested with momentary ground, then 4.5V applied to CLOCK.
Units MHz ns ns ns
Timing Diagram
Typical Clear, Load, Right-Shift, Left-Shift, Inhibit, and Clear Sequences
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DM74LS194A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A
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16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E
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