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Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
Timing Analysis
Dynamic Timing Analysis (DTA) Static Timing Analysis (STA)
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
So-called Simulation
Input vectors are applied during the simulation time Simulator calculates the logic value and delays Virtually impossible to do exhaustive analysis
Disadvantages of DTA
Hard to discern the cause of failure because the function and timing are analyzed at the same time Requires more memory and CPU resources over STA
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
Break the design into sets of timing paths Calculate the delay of each path (create timing graph) Check all path delays to see if the given timing constraints are met
D Q QN D Q QN
IN
OUT
CLK
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
IN
Q QN
Q QN
OUT
CLK
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
observed that you could exhaustively test all behaviors within a single clock cycle
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
Advantages of STA
Exhaustive timing coverage Does not require input vectors More efficient than DTA in memory and CPU resources
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
Disadvantages of STA
For synchronous logic only Difficult to learn Tricky constraints beyond the boundaries of single clock flip-flop design chips:
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
Start Point: clock pin of sequential device End Point: data input pin of sequential devices
Start Point: primary input port End Point: data input pin of sequential devices
Start Point: clock pin of sequential device End Point: primary output port
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
Start Point: primary input port End Point: primary output port
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Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Netlist is represented as directed acyclic graph (DAG) Delay values associated with links (Cells & Nets) are calculated Create the timing graph of arrival time (AT) Create the timing graph of required time (RT) Create the slack graph
Timing is met when slack is greater than or equal to zero (RT should always be after AT)
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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0.55 1.3 0.1 1.2 0.65 0.20.85 0.1 0.2 0.7 0.2 0.9 1.0 0.1 0.1
Tarr = 0.1
0.2
0.15
Timing Arc
0.3 0.4
0.1 1.3
Tarr = 0.1
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Treq = 1.5
0.05
1.15 0.65 0.20.85 0.1 0.2 1.4 0.65 0.2 0.95 0.25 0.35 0.1 0.2 0.1 0.2 0.55
0.1
Tarr = 1.5
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Slack Graph
0 0 0 -0.05 -0.05 -0.05 -0.05 -0.55 -0.05 0 0 -0.05
-0.05 -0.05
-0.05 -0.05
0.2
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Block-based: timing information is associated with discrete design elements (ports, pins, gates)
Path-based: timing information is associated with topological paths (collections of design elements)
Used in Primetime
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Path-based:
2 1 3 2 3 1 RAT=10 2+2+3 = 7 (OK) 2+3+1+3 = 9 (OK) 2+3+3+2 = 10 (OK) 5+1+1+3 = 10 (OK) 5+1+3+2 = 11 (Fail) 5+1+2 = 8 (OK)
AT=2
AT=2 RAT=5
3 1 AT=5
AT=5 RAT=4
2 1
AT=6 RAT=5
AT=7 RAT=7
Block-based:
3 2 RAT=10
AT=11 RAT=10
3 1
AT=9 RAT=8
Critical path is determined as collection of gates with the same, negative slack: In our case, we see one critical path with slack = -1
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Timing Arcs
Describes the timing relationship between two nodes When traversing the design structure to update AT and RT, STA is actually traversing through timing arcs from node to node Defined in cell library
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Combinational Arcs
Combinational arcs are the default arcs Each combinational arc has one of three timing senses Timing senses are specified in the library or automatically derived from the logic function
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Constrains the time before the active clock edge when the data needs to be stable
setup_rising setup_falling
CK
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Constraints for the time after the active clock edge when the data still needs to be stable
hold_rising hold_falling
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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After a launching clock edge, the clock node is converted to a data node
falling_edge rising_edge
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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After an active asynchronous signal occurs, the time the data appears at the output of the register
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Recovery Types
The amount of time before an active clock edge an asynchronous signal needs to be inactive
recovery_rising recovery_falling
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Removal Arcs
The amount of time after an active clock edge an asynchronous signal needs to be inactive
removal_rising removal_falling
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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three_state_enable three_state_disable
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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nochange_high nochange_low
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Timing Checks
Setup time Hold time Recovery time Removal time Minimum pulse width Glitch detection (clock gating) User-defined Max capacitance Max transition Max fan-out
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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U1
Hold Margin
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STA
Descriptions of Clocks Cell Library Library Data Operating Conditions Timing Exceptions Timing Constraints Boundary Conditions
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Library Data
Operating conditions
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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T0
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Vin
50%
50%
Vout
20% 80%
I1 I2 Dtransition(I1)
Dc Req
Dtransition(I2) I3 Ceq
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Dcell(I2)
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
Delay Tables
Cell Delay Transition Delay
Output Capacitance 0.1 0.2
Vin I1 I2 Dtransition(I1)
I3
Dcell(I2)
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
R or F R
edge_rising edge_falling
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Operating Conditions
The process, voltage, and temperature (PVT) ranges a design encounters Specified in the technology library Cell and interconnect delays are scaled
Dscale = D (1 + P K P )(1 + V KV )(1 + T K T ) P = Pr ocess nom _ process / V = Voltage nom _ voltage T = Temperature nom _ temperature
delay Worst Typical Best Process Voltage Best Temperature 36 delay Worst Typical Best delay Worst Typical
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
STA
Descriptions of Clocks Cell Library Library Data Operating Conditions Timing Exceptions Timing Constraints Boundary Conditions
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Set fan-out constraints Set capacitance constraints Set transition time constraints Define clock specification Specify boundary conditions (I/O timing requirements) Specify combinational path delay requirements Specify timing exceptions
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Uncertainty
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
clock 0 5 10
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Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
Clock Latency
Source latency (delay): the timing a clock signal takes to propagate from its ideal waveform original point to the clock definition point Budgeted network latency (delay) : the time the clock signal takes to propagate from the clock definition point to the clock pin of the sequential cells Actual insertion delay D Q
QN
On Chip cause:
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The maximum difference between the arrival of clock signals at sequential cells in one clock domain or between domains
P1
FF
P4
FF
P2 P3
FF
= = = =
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Clock Uncertainty
On Chip impact:
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Source Latency Jitter Budgeted network latency Budgeted skew Actual insertion delay (network latency) Actual skew
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Set fan-out constraints Set capacitance constraints Set transition time constraints Define clock specification Specify boundary conditions (I/O timing requirements) Specify combinational path delay requirements Specify timing exceptions
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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I/O Constraints
Only comboin needs a "budgeted" arrival time Only combout needs a "budgeted" required time
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Boundary Conditions
Input driving cell Input transition time Output capacitance load Input delay Output delay
D Q QN
b
5pf
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Input Block
My Design
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Set fan-out constraints Set capacitance constraints Set transition time constraints Define clock specification Specify boundary conditions (I/O timing requirements) Specify combinational path delay requirements Specify timing exceptions
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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IN
Logic
Out
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Set fan-out constraints Set capacitance constraints Set transition time constraints Define clock specification Specify boundary conditions (I/O timing requirements) Specify combinational path delay requirements Specify timing exceptions
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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False Path
A path may exist in the circuit but never be used in its normal functional operation A functional path may exist but the timing is very slow or irrelevant A block may be reused and certain signal functions are no longer required A path may exist in the circuit but no combination of input vectors may ever exercise it A combinational loop exists in the design that needs to be broken
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Unexercised Path
A path may exist in the circuit but never be used in its normal functional operation
A test register PROBE is inserted in the circuit to enable chip debugging in the field. Data can be read through the probe register. Data can be written from the probe register. Probing would not occur at speed. (An alternative to scan)
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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False Path
A path may exist in the circuit but never be used in its normal functional operation A functional path may exist but the timing is very slow or irrelevant A block may be reused and certain signal functions are no longer required A path may exist in the circuit but no combination of input vectors may ever exercise it A combinational loop exists in the design that needs to be broken
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Irrelevant Path
The chip uses a synchronized synchronous reset. The reset cycle has a huge number of cycles before it needs to settle.
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Asynchronous Path
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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False Path
A path may exist in the circuit but never be used in its normal functional operation A functional path may exist but the timing is very slow or irrelevant A block may be reused and certain signal functions are no longer required A path may exist in the circuit but no combination of input vectors may ever exercise it A combinational loop exists in the design that needs to be broken
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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IP Reuse
A block may be reused and certain signal functions are no longer required
This piece of logic is a custom adder. With design re-use, often the blocks contain all of the potentially useful functions. When the design is implemented in a chip, often particular signals are not implemented
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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False Path
A path may exist in the circuit but never be used in its normal functional operation A functional path may exist but the timing is very slow or irrelevant A block may be reused and certain signal functions are no longer required A path may exist in the circuit but no combination of input vectors may ever exercise it A combinational loop exists in the design that needs to be broken
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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A path may exist in the circuit but no combination of input vectors may ever exercise it
A signal cannot travel from the Q output of a_reg through the two muxes to b_reg PrimeTime attempts to automatically detect "logically impossible false paths (requires many CPU cycles) These situations are quite rare
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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False Path
A path may exist in the circuit but never be used in its normal functional operation A functional path may exist but the timing is very slow or irrelevant A block may be reused and certain signal functions are no longer required A path may exist in the circuit but no combination of input vectors may ever exercise it A combinational loop exists in the design that needs to be broken
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Combinational Loops
Most STAs cant leave combinational loops in the design, as a race condition will occur PrimeTime dynamically breaks combinational loops.
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Set fan-out constraints Set capacitance constraints Set transition time constraints Define clock specification Specify boundary conditions (I/O timing requirements) Specify combinational path delay requirements Specify timing exceptions
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Multicycle Paths
Multicycle paths occur because the designer knows that the particular logic function will not be used till a later cycle
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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STA
Descriptions of Clocks Cell Library Library Data Operating Conditions Timing Exceptions Timing Constraints Boundary Conditions
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Interconnect Data
Estimated delay information for nets based on a wire load model is used before P&R Back-annotated (Actual) delay information based on the P&R result is often described in the form of
RSPF Reduced Standard Parasitic Format DSPF Detailed Standard Parasitic Format SPEF Standard Parasitic Exchange Format
SPEF also has syntax that allows the modeling of capacitance between different nets, so it is used by the crosstalk analysis tool
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Wireload Model
Very inaccurate!
wire_load (500) ( resistance : 3.0 capacitance: 1.3 area: 0.04 slop: 0.15 fanout_length ( 1 , 2.1 ) fanout_length ( 2 , 2.5) fanout_length ( 3 , 2.8) fanout_length ( 4 , 3.3) /* R per unit length*/ /* C per unit length */ /* area per unit length */ /* extrapolation slope*/ /* fanout-length pairs */
Cwire = (fanout=3, length =2.8) x capacitance coefficient (1.3) = 3.64 load units Rwire = (fanout=3, length =2.8) x resistance coefficient (3.0) = 8.4 resistance units AreaNet = (fanout=3, length =2.8) x area coefficient (0.04) = 0.112 net area units
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Wireload Modes
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Ideal Manhattan Model Computed Manhattan Model Global Routing Model Linear parasitic model Table lookup parasitic model Elmore Model Final Layout Model
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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CapTable
cap_value = f(configuration, width, spacing) Assign CapTable to the reference layer according to the configuration Capacitances are categorized into bottom, top and lateral group
CapModel
M2 M1 Poly
configuration1
air
configuration2
configuration3
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Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
Elmore Model
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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p1 , p2 Poles r1 , r2 - Residues
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Check setup time violations Assume all gates have 3ns max rise delay and 2ns min rise delay Assume all gates have 2ns max fall delay and 1ns min fall delay Assume all nets have 2ns max delay and 1ns min delay 3ns CLK-Q delay 1ns setup time (Ts) 1ns hold time (Th)
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Clock definition
Clock period: 14ns (Dclkp) Clock source latency: 2ns (Dclks) Clock network latency: 3ns (Dclkn) Clock uncertainty: 1ns (Dclku) Input delay of A, B, C: 1ns (Da , Db , Dc) Output delay of Y: 3ns (DY)
IO constraints
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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80
launch edge 0
2 3 R 2
AT = 13 2
R 3
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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launch edge 0
2 2 F 2
AT = 12 2
R 3
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Required time at end point: Dclkp + Dclks + Dclkn - Dclku - Ts = 14+2+3-1-1 = 17ns
source clock (ideal) 14 target clock (ideal) 16 target clock (source)
launch edge 0
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Slack at end point: RT - AT = 17-13 = 4ns Timing is met since slack is greater than 0
R 2 3 R 2 R 3 2
AT = 13 RT = 17
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Slack at end point: RT - AT = 17-12 = 5ns Timing is met since slack is greater than 0
AT = 12 RT = 17 2 F 2 R 3 2
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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AT = 20 3 R2 3 R 2 3 2 R
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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AT = 19 3 F2 2 F 2 3 2 R
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Required time at end point: Dclkp + Dclks + Dclkn - Dclku - Ts = 14+2+3-1-1 = 17ns
launch edge 0 5 14 16 source clock (source+ network) target clock (ideal) target clock (source)
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Slack at end point: RT - AT = 17-20 = -3ns Timing is not met since slack value is negative
AT = 20 3 3 RT = 17 R 2 3 2 R
R2
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Slack at end point: RT - AT = 17-19 = -2ns Timing is not met since slack value is negative
AT = 19 RT = 17 3 F2 2 F 2 3 2 R
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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AT
3 R 2 3
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
AT = 15 R 2
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3 F 2 2
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
AT = 14 F 2
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3 F 2 2
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
RT = 11 F 2
Q QN
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Slack at end point: RT - AT = 11-15 = -4ns Timing is not met since slack value is negative This is the critical path
3 R 2 3
AT = 15 RT = 11 3 R 2
QN D Q
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Slack at end point: RT - AT = 11-14 = -3ns Timing is not met since slack value is negative
3 F 2 2
AT = 14 RT = 11 F 2 3
D Q QN
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Check hold time violations Assume all gates have 3ns max rise delay and 2ns min rise delay Assume all gates have 2ns max fall delay and 1ns min fall delay Assume all nets have 2ns max delay and 1ns min delay 3ns CLK-Q delay 1ns setup time (Ts) 1ns hold time (Th)
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Clock definition
Clock period: 14ns (Dclkp) Clock source latency: 2ns (Dclks) Clock network latency: 3ns (Dclkn) Clock uncertainty: 1ns (Dclku) Input delay of A, B, C: 1ns (Da , Db , Dc) Output delay of Y: 3ns (DY)
IO constraints
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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98
R/F 1 1
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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launch edge 0
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Slack at end point: AT - RT = 2-7 = -5ns Timing is not met since slack value is negative This is the critical path
Q QN
R/F 1 1 AT = 2 RT = 7
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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AT
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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launch edge 0
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Slack at end point: AT - RT = 15-7 = 8ns Timing is met since slack is greater than 0
AT = 15 RT = 7 3 2 R 1 2 1 R
R1
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Slack at end point: AT - RT = 14-7 = 7ns Timing is met since slack is greater than 0
AT = 14 RT = 7 3 F1 1 F 1 2 1 R
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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3 R 1 2
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
AT = 12 R 1
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3 F 1 1
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
AT = 11 F 1
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F 1 1
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
RT = -3 F 1
Q QN
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Slack at end point: AT - RT = 12-(-3) = 15ns Timing is met since slack is greater than 0
AT = 12 R 1 2 RT = -3 R 1
D Q QN
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Slack at end point: AT - RT = 11-(-3) = 14ns Timing is met since slack is greater than 0
AT = 11 F 1 1 RT = -3 F 1 3
Q QN
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Determine the least common multiple (LCM) of the 2 clock periods first and then find the setup and hold relationship
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Setup Relationships
Find the Setup Relationship between A rising to B rising The setup relationship is the closest distance between the launching clock edge (A) to the receiving clock edge (B)
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Hold Relationships
Find the Hold Relationship between A rising to B rising The hold relationship is the closest distance between the launching edge (A) to the previous receiving edge (B)
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Yes! In fact there is extra time before the activating edge of c_reg
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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No. The earliest b_reg can launch the data is at time 5. c_reg will receive the data too late
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Single OC Analysis
Typically, you need to perform timing analysis for at least two operating conditions to ensure that the design has no timing violations
Best case (minimum path report) (Hold Time Check) Worst case (maximum path report) (Setup Time Check) fast.lib typical.lib slow.lib
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For most of STA tools, you can simultaneously perform timing analysis for the best-case and worstcase operating conditions.
Max paths analyzed with worst case OC (Setup Time Check) Min paths analyzed with best case OC (Hold Time Check) SDF back-annotated delays Input and output delays Wire load models Net resistance-capacitance Clock latency/transition Driving cell
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Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Case Analysis
Timing analysis with specified logic value conditions on pins or ports Logic constants are propagated to avoid unnecessary timing path analysis (3 paths in this example)
F2
F 2 2 0 2 F 0
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Synopsys Design Compiler / Cadence Ambit Magma Blast RTL / Blast Fusion Synopsys Physical Compiler / Synopsys Saturn Synopsys Astro / Cadence SE / Cadence SOC Encounter Synopsys Apollo / Astro Cadence SE / Cadence SOC Encounter Magma Blast Fusion Primetime
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STA sign-off
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis