SOI wafer

Delphine Chang

Whats SOI
Silicon on insulator Insulator: mostly silicon dioxide or sapphire

Si 2 Si

Advantage of SOI
Low power consumption Reason: SOI has lower parasitic capacitance due to isolation from the bulk silicon Latch-up immunity Reason: No resistance to latchup due to complete isolation of the n- and p-well structures. High speed Manufacturing process simplificatio Improved scaling.

Weakness of SOI
More consideration for the process- the oxide layer Differential stress in the topmost silicon layer The increasing cost of substrate e.g. 1015% increase

The fabrication of SOI wafer

Two main methods:
implantation of oxygen into silicon (SIMOX) bonded wafer approach

Bonded wafer approach

Etch back

Improves bonded wafer approach

Add Smart Cut Approach

Step 5: Bottom=SOI wafer Top=new Si

Back-up

Latch-up
When A is big enough(VGS>vth) Turn on NMOS Provide current on the left Lower the voltage at B VGS(PMOS) is bigger Increase the current on the right VGS(NMOS) increases The current on the left increases etc It forms a positive feedback, which would continue increase the current until the circuit fails or burns out.)
B